GSI GS71116U-15I, GS71116U-15, GS71116U-12I, GS71116U-12, GS71116U-10I Datasheet

GS71116TP/J/U

SOJ, TSOP, FP-BGA

64K x 16

Commercial Temp
Industrial Temp

1Mb Asynchronous SRAM

Features

• Fast access time: 10, 12, 15ns

• CMOS low power operation: 100/85/70 mA at min. cycle time.

• Single 3.3V ± 0.3V power supply

• All inputs and outputs are TTL compatible

• Byte control

• Fully static operation

• Industrial Temperature Option: -40° to 85°C

• Package line up
J: 400mil, 44 pin SOJ package
TP: 400mil, 44 pin TSOP Type II package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package

Description

The GS71116 is a high speed CMOS static RAM organized as
65,536-words by 16-bits. Static design eliminates the need for exter­nal clocks or timing strobes. Operating on a single 3.3V power supply
and all inputs and outputs are TTL compatible. The GS71116 is avail­able in a 6x8 mm Fine Pitch BGA package as well as in 400 mil SOJ
and 400 mil TSOP Type-II packages.

SOJ 64K x 16 Pin Configuration

A4
A3
A2
A1
A0

CE
DQ1
DQ2
DQ3
DQ4
VDD

VSS
DQ5
DQ6
DQ7
DQ8

WE
A15
A14
A13

A12

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

16
17
18
19
20
21
22

Top view

44 pin

SOJ

10, 12, 15ns

3.3V VDD

Center VDD & VSS

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

27
26
25
24
23

A5
A6
A7
OE
UB
LB
DQ16
DQ15
DQ14

DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
A11
NCNC

Pin Descriptions

Symbol Description

A0 to A15

DQ1 to DQ16 Data input/output

CE Chip enable input

LB

UB

WE Write enable input
OE Output enable input
VDD +3.3V power supply
VSS Ground
NC No connect

Address input

Lower byte enable input

(DQ1 to DQ8)

Upper byte enable input

(DQ9 to DQ16)

Fine Pitch BGA 64K x 16 Bump Configuration

1 2 3 4 5 6

A LB OE A0 A1 A2 NC
B DQ16 UB A3 A4 CE DQ1
C DQ14 DQ15 A5 A6 DQ2 DQ3
D VSS DQ13 NC A7 DQ4 VDD
E VDD DQ12 NC NC DQ5 VSS
F DQ11 DQ10 A8 A9 DQ7 DQ6
G DQ9 NC A10 A11 WE DQ8
H NC A12 A13 A14 A15 NC

6mm x 8mm, 0.75mm Bump Pitch

Top View

Rev: 1.06 6/2000 1/15 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. M

TSOP-II 64K x 16 Pin Configuration

GS71116TP/J/U

CE
DQ1
DQ2
DQ3
DQ4
VDD

VSS

DQ5
DQ6
DQ7
DQ8

WE
A15

A14

A13

A12

A4
A3
A2
A1
A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

16
17
18
19
20
21
22

Top view

44 pin

TSOP II

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

A5
A6
A7
OE
UB
LB
DQ16
DQ15
DQ14

DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC

27

A8

26

A9

25

A10

24

A11

23

NCNC

Block Diagram

A0

A15

CE

WE

OE

UB
LB

_____

_____

Address

Input

Buffer

Control

Row

Decoder

Memory Array

Column
Decoder

I/O Buffer

DQ1

DQ16

Rev: 1.06 6/2000 2/15 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71116TP/J/U

Truth Table

CE OE WE LB UB DQ1 to DQ8 DQ9 to DQ16 VDD Current

H X X X X Not Selected Not Selected ISB1, ISB2

L L Read Read

L L H

L X L

L H H X X High Z High Z
L X X H H High Z High Z

Note: X: “H” or “L”

L H Read High Z

H L High Z Read

L L Write Write
L H Write Not Write, High Z

H L Not Write, High Z Write

Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply Voltage VDD -0.5 to +4.6 V

Input Voltage VIN

Output Voltage VOUT

-0.5 to VDD+0.5
(≤ 4.6V max.)

-0.5 to VDD+0.5
(≤ 4.6V max.)

IDD

V

V

Allowable power dissipation PD 0.7 W

Storage temperature TSTG -55 to 150

Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

Rev: 1.06 6/2000 3/15 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

o

C

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

Supply Voltage for -12/15 VDD 3.0 3.3 3.6 V

Supply Voltage for -10 VDD 3.135 3.3 3.6 V

Input High Voltage VIH 2.0 - VDD+0.3 V

Input Low Voltage VIL -0.3 - 0.8 V

GS71116TP/J/U

Ambient Temperature,

Commercial Range

Ambient Temperature,

Industrial Range

Note:

1. Input overshoot voltage should be less than VDD+2V and not exceed 20ns.

2. Input undershoot voltage should be greater than -2V and not exceed 20ns.

TAc 0 - 70

TAI -40 - 85

Capacitance

Parameter Symbol Test Condition Max Unit

Input Capacitance CIN VIN=0V 5 pF

Output Capacitance COUT VOUT=0V 7 pF

Notes:

1. Tested at TA=25°C, f=1MHz

2. These parameters are sampled and are not 100% tested

DC I/O Pin Characteristics

Parameter Symbol Test Conditions Min Max

o

C

o

C

Input Leakage

Current

Output Leakage

Current

Output High Voltage VOH IOH = - 4mA 2.4

Output Low Voltage VOL ILO = + 4mA 0.4V

Rev: 1.06 6/2000 4/15 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

IIL VIN = 0 to VDD -1uA 1uA

ILO

Output High Z

VOUT = 0 to VDD

-1uA 1uA

Power Supply Currents

Parameter Symbol Test Conditions

CE ≤ VIL

Operating

Supply

Current

Standby

Current

IDD (max)

ISB1 (max)

All other inputs

≥ VIH or ≤ VIL

Min. cycle time

IOUT = 0 mA

CE ≥ VIH

All other inputs

≥ VIH or ≤VIL

Min. cycle time

GS71116TP/J/U

0 to 70°C -40 to 85°C

10ns 12ns 15ns 10ns 12ns 15ns

100mA 85mA 70mA 115mA 100mA 85mA

45mA 40mA 35mA 50mA 45mA 40mA

Standby

Current

ISB2 (max)

CE ≥ VDD - 0.2V

All other inputs

≥ VDD - 0.2V or ≤ 0.2V

10mA 15mA

Rev: 1.06 6/2000 5/15 © 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.