GSI GS71116AU-8I, GS71116AU-8, GS71116ATP-12I, GS71116ATP-12, GS71116ATP-10I Datasheet
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GS71116ATP/J/U
SOJ, TSOP, FP-BGA
64K x 16
Commercial Temp
Industrial Temp
1Mb Asynchronous SRAM
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 145/125/100/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J: 400 mil, 44-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
Description
The GS71116A is a high speed CMOS static RAM organized
as 65,536-words by 16-bits. Static design eliminates the need
for external clocks or timing strobes. Operating on a single
3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS71116A is available in a 6 mm x 8 mm
Fine Pitch BGA package, as well as in 400 mil SOJ and 400
mil TSOP Type-II packages.
Pin Descriptions
Symbol Description
0–A15
A
DQ
1–DQ16 Data input/output
CE
LB
UB
WE
OE
V
DD
V
SS
NC No connect
Address input
Chip enable input
Lower byte enable input
(DQ1 to DQ8)
Upper byte enable input
(DQ9 to DQ16)
Write enable input
Output enable input
+3.3 V power supply
Ground
7, 8, 10, 12 ns
3.3 V V
Center VDD and V
SOJ 64K x 16-Pin Configuration
A
A
A
A
A
CE
DQ
DQ
DQ
DQ
V
DD
V
SS
DQ
DQ6
DQ7
DQ
WE
A
A
A
A
12
4
3
2
1
0
1
2
3
4
5
8
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Top view
44-pin
SOJ
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Package J
Fine Pitch BGA 64K x 16-Bump Configuration
123456
0
ALB
OE A
BDQ16UB A
CDQ14DQ15A
V
D
E
DQ13NC A7DQ
SS
V
DQ12NC NC DQ
DD
FDQ11DQ10A
GDQ9NC A
HNCA12A
1
A
3
A4CE DQ
5
A6DQ2DQ
8
A9DQ7DQ
10A11
13A14A15
WE DQ
A2NC
V
4
V
5
NC
A
A
A
OE
UB
LB
DQ
DQ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
NC
A
A
A
A
NCNC
DD
SS
DD
SS
5
6
7
16
15
14
13
SS
DD
12
11
10
9
8
9
10
11
1
3
6
8
6 mm x 8 mm, 0.75 mm Bump Pitch (Package U)
Rev: 1.04a 10/2002 1/15 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
TSOP-II 64K x 16-Pin Configuration
GS71116ATP/J/U
Top View
DQ
DQ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
WE
A
A14
A
A
CE
A
4
A
3
A
2
A
1
A
0
1
2
3
4
DD
SS
5
6
7
8
15
13
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Top view
44-pin
TSOP II
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
A
A
OE
UB
LB
DQ
DQ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
NC
A
A
A
A
NCNC
5
6
7
16
15
14
13
SS
DD
12
11
10
9
8
9
10
11
Package TP
Block Diagram
A
A
CE
WE
OE
UB
LB
0
15
_____
_____
Address
Input
Buffer
Control
Row
Decoder
Memory Array
Column
Decoder
I/O Buffer
DQ
1
DQ
16
Rev: 1.04a 10/2002 2/15 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Truth Table
GS71116ATP/J/U
CE OE WE LB UB DQ1 to DQ
8
DQ9 to DQ
16
H X X X X Not Selected Not Selected ISB1, ISB
L L Read Read
LLH
L H Read High Z
H L High Z Read
LL Write Write
LXL
L H Write Not Write, High Z
H L Not Write, High Z Write
L H H X X High Z High Z
L X X H H High Z High Z
Note: X: “H” or “L”
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply Voltage V
DD
–0.5 to +4.6 V
VDD Current
2
I
DD
Input Voltage V
Output Voltage V
IN
OUT
–0.5 to V
(≤ 4.6 V max.)
–0.5 to V
(≤ 4.6 V max.)
DD
DD
+0.5
+0.5
V
V
Allowable power dissipation PD 0.7 W
Storage temperature T
STG –55 to 150
o
C
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Rev: 1.04a 10/2002 3/15 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
GS71116ATP/J/U
Supply Voltage for -7/-8/-10/-12
Input High Voltage V
Input Low Voltage V
Ambient Temperature,
Commercial Range
Ambient Temperature,
Industrial Range
V
DD
IH
IL
T
Ac
I
T
A
3.0 3.3 3.6 V
2.0 —
–0.3 — 0.8 V
0 — 70
–40 — 85
Notes:
1. Input overshoot voltage should be less than V
+2 V and not exceed 20 ns.
DD
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Capacitance
Parameter Symbol Test Condition Max Unit
Input Capacitance C
Output Capacitance C
IN
OUT
Notes:
1. Tested at T
A
= 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
IN
V
= 0 V 5 pF
OUT
V
= 0 V 7 pF
V
DD
+0.3
V
o
C
o
C
DC I/O Pin Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current I
Output Leakage
Current
Output High Voltage V
Output Low Voltage V
IL
LO
I
OH
OL ILO = +4 mA 0.4V
Rev: 1.04a 10/2002 4/15 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
VIN = 0 to V
DD
Output High Z
V
OUT = 0 to V
OH
I
DD
= –4 mA 2.4
–1 uA 1uA
–1 uA 1uA
Power Supply Currents
Parameter Symbol Test Conditions
CE ≤ V
Operating
Supply
Current
Standby
Current
IDD
I
SB1
All other inputs
≥ VIH
or ≤ V
Min. cycle time
IOUT
= 0 mA
CE ≥ V
All other inputs
≥ V
IH
or ≤V
Min. cycle time
GS71116ATP/J/U
0 to 70°C –40 to 85°C
7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns
IL
IL
IH
IL
145 mA 125 mA 100 mA 85 mA 150 mA 130 mA 105 mA 90 mA
25 mA 20 mA 20 mA 15 mA 30 mA 25 mA 25 mA 20 mA
Standby
Current
I
SB2
CE ≥ VDD – 0.2 V
All other inputs
≥ V
DD – 0.2 V or ≤ 0.2 V
2 mA 5 mA
Rev: 1.04a 10/2002 5/15 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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