GSI GS71108AU-8I, GS71108AU-8, GS71108AU-7I, GS71108AU-7, GS71108AU-12I Datasheet

Rev: 1.04a 10/2002 1/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71108ATP/J/SJ/U

128K x 8

1Mb Asynchronous SRAM

7, 8, 10, 12 ns

3.3 V V

DD

Center VDD and V

SS

SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp

Features

• Fast access time: 7, 8, 10, 12 ns

• CMOS low power operation: 140/120/95/80 mA at minimum
cycle time

• Single 3.3 V power supply

• All inputs and outputs are TTL-compatible

• Fully static operation

• Industrial Temperature Option: –40° to 85°C

• Package line up

J: 400 mil, 32-pin SOJ package
TP: 400 mil, 32-pin TSOP Type II package
SJ: 300 mil, 32-pin SOJ package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package

Description

The GS71108A is a high speed CMOS Static RAM organized
as 131,072 words by 8 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL­compatible. The GS71108A is available in a 6 mm x 8 mm
Fine Pitch BGA package, as well as in 300 mil and 400 mil
SOJ and 400 mil TSOP Type-II packages.

Pin Descriptions

SOJ & TSOP-II 128K x 8-Pin Configuration

Packages J, TP, and SJ

Fine Pitch BGA 128K x 8-Bump Configuration

Package U

6 mm x 8 mm, 0.75 mm Bump Pitch

Top View

Symbol Description

A0–A16 Address input

DQ

1–DQ8 Data input/output

CE

Chip enable input

WE

Write enable input

OE

Output enable input

V

DD

+3.3 V power supply

V

SS

Ground

NC No connect

123456

ANCOEA

2

A

6

A7NC

BDQ1NC A

1

A5CE DQ

8

CDQ2NC A

0

A4NC DQ

7

D

V

SS

NC NC A3NC

V

DD

E

V

DD

NC NC NC NC

V

SS

FDQ3NC A

14A11

DQ5DQ

6

GDQ4NC A

15A12

WE A

8

HNCA10A

16A13A9

NC

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

3

A

2

A

1

A

0

CE

DQ

1

DQ

2

V

DD

V

SS

DQ

3

DQ

4

WE

A

16

A

15

A

14

A

13

A

4

A5

A6

A

7

OE

DQ

8

DQ

7

V

SS

V

DD

DQ6

DQ

5

A

8

A

9

A

10

A

11

A

12

32-pin

400 mil SOJ

300 mil SOJ

&

&

400 mil TSOP II

Rev: 1.04a 10/2002 2/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71108ATP/J/SJ/U

Note: X: “H” or “L”

Truth Table

CE OE WE DQ1 to DQ

8

VDD Current

H X X Not Selected ISB1, ISB

2

L L H Read

I

DD

LX L Write

LH H High Z

Memory Array

Row

Decoder

Column
Decoder

Address

Input

Buffer

Control

I/O Buffer

A

0

CE

WE

OE

DQ

1

A

16

Block Diagram

DQ

8

Rev: 1.04a 10/2002 3/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71108ATP/J/SJ/U

Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec­ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.

Notes:

1. Input overshoot voltage should be less than V

DD

+2 V and not exceed 20 ns.

2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.

Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply Voltage V

DD

–0.5 to +4.6 V

Input Voltage V

IN

–0.5 to V

DD

+0.5

(≤ 4.6 V max.)

V

Output Voltage V

OUT

–0.5 to V

DD

+0.5

(≤ 4.6 V max.)

V

Allowable power dissipation PD 0.7 W

Storage temperature T

STG

–55 to 150

o

C

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit

Supply Voltage for -7/-8/-10/-12

V

DD

3.0 3.3 3.6 V

Input High Voltage V

IH

2.0 —

V

DD

+0.3

V

Input Low Voltage V

IL

–0.3 — 0.8 V

Ambient Temperature,

Commercial Range

T

Ac 0 — 70

o

C

Ambient Temperature,

Industrial Range

T

A

I

–40 — 85

o

C

Rev: 1.04a 10/2002 4/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71108ATP/J/SJ/U

Notes:

1. Tested at T

A

= 25°C, f = 1 MHz

2. These parameters are sampled and are not 100% tested.

Capacitance

Parameter Symbol Test Condition Max Unit

Input Capacitance C

IN

V

IN

= 0 V 5 pF

Output Capacitance C

OUT VOUT = 0 V 7 pF

DC I/O Pin Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage

Current

I

IL

V

IN

= 0 to V

DD

–1 uA 1 uA

Output Leakage

Current

I

LO

Output High Z

V

OUT

= 0 to V

DD

–1 uA 1 uA

Output High Voltage V

OH IOH = –4 mA 2.4 —

Output Low Voltage V

OL

I

LO

= +4 mA — 0.4 V

Power Supply Currents

Parameter Symbol Test Conditions

0 to 70°C –40 to 85°C

7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns

Operating

Supply

Current

I

DD

CE ≤ VIL

All other inputs

≥ V

IH or ≤ VIL

Min. cycle time

I

OUT = 0 mA

140 mA 120 mA 95 mA 80 mA 145 mA 125 mA 100 mA 85 mA

Standby

Current

I

SB1

CE ≥ VIH

All other inputs

≥ V

IH or ≤VIL

Min. cycle time

25 mA 20 mA 20 mA 15 mA 30 mA 25 mA 25 mA 20 mA

Standby

Current

I

SB2

CE ≥ VDD – 0.2 V

All other inputs

≥ V

DD – 0.2 V or ≤ 0.2 V

2 mA 5 mA

Rev: 1.04a 10/2002 5/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71108ATP/J/SJ/U

AC Test Conditions

AC Characteristics

* These parameters are sampled and are not 100% tested

Read Cycle

Parameter Symbol

-7

-8

-10 -12
Unit

Min Max Min Max Min Max Min Max

Read cycle time t

RC 7 — 8 — 10 — 12 — ns

Address access time t

AA — 7 — 8 — 10 — 12 ns

Chip enable access time (CE

)tAC— 7 — 8 — 10 — 12 ns

Output enable to output valid (OE

)tOE —3—3.5—4—5ns

Output hold from address change t

OH

3—3—3—3—ns

Chip enable to output in low Z (CE

)tLZ*3—3—3—3—ns

Output enable to output in low Z (OE

)tOLZ*0 — 0 — 0—0—ns

Chip disable to output in High Z (CE

)t

HZ

*—3.5— 4 —5—6ns

Output disable to output in High Z (OE

)tOHZ*— 3 —3.5— 4 — 5ns

DQ

VT = 1.4 V

50Ω

30pF

1

DQ

3.3 V

Output Load 1

Output Load 2

589Ω

434Ω

5pF

1

Note:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.

3. Output load 2 for t

LZ, tHZ, tOLZ and tOHZ

Parameter Conditions

Input high level VIH = 2.4 V

Input low level V

IL

= 0.4 V

Input rise time tr = 1 V/ns

Input fall time tf = 1 V/ns

Input reference level 1.4 V

Output reference level 1.4 V

Output load Fig. 1& 2

Rev: 1.04a 10/2002 6/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71108ATP/J/SJ/U

Read Cycle 1: CE = OE = VIL, WE = V

IH

Read Cycle 2: WE = V

IH

tAA

t

OH

t

RC

Address

Data Out Previous Data Data valid

t

AA

t

RC

Address

t

AC

t

LZ

t

OE

t

OLZ

CE

OE

Data Out

tHZ

t

OHZ

D

ATA VALID

High impedance

Rev: 1.04a 10/2002 7/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71108ATP/J/SJ/U

* These parameters are sampled and are not 100% tested

Write Cycle

Parameter Symbol

-7 -8 -10 -12
Unit

Min Max Min Max Min Max Min Max

Write cycle time tWC 7 — 8 — 10 — 12 — ns

Address valid to end of write tAW 5 — 5.5 — 7 — 8 — ns

Chip enable to end of write tCW 5 — 5.5 — 7 — 8 — ns

Data set up time tDW 3 — 4 — 5 — 6 — ns

Data hold time tDH 0 — 0 — 0 — 0 — ns

Write pulse width tWP 5 — 5.5 — 7 — 8 — ns

Address set up time tAS 0 — 0 — 0 — 0 — ns

Write recovery time (WE

) tWR0—0—0—0—ns

Write recovery time (CE

) tWR10—0—0—0—ns

Output Low Z from end of write

tWLZ

*

3—3—3—3—ns

Write to output in High Z

tWHZ

*

—3—3.5—4—5 ns

Rev: 1.04a 10/2002 8/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71108ATP/J/SJ/U

Write Cycle 1: WE control

Write Cycle 2: CE control

t

WC

Address

CE

WE

Data In

OE

Data Out

tAW

tCW

t

AS

t

WP

tWR

t

DW

t

DH

tWLZtWHZ

D

ATA VALID

H

IGH IMPEDANCE

tWC

Address

CE

WE

Data In

OE

Data Out

t

AW

tWP

tAS tCW

t

WR1

t

DW

t

DH

D

ATA VALID

H

IGH IMPEDANCE

Rev: 1.04a 10/2002 9/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71108ATP/J/SJ/U

32-Pin SOJ, 400 mil

1

e

B1

D

A1

A2

y

E

H

E

Q

c

L

G

E

Detail A

A

B

A

Notes:

1. Dimension D& E do not include interlead flash.

2. Dimension B1 does not include dambar protrusion/intrusion.

3. Controlling dimension: inches

Symbol

Dimension in inch Dimension in mm

min nom max min nom max

A — — 0.146 — — 3.70

A1 0.026 — — 0.66 — —

A2 0.105 0.110 0.115 2.67 2.80 2.92

B 0.013 0.017 0.021 0.33 0.43 0.53

B1 0.024 0.028 0.032 0.61 0.71 0.81

c 0.006 0.008 0.012 0.15 0.20 0.30

D 0.820 0.824 0.829 20.83 20.93 21.06

E 0.395 0.400 0.405 10.04 10.16 10.28

e — 0.05 — — 1.27 —

H

E

0.430 0.435 0.440 10.93 11.05 11.17

G

E 0.354 0.366 0.378 9.00 9.30 9.60

L 0.082 — — 2.08 — —

y — — 0.004 — — 0.10

Q

0

o

—

10

o

0

o

—

10

o

Rev: 1.04a 10/2002 10/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71108ATP/J/SJ/U

32-Pin TSOP-II, 400mil

D

1

32

e

b

Q

A

A1

A2

y

c

Detail A

E1

E

L

A

ZD

L1

Notes:

1.Dimension D includes mold flash, protrusions or gate burrs.

2. Dimension E does not include interlead flash

3. Controlling dimension: mm

Symbol

Dimension in inch Dimension in mm

min nom max min nom max

A 0.039 — 0.05 — — 1.27

A1 0.002 — 0.006 0.01 — 0.15

A2 0.037 0.040 0.045 0.90 1.02 1.14

b 0.012 0.016 0.018 0.30 0.40 0.45

c 0.0047 0.0051 0.0062 0.12 0.13 0.16

D 0.820 0.825 0.830 20.82 20.95 21.08

ZD — 0.037 — — 0.95 —

E 0.455 0.463 0.471 11.56 11.76 11.96

E1 0.395 0.400 0.405 10.03 10.16 10.29

e — 0.05 — — 1.27 —

L 0.017 0.020 0.023 0.40 0.50 0.60

L1 0.024 0.031 0.039 0.60 0.80 1.00

y 0.00 — 0.003 0.00 — 0.76

Q

0

o

—

5

o

0

o

—

5

o

Rev: 1.04a 10/2002 11/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71108ATP/J/SJ/U

6 mm x 8 mm Fine Pitch BGA

C

5.25

0.75(typ).

3.75

pin A1 index

654321

A

B

D

E

F

G

H

0.22 ± 0.05

1.20(max)

0.36(typ)

Ball Dia. 0.35

Pitch 0.75

D

0.10

pin A1 index

Bottom View Top View

6.00 ± 0.10

8.00 ± 0.10

units: mm

Rev: 1.04a 10/2002 12/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71108ATP/J/SJ/U

Ordering Information

Part Number

*

Package Access Time Temp. Range Status

GS71108ATP-7 400 mil TSOP-II 7 ns Commercial

GS71108ATP-8 400 mil TSOP-II 8 ns Commercial

GS71108ATP-10 400 mil TSOP-II 10 ns Commercial

GS71108ATP-12 400 mil TSOP-II 12 ns Commercial

GS71108ATP-7I 400 mil TSOP-II 7 ns Industrial

GS71108ATP-8I 400 mil TSOP-II 8 ns Industrial

GS71108ATP-10I 400 mil TSOP-II 10 ns Industrial

GS71108ATP-12I 400 mil TSOP-II 12 ns Industrial

GS71108ASJ-7 300 mil SOJ 7 ns Commercial

GS71108ASJ-8 300 mil SOJ 8 ns Commercial

GS71108ASJ-10 300 mil SOJ 10 ns Commercial

GS71108ASJ-12 300 mil SOJ 12 ns Commercial

GS71108ASJ-7I 300 mil SOJ 7 ns Industrial

GS71108ASJ-8I 300 mil SOJ 8 ns Industrial

GS71108ASJ-10I 300 mil SOJ 10 ns Industrial

GS71108ASJ-12I 300 mil SOJ 12 ns Industrial

GS71108AJ-7 400 mil SOJ 7 ns Commercial

GS71108AJ-8 400 mil SOJ 8 ns Commercial

GS71108AJ-10 400 mil SOJ 10 ns Commercial

GS71108AJ-12 400 mil SOJ 12 ns Commercial

GS71108AJ-7I 400 mil SOJ 7 ns Industrial

GS71108AJ-8I 400 mil SOJ 8 ns Industrial

GS71108AJ-10I 400 mil SOJ 10 ns Industrial

GS71108AJ-12I 400 mil SOJ 12 ns Industrial

Rev: 1.04a 10/2002 13/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71108ATP/J/SJ/U

*

Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example:

GS71108ATP-8T

GS71108AU-7 6 mm x 8 mm Fine Pitch BGA 7 ns Commercial

GS71108AU-8 6 mm x 8 mm Fine Pitch BGA 8 ns Commercial

GS71108AU-10 6 mm x 8 mm Fine Pitch BGA 10 ns Commercial

GS71108AU-12 6 mm x 8 mm Fine Pitch BGA 12 ns Commercial

GS71108AU-7I 6 mm x 8 mm Fine Pitch BGA 7 ns Industrial

GS71108AU-8I 6 mm x 8 mm Fine Pitch BGA 8 ns Industrial

GS71108AU-10I 6 mm x 8 mm Fine Pitch BGA 10 ns Industrial

GS71108AU-12I 6 mm x 8 mm Fine Pitch BGA 12 ns Industrial

Ordering Information

Part Number

*

Package Access Time Temp. Range Status

Rev: 1.04a 10/2002 14/14 © 2001, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS71108ATP/J/SJ/U

1Mb Asynchronous Datasheet Revision History

Rev. Code: Old;

New

Types of Changes
Format or Content

Page #/Revisions/Reason

71108A_r1

• Creation of new datasheet

71108A_r1; 71108A_r1_01 Content

• Added 6 ns speed bin to entire document

71108A_r1_01; 71108A _r1_02 Content

• Updated all power numbers

• Changed 6 mm x 10 mm package designator from U to X

71108A_r1_02; 71108A _r1_03 Content

• Updated Recommended Operating Conditions table on page 3

• Updated Power Supply Currents table

• Changed FPBGA package from 6 x 10 to 6 x 8 (package U)

71108A_r1_03; 71108A _r1_04 Content

• Removed 6 ns speed bin from entire document

• Added 7 ns speed bin to entire document