GSI GS71108AU-8I, GS71108AU-8, GS71108AU-7I, GS71108AU-7, GS71108AU-12I Datasheet
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Rev: 1.04a 10/2002 1/14 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
128K x 8
1Mb Asynchronous SRAM
7, 8, 10, 12 ns
3.3 V V
DD
Center VDD and V
SS
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 140/120/95/80 mA at minimum
cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J: 400 mil, 32-pin SOJ package
TP: 400 mil, 32-pin TSOP Type II package
SJ: 300 mil, 32-pin SOJ package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
Description
The GS71108A is a high speed CMOS Static RAM organized
as 131,072 words by 8 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS71108A is available in a 6 mm x 8 mm
Fine Pitch BGA package, as well as in 300 mil and 400 mil
SOJ and 400 mil TSOP Type-II packages.
Pin Descriptions
SOJ & TSOP-II 128K x 8-Pin Configuration
Packages J, TP, and SJ
Fine Pitch BGA 128K x 8-Bump Configuration
Package U
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Symbol Description
A0–A16 Address input
DQ
1–DQ8 Data input/output
CE
Chip enable input
WE
Write enable input
OE
Output enable input
V
DD
+3.3 V power supply
V
SS
Ground
NC No connect
123456
ANCOEA
2
A
6
A7NC
BDQ1NC A
1
A5CE DQ
8
CDQ2NC A
0
A4NC DQ
7
D
V
SS
NC NC A3NC
V
DD
E
V
DD
NC NC NC NC
V
SS
FDQ3NC A
14A11
DQ5DQ
6
GDQ4NC A
15A12
WE A
8
HNCA10A
16A13A9
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
3
A
2
A
1
A
0
CE
DQ
1
DQ
2
V
DD
V
SS
DQ
3
DQ
4
WE
A
16
A
15
A
14
A
13
A
4
A5
A6
A
7
OE
DQ
8
DQ
7
V
SS
V
DD
DQ6
DQ
5
A
8
A
9
A
10
A
11
A
12
32-pin
400 mil SOJ
300 mil SOJ
&
&
400 mil TSOP II
Rev: 1.04a 10/2002 2/14 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Note: X: “H” or “L”
Truth Table
CE OE WE DQ1 to DQ
8
VDD Current
H X X Not Selected ISB1, ISB
2
L L H Read
I
DD
LX L Write
LH H High Z
Memory Array
Row
Decoder
Column
Decoder
Address
Input
Buffer
Control
I/O Buffer
A
0
CE
WE
OE
DQ
1
A
16
Block Diagram
DQ
8
Rev: 1.04a 10/2002 3/14 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Notes:
1. Input overshoot voltage should be less than V
DD
+2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply Voltage V
DD
–0.5 to +4.6 V
Input Voltage V
IN
–0.5 to V
DD
+0.5
(≤ 4.6 V max.)
V
Output Voltage V
OUT
–0.5 to V
DD
+0.5
(≤ 4.6 V max.)
V
Allowable power dissipation PD 0.7 W
Storage temperature T
STG
–55 to 150
o
C
Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply Voltage for -7/-8/-10/-12
V
DD
3.0 3.3 3.6 V
Input High Voltage V
IH
2.0 —
V
DD
+0.3
V
Input Low Voltage V
IL
–0.3 — 0.8 V
Ambient Temperature,
Commercial Range
T
Ac 0 — 70
o
C
Ambient Temperature,
Industrial Range
T
A
I
–40 — 85
o
C
Rev: 1.04a 10/2002 4/14 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Notes:
1. Tested at T
A
= 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
Capacitance
Parameter Symbol Test Condition Max Unit
Input Capacitance C
IN
V
IN
= 0 V 5 pF
Output Capacitance C
OUT VOUT = 0 V 7 pF
DC I/O Pin Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage
Current
I
IL
V
IN
= 0 to V
DD
–1 uA 1 uA
Output Leakage
Current
I
LO
Output High Z
V
OUT
= 0 to V
DD
–1 uA 1 uA
Output High Voltage V
OH IOH = –4 mA 2.4 —
Output Low Voltage V
OL
I
LO
= +4 mA — 0.4 V
Power Supply Currents
Parameter Symbol Test Conditions
0 to 70°C –40 to 85°C
7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns
Operating
Supply
Current
I
DD
CE ≤ VIL
All other inputs
≥ V
IH or ≤ VIL
Min. cycle time
I
OUT = 0 mA
140 mA 120 mA 95 mA 80 mA 145 mA 125 mA 100 mA 85 mA
Standby
Current
I
SB1
CE ≥ VIH
All other inputs
≥ V
IH or ≤VIL
Min. cycle time
25 mA 20 mA 20 mA 15 mA 30 mA 25 mA 25 mA 20 mA
Standby
Current
I
SB2
CE ≥ VDD – 0.2 V
All other inputs
≥ V
DD – 0.2 V or ≤ 0.2 V
2 mA 5 mA
Rev: 1.04a 10/2002 5/14 © 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
AC Test Conditions
AC Characteristics
* These parameters are sampled and are not 100% tested
Read Cycle
Parameter Symbol
-7
-8
-10 -12
Unit
Min Max Min Max Min Max Min Max
Read cycle time t
RC 7 — 8 — 10 — 12 — ns
Address access time t
AA — 7 — 8 — 10 — 12 ns
Chip enable access time (CE
)tAC— 7 — 8 — 10 — 12 ns
Output enable to output valid (OE
)tOE —3—3.5—4—5ns
Output hold from address change t
OH
3—3—3—3—ns
Chip enable to output in low Z (CE
)tLZ*3—3—3—3—ns
Output enable to output in low Z (OE
)tOLZ*0 — 0 — 0—0—ns
Chip disable to output in High Z (CE
)t
HZ
*—3.5— 4 —5—6ns
Output disable to output in High Z (OE
)tOHZ*— 3 —3.5— 4 — 5ns
DQ
VT = 1.4 V
50Ω
30pF
1
DQ
3.3 V
Output Load 1
Output Load 2
589Ω
434Ω
5pF
1
Note:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for t
LZ, tHZ, tOLZ and tOHZ
Parameter Conditions
Input high level VIH = 2.4 V
Input low level V
IL
= 0.4 V
Input rise time tr = 1 V/ns
Input fall time tf = 1 V/ns
Input reference level 1.4 V
Output reference level 1.4 V
Output load Fig. 1& 2
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