GSI GS71024U-8I, GS71024U-8, GS71024U-15I, GS71024U-15, GS71024U-12I Datasheet
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GS71024T/U
TQFP, FPBGA
64K x 24
Commercial Temp
Industrial Temp
1.5Mb Asynchronous SRAM
Features
• Fast access time: 8, 10, 12, 15 ns
• CMOS low power operation: 190/160/130/110 mA at
minimum cycle time.
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40 to 85°C
• Package
T: 100-pin TQFP package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array
Description
The GS71024 is a high speed CMOS static RAM organized as
65,536 words by 24 bits. Static design eliminates the need for
external clocks or timing strobes. The GS71024 operates on a
single 3.3 V power supply, and all inputs and outputs are TTLcompatible. The GS71024 is available in a 6 mm x 8 mm Fine
Pitch BGA package, as well as in a 100-pin TQFP package.
Fine Pitch BGA Bump Configuration
1 2 3 4 5 6
A
DQ A3 A2 A1 A0 DQ
B
DQ DQ CE2 WE DQ DQ
C
DQ DQ CE1 OE DQ DQ
V
D
E
F
G
H
6 mm x 8 mm, 0.75 mm Bump Pitch
DQ A5 A4 DQ
SS
V
DQ A7 A6 DQ
DD
DQ DQ A9 A8 DQ DQ
DQ DQ A11 A10 DQ DQ
DQ A15 A14 A13 A12 DQ
Top View
8, 10, 12, 15 ns
3.3 V V
V
DD
V
SS
DD
Pin Descriptions
Symbol Description Symbol Description
A0 to A15 Address input DQ1 to DQ24 Data input/output
X/Y Vector Input V/S Address Multiplexer Control
WE Write enable input OE Output enable input
CE1, CE2 Chip enable input — —
V
DD
Block Diagram
A14
A15
X/Y
V/S
CE1
CE2
WE
OE
+3.3 V power supply
A0
Address
Input
0
Q
1
Control
Row
Decoder
V
SS
Memory Array
1024 x 1536
Column
Decoder
I/O Buffer
DQ1 DQ24
Ground
Rev: 1.03 11/2000 1/13 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
100-Pin TQFP Pinout
GS71024T/U
DD
A14
CE2
CE1
A15
NC
NC
V/S
NC
X/Y
SS
V
V
NC
WE
OE
NC
NC
A0
A1
NC
NC
NC
NC
NC
NC
NC
DQ13
DQ14
DQ15
DQ16
V
SS
V
DD
DQ17
DQ18
NC
V
DD
NC
V
SS
DQ19
DQ20
V
DD
V
SS
DQ21
DQ22
DQ23
DQ24
NC
NC
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Top View
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
NC
NC
DQ12
DQ11
DQ10
DQ9
V
SS
V
DD
DQ8
DQ7
V
SS
NC
V
DD
NC
DQ6
DQ5
V
DD
V
SS
DQ4
DQ3
DQ2
DQ1
NC
NC
NC
NC
NC
SS
A9
NC
A11
A13
A12
A8
A10
NC
DD
NC
V
V
A7
A6
A5
A4
A3
NC
NC
NC
A2
Rev: 1.03 11/2000 2/13 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Truth Table
GS71024T/U
CE1 CE2 OE WE V/S Mode DQ0 to DQ23
H X X X X Not selected High Z
X L X X X Not selected High Z
L H L H H Read using X/Y Data Out
L H L H L Read using A15 Data Out
L H X L H Write using X/Y Data In
L H X L L Write using A15 Data In
L H H H X Output disable High Z
X: “H” or “L”
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Supply Voltage VDD –0.5 to +4.6 V
Input Voltage VIN
–0.5 to V
(≤ 4.6 V max.)
DD
+ 0.5
VDD Current
ISB1, ISB2
I
V
DD
Output Voltage VOUT
Allowable TQFP power dissipation PD 1 W
Allowable FPBGA power dissipation PD 1 W
Storage temperature
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
T
STG
–0.5 to V
(≤ 4.6 V max.)
–55 to 150
DD
+ 0.5
V
o
C
Rev: 1.03 11/2000 3/13 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Recommended Operating Conditions
Parameter Symbol Minimum Typical Maximum Unit
GS71024T/U
Supply Voltage for -10/12/15
Supply Voltage for -8
Input High Voltage
Input Low Voltage
Ambient Temperature,
Commercial Range
Ambient Temperature,
Industrial Range
V
DD
V
DD
V
IH
V
IL
T
Ac
T
Ai
3.0 3.3 3.6 V
3.135 3.3 3.6 V
2.0 —
–0.3 — 0.8 V
0 — 70
–40 — 85
Notes:
1. Input overshoot voltage should be less than V
+ 2 V and not exceed 20 ns.
DD
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Capacitance
Parameter Symbol Test Condition Maximum Unit
C
C
OUT
IN
Input Capacitance
I/O Capacitance
V
V
IN
OUT
= 0 V
= 0 V
V
+ 0.3
DD
5 pF
7 pF
V
o
C
o
C
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested
DC I/O Pin Characteristics
Parameter Symbol Test Conditions Minimum Maximum
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
I
IL
I
OL
V
OH
V
OL
Rev: 1.03 11/2000 4/13 © 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
V
= 0 to V
IN
Output High Z, V
to V
DD
I
= –4mA
OH
I
= +4mA
OL
DD
OUT
= 0
–1uA 1uA
–1uA 1uA
2.4 —
— 0.4 V
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