The Marvell® 88MW300/302 is a highly integrated,
low-power WLAN Microcontroller System-on-Chip (SoC)
solution designed for a broad array of smart devices for
Internet of Things (IoT), wearables, accessories,
Machine-to-Machine (M2M), home automation, and
Smart Energy applications.
A high degree of integration enables very low system
costs requiring only a single 3.3V power input, a
38.4 MHz crystal, and SPI Flash. The RF path needs
only a lowpass filter for antenna connection.
The SoC includes a full-featured W LAN subsystem
powered by proven and mature IEEE 802.11n/g/b
Marvell technology. The WLAN subsystem integrates a
WLAN MAC, baseband, and direct-conversion RF radio
with integrated PA, LNA, and transmit/receive switch. It
also integrates a CPU subsystem with integrated
memory to run Marvell WLAN firmware to handle real
time WLAN protocol processing to off-load many WLAN
functions from the main application CPU.
The 88MW300/302 application subsystem is powered by
an ARM Cortex-M4F CPU that operates up to 200 MHz.
The device supports an integrated 512 KB SRAM,
128 KB mask ROM, and a QSPI interface to external
Flash. An integrated Flash Controller with a 32 KB
SRAM cache enables eXecute In Place (XIP) support for
firmware from Flash.
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The SoC is designed for low-power operation and
includes several low-power states and fast wake-up
times. Multiple power domains and clocks can be
individually shut down to save power. The SoC also has
a high-efficiency internal PA that can be operated in
low-power mode to save power. The microcontroller and
WLAN subsystems can be placed into low-power states,
independently, supporting a variety of application use
cases. An internal DC-DC regulator provides the 1.8V
rail for the WLAN subsystem.
The SoC provides a full array of peripheral interfaces
including SSP/SPI/I
Purpose Timers and PWM, ADC, DAC, Analog
Comparator, and GPIOs. It also includes a hardware
cryptographic engine, RTC, and Watchdog Timer. The
88MW302 includes a high speed USB On-The-Go
(OTG) interface to enable USB audio, video, and other
applications.
A complete set of digital and analog interfaces enable
direct interfacing for I/O avoiding the need for external
chips. The application CPU can be used to support
custom application development avoiding the need for
another microcontroller or processor.
Figure 1 shows an overall block diagram of the device.
2
S (3x), UART (3x), I2C (2x), General
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Multiple low-power modes and fast wake-up times
Full-featured, single stream 802.11n/g/b WLAN
High-efficiency PA with a low-power (10 dB) mode
Cortex-M4F application CPU for applications with
Flash Controller with embedded 32 KB SRAM
sensor, door lock, door bell, garage door, security system
Integrated high efficiency buck DC-DC converter
Independent power domains
Brown-out detection
Integrated POR
Wake-up through dedicated GPIO, IRQ, and RTC
components for a full system operation
integrated 512 KB SRAM and 128 KB mask ROM
cache to support XIP from external SPI Flash
power-down
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Con
trol In
150
Product Overview
Chip Package
Chip Package
88MW300—68-pin QFN, 8x8 mm
• USB OTG not supported
• 35 GPIOs
• 2 GPTs
88MW302—88-pin QFN, 10x10 mm
• USB OTG supported
• 50 GPIOs
• 4 GPTs
Table 1:Package Feature Differences
Feature68-Pin88-Pin
GPIO35 total
GPIO_0 to GPIO_10
GPIO_16
GPIO_22 to GPIO_33
GPIO_39 to GPIO_49
USB 2.0
OTG
GPT24
1. All I/O features are muxed on GPIOs, except WLAN RF
--1
TX/RX, USB, reference clock, and reset functionality.
50 total
GPIO_0 to
GPIO_49
WLAN Rx Path
Direct conversion architecture eliminates need for
external SAW filter
On-chip gain selectable LNA with optimized noise
figure and power consumption
High dynamic range AGC function in receive mode
WLAN Tx Path
Integrated PA with power control
Optimized Tx gain distribution for linearity and noise
1
performance
WLAN Local Oscillator
Fractional-N for multiple reference clock support
Fine channel step
WLAN Encryption
WEP 64- and 128-bit encryption with hardware TKIP
802.11 data rates of 1 and 2 Mbps
802.11b data rates of 5.5 and 11 Mbps
802.11g data rates 6, 9, 12, 18, 24, 36, 48, and
54 Mbps for multimedia content transmission
802.11g/b performance enhancements
802.11n compliant with maximum data rates up to
72.2 Mbps (20 MHz channel)
baseband, direct conversion RF radio, encryption
Antenna diversity
CMOS and low-swing sine wave input clock
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Low-power with deep sleep and standby modes
Pre-regulated supplies
Integrated T/R switch, PA, and LNA
Optional 802.11n features
One Time Programmable (OTP) memory to
eliminate need for external EEPROM
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