Depop Circuitry Integrated
Output Power at 1% THD+N, VDD=5V
--1.8W/CH (typical) into a 4Ω Load
--1.2W/CH (typical) into a 8Ω Load
Maximum Output Power Clamping Circuitry
Integrated
Bridge-Tied Load (BTL)
Stereo Input MUX
Mute and Shutdown Control Available
Surface-Mount Power Package
24-Pin TSSOP-P & 24-Pin QFN Available
Applications
Stereo Power Amplifiers for Notebooks or
Desktop Computers
Multimedia Monitors
Stereo Power Amplifiers for Portable Audio
Systems
Pin Configuration
General Description
The G1432 is a stereo audio power amplifier in 24pin
TSSOP thermal pad package or 24pin QFN package.
It can drive 1.8W continuous RMS power into 4Ω load
per channel in Bridge-Tied Load (BTL) mode at 5V
supply voltage. Its THD is smaller than 1% under the
above operation condition. The G1432 can mute the
output when Mute is activated. For the low current
consumption applications, the SHDN mode is supported to disable the G1432 when it is idle. The current consumption can be further reduced to below
5µA.
The G1432 also supports two input paths, that means
two different gain loops can be set in the same PCB
and choosing either one by setting
1IN
/IN2 pin. It enhances the hardware designing flexibility. The G1432
also supports an extra function -- the maximum output
power clamping function to protect the speakers from
burned-out.
Maximum output power bandwidth BOM G = 1, THD 1% --- 20 --- kHz
Phase margin
Power supply ripple rejection PSRR f = 120Hz --- 75 --- dB
Mute attenuation --- 85 --- dB
Channel-to-channel output separation f = 1kHz --- 80 --- dB
1IN /IN2 input separation
Input impedance ZI --- 2 ---
Signal-to-noise ratio PO = 500mW, BTL --- 90 --- dB
Output noise voltage V
Note : Output power is measured at the output terminals of the IC at 1kHz.
(OUT)
THD = 1%, BTL, RL = 8Ω
THD = 10%, BTL, RL = 4Ω
THD = 10%, BTL, R
PO = 0.7W, BTL, RL = 4Ω
PO = 0.45W, BTL, RL = 8Ω
V
= 1V, RL = 10KΩ, G = 1
I
= 4Ω, Open Load
R
L
--- 80 --- dB
Output noise voltage --- 55 --- µV (rms)
n
= 8Ω
L
--- 0.8 ---
--- 0.5 ---
--- 1 ---
--- 0.6 ---
--- 270 ---
--- 100 ---
--- 10 ---
--- 60 ---
W
m%
°
MΩ
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Typical Characteristics
Table of Graphs
G1432
HD +N Total Harmonic Distortion Plus Noise
Output Noise Voltage
Supply Ripple Rejection Ratio
Vn
Crosstalk
Closed loop Response
IDD Supply Current
PO Output Power
PD Power Dissipation
Total Ha rm oni c Distortion Plus
Noise vs Output Power
10
5
2
1
1kHz
0.5
%
0.2
0.1
20 Hz
0.05
0.02
0.01
3m35m10 m 20m50m 100m 200m500 m12
20kHz
W
Figure 1Figure 2
VDD=5V
RL= 3
Ω
BTL
FIGURE
s Output Power 1,3,6,9,10,13,16
s Frequency
,4,5,7,8,11,12,14,15
s Frequency 16,17
s Frequency 18,19
s Frequency
s Frequency
s Supply Voltage
s Supply Voltage
s Load Resistance
s Output Power
0,21
2,23
4
5
6
7,28
Total Ha rm oni c Distortion Plus
Noise vs Output Fre qu e ncy
10
5
2
1
0.5
%
0.2
0.1
0.05
0.02
0.01
2020k501002 005 001k2 k5 k10 k
Po =1 .5 W
Po =1 .8 W
Hz
VDD=5V
RL= 3
Ω
BTL
v=-2V/V
10
5
2
1
0.5
%
0.2
0.1
0.05
0.02
0.01
3m35m10 m 20m50m 100m 200m500 m12
Ver: 1.1
Jun 21, 2006
Total Ha rm oni c Distortion Plus
Noise vs Output Power
20kHz
1kHz
20 Hz
VDD=5V
RL= 4
Ω
BTL
W
Figure 3Figure 4
4
Total Ha rm oni c Distortion Plus
Noise vs Output Fre q uency
10
5
2
1
0.5
%
0.2
0.1
0.05
0.02
0.01
2020k5010 02 005 001k2 k5 k1 0k
v=-2V/V
v=-1V/V
Hz
v=-4V/V
VDD=5V
RL= 4
Ω
BTL
Po =1 . 5 W
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G1432
Total Harmonic Distortion Plus
Noise vs Output Frequency
10
V DD=5V
5
RL= 4
Ω
BTL
2
v=-2V/V
1
0.5
%
0.2
0.1
0.05
0.02
0.01
2020k50100 2 005 001k2k5k10k
Po=0.25W
Hz
Figure 5Figure 6
Total Harmonic Distortion Plus
Noise vs Output Frequency
10
5
VDD=5V
RL= 8
Ω
2
BTL
v=-2V/V
1
0.5
%
0.2
0.1
0.05
0.02
0.01
2020k50100 2 005 001k2k5k10k
Po=0.25W
Hz
Figure 7
Po =1 . 5W
Po=0.75W
Po =1 W
Po =0 . 5W
Total Ha rm o ni c Distortion Pl us
Noi se vs Outp u t Power
10
5
2
1
0.5
%
0.2
0.1
0.05
0.02
0.01
3m35m 10m20m50m 1 00m 200m500 m12
20kHz
1kHz
20Hz
VDD=5V
RL= 8
BTL
W
Ω
v=-2V/V
Total Harmonic Distortion Plus
Noise vs Output Frequency
10
5
VDD=5V
RL= 8
2
1
0.5
%
0.2
0.1
0.05
0.02
0.01
Ω
BTL
Po =1 W
v=-2V/V
2020k50100 2 005 001k2 k5k10 k
Hz
Figure 8
v=-4V/V
v=-1V/V
Total Harmonic Distortion Plus
Noise vs Output Power
10
5
2
1
0.5
%
0.2
0.1
VDD=3.3V
0.05
RL= 3
Ω
BTL
0.02
0.01
1m12m5m 1 0m 20 m50 m 10 0m 200 m500 m
20kHz
1kHz
20Hz
W
%
Total Harmonic Distortion Plus
Noise vs Output Power
10
5
2
1
0.5
0.2
0.1
VDD=3.3V
RL= 4
0.05
BTL
0.02
0.01
1m12m5m 1 0m 20 m50 m 10 0m 2 00 m500 m
1kHz
Ω
20kHz
20Hz
W
Figure 9Figure 10
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G1432
Total Ha rm oni c Distortion Plus
Noise vs Output Frequency
10
5
VDD=3.3V
RL= 4
Ω
2
BTL
1
Po=0.65W
0.5
%
0.2
0.1
0.05
0.02
0.01
2020k50100 2 005 001k2k5k10 k
v=-2V/V
Hz
Figure 11
v=-4V/V
%
v=-1V/V
Total Harmonic Distortion Plus
Noise vs Output Frequency
10
VDD=3.3V
5
RL= 4
Ω
BTL
2
v=-2V/VPo= 0. 7 W
1
0.5
0.2
0.1
0.05
0.02
0.01
2020k50100 2 005 001k2k5k10 k
Po =0 . 1 W
Po =0 .3 5 W
Hz
Figure 12
Total Ha rm oni c Distortion Plus
Noise vs Output Power
10
5
2
1
0.5
%
0.2
0.1
0.05
0.02
0.01
1m12m5m 1 0m 20 m50m 10 0m 2 00 m500 m
20kHz
1kHz
20Hz
VDD=3.3V
RL= 8
BTL
W
Figure 13Figure 14
Total Ha rm onic Distortion Plus
Noise vs Output Frequency
10
VDD=3.3V
5
RL= 8
Ω
2
BTL
v=-2V/V
1
0.5
%
0.2
0.1
0.05
0.02
0.01
2020k50100 2 005 001k2k5k10 k
Po =0 .1 W
Po =0 .4 W
Hz
Ω
Po =0 . 25 W
Total Harmonic Distortion Plus
Noise vs Output Frequency
10
5
V DD=3. 3V
RL= 8
2
1
0.5
%
0.2
0.1
0.05
0.02
0.01
2020k50100 2 005 001k2 k5 k10k
Ω
BTL
Po =0 . 4W
v=-2V/V
Hz
Output Noise Voltage
vs Fre que ncy
100u
90u
80u
70u
60u
50u
40u
V
30u
20u
VDD=5V
RL= 4
Ω
10u
2020k50100 2 0050 01k2k5 k10k
BW=22Hz to 22kHz
- Weighted Filter
Hz
v=-4V/V
v=-1V/V
Figure 16
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Figure 15
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G1432
Output Noise Voltage
vs Frequency
100u
90u
80u
70u
60u
50u
40u
V
30u
BW=22Hz to 22kHz
- Weighted Filter
20u
VDD=3.3V
RL=4
Ω
10u
2020k501002005001k2k5k10k
Hz
+0
T
-10
-20
-30
-40
-50
d
-60
B
-70
-80
-90
-100
-110
-120
2020k501002005001 k2k5k1 0k
Figure 17
Supply Ripple Rejection
Ratio vs Frequency
VDD=5V
RL= 4
Ω
CB= 4.7µF
Hz
Figure 18
Supply Ripple Rejection
Ratio vs Freque ncy
+0
T
-10
VDD=5V
-20
RL= 4
-30
-40
-50
d
-60
B
-70
-80
-90
-100
-110
-120
2020k501002005001k2 k5k10k
Ω
CB= 4.7µF
Hz
Figure 19
-20
-25
-30
-35
-40
-45
-50
-55
d
-60
B
-65
-70
-75
-80
-85
-90
-95
-100
2020k5010 0 20 050 01k2k5k10 k
Crosstal k vs Fre q u ency
VDD=5V
Po =1 .5 W
RL=4
Ω
BTL
L to R
R to L
Figure 20
Hz
Closed Loop Response
Figure 22
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-20
-25
-30
-35
-40
-45
-50
-55
d
-60
B
-65
-70
-75
-80
-85
-90
-95
-100
2020k501002005001k2 k5k10 k
Ver: 1.1
Jun 21, 2006
Crosstal k vs Frequency
VDD=3.3V
Po =0 . 7 5W
RL= 4
Ω
BTL
L to R
R to L
Figure 21
Hz
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G1432
Closed Loop ResponseSupply Current vs Supply Vol tage
10
9
Stereo BTL
Supply Voltage (V )
Figure 23
8
7
6
5
4
Supply Current( mA
3
2
1
0
3456
Figure 24
Output Power vs Supply Voltage
2.5
THD+N=1%
BTL
2
Each Channel
1.5
RL= 3
Ω
1
Po-Output Power (W
0.5
0
2.53.54.55.56.5
Supply Voltage (V )
RL= 8
Ω
RL= 4
Figure 25
Pow er Dissipation vs Output Powe r
1.8
1.6
1.4
1.2
1
0.8
0.6
Power Dissipation(W)
0.4
0.2
0
00.511.522.5
RL= 8
Po-Output Pow er(W)
Ω
VDD=5V
BTL
Each Channel
Figure 27
RL= 3
RL= 4
Output P ower vs Load Resistance
2
1.8
1.6
Ω
1.4
1.2
1
VDD=3.3V
0.8
0.6
Po-Output Power( W
0.4
0.2
0
048121620242832
VDD=5V
Load Resistance(Ω)
THD+N= 1%
BTL
Eac h Channel
Figure 26
Pow er Dissipation vs Output Powe r
0.8
Ω
Ω
0.7
0.6
0.5
0.4
0.3
Power Dissipation(W)
0.2
0.1
0
00.250.50.751
Output Pow er(W)
RL= 8
RL= 3
RL= 4
Ω
VDD=3.3V
BTL
Each Channel
Ω
Ω
Figure 28
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Pin Description
G1432
PIN
TSSOP QFN
1,12,13,24 9,10,21,22 GND/HS Ground connection for circuitry, directly connected to thermal pad.
2,9,11 6,8,23 NC NC Embedded test mode pin, please keep it floating.
3 24 LOUT+ O Left channel + output in BTL mode
4 1 LIN1 I
5 2 LIN2 I
6 3 LBYPASS Connect to voltage divider for left channel internal mid-supply bias.
7 4 LVDD I Supply voltage input for left channel and for primary bias circuits.
8 5 SHUTDOWN I Shutdown mode control signal input, places entire IC in shutdown mode
10 7 LOUT- O Left channel - output in BTL mode.
14 11 MUTE I Mode control signal input, hold low for activation, hold high for mute.
15 12 ROUT- O Right channel - output in BTL mode
16 13
17 14 GND Ground connection for circuitry.
18 15 RVDD I Supply voltage input for right channel.
19 16 RBYPASS Connect to voltage divider for right channel internal mid-supply bias.
20 17 RIN2 I
21 18 RIN1 I
22 19 ROUT+ O Right channel + output in BTL mode
23 20 VOL I The output power can be clamped by setting a low bound voltage to this pin.
Thermal
Pad
Thermal
Pad
NAME I/O FUNCTION
Left channel IN1 input, selected when
Left channel IN2 input, selected when
when held high, I
1IN /IN2
Recommend connecting the Thermal Pad to the GND for excellent power
I MUX control input, hold high to select in2 inputs (5,20)/(2/17), hold low to
select in1 inputs (4,21)/(1,18).
Right channel in2 input, selected when
Right channel lin1 input, selected when
The high bound voltage will be generated internally. The output voltage will
be clamped between high/low bound voltages. Then the output power is limited. It is weakly pull-low internally, let this pin floating or tied to GND can
deactivate this function.
dissipation.
< 5µA.
DD
1IN /IN2 pin is held low.
1IN /IN2 pin is held high.
1IN /IN2 pin is held high.
1IN /IN2 pin is held low.
Recommended Minimum Footprint
TSSOP-24 (FD)
QFN4X4-24
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Block Diagram
(TSSOP/QFN Pin No.)
Parameter Measurement Information
21/18
21/18
20/17
20/17
19/16
19/16
14/11
14/11
23/20
23/20
8/5
8/5
6/3
6/3
5/2
5/2
4/1
4/1
RIN1
RIN1
RIN2
RIN2
RBYPASS
RBYPASS
MUTE
MUTE
SHUTDOWN
SHUTDOWN
VOL
VOL
LBYPASS
LBYPASS
LIN2
LIN2
LIN1
LIN1
RIGHT
RIGHT
MUX
MUX
LEFT
LEFT
MUX
MUX
_
_
+
+
BIAS CIRCUITS
BIAS CIRCUITS
MODES CONTROL
MODES CONTROL
CIRCUITS
CIRCUITS
+
+
_
_
20k
20k
20k
20k
ROUT+
ROUT+
ROUT-
ROUT-
IN1/IN2
IN1/IN2
LOUT-
LOUT-
LOUT+
LOUT+
22/19
22/19
15/12
15/12
18/15RVDD
18/15RVDD
16/13
16/13
7/4LVDD
7/4LVDD
10/7
10/7
3/24
3/24
G1432
Ver: 1.1
Jun 21, 2006
AC source
AC source
CB
CB
4.7µF
4.7µF
CI
CI
14/11
14/11
MUTE
MUTE
IN1/IN2
8/5
SHUTDOWN
8/5
SHUTDOWN
23/20
VOL
23/20
VOL
6/3
6/3
LBYPASS
LBYPASS
+
+
5/2
LIN2
5/2
LIN2
4/1
LIN1
4/1
LIN1
RI
RI
LEFT
LEFT
MUX
MUX
RF
RF
BTL Mode Test Circuit
BTL Mode Test Circuit
_
_
IN1/IN2
LOUT+
LOUT+
LVDD
LVDD
LOUT-
LOUT-
16/13
16/13
7/4
7/4
10/7
10/7
3/24
3/24
RL 4/8/32Ω
RL 4/8/32Ω
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Application Circuits
(TSSOP-24)
G1432
CFR
RFL
RFL
CFR
AUDIO SOURCE
AUDIO SOURCE
CIR
CIR
GND/HS
GND/HS
NC
NC
LOUT+
LOUT+
LIN1
LIN1
RIR
RIR
LIN2
LIN2
LBYPASS
LBYPASS
RBYPASS
RBYPASS
SHUTDOWN
SHUTDOWN
NC
NC
LOUT-
LOUT-
NC
NC
GND/HS
GND/HS
GND/HS
GND/HS
24
1
1
2
2
322
322
4
4
5
5
6
6
G1432
G1432
19
19
8
8
916
916
10
10
11
11
12
12
24
23
23
21
21
20
20
18
18
17
17
15
15
14
14
13
13
7
7
VOL
VOL
ROUT+
ROUT+
RIN1
RIN1
RIN2
RIN2
LVDD
LVDD
RVDD
RVDD
GND
GND
IN1/IN2
IN1/IN2
ROUT-
ROUT-
MUTE
MUTE
GND/HS
GND/HS
RIL
RIL
CSR
CSR
CIL
CIL
AUDIO SOURCE
AUDIO SOURCE
CFLRFL
CFLRFL
Logical Truth Table
OUTPUT
Mute
1IN /IN2
X X
Low Low Low L/R IN1 OutputOutputBTL
Low High Low L/R IN2 OutputOutputBTL
High Low Low L/R IN1 Output---- Mute
High High Low L/R IN2 Output---- Mute
Shutdown Input L/R Out+ L/R Out-Mode
High
X
---- ---- Shutdown (Mute)
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Application Information
(TSSOP-24/QFN4X4-24 Pin No.)
Input MUX Operation
There are two input signal paths – IN1 & IN2. With the
prompt setting, the G1432 allows the setting of different gains for different input sources. If setting the
1IN /IN2 pin low, the IN1 input source is selected.
When setting the
source is chosen.
Bridged-Tied Load Mode Operation
The G1432 has two linear amplifiers to drive both ends
of the speaker load in Bridged-Tied Load (BTL) mode
operation. Figure A shows the BTL configuration. The
differential driving to the speaker load means that
when one side is slewing up, the other side is slewing
down, and vice versa. This configuration in effect will
double the voltage swing on the load as compared to a
ground reference load. In BTL mode, the peak-to-peak
voltage V
(PP) on the load will be two times than a
O
ground reference configuration. The voltage on the
load is doubled, this will also yield 4 times output
power on the load at the same power supply rail and
loading. Another benefit of using differential driving
configuration is that BTL operation cancels the dc offsets, which eliminates the dc coupling capacitor that is
needed to cancelled dc offsets in the ground reference
configuration. Low-frequency performance is then limited only by the input network and speaker responses.
Cost and PCB space can be minimized by eliminating
the dc coupling capacitors.
1IN /IN2 pin high, the IN2 input
VDD
VDD
Vo(PP)
Vo(PP)
R
R
L
VDD
VDD
Figure A
Figure A
L
2xVo(PP)
2xVo(PP)
-Vo(PP)
-Vo(PP)
G1432
MUTE and SHUTDOWN Mode Operations
The G1432 implements the mute and shutdown
mode operations to reduce supply current, I
the absolute minimum level during nonuse periods
for battery-power conservation. When the shutdown
pin (pin 8/5) is pulled high, all linear amplifiers will
be deactivated to mute the amplifier outputs. And
the G1432 enters an extra low current consumption
state, I
is smaller than 5µA. If pulling the mute pin
DD
(pin 14/11) high, it will force the activated linear
amplifier to supply the VDD/2 dc voltage on the
output & shutdown the second linear amplifiers to
mute the AC performance. In the mute mode operation, the current consumption will be a smaller than
BTL modes. Shutdown and Mute pins should never
be left unconnected, this floating condition will
cause the amplifier operations unpredictable.
Maximum Power Clampping Function
The G1432 supports the maximum output power
clamping function to avoid damaging the speaker
when the amplifier output a power beyond the speaker
tolerance. The Vol pin (pin 23/20) is weakly pull-low
internally. If inputting a non-zero voltage (low boundary voltage) to the Vol pin, the G1432 will generate a
high boundary voltage which the difference between
the VDD/2 and the high boundary voltage is the same
as the difference between the VDD/2 and the low
boundary voltage. ( i.e. V
VDD/2 = VDD/2 – VOL )
OH –
Then the outputs of linear amplifiers will be effectively
limited between the high/low boundary voltage, the
maximum output power is clamped. By setting the
voltage of Vol, the maximum output power can be well
controlled. When the maximum power clamping function is not used, the Vol pin should be floated or tied to
GND.
DD,
to
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Optimizing DEPOP Operation
Circuitry has been implemented in the G1432 to
minimize the amount of popping heard at power-up
and when coming out of shutdown mode. Popping
occurs whenever a voltage step is applied to the
speaker and making the differential voltage generated at the two ends of the speaker. To avoid the
popping heard, the bypass capacitor should be
chosen promptly, 1/(C
Where 100kΩ is the output impedance of the
mid-rail generator, C
pacitor, C
is the input coupling capacitor, RI is the
I
input impedance, R
which is on the feedback path. C
portant capacitor. Besides it is used to reduce the
popping, C
can also determine the rate at which
B
the amplifier starts up during startup or recovery
from shutdown mode.
De-popping circuitry of the G1432 is shown on Figure B. The PNP transistor limits the voltage drop
across the 50kΩ by slewing the internal node slowly
when power is applied. At start-up, the voltage at
BYPASS capacitor is 0. The PNP is ON to pull the
mid-point of the bias circuit down. So the capacitor
sees a lower effective voltage, and thus the charging is slower. This appears as a linear ramp (while
the PNP transistor is conducting), followed by the
expected exponential ramp of an R-C circuit.
x100kΩ) ≦ 1/(CI*(RI+RF)).
B
is the mid-rail bypass ca-
B
is the gain setting impedance
F
is the most im-
B
G1432
VDD
VDD
100 kΩ
100 kΩ
50 kΩ
50 kΩ
Bypass
Bypass
100 kΩ
100 kΩ
Figure B
Figure B
Ver: 1.1
Jun 21, 2006
13
TEL: 886-3-5788833
http://www.gmt.com.tw
Page 14
Global Mixed-mode Technology Inc.
G1432
Package Information
C
D
24
24
1
1
D
D1
D1
E
E
E1
E1
E2
E2
Note 5
Note 5
A2
A2
e
e
b
b
A1
A1
A
A
C
L
L
θ
θ
TSSOP-24 (FD) Package
NOTE:
1. Package body sizes exclude mold flash protrusions or gate burrs
2. Tolerance
±0.1mm unless otherwise specified
3. Coplanarity : 0.1mm
4. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.
5. Die pad exposure size is according to lead frame design.
6. Follow JEDEC MO-153
SYMBOLS
MIN NOM MAX MIN NOM MAX
A ----- ----- 1.20 ----- ----- 0.047
A1 0.00 ----- 0.15 0.000 ----- 0.006
A2 0.80 1.00 1.05 0.031 0.039 0.041
b 0.19 ----- 0.30 0.007 ----- 0.012
C 0.20 ----- ----- 0.008 ----- -----
D 7.7 7.8 7.9 0.303 0.307 0.311
D1 4.4 ----- 4.9 0.173 ----- 0.193
E 6.40 BSC 0.252 BSC
E1 4.30 4.40 4.50 0.169 0.173 0.177
E2 2.7 ----- 3.2 0.106 ----- 0.126
e 0.65 BSC 0.026 BSC
L 0.45 0.60 0.75 0.018 0.024 0.030
θ 0° ----- 8° 0° ----- 8°
DIMENSION IN MM DIMENSION IN INCH
Ver: 1.1
Jun 21, 2006
14
TEL: 886-3-5788833
http://www.gmt.com.tw
Page 15
Global Mixed-mode Technology Inc.
G1432
D2
Pin 1 Dot
Pin 1 Dot
By Marking
By Marking
D
D
L
L
D2
b
b
Pin #1 Identification
Pin #1 Identification
Pin #1 Identification
Chamfer 0.3 X 45°
Chamfer 0.3 X 45°
Chamfer 0.3 X 45°
e
E
E
e
E2
E2
Top View
Top View
e1
e1
A
A
A2
A2
A1
A1
QFN4X4-24 Package
SYMBOL
MIN. NOM. MAX. MIN. NOM. MAX.
A 0.700 ----- 1.000 0.028 ----- 0.039
A1 0.000 ----- 0.050 0.000 ----- 0.002
A2 0.178 0.203 0.228 0.007 0.008 0.009
b 0.225 0.250 0.275 0.009 0.010 0.011
D 3.950 4.000 4.050 0.156 0.157 0.159
D2 2.650 2.700 2.750 0.104 0.106 0.108
E 3.950 4.000 4.050 0.156 0.157 0.159
E2 2.650 2.700 2.750 0.104 0.106 0.108
e 0.500 BSC 0.020 BSC
e1 2.500 REF 0.098 REF
L 0.350 0.400 0.450 0.014 0.016 0.018
DIMENSION IN MM DIMENSION IN INCH
Taping Specification
Typical TSSOP Package Orientation
Typical TSSOP Package Orientation
GMT Inc. does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and GMT Inc. reserves the right at any time without notice to change said circuitry and specifications.
Ver: 1.1
Jun 21, 2006
Feed Direction
Feed Direction
Feed Direction
Feed Direction
Typical QFN Package Orientation
Typical QFN Package Orientation
15
PACKAGE Q’TY/REEL
TSSOP-24 (FD) 2,500 ea
QFN4X4-24 3,000 ea
TEL: 886-3-5788833
http://www.gmt.com.tw
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