Glitch Works GW-OSI-RAM1 User Manual

Glitch Works GW-OSI-RAM1

User’s Manual and Assembly Guide

Revision 1, 2017-09-04

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Contents

1 Introduction 2

2 Configuration 2

2.1 Configuring I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2 Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.3 Prototyping Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.4 12-Bit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.5 Inverted and Non-Inverted Data Busses . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Assembly 5

3.1 Assembling the GW-OSI-RAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.2 0-64K Memory, no Memory Management or ROM Overlay . . . . . . . . . . . . . . . 6

3.3 Memory Management or ROM Overlay Support . . . . . . . . . . . . . . . . . . . . . 6

3.4 I/O Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.5 12-Bit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.6 Insert Socketed ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Initial Checkout and Testing 8

4.1 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.2 Repair and Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 Parts List 9

Assembly Drawing 10

Schematics 11

1

1 Introduction

The Glitch Works GW-OSI-RAM1 is a universal RAM/ROM board for the Ohio Scientific bus. It
includes the following features:

• Fully static operation

• No expensive or hard-to-get components (8T26 buffers, etc.)

• 8- and 12-bit support

• Support for inverted and non-inverted data bus

• Optional bank switching

• ROM support/overlay

• Mappable around existing RAM, ROM, and I/O in 4K segments

• Header for lamp register

• General purpose prototype area

The GW-OSI-RAM1 uses JEDEC pinout 32K x 8 memory devices, such as the 62256 SRAM, 27256
EPROM, or 28256 EEPROM. Memory can be enabled in 4K segments to map around existing RAM,
ROM, and I/O. The board can be configured to mix RAM and ROM in two separate banks. It can be
used with any system that uses the Ohio Scientific bus, including the SYS bus of the Ohio Scientific
560Z Processor Lab. Full 12-bit operation allows it to be used with the OSI 560Z in PDP-8 compatible
mode.

2 Configuration

Due to its flexibility, the GW-OSI-RAM1 contains a large number of DIP switches and several
jumpers. Memory management requires jumper wires to be inserted. The following table explains
switch and jumper function. Please refer to the assembly drawing for the locations of switches and
jumpers.

Name Function

SW1 First bank 0-32K, each position enables a 4K segment when ON
SW2 First bank 32-64K, each p osition enables a 4K segment when ON
SW3 Second bank 0-32K, each position enables a 4K segment when ON
SW4 Low byte of I/O address, ON = 1
SW5 High byte of I/O address, ON = 1
SW6 Second bank 32-64K, each p osition enables a 4K segment when ON

J1 I/O address size selection, 1-2 for 1 byte, 2-3 for 2 bytes
J2 I/O address decode enable, closed enables I/O deco de

For instance, if you wished to enable 12K of RAM starting at 0x0000 in the first bank, close positions
1, 2, and 3 of SW1.

Any memory segment that contains RAM, ROM, or I/O on another board should have its segment
disabled on the GW- OSI-RAM1. Consult your system’s documentation to determine which segments
are in use for the system and board set you have. Generally, the 4K segment at 0xF000 will be
required for I/O devices and boot ROMs, and should be disabled on the GW-OSI-RAM1. Video
systems should disable the two 4K segments at 0xD000 and 0xE000. Systems with ROM BASIC
should disable the two 4K segments at 0xA000 and 0xB000.

2

For systems that include RAM on the CPU board, you must either disable the RAM on the CPU
board and use only the RAM on the GW-OSI-RAM1, or disable the segments occupied by CPU board
RAM. The procedure for disabling CPU board RAM will depend on the particular CPU board in
use. It is usually easier to disable those segments on the GW-OSI-RAM1, unless there are suspected
reliability problems with the CPU board’s onboard RAM.

2.1 Configuring I/O

SW4, SW5, J1, and J2 control I/O configuration. If no I/O is desired, remove the shunt from J2 –
all other I/O settings will be ignored if J2 is open.

If J2 is closed, SW4 specifies the low byte of the I/O address, while SW5 specifies the upper byte. If
the I/O device is write-only (for example, a GW-OSI-HLR1 Hex Lamp Register), it can be addressed
over existing RAM on the GW-OSI-RAM1 but not on another RAM board. I f the I/O device is read-
only or read/write, it must not overlap RAM. The GW-OSI-RAM1 provides memory management
inputs in the memory address decoding sections to allow a read-only or read-write I/O device to be
inserted into RAM on the GW-OSI-RAM1. These memory management inputs will not work for
RAM on other boards.

J1 selects the I/O size. Placing a shunt between pins 1 and 2 set it to one byte, a shunt between
pins 2 and 3 set it two two bytes. Determine this setting from the module you plan to install in J3,
or your own needs if using the prototype area.

2.2 Memory Management

The GW-OSI-RAM1 supports Ohio Scientific 1 MB memory management, which is implemented on
some OSI CPU boards, such as the OSI 510. Most smaller systems will not use memory management
and will be limited to 64K of RAM, ROM, and I/O devices.

If OSI 1 MB memory management is not being used, the second bank on the GW-OSI-RAM1 can
be used for ROM overlays. This allows mixing RAM and ROM on the same b oard, in 4K segments.
Resistors R2 - R7 control which banks are active by default, and must be configured for ROM
overlays, if desired. The following table describes possible configurations of R2 - R7:

Resistors Installed Function

R2, R3 Default configuration, first bank enabled at 0x0000 - 0xFFFF

R4 Second bank 0-32K enabled, used for ROM overlay
R6 Second bank 32-64K enabled, used for ROM overlay
R5 Second bank 0-32K to be controlled by custom memory management
R7 Second bank 32-64K to be controlled by custom memory management

For a 64K system with no memory management, R2, R3, R4 and R6 are installed, allowing 0-64K of
RAM with 0-64K of ROM overlays. For a system with memory management, R2, R3, R5, and R7
are installed, and jumper connections are made from U3 and/or U6. Consult the schematics for 1
MB memory management jumpering.

3

2.3 Prototyping Area

A prototyping area is provided on the GW-OSI-RAM1, and can be used whether or not a mezzanine
expansion module is to be installed, provided devices under the mezzanine module are short enough.
The prototyping area consists of a section of plated-through holes, siz ed to fit the leads of a 2 W
resistor without drilling. This allows multiple wires to be inserted in a single hole, making point-to­point prototyping very easy.

Header J3 provides buffered data lines, address lines A0 and A1, and read/write signals for both the
mezzanine modules and prototyping space. The *IOSEL signal is used by mezzanine modules, but
may be used by the prototype area if no mezzanine module is installed, or if the circuitry in the
prototype area is designed to co-exist with the mezzanine module in use.

Consult the schematics for J3 pinout and signal functions.

2.4 12-Bit Operation

The GW-OSI-RAM1 was designed with 12-bit operation in mind, for use on the SYS bus of the OSI
560Z Processor Lab. Addressing and configuration is the same as 8-bit mode, but the data buffer at
U24 must be installed, and RAM or ROM must be installed in U14 - U17 to provide the additional
upper 4 data bits. Refer to the assembly drawing for addresses covered by U14 - U17.

While extended memory management is techincally possible in 12-bit mode, no current boards im­plement it.

Expansion connector J3 supports 12-bit data operation, and modules such as the GW-OSI-HLR1
Hex Lamp Register will display 12-bit data if the system controlling the GW-OSI-RAM1 supports it.
Leaving 12-bit operation enabled when using the GW-OSI-RAM1 in an 8-bit system is acceptable,
as long as the four additional data lines used in 12-bit operation are not used for other purposes.
Consult your system documentation and/or schematics to determine this. If in doubt, remove the
data buffer at U24 to disable 12-bit operation.

2.5 Inverted and Non-Inverted Data Busses

The GW-OSI-RAM1 can be used with either inverted or non-inverted data busses. Inverted busses
are typically found on larger or later OSI systems, which non-inverted data busses are found on some
of the smaller and earlier OSI systems. Most OSI boards can be configured for either operation.

Data bus polarity does not matter if the GW-OSI-RAM1 will only be used for RAM; however, it
should match the system’s data bus polarity if using ROM, mezzanine modules, or the prototyping
area. The following table describes which buffers should be used in U24, U27, and U28:

Bus Polarity Buffers on CPU Board Buffers in U24, U27 and U28

Inverted 8T26 or MC6880 74LS240

Non-Inverted 8T28 or MC6889 74LS244

4