Glitch Works 8085 SBC, GW-8085SBC-3 User Manual And Assembly Manual
Glitch Works 8085 SBC rev 3
GW-8085SBC-3
User’s Manual and Assembly Guide
Revision 1, 2018-06-30
Creative Commons “Attribution-NonCommercial-ShareAlike 4.0” license.
c
2018 The Glitch Works
http://www.glitchwrks.com/
This manual is licensed under a
Contents
1 Introduction 2
2 Configuration 2
2.1 Configuring I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 ROM Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 Interrupt Jumpering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.4 Glitchbus Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Assembly 4
3.1 Assembling the 8085 SBC rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Assembly Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 Insert Socketed ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.4 Solder Console Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 Initial Checkout and Testing 7
4.1 Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Repair and Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Technical Notes 8
5.1 Board Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2 Board Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.3 Default Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.4 Default I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6 Errata and Clarifications 10
6.1 Resistor Pack Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.2 ROM Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7 Parts List 11
Assembly Drawing 13
Schematics 14
1
1 Introduction
The Glitch Works 8085 SBC rev 3 (GW-8085SBC-3) is a single-board computer based on the Intel
8085 CPU. It includes the following features:
• Intel 8085 CPU at 2 MHz (guaranteed operation, overclocking possible)
• 64 KB static RAM, FeRAM compatible
• 32 KB ROM, EEPROM, or FeRAM in 4K pages, in-board programmable
• Serial console via Intel 8251A USART
• USART clock independent of system clock
• Software controlled power-on jump
• ROM paging and switch-out
• Debounced reset and power supply supervisory circuit
• Glitchbus expansion header
The 8085 SBC rev 3, when paired with GWMON, is a self-contained system needing only a serial
terminal (or teminal emulation software on a PC) for full operation. GWMON for the 8085 SBC
rev 3 includes Glitch Works ROM-FS, which allows for the storage of file records in ROM. These
records can be loaded from the monitor, or automatically selected by option switches on reset/powerup. This also allows for in-board up dates to GWMON without overwriting the current, known-good
copy.
2 Configuration
The 8085 SBC rev 3 includes a number of jumpers and switch packs for configuring system options:
Name Function
J1 ROM Boot, 1-2 disables ROM boot, 2-3 enables ROM boot
J2 ROM Enabled, 1-2 disables ROM on reset, 2-3 enables ROM on reset
J5 Console USART Bitrate, jumper one position only for printed speed
SW2 I/O Port Block Base Address
SW3 ROM Base Address, Write Protect, and Boot Page Address
For normal operation with standard GWMON ROM images, J1 and J2 should both be set 2-3, SW2
should be all open, SW3 1-4 should be closed, and SW3 5-8 should be open. This places the I/O block
at 0x00 - 0x03, ROM at 0xF000 - 0xFFFF, and enables jump to ROM on reset and power-up.
Console bitrate is selected with J5. The board’s silkscreen shows each position’s speed. Only one
speed may be selected. Note that the silkscreen legend will be incorrect if anything other than a
2.4576 MHz crystal is used at Y2.
2
2.1 Configuring I/O
The addresses of the USART registers, the board status register, and the board control register are
controlled by switch pack SW2. In a default configuration, SW2 is set to all open and places the
I/O base at 0x00 - 0x03. The base I/O block may be re-addressed on any four-byte boundary in
address space for use with other software.
2.2 ROM Options
ROM configuration on the 8085 SBC rev 3 is flexible. ROM is addressed in 4K pages, using the
ROM base set on SW3 and three bits from the board control register. The board control register is
software programmable, and is reset to 0x00 at reset and power-on.
A pair of D-type flip-flops allows switching the ROM on or off under software control, as well as
mapping ROM to 0x0000 for booting. The default states for these flip-flops are controlled by jumpers
J1 and J2. J1 controls remapping to 0x0000 for b ooting: place its shunt from 1-2 to disable ROM
boot, or from 2-3 to enable ROM boot. J2 controls whether the ROM is enabled or disabled at reset.
Place its shunt from 1-2 to disable ROM at reset, or from 2-3 to enable ROM at reset. Note that
ROM must be enabled at reset for ROM boot to work (both J1 and J2 must be strapped for 2-3).
2.3 Interrupt Jumpering
The five hardware interrupt lines of the Intel 8085 are pulled down to an inactive state with 4.7 kΩ
resistors. While they are not used by the default Glitch Works software package, they are available
for use. Additionally, the *BINT line from the Glitchbus expansion header is inverted and brought to
TP1, INTERRUPT. It may be jumpered to any of the five available hardware interrupts. Consult the
schematic for further details.
2.4 Glitchbus Expansion
The 8085 SBC rev 3 is expandable through a Glitchbus expansion header. The Glitchbus is a generic
8-bit bus intended to be processor-agnostic. We plan on offering many expansion boards that utilize
this bus design. As implemented on the 8085 SBC rev 3, the Glitchbus is designed to stack above
the SBC using PC/104 style stacking headers.
Do note that some of the status and control lines are not fully buffered on the 8085 SBC rev 3 and
are subject to loading limitations.
The 8085 SBC’s Glitchbus expansion header is not compatible with previous expansion boards designed
for past revisions of the Glitch Works 8085 SBC. Previous boards will not work with the 8085 SBC
rev 3 – use only Glitchbus compatible expansion boards! Previous boards are of a different physical
size and should be fairly hard to get mixed up with Glitchbus boards.
3
3 Assembly
The 8085 SBC rev 3 is designed to be easy to assemble for anyone with moderate soldering ability.
It is a mo derately complex board and will typically require between one and three hours of assembly
time, depending on the skill of the assembler. The following tools will be required:
• Soldering iron, 20-40 W recommended, grounded tip
• Solder, 63/37 leaded solder recommended, Kester “44 Core” or similar
• Diagonal cutters or flush cutters
• Solder braid, solder sucker, or desoldering station, in the event errors are made
• Needle-nose pilers for bending component leads
• 1/4 and 1/8 W resistor lead forms (optional)
This manual does not cover basic soldering technique. If you are new to soldering, we recommend the
Adafruit soldering guide and plenty of practice on a piece of protoboard, before beginning assembly
of the 8085 SBC rev 3. The Adafruit guide can be found at:
https://learn.adafruit.com/adafruit-guide-excellent-soldering
3.1 Assembling the 8085 SBC rev 3
If you purchased a full Glitch Works parts kit, we recommend completing all assembly sections, since
extra features can be disabled as needed. If supplying your own parts, you may choose which sections
to complete based on the functionality required.
Note that pin 1 is designated with a square pad for all ICs, resistor packs, switches, and most
connectors. Pin 1 is toward the top of the board, as seen from the front, for all ICs, diodes, resistor
packs, and switches. The component (front) side of the board is the side which contains the white
silkscreen legend. It is recommended to install components from shortest to tallest, which makes
assembly without an assembly vise or jig easier, assuming the board is flipped over and soldered with
the component side resting on a table top.
All jumper headers and connector headers are press-fit and may require a bit of force or gentle
wiggling to install. This is normal and helps keep the headers in place when the board is flipped over
for soldering.
4
3.2 Assembly Checklist
Verify parts list against kit contents or builder-provided parts
Consult the assembly drawing for component locations and values
Bend all 0.01 µF bypass capacitors (yellow axial bead) – position 2 on a 1/8 W lead form
Install all 0.01 µF capacitors in positions marked C in assembly diagram
Hairpin bend three 4.7 kΩ resistors and set aside
Bend remaining 4.7 kΩ resistors and install in their marked locations – position 1 on a 1/4 W
lead form
Bend all 330 Ω resistors and install in their marked locations – position 1 on a 1/4 W lead form
Install non-socketed DIP ICs at their marked locations. Do not install U9, U15, U16, U17,
U19, or U21
Install a 16-pin socket at U21
Install 28-pin sockets at U15, U16, U17, and U19
Install a 40-pin socket at U9
Install 22 µF 10V capacitors at C8 and C17, bend leads with needle-node pliers
Install micro tact pushbutton at SW1
Install 20 pF radial ceramic capacitor at C9
Install 10 nF radial ceramic capacitors at C1, C16
Install resistor packs at RP1, RP2
Install DIP switches at SW2, SW3
Install five 22 µF 16 V radial electrolytic capacitors at C25 - C29
Install TO-92 DS1233 at U1
Hairpin bend all 1 kΩ resistors and install at R21, R22
Install three previously hairpinned 4.7 kΩ resistors at R3, R4, R20
Install three LEDs at D1, D2, D3
Break the 22-pin pin header strip into two 8-pin sections and two 3-pin sections
Install two 3-pin header sections at J1, J2
Install two 8-pin header sections next to one another at J5
Install 4 MHz CPU clock crystal at Y1
Install 2.4576 MHz serial clock crystal at Y2
5
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