G-LINK GLT6400L08SL-70ST, GLT6400L08SL-70FC, GLT6400L08LLI-85FC, GLT6400L08LLI-70FC, GLT6400L08LL-85ST Datasheet
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G-LINK
GLT6400L08
Ultra Low Power 512k x 8 CMOS SRAM
Feb 2001(Rev. 1.1)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 1 -
Features : Description :
∗ Low-power consumption.
-active: 45mA at 85ns.
-stand by :
20 µA (CMOS input / output)
5 µA (CMOS input / output, SL)
∗ Single +2.7 to 3.3V power supply.
∗ Equal access and cycle time.
∗ 85 ns access time at 2.7V to 3.3V 70ns
access time at 3V to 3.6V
∗ 1.0V data retention mode.
∗ TTL compatible, tri-state input/output.
∗ Automatic power-down when deselected.
∗ Industrial grade (-40°C ~ 85°C)
available.
∗ Package available: sTSOP , SOP.
The GLT6400L08 is a low power CMOS Static
RAM organized as 524,288 x 8 bits. Easy memory
expansion is provided by an active LOW CE1 an
active LOW OE , and Tri-state I/O’s. This device has
an automatic power-down mode feature when
deselected.
Writing to the device is accomplished by taking
chip Enable 1 ( CE1 ) with Write Enable ( WE ) LOW.
Reading from the device is performed by taking Chip
Enable 1 ( CE1 ) with Output Enable ( OE ) LOW
while Write Enable ( WE ) and Chip Enable 2 (CE2)
is HIGH. The I/O pins are placed in a high-impedance
state when the device is deselected : the outputs are
disabled during a write cycle.
The GLT6400L08 comes with a 1V data retention
feature and Lower Standby Power. The GLT6400L08
is available in a 32-pin sTSOP packages,and 32pin
SOP package.
Function Block Diagram :
ROW DECODER
Cell
Array
SENSE AMP
INPUT BUFFER
COLUMN DECODER
CONTROL
CIRCUIT
OE
WE
CE1
CE2
I/O
7
I/O1
Column Address
Row Address
G-LINK
GLT6400L08
Ultra Low Power 512k x 8 CMOS SRAM
Feb 2001(Rev. 1.1)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 2 -
Pin Configurations :
GLT6400L08 GLT6400L08
sTSOPI SOP
A
16
A
7
1
2
3
4
5
6
8
9
10
11
12
13
22
21
19
18
17
26
25
2423GND
OE
A
10
14
27
28
I/O
7
I/O
6
20 A
0
7
WE
V
CC
15
16
29
30
31
32A
11
A
9
A
8
A
13
A
17
A
15
A
14
A
12
A
6
A
5
A
4
A
3
A
2
A
1
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
CE
1
A
18
1
2
3
4
5
6
7
9
10
11
12
13
8
14
15
16 17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A
18
A
16
A
14
A
12
A
6
A
5
A
3
A
2
A
1
A
0
I/O
0
GND I/O
3
I/O
7
CE
A
10
OE
A
11
WE
A
15
A
7
A
4
I/O
1
I/O
2
I/O
4
I/O
5
I/O
6
A
9
A
8
A
13
A
17
V
CC
Pin Descriptions:
Name
Function
A0 – A
18
Address Inputs
CE
1
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0 – I/O
7
Data Input and Data Output
V
CC
Power Supply
GND Ground
NC No Connection
Truth Table:
CE
1
WE
OE
Data Mode
HXX
High-Z
Standby
XXX
High-Z
Standby
LHL
Data Out
Active, Read
LHH
High-Z
Active, Output Disable
LLX
Data Out
Active, Write
*Key : X = Don’t Care, L = Low, H = High
G-LINK
GLT6400L08
Ultra Low Power 512k x 8 CMOS SRAM
Feb 2001(Rev. 1.1)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 3 -
Absolute Maximum Ratings*
Parameter Symbol Minimum Maximum Unit
Voltage on Any Pin Relative to Gnd Vt -0.5 Vcc+0.3 V
Power Dissipation P
T
- 1.0 W
Storage Temperature (Plastic) Tstg -55 +150
°C
Temperature Under Bias Tbias -40 +85
°C
*Note : Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any conditions outside those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
V
CC
2.7 3 3.3 V
Supply Voltage
Gnd 0.0 0.0 0.0 V
V
IH
2.0 - VCC+0.2 V
Input Voltage
V
IL
-0.5* - 0.6 V
* VIL min = -1.0V for pulse width less than tRC/2.
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