G-LINK GLT6100L08SL-100TC, GLT6100L08LL-85TC, GLT6100L08LL-70TC, GLT6100L08SL-85TC, GLT6100L08SL-70TC Datasheet
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G-LINK
GLT6100L16
Ultra Low Power 64k x 16 CMOS SRAM
May 2000(Rev. 0.3)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 1 -
Features : Description :
∗ Low-power consumption.
-Active: 40mA Icc at 55ns.
-Stand by :
5 µA (CMOS input / output)
1 µA (CMOS input / output, SL)
∗ Single +2.7 to 3.3V Power Supply.
∗ Equal access and cycle time.
∗ 55/70/85/100 ns access time.
∗ Tri-state output.
∗ Automatic power-down when
deselected.
∗ Multiple center power and ground pins
for improved noise immunity.
∗ Individual byte controls for both Read
and Write cycles.
∗ Available in 44pin TSOPII Package.
The GLT6100L16 is a low power CMOS Static
RAM organized as 65,536 words by 16 bits. Easy
memory expansion is provided by an active LOW CE
and OE pin.
This device has an automatic power – down
mode feature when deselected. Separate Byte
Enable controls ( BLE and BHE ) allow individual
bytes to be accessed. BLE controls the lower bits
I/O0 – I/O7. BHE controls the upper bits I/O8 – I/O15.
Writing to these devices is performed by taking
Chip Enable CE with Write Enable WE and byte
Enable ( BLE / BHE ) Low.
Reading from the device is performed by taking
Chip Enable CE with Output enable OE and byte
Enable ( BLE / BHE ) Low while Write Enable WE
is held HIGH.
Pin Configurations :
GLT6100L16
A
4
1
2
3
4
5
6
7
9
10
12
13
14
Vcc
8
15
16
17
18
19
20
21 24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
CE
I/O
0
OE
BLE
NC 22 23
3411Vcc
WE
A
3
A
2
A
1
A
0
I/O
1
I/O
2
I/O
3
Vss
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
A
11
A
10
A
9
A
8
NC
I/O
8
I/O
9
I/O
10
I/O
11
Vss
I/O
12
I/O
13
I/O
14
I/O
15
BHE
A
7
A6
A
5
Function Block Diagram :
Row Select
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
Memory Array
1024 x 1024
Pre-Charge Circuit
I/O Circuit
Column Select
A
10
A11A12A13A14A
15
Data
Circuit
Data
Circuit
Vcc
Vss
WE
OE
BLE
BHE
CE
I/O8 - I/O
15
I/O0 - I/O
7
G-LINK
GLT6100L16
Ultra Low Power 64k x 16 CMOS SRAM
May 2000(Rev. 0.3)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 2 -
Pin Descriptions:
Name Function
A0 – A
15
Address Inputs
CE
1
and CE
2
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0 – I/O
15
Data Input and Data Output
V
CC
3V Power Supply
GND Ground
NC No Connection
Truth Table:
CE OE WE BLE BHE
I/O0-I/O7 I/O8-I/O15 Power Mode
HXXXX
High-Z High-Z
Standby
Standby
LLHLH
Data Out High-Z
Active
Low byte Read
LLHHL
High-Z Data Out
Active
High Byte Read
LLHLL
Data Out Data Out
Active
Word Read
LXLLL
Data In Data In
Active
Word Write
LXLLH
Data In
High-Z
Active
Low Byte Write
LXLHL
High-Z Data In
Active
High byte Write
LHHXX
High-Z High-Z
Active
Output Disable
LXXHH
High-Z High-Z
Active
Output Disable
Absolute Maximum Ratings*
Parameter Symbol Minimum Maximum Unit
Voltage on Any Pin Relative to Gnd Vt -0.5 4.6 V
Power Dissipation P
T
- 1.0 W
Storage Temperature (Plastic) Tstg -55 +150
°C
Temperature Under Bias Tbias -40 +85
°C
*Note : Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any conditions outside those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
G-LINK
GLT6100L16
Ultra Low Power 64k x 16 CMOS SRAM
May 2000(Rev. 0.3)
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 3 -
Recommended Operating Conditions ( TA = -25°C to + 85°C** )
Parameter Symbol Min Typ Max Unit
V
CC
2.7 3.0 3.3 V
Supply Voltage
Gnd 0.0 0.0 0.0 V
V
IH
2.2 - VCC+0.5 V
Input Voltage
V
IL
-0.5* - 0.6 V
* VIL min = -2.0V for pulse width less than tRC/2.
** For Industrial Temperature.
DC Operating Characteristics ( Vcc=2.7 to 3.3V , T
A
=-25°C to + 85°C)
55 70 85 100
Parameter Sym. Test Conditions
Min Max Min Max Min Max Min Max
Unit
Input Leakage Current
I
LI
VCC = Max,
Vin = Gnd to V
CC
1 1 1 1
µA
Output Leakage
Current
I
LO
CE =VIH or VCC = Max,
V
OUT
= Gnd to V
CC
1 1 1 1
µA
Operating Power
Supply Current
I
CC
CE =VIL ,VIN=VIH or VIL, I
OUT
=0
3 3 3 3 mA
I
CC1IOUT
= 0mA,
Min Cycle, 100% Duty
40 35 30 30 mA
Average Operating
Current
I
CC2
CE ≤ 0.2V
I
OUT
= 0mA,
Cycle Time=1µs, 100% = Duty
3 3 3 3 mA
Standby Power Supply
Current(TTL Level)
I
SB
CE =V
IH
0.5 0.5 0.5 0.5 mA
GLT6100L16LL 5 5 5 5
µA
Standby Power Supply
Current (CMOS Level)
I
SB1
CE ≥ VCC-0.2V
VIN ≤ 0.2V or
VIN ≥ VCC-0.2V
GLT6100L16SL 1 1 1 1
µA
Output Low Voltage V
OLIOL
= 2 mA 0.4 0.4 0.4 0.4 V
Output High Voltage V
OHIOH
= -2 mA 2.4 2.4 2.4 2.4 V
Data Retention
Parameter Sym. Test Conditions Min. Max. Unit
VCC for Data retention
V
DR
2.0 - V
Data Retention Current
I
CCDR
1
µA
Chip Deselect to Data Retention Time
t
CDR
0 - ns
Operating Recovery Time
(2)
t
R
CE
≥
VCC -0.2V
V
IN
≥
VCC -0.2V or
V
IN
≤ 0.2V
t
RC
- ns
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