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GLT6100L08SL-85TC
Datasheet
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G-LINK GLT6100L08SL-100TC, GLT6100L08LL-85TC, GLT6100L08LL-70TC, GLT6100L08SL-85TC, GLT6100L08SL-70TC Datasheet

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G-LINK
GLT6100L16
Ultra Low Power 64k x 16 CMOS SRAM
May 2000(Rev. 0.3)
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
- 1 -
Features : Description :
∗ Low-power consumption.
-Active: 40mA Icc at 55ns.
-Stand by : 5 µA (CMOS input / output) 1 µA (CMOS input / output, SL)
∗ Single +2.7 to 3.3V Power Supply. ∗ Equal access and cycle time. ∗ 55/70/85/100 ns access time. ∗ Tri-state output. ∗ Automatic power-down when
deselected.
∗ Multiple center power and ground pins
for improved noise immunity.
∗ Individual byte controls for both Read
and Write cycles.
∗ Available in 44pin TSOPII Package.
The GLT6100L16 is a low power CMOS Static
RAM organized as 65,536 words by 16 bits. Easy memory expansion is provided by an active LOW CE
and OE pin.
This device has an automatic power – down
mode feature when deselected. Separate Byte Enable controls ( BLE and BHE ) allow individual bytes to be accessed. BLE controls the lower bits
I/O0 – I/O7. BHE controls the upper bits I/O8 – I/O15.
Writing to these devices is performed by taking
Chip Enable CE with Write Enable WE and byte Enable ( BLE / BHE ) Low.
Reading from the device is performed by taking
Chip Enable CE with Output enable OE and byte Enable ( BLE / BHE ) Low while Write Enable WE
is held HIGH.
Pin Configurations :
GLT6100L16
A
4
1
2 3 4 5 6
7
9 10
12 13
14
Vcc
8
15 16 17 18 19 20
21 24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
CE
I/O
0
OE
BLE
NC 22 23
3411Vcc
WE
A
3
A
2
A
1
A
0
I/O
1
I/O
2
I/O
3
Vss I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
A
11
A
10
A
9
A
8
NC
I/O
8
I/O
9
I/O
10
I/O
11
Vss
I/O
12
I/O
13
I/O
14
I/O
15
BHE
A
7
A6
A
5
Function Block Diagram :
Row Select
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
Memory Array
1024 x 1024
Pre-Charge Circuit
I/O Circuit
Column Select
A
10
A11A12A13A14A
15
Data
Circuit
Data
Circuit
Vcc Vss
WE
OE
BLE
BHE
CE
I/O8 - I/O
15
I/O0 - I/O
7
G-LINK
GLT6100L16
Ultra Low Power 64k x 16 CMOS SRAM
May 2000(Rev. 0.3)
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
- 2 -
Pin Descriptions:
Name Function
A0 – A
15
Address Inputs
CE
1
and CE
2
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0 – I/O
15
Data Input and Data Output
V
CC
3V Power Supply
GND Ground NC No Connection
Truth Table:
CE OE WE BLE BHE
I/O0-I/O7 I/O8-I/O15 Power Mode
HXXXX
High-Z High-Z
Standby
Standby
LLHLH
Data Out High-Z
Active
Low byte Read
LLHHL
High-Z Data Out
Active
High Byte Read
LLHLL
Data Out Data Out
Active
Word Read
LXLLL
Data In Data In
Active
Word Write
LXLLH
Data In
High-Z
Active
Low Byte Write
LXLHL
High-Z Data In
Active
High byte Write
LHHXX
High-Z High-Z
Active
Output Disable
LXXHH
High-Z High-Z
Active
Output Disable
Absolute Maximum Ratings*
Parameter Symbol Minimum Maximum Unit
Voltage on Any Pin Relative to Gnd Vt -0.5 4.6 V Power Dissipation P
T
- 1.0 W
Storage Temperature (Plastic) Tstg -55 +150
°C
Temperature Under Bias Tbias -40 +85
°C
*Note : Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
G-LINK
GLT6100L16
Ultra Low Power 64k x 16 CMOS SRAM
May 2000(Rev. 0.3)
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
- 3 -
Recommended Operating Conditions ( TA = -25°C to + 85°C** )
Parameter Symbol Min Typ Max Unit
V
CC
2.7 3.0 3.3 V
Supply Voltage
Gnd 0.0 0.0 0.0 V
V
IH
2.2 - VCC+0.5 V
Input Voltage
V
IL
-0.5* - 0.6 V
* VIL min = -2.0V for pulse width less than tRC/2. ** For Industrial Temperature.
DC Operating Characteristics ( Vcc=2.7 to 3.3V , T
A
=-25°C to + 85°C)
55 70 85 100
Parameter Sym. Test Conditions
Min Max Min Max Min Max Min Max
Unit
Input Leakage Current
I
LI
VCC = Max, Vin = Gnd to V
CC
1 1 1 1
µA
Output Leakage Current
I
LO
CE =VIH or VCC = Max,
V
OUT
= Gnd to V
CC
1 1 1 1
µA
Operating Power Supply Current
I
CC
CE =VIL ,VIN=VIH or VIL, I
OUT
=0
3 3 3 3 mA
I
CC1IOUT
= 0mA,
Min Cycle, 100% Duty
40 35 30 30 mA Average Operating Current
I
CC2
CE ≤ 0.2V
I
OUT
= 0mA,
Cycle Time=1µs, 100% = Duty
3 3 3 3 mA
Standby Power Supply
Current(TTL Level)
I
SB
CE =V
IH
0.5 0.5 0.5 0.5 mA
GLT6100L16LL 5 5 5 5
µA
Standby Power Supply Current (CMOS Level)
I
SB1
CE ≥ VCC-0.2V
VIN ≤ 0.2V or VIN ≥ VCC-0.2V
GLT6100L16SL 1 1 1 1
µA
Output Low Voltage V
OLIOL
= 2 mA 0.4 0.4 0.4 0.4 V
Output High Voltage V
OHIOH
= -2 mA 2.4 2.4 2.4 2.4 V
Data Retention
Parameter Sym. Test Conditions Min. Max. Unit
VCC for Data retention
V
DR
2.0 - V
Data Retention Current
I
CCDR
1
µA
Chip Deselect to Data Retention Time
t
CDR
0 - ns
Operating Recovery Time
(2)
t
R
CE
≥
VCC -0.2V
V
IN
≥
VCC -0.2V or
V
IN
≤ 0.2V
t
RC
- ns
G-LINK
GLT6100L16
Ultra Low Power 64k x 16 CMOS SRAM
May 2000(Rev. 0.3)
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
- 4 -
Data Retention Waveform (TA = -25°C to + 85°C)
Data Retention Mode
Vcc
CE
VDR
V
DR >= 2.0V
tRtCDR
Vcc_typ
Vcc_typ
VIH
VIH
AC Test Conditions AC Test Loads and Waveforms
CL*
TTL
Output Load Condition *Including Scope and Jig Capacitance 55ns / 70ns / 85ns CL = 30pf + 1TTL Load Load 100ns CL = 100pf + 1TTL Load
Read Cycle
(9)
( Vcc=2.7V to 3.3V, TA = -25°C to + 85°C)
55 70 85 100
Parameter Symbol
Min Max Min Max Min Max Min Max
Unit Note
Read Cycle Time t
RC
55 70 85 100 ns
Address Access Time t
AA
55 70 85 100 ns
Chip Enable Access Time t
ACE
55 70 85 100 ns
Output Enable Access Time t
OE
35 40 40 50 ns
Output Hold from address Change t
OH
10 10 10 10 ns
Chip Enable to Output in Low-Z t
LZ
10 10 10 10 ns 4,5
Chip Disable to Output in High-Z t
HZ
25 30 35 40 ns 3,4,5
Output Enable to Output in Low-Z t
OLZ
5 5 5 5 ns
Output Disable to Output in High-Z t
OHZ
25 25 30 35 ns
BLE , BHE Enable to Output in Low-Z
t
BLZ
5 5 5 5 ns 4,5
BLE , BHE Disable to Output in High-Z
t
BHZ
25 25 30 35 ns 3,4,5
BLE , BHE Access Time
t
BA
35 40 40 50 ns
Input Pulse Levels 0.6V to 2.2V Input Rise and Fall Time Input and Output Timing Reference Level
5 ns
1.4V
G-LINK
GLT6100L16
Ultra Low Power 64k x 16 CMOS SRAM
May 2000(Rev. 0.3)
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
- 5 -
Timing Waveform of Read Cycle 1 (Address Controlled)
DOUT
tRC
Address
tOH
tAA
Previous Data Valid
Data Valid
Timing Waveform of Read Cycle 2
(14~16)
DOUT
tRC
Address
tOH
tAA
tLZ
tOE
tBA
tOLZ
tBLZ
tHZ
tBHZ
tOHZ
tOH
Data Valid
High - Z
CE
BLE / BHE
OE
Write Cycle
(11)
( Vcc=2.7V to 3.3V, TA = -25°C to + 85°C)
55 70 85 100
Parameter Symbol
Min Max Min Max Min Max Min Max
Unit Note
Write Cycle Time t
WC
55 70 85 100 ns
Chip Enable to Write End t
CW
50 60 70 80 ns
Address Setup to Write End t
AW
50 60 70 80 ns
Address Setup Time t
AS
0 0 0 0 ns
Write Pulse Width t
WP
45 50 60 70 ns
Write Recovery Time t
WR
0 0 0 0 ns
Data Valid to Write End t
DW
25 30 35 40 ns
Data Hold Time t
DH
0 0 0 0 ns
Write Enable to Output in High-Z t
WHZ
25 30 35 40 ns
Output Active from Write End t
OW
5 5 5 5 ns
BLE , BHE Setup to Write End
t
BW
50 60 70 80 ns
G-LINK
GLT6100L16
Ultra Low Power 64k x 16 CMOS SRAM
May 2000(Rev. 0.3)
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
- 6 -
Timing Waveform of Write Cycle 1 (Address Controlled)
(22~25,28)
DOUT
tWC
Address
tAW tWR
CE
BLE / BHE
WE
tCW
tBW
tAS
tWP
tDW tDH
tOW
High-Z
High-Z
DIN
Timing Waveform of Write Cycle 2 ( CE Controlled)
(22~26,28)
DOUT
tWC
Address
tAW
tWR
CE
BLE / BHE
WE
tCW
tAS tBW
tWP
tDW
tDH
tWHZtLZ
High - Z
High - Z
High - Z
D
IN
G-LINK
GLT6100L16
Ultra Low Power 64k x 16 CMOS SRAM
May 2000(Rev. 0.3)
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
- 7 -
Timing Waveform of Write Cycle 3 ( BLE / BHE Controlled)
(22~26,28)
DOUT
tWC
Address
tAW
tWR
CE
BLE / BHE
WE
tCW
tAS tBW
tWP
tDW tDH
tWHZtBLZ
High - Z
High - Z
High - Z
DIN
G-LINK
GLT6100L16
Ultra Low Power 64k x 16 CMOS SRAM
May 2000(Rev. 0.3)
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
- 8 -
Notes :
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see AC Test Condition.
4. This parameter is tested with CL = 5pF. Transition is measured ± 500mV from steady – state voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is HIGH for read cycle.
7. CE and OE are LOW for read cycle.
8. Address valid prior to or coincident with CE transition LOW.
9. All read cycle timings are referenced from the last valid address to the first transition address.
10. CE or WE must be HIGH during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
12. WE are high for read cycle.
13. All read cycle timing is referenced from the last valid address to the first transition address.
14. tHZ and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or V
OL
levels.
15. At any given temperature and voltage condition tHZ(max.) is less than tLZ (min.) both for a given device and from device to device.
16. Transition is measured ± 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
17. Device is continuously selected with CE = VIL.
18. Address valid prior to coincident with CE transition Low.
19. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read write cycle.
20. For test conditions, see AC Test Condition.
21. All write timing is referenced from the last valid address to the first transition address.
22. A write occurs during the overlap of a low CE and WE . A write begins at the latest transition among CE and
WE going low: A write ends at the earliest transition among CE going high and WE going high. tWP is
measured from the beginning of write to the end of write.
23. tCW is measured from the later of CE going low to end of write.
24. tAS is measured from the address valid to the beginning of write.
25. tWR is measured from the end of write to the address change.
26. If OE , CE and WE are in the Read Mode during this period, the I/O pins are in the output Low-Z state.
27. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
28. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.
29. D
OUT
is the read data of the new address.
30. When CE is low : I/O pins are in the outputs state. The input signals in the opposite phase leading to the output should not be applied.
31. For test conditions, see AC Test Condition.
G-LINK
GLT6100L16
Ultra Low Power 64k x 16 CMOS SRAM
May 2000(Rev. 0.3)
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
- 9 -
Ordering Information
GLT6100L08LL-55TC
55ns
Normal
TSOPII 32L
GLT6100L08LL-70TC
70ns
Normal
TSOPII 32L
GLT6100L08LL-85TC
85ns
Normal
TSOPII 32L
GLT6100L08LL-100TC
100ns
Normal
TSOPII 32L
GLT6100L08SL-55TC
55ns
Normal
TSOPII 32L
GLT6100L08SL-70TC
70ns
Normal
TSOPII 32L
GLT6100L08SL-85TC
85ns
Normal
TSOPII 32L
GLT6100L08SL-100TC
100ns
Normal
TSOPII 32L
Parts Numbers (Top Mark) Definition :
GLT 6 100 L 16 LL- 55 TC
Note : CÙCDROM , HÙHDD. Example :
1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type.
2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type.
4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM
-SRAM
064 : 64K 256 : 256K 512 : 512K 100 : 1M
-DRAM
10 : 1M(C/EDO)* 11 : 1M(C/FPM)* 12 : 1M(H/EDO)* 13 : 1M(H/FPM)* 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) *See note
VOLTAGE
Blank : 5V L : 3.3V M : 2.5V N : 2.1V
CONFIG.
04 : x04 08 : x08 16 : x16 32 : x32
SPEED
-SRAM
10 : 10ns 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns
-DRAM
35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns
PACKAGE
T : PDIP(300mil) TS : TSOP(Type I) ST : sTSOP (Type I) TC : TSOP(Type ll) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP
LL : Low Low power L : Low power SL : Super Low power
G-LINK
GLT6100L16
Ultra Low Power 64k x 16 CMOS SRAM
May 2000(Rev. 0.3)
G-Link Technology Corporation
2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
- 10 -
Package Information
44 pin Small Outline J-form Package (TSOPII)
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