G-LINK GLT440L16-50TC, GLT440L16-50J4, GLT440L16-40TC, GLT440L16-40J4, GLT440L16-35TC Datasheet

G-LINK

CAS

RAS

CAS

RAS

CAS

RAS

CAS

256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

Features : Description :

GLT440L16

Aug. 2000 (Rev.1.1)

∗ 262,144 words by 16 bits organization.
∗ Fast access time and cycle time.

∗ Dual

Input.

∗ Low power dissipation.
∗ Read-Modify-Write,

-Before-

and Test Mode Capability.

Refresh, Hidden Refresh

-Only Refresh,

∗ 512 refresh cycles per 8ms.
∗ Available in 40-Pin 400 mil SOJ and 40/44

Pin TSOP(II)

∗ Single +3.3V±10% Power Supply.
∗ All inputs and Outputs are TTL compatible.
∗ Extended Data-Out(EDO) Page Mode

operation.

The GLT440L16 is a 262,144 x 16 bit
high-performance CMOS dynamic random
access memory. The GLT44016 offers Fast
Page mode with Extended Data Output, and
has both BYTE WRITE and WORD WRITE

access cycles via two

pins. The
GLT440L16 has symmetric address and
accepts 512-cycle refresh in 8ms interval.

All inputs are TTL compatible. EDO
Page Mode operation allows random access
up to 512 x 16 bits within a page, with cycle
time as short as 14ns.

The GLT440L16 is best suited for
graphics, and DSP applications requiring
high performance memories.

HIGH PERFORMANCE 35 40 50

Max.

Access Time, (t

RAC

)

Max. Column Address Access Time, (t

) 13 ns 20 ns 25 ns

CAA

35 ns 40 ns 50 ns

Min. Extended Data Out Page Mode Cycle Time, (tPC) 14 ns 15 ns 19 ns
Min. Read/Write Cycle Time, (tRC) 45 ns 75 ns 90 ns

Max.

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

Access Time, (t

CAC

)

G-Link Technology Corporation,Taiwan

6F, No. 24-2, Industry E, RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

11 ns 12 ns 13 ns

- 1 -

G-LINK

RAS

UCAS

LCAS

WE

OE

Pin Configuration :

SOJ Top View

GLT440L16

GLT440L16

256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

Aug. 2000 (Rev.1.1)

TSOP(Type II)

Top View

Pin Descriptions:

A0 - A

8

DQ1 - DQ
V

CC

V

SS

NC No Connection

Name Function

Address Inputs
Row Address Strobe

Column Address Strobe/Upper Byte Control
Column Address Strobe/Lower Byte Control
Write Enable
Output Enable

16

Data Inputs / Outputs
+3.3V Power Supply
0V Supply

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation,Taiwan

6F, No. 24-2, Industry E, RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 2 -

G-LINK

RAS,LCAS

UCAS

OE

CAS

UCAS

LCAS

CAS

RAS

RAS

.

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

I/O9

I/O12

I/O13

I/O16

256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

Absolute Maximum Ratings* Capacitance*

TA=25°C, VCC=3.3V±10%, VSS=0V

GLT440L16

Aug. 2000 (Rev.1.1)

Operating Temperature, TA (ambient)

Symbol

.....................................-10°C to +70°C

C

Storage Temperature(plastic)....-55°C to +150°C

Voltage Relative to VSS............….-1.0V to + 4.6V

IN1

C

IN2

Short Circuit Output Current......................50mA

C

Power Dissipation......................................1.0W

*Note:Operation above Absolute Maximum Ratings can

OUT

*Note: Capacitance is sampled and not 100% tested

abversely affect device reliability.

Electrical Specifications

l

l All voltages are referenced to GND.
l After power up, wait more than 100µs and then, execute eight

means

and

.

refresh cycles as dummy cycles to initialize internal circuit.

Block Diagram :

OE

WE

UCAS

LCAS
RAS

RAS

CLOCK

GENERATOR

CAS

CLOCK

GENERATOR

WE

GENERATOR

Parameter

Address Input

,

Data Input/Output

-before-

CLOCK

OE

GENERATOR

,WE,

CLOCK

Typ

3
4
5

or

Max.

4
5
7

-only

Unit

pF
pF
pF

V

CC

V

SS

REFRESH

COUNTER

9

A

0

A

1

.

A

7

A

8

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

ADDRESS BUFFERS

AND PREDECODERS

X0 - x

Y0 - Y

8

Data I/O BUS

COLUMN DECODERS

SENSE AMPLIFIERS

8

DECODERS

ROW

512 × 16

MEMORY

512

G-Link Technology Corporation,Taiwan

6F, No. 24-2, Industry E, RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 3 -

I/O

BUFFER

I/O10

ARRAY

G-LINK

RAS

UCAS

LCAS

UCAS

LCAS

UCAS

LCAS

Truth Table: GLT440L16

GLT440L16

256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

Aug. 2000 (Rev.1.1)

Function

RAS CASL CASH WE OE

ADDRESS DQs Notes

Stanby H H H X X High-Z
Read: Word L L L H L ROW/COL Data Out

Read: Lower Byte L L H H L ROW/COL Lower Byte,Data-Out

Upper Byte,High-Z

Read: Upper Byte L H L H L ROW/COL Lower Byte,High-Z

Upper Byte,Data-Out

Write: Word(Early

L L L L X ROW/COL Data-In

Write)

Write: Lower Byte

(Early)

Write: Upper Byte

(Early)

Read Write L L L
EDO-Page­Mode Read

EDO-Page­Mode Write

1st Cycle
2nd Cycle

1st Cycle
2nd Cycle

L L H L X ROW/COL Lower Byte,Data-In

Upper Byte,High-Z

L H L L X ROW/COL Lower Byte,High-Z

Upper Byte,Data-In

H→L L→H

L
L

L
L

H→L
H→L
H→L
H→L

H→L
H→L
H→L
H→L

H
H

L
L

ROW/COL Data-Out,Data-In 1,2

L

ROW/COL

L

COL

XXROW/COL

COL

Data-Out
Data-Out

Data-In
Data-In

2
2

2
2

EDO-Page-

1st Cycle

L

H→L

H→L

H→L

Mode Read­Write

Hidden

2nd Cycle
Read

L

L→H→L

H→L

L

H→L

L

H→L

H

Refresh

-Only Refresh

CBR Refresh

Write

L→H→L

L H H X X ROW High-Z

H→L

L

L

H

L L X X High-Z 3

Notes:

1. These READ cycles may also be BYTE READ cycles (either

2. These WRITE cycles may also be BYTE READ cycles (either

3. EARLY WRITE only.

4. At least one of the two CAS signals must be active (

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

- 4 -

L

L

ROW/COL

COL

ROW/COL

ROW/COL

L→H

L→H

or

or

or

G-Link Technology Corporation,Taiwan

6F, No. 24-2, Industry E, RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

).

Data-Out,Data-In

Data-Out,Data-In
Data-Out

Data-In

active).

active).

1,2

1,2

2

2

G-LINK

RAC

RAC

RAC

RAS, UCAS

LCAS

RAS

RAS

UCAS

LCAS

RAC

RAC

RAC

RAS

UCAS

LCAS

RAC

RAC

RAC

CAS

RAS

RAS, UCAS

LCAS

RAC

RAC

RAC

RAS

UCAS

LCAS

256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

DC and Operating Characteristics (1-2)

TA = 0°C to 70°C, VCC=3.3V±10%, VSS=0V, unless otherwise specified.

GLT440L16

Aug. 2000 (Rev.1.1)

Sym. Parameter Test Conditions Access

Time

I

I

I

I

I

I

I

I

Input Leakage Current

LI

(any input pin)

0V ≤ V
(All other pins not under
test=0V)

Output Leakage Current

LO

(for High-Z State)
Operating Current,

CC1

0V ≤ V
Output is disabled (Hiz)

Random READ/WRITE tRC = tRC (min.)

Standby Current,(TTL)

CC2

V
other inputs ≥V

Refresh Current,

CC3

-Only
tRC = tRC (min.)

Operating Current,

CC4

EDO Page Mode

cycling:tPC=tPC(min.)

Refresh Current,

CC5

Before

address cycling:
tRC=tRC (min.)

Standby Current, (CMOS)

CC6

IN

out

IH

cycling,

at V

at VIL,

,

≥VCC-0.2V,

≥VCC-0.2V,

≤ 5.5V

≤ 5.5V

,

IH

address

,

SS

at

,

t
t
t

t
t
t

t
t
t

t
t
t

= 35ns
= 40ns
= 50ns

= 35ns
= 40ns
= 50ns

= 35ns
= 40ns
= 50ns

= 35ns
= 40ns
= 50ns

Min. Typ Max. Unit Notes

-10 +10

-10 +10

160
145
125

4 mA

160
145
125

160
145
125

160
145
125

1 mA

µA

µA

mA 1,2

mA 2

mA 1,2

mA 1

≥VCC-0.2V,

All other inputs V

V
V
V
V
V

Supply Voltage 3.0 3.6 V

CC

Input Low Voltage -0.3 0.8 V 3

IL

Input High Voltage 2.0V VCC+0.3 V 3

IH

Output Low Voltage IOL = 2mA 0.4 V

OL

Output High Voltage IOH = -2mA 2.4 V

OH

SS

Notes:

1.I

is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with

CC

the output open.

2.ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of
one transition per address cycle in random Read/Write and EDO Fast Page Mode.

3.Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to –0.3V for a period
not to exceed 20ns. All AC parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC.

AC Characteristics

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

- 5 -

G-Link Technology Corporation,Taiwan

6F, No. 24-2, Industry E, RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

G-LINK

CAS

RAS

RAS

OE

256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

TA = 0°C to 70°C , VCC = 3.3 V ± 10% VIH/VIL = 2.0/0.8V , VOH/VOL = 2.0/0.8V

GLT440L16

Aug. 2000 (Rev.1.1)

An initial pause of 100 µs and 8

-before-

or

-only refresh cycles are required after power-up.

35 40 50

Parameter Symbol Min. Max. Min. Max. Min. Max. Unit Notes

Read or Write Cycle Time
Read Modify write Cycle Time

RAS Precharge Time
RAS Pulse Width

Access Time from RAS
Access Time from CAS

Access Time from Column Address

CAS to Output Low-Z
CAS to Output High-Z
RAS Hold Time
RAS Hold Time Referenced to
CAS Hold Time
CAS Pulse width
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Precharge Time

Row Address Set-Up Time
Row Address Hold Time
Column Address Set-Up Time
Column Address Hold Time

Column Address to RAS Lead Time
Column Address Hold Time Referenced to RAS

Read Command Set-Up Time
Read Command Hold Time Referenced to CAS

Read Command Hold Time Referenced to RAS
Write Command Set-Up Time

Write Command Hold Time
Write Command Pulse Width

Write Command to RAS Lead Time

t

RC

t

RWC

t

RP

t

RAS

t

RAC

t

CAC

t

AA

t

CLZ

t

CEZ

t

RSH

t

ROH

t

CSH

t

CAS

t

RCD

t

RAD

t

CRP

t

ASR

t

RAH

t

ASC

t

CAH

t

RAL

t

AR

t

RCS

t

RCH

t

RRH

t

WCS

t

WCH

t

WP

t

RWL

70 75 90 ns
90 93 109 ns
25 25 30 ns

35 75k 40 100k 50 100k ns

35 40 50 ns 1,2,3
11 12 13 ns 1,5,10
18 20 25 ns 1,5,6

0 0 0 ns
3 8 3 8 3 8 ns

10 12 14 ns

7 8 9 ns

34 34 45 ns

6 6 8 ns
13 24 18 28 19 37 ns
10 17 13 20 14 25 ns 7

5 5 5 ns

0 0 0 ns

6 8 9 ns

0 0 0 ns

5 6 7 ns
18 20 25 ns

25 34 44 ns

0 0 0 ns

0 0 0 ns 4

0 0 0 ns 4

0 0 0 ns 8,9

5 6 7 ns

5 6 7 ns
10 12 13 ns

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation,Taiwan

6F, No. 24-2, Industry E, RD, IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 6 -