G-LINK GLT44016-50TC, GLT44016-40TC, GLT44016-35TC, GLT44016-30TC, GLT44016-30J4 Datasheet

G-LINK

CAS

RAS

CAS

RAS

CAS

RAS

CAS

256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

Features : Description :

GLT44016

Aug, 2000(Rev.3.1)

∗ 262,144 words by 16 bits organization.
∗ Fast access time and cycle time.

∗ Dual

Input.

∗ Low power dissipation.
∗ Read-Modify-Write,

-Before-

Refresh and Test Mode Capability.

Refresh, Hidden

-Only Refresh,

∗ 512 refresh cycles per 8ms.
∗ Available in 40-Pin 400 mil SOJ and 40/44

Pin TSOP(II)

∗ Single 5.0V±10% Power Supply.
∗ All inputs and Outputs are TTL

compatible.

∗ Extended Data-Out(EDO) Page Mode

operation.

The GLT44016 is a 262,144 x 16 bit
high-performance CMOS dynamic random
access memory. The GLT44016 offers Fast
Page mode with Extended Data Output, and
has both BYTE WRITE and WORD WRITE

access cycles via two

pins. The
GLT44016 has symmetric address and
accepts 512-cycle refresh in 8ms interval.

All inputs are TTL compatible. EDO
Page Mode operation allows random access
up to 512 x 16 bits within a page, with cycle
times as short as 10ns.

The GLT44016 is best suited for
graphics, and DSP applications requiring
high performance memories.

HIGH PERFORMANCE 25 28 30 35 40 50

Max.

Access Time, (t

RAC

)

Max. Column Address Access Time, (t

) 13 ns 13 ns 16 ns 18 ns 20 ns 25 ns

CAA

25 ns 28 ns 30 ns 35 ns 40 ns 50 ns

Min. Extended Data Out Page Mode Cycle Time, (tPC) 10 ns 10 ns 12 ns 13 ns 15 ns 20 ns
Min. Read/Write Cycle Time, (tRC) 45 ns 45 ns 60 ns 65 ns 70 ns 85 ns

Max.

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

Access Time (t

CAC

)

8 ns 8 ns 10 ns 11 ns 12 ns 14 ns

G-Link Technology Corporation,Taiwan

6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

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G-LINK

RAS

UCAS

LCAS

WE

OE

Pin Configuration :

GLT44016

256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

Aug, 2000(Rev.3.1)

Pin Descriptions:

GLT44016

SOJ Top View

TSOP(Type II)

Top View

Name Function

A0 - A

DQ1 - DQ
V
V

8

16
CC
SS

NC No Connection

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

Address Inputs
Row Address Strobe

Column Address Strobe/Upper Byte Control
Column Address Strobe/Lower Byte Control
Write Enable
Output Enable
Data Inputs / Outputs

+5V Power Supply
Ground

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G-LINK

RAS,LCAS

UCAS

OE

CAS

UCAS

LCAS

CAS

RAS

RAS

.

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

I/O8

I/O9

I/O12

I/O13

I/O16

256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

Absolute Maximum Ratings* Capacitance*

TA=25°C, VCC=5V±10%, VSS=0V

GLT44016

Aug, 2000(Rev.3.1)

Operating Temperature, TA (ambient)

Symbol

.......................................-0°C to +70°C

C

Storage Temperature(plastic)....-55°C to +150°C

Voltage Relative to VSS...............-1.0V to + 7.0V

IN1

C

IN2

Short Circuit Output Current......................50mA

C

Power Dissipation......................................1.0W

*Note:Operation above Absolute Maximum Ratings can

OUT

*Note: Capacitance is sampled and not 100% tested

abversely affect device reliability.

Electrical Specifications

l

l All voltages are referenced to GND.
l After power up, wait more than 100µs and then, execute eight

means

and

.

refresh cycles as dummy cycles to initialize internal circuit.

Block Diagram :

OE

WE

UCAS

LCAS
RAS

RAS

CLOCK

GENERATOR

CAS

CLOCK

GENERATOR

WE

GENERATOR

Parameter

Address Input

,

Data Input/Output

-before-

CLOCK

OE

GENERATOR

,WE,

CLOCK

or

Max.

5
7
7

Unit

pF
pF
pF

-only

V

CC

V

SS

REFRESH

COUNTER

9

A

0

A

1

.

A

7

A

8

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

ADDRESS BUFFERS

AND PREDECODERS

X0 - x

Y0 - Y

8

Data I/O BUS

COLUMN DECODERS

SENSE AMPLIFIERS

8

DECODERS

ROW

512 × 16

MEMORY

512

G-Link Technology Corporation,Taiwan

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Industrial Park, Hsin Chu, Taiwan.

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I/O

BUFFER

I/O10

ARRAY

G-LINK

RAS

UCAS

LCAS

UCAS

LCAS

UCAS

LCAS

Truth Table: GLT44016

GLT44016

256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

Aug, 2000(Rev.3.1)

Function

RAS CASL CASH WE OE

Stanby H

H→X H→X

X X High-Z

ADDRESS DQs Notes

Read: Word L L L H L ROW/COL Data Out
Read: Lower Byte L L H H L ROW/COL Lower Byte,Data-Out

Upper Byte,High-Z

Read: Upper Byte L H L H L ROW/COL Lower Byte,High-Z

Upper Byte,Data-Out

Write: Word(Early

L L L L X ROW/COL Data-In

Write)

Write: Lower Byte

(Early)

Write: Upper Byte

(Early)

Read Write L L L
EDO-Page­Mode Read

EDO-Page­Mode Write

1st Cycle
2nd Cycle

1st Cycle
2nd Cycle

L L H L X ROW/COL Lower Byte,Data-In

Upper Byte,High-Z

L H L L X ROW/COL Lower Byte,High-Z

Upper Byte,Data-In

H→L L→H

L
L

L
L

H→L
H→L
H→L
H→L

H→L
H→L
H→L
H→L

H
H

L
L

ROW/COL Data-Out,Data-In 1,2

L

ROW/COL

L

COL

XXROW/COL

COL

Data-Out
Data-Out

Data-In
Data-In

1
1

2
2

EDO-Page-

1st Cycle

L

H→L

H→L

H→L

Mode Read­Write

Hidden

2nd Cycle
Read

L

L→H→L

H→L

L

H→L

L

H→L

H

Refresh

-Only Refresh

CBR Refresh

Write

L→H→L

L H H X X ROW High-Z

H→L

L

L

L

L L X X High-Z 4

Notes:

1. These READ cycles may also be BYTE READ cycles (either

2. These WRITE cycles may also be BYTE READ cycles (either

3. EARLY WRITE only.

4. At least one of the two CAS signals must be active (

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L

X

ROW/COL

COL

ROW/COL

ROW/COL

L→H

L→H

or

or

or

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6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

).

Data-Out,Data-In

Data-Out,Data-In
Data-Out

Data-In

active).

active).

1,2

1,2

1

2,3

G-LINK

RAS, UCAS

LCAS

RAS

RAS

UCAS

LCAS

RAS

UCAS

LCAS

CAS

RAS

RAS, UCAS

LCAS

RAS

UCAS

LCAS

256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

DC and Operating Characteristics (1-2)

TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified.

GLT44016

Aug, 2000(Rev.3.1)

Sym. Parameter Test Conditions Access

Time

I

I

I

I

I

I

I

I

Input Leakage Current

LI

(any input pin)

Output Leakage Current

LO

(for High-Z State)
Operating Current,

CC1

Random READ/WRITE tRC = tRC (min.)

Standby Current,(TTL)

CC2

Refresh Current,

CC3

-Only

Operating Current,

CC4

EDO Page Mode

Refresh Current,

CC5

Before

Standby Current, (CMOS)

CC6

0V ≤ V

≤ 5.5V

IN

(All other pins not under
test=0V)

0V ≤ V

out

≤ 5.5V

Output is disabled (Hiz)

,

at V

other inputs ≥V

cycling,

at V

SS

,

IH

tRC = tRC (min.)

at VIL,

,

address cycling:tPC=tPC(min.)

,
address cycling:
tRC=tRC (min.)

≥VCC-0.2V,

≥VCC-0.2V,

t

= 25ns

RAC

t

= 28ns

RAC

t

= 30ns

RAC

t

= 35ns

RAC

t

= 40ns

RAC

t

= 50ns

RAC

IH

t

= 25ns

RAC

t

= 28ns

RAC

t

= 30ns

RAC

t

= 35ns

RAC

t

= 40ns

RAC

t

= 50ns

RAC

t

= 25ns

RAC

t

= 28ns

RAC

t

= 30ns

RAC

t

= 35ns

RAC

t

= 40ns

RAC

t

= 50ns

RAC

t

= 25ns

RAC

t

= 28ns

RAC

t

= 30ns

RAC

t

= 35ns

RAC

t

= 40ns

RAC

t

= 50ns

RAC

Min. Typ Max. Unit Notes

-10 +10

-10 +10

270
270
250
210
190
170

270
270
250
210
190
170
270
270
250
210
190
170
270
270
250
210
190
170

µA

µA

mA 1,2

4 mA

mA 2

mA 1,2

mA 1

2 mA

≥VCC-0.2V,

All other inputs V

V
V
V
V

Input Low Voltage -1 +0.8 V 3

IL

Input High Voltage 2.4 VCC+1 V 3

IH

Output Low Voltage IOL = 4.2mA 0.4 V

OL

Output High Voltage IOH = -5.0mA 2.4 V

OH

SS

Notes:

1.ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open.

2.ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle in
random Read/Write and EDO Fast Page Mode.

3.Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not to exceed 20ns. All AC
parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC.

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation,Taiwan

6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

- 5 -

G-LINK

CAS

RAS

RAS

256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

AC Characteristics

TA = 0°C to 70°C , VCC = 5 V ± 10%, VIH/VIL = 2.4/0.8 V, VOH/VOL = 2.0/0.8V

GLT44016

Aug, 2000(Rev.3.1)

An initial pause of 100 µs and 8

-before-

or

-only refresh cycles are required after power-up.

25 28 30 35 40 50

Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes

Read or Write Cycle Time t
Read Modify Write Cycle Time t

RAS Precharge Time
RAS Pulse Width

Access Time from RAS
Access Time from CAS

Access Time from Column Address t

CAS to Output Low-Z
CAS to Output High-Z
RAS Hold Time
RAS Hold Time Referenced to OE
CAS Hold Time
CAS Pulse Width
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Precharge Time

Row Address Set-Up Time t
Row Address Hold Time t
Column Address Set-Up Time t
Column Address Hold Time t
Column Address to RAS Lead Time t

Column Address Hold Time Referenced to RAS
Read Command Set-Up Time t

Read Command Hold Time Referenced to CAS
Read Command Hold Time Referenced to RAS

Write Command Set-Up Time t
Write Command Hold Time t
Write Command Pulse Width t

Write Command to RAS Lead Time
Write Command to CAS Lead Time

RC

RWC

t

RP

t

RAS

t

RAC

t

CAC

AA

t

CLZ

t

CEZ

t

RSH

t

ROH

t

CSH

t

CAS

t

RCD

t

RAD

t

CRP

ASR

RAH

ASC

CAH

RAL

t

AR

RCS

t

RCH

t

RRH

WCS

WCH

WP

t

RWL

t

CWL

45 45 60 65 70 85 ns
67 67 79 86 91 106 ns
15 15 25 25 25 30 ns
25 100k 28 100k 30 100k 35 100k 40 100k 50 100k ns

25 28 30 35 40 50 ns 1,2,3

8 8 10 11 12 14 ns 1,5,10

13 13 16 18 20 25 ns 1,5,6

0 0 0 0 0 0 ns
0 5 0 5 3 7 3 8 3 8 3 8 ns
7 7 7 8 8 8 ns
4 4 7 8 8 8 ns

25 25 25 30 35 42 ns

4 4 4.5 5 6 8 ns

10 17 10 17 10 20 11 24 12 28 13 36 ns

8 12 8 12 8 14 9 17 10 20 11 25 ns 7
5 5 5 5 5 5 ns
0 0 0 0 0 0 ns
4 4 6 7 8 9 ns
0 0 0 0 0 0 ns
4 4 5 6 6 7 ns

13 13 16 18 20 25 ns
19 19 25 30 34 35 ns

0 0 0 0 0 0 ns
0 0 0 0 0 0 ns 4
0 0 0 0 0 0 ns 4
0 0 0 0 0 0 ns 8,9
4 4 5 6 6 6 ns
4 4 5 6 6 6 ns
7 7 7 8 8 8 ns
5 5 6 7 7 7 ns

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation,Taiwan

6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.

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