G-LINK GLT44016-50TC, GLT44016-40TC, GLT44016-35TC, GLT44016-30TC, GLT44016-30J4 Datasheet
...
G-LINK
CAS
RAS
CAS
RAS
CAS
RAS
CAS
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Features : Description :
GLT44016
Aug, 2000(Rev.3.1)
∗ 262,144 words by 16 bits organization.
∗ Fast access time and cycle time.
∗ Dual
Input.
∗ Low power dissipation.
∗ Read-Modify-Write,
-Before-
Refresh and Test Mode Capability.
Refresh, Hidden
-Only Refresh,
∗ 512 refresh cycles per 8ms.
∗ Available in 40-Pin 400 mil SOJ and 40/44
Pin TSOP(II)
∗ Single 5.0V±10% Power Supply.
∗ All inputs and Outputs are TTL
compatible.
∗ Extended Data-Out(EDO) Page Mode
operation.
The GLT44016 is a 262,144 x 16 bit
high-performance CMOS dynamic random
access memory. The GLT44016 offers Fast
Page mode with Extended Data Output, and
has both BYTE WRITE and WORD WRITE
access cycles via two
pins. The
GLT44016 has symmetric address and
accepts 512-cycle refresh in 8ms interval.
All inputs are TTL compatible. EDO
Page Mode operation allows random access
up to 512 x 16 bits within a page, with cycle
times as short as 10ns.
The GLT44016 is best suited for
graphics, and DSP applications requiring
high performance memories.
HIGH PERFORMANCE 25 28 30 35 40 50
Max.
Access Time, (t
RAC
)
Max. Column Address Access Time, (t
) 13 ns 13 ns 16 ns 18 ns 20 ns 25 ns
CAA
25 ns 28 ns 30 ns 35 ns 40 ns 50 ns
Min. Extended Data Out Page Mode Cycle Time, (tPC) 10 ns 10 ns 12 ns 13 ns 15 ns 20 ns
Min. Read/Write Cycle Time, (tRC) 45 ns 45 ns 60 ns 65 ns 70 ns 85 ns
Max.
G-Link Technology Corporation
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Access Time (t
CAC
)
8 ns 8 ns 10 ns 11 ns 12 ns 14 ns
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Industrial Park, Hsin Chu, Taiwan.
- 1 -
G-LINK
RAS
UCAS
LCAS
WE
OE
Pin Configuration :
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Pin Descriptions:
GLT44016
SOJ Top View
TSOP(Type II)
Top View
Name Function
A0 - A
DQ1 - DQ
V
V
8
16
CC
SS
NC No Connection
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
Address Inputs
Row Address Strobe
Column Address Strobe/Upper Byte Control
Column Address Strobe/Lower Byte Control
Write Enable
Output Enable
Data Inputs / Outputs
+5V Power Supply
Ground
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G-LINK
RAS,LCAS
UCAS
OE
CAS
UCAS
LCAS
CAS
RAS
RAS
.
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O12
I/O13
I/O16
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Absolute Maximum Ratings* Capacitance*
TA=25°C, VCC=5V±10%, VSS=0V
GLT44016
Aug, 2000(Rev.3.1)
Operating Temperature, TA (ambient)
Symbol
.......................................-0°C to +70°C
C
Storage Temperature(plastic)....-55°C to +150°C
Voltage Relative to VSS...............-1.0V to + 7.0V
IN1
C
IN2
Short Circuit Output Current......................50mA
C
Power Dissipation......................................1.0W
*Note:Operation above Absolute Maximum Ratings can
OUT
*Note: Capacitance is sampled and not 100% tested
abversely affect device reliability.
Electrical Specifications
l
l All voltages are referenced to GND.
l After power up, wait more than 100µs and then, execute eight
means
and
.
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
OE
WE
UCAS
LCAS
RAS
RAS
CLOCK
GENERATOR
CAS
CLOCK
GENERATOR
WE
GENERATOR
Parameter
Address Input
,
Data Input/Output
-before-
CLOCK
OE
GENERATOR
,WE,
CLOCK
or
Max.
5
7
7
Unit
pF
pF
pF
-only
V
CC
V
SS
REFRESH
COUNTER
9
A
0
A
1
.
A
7
A
8
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ADDRESS BUFFERS
AND PREDECODERS
X0 - x
Y0 - Y
8
Data I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
8
DECODERS
ROW
512 × 16
MEMORY
512
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I/O
BUFFER
I/O10
ARRAY
G-LINK
RAS
UCAS
LCAS
UCAS
LCAS
UCAS
LCAS
Truth Table: GLT44016
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Function
RAS CASL CASH WE OE
Stanby H
H→X H→X
X X High-Z
ADDRESS DQs Notes
Read: Word L L L H L ROW/COL Data Out
Read: Lower Byte L L H H L ROW/COL Lower Byte,Data-Out
Upper Byte,High-Z
Read: Upper Byte L H L H L ROW/COL Lower Byte,High-Z
Upper Byte,Data-Out
Write: Word(Early
L L L L X ROW/COL Data-In
Write)
Write: Lower Byte
(Early)
Write: Upper Byte
(Early)
Read Write L L L
EDO-PageMode Read
EDO-PageMode Write
1st Cycle
2nd Cycle
1st Cycle
2nd Cycle
L L H L X ROW/COL Lower Byte,Data-In
Upper Byte,High-Z
L H L L X ROW/COL Lower Byte,High-Z
Upper Byte,Data-In
H→L L→H
L
L
L
L
H→L
H→L
H→L
H→L
H→L
H→L
H→L
H→L
H
H
L
L
ROW/COL Data-Out,Data-In 1,2
L
ROW/COL
L
COL
XXROW/COL
COL
Data-Out
Data-Out
Data-In
Data-In
1
1
2
2
EDO-Page-
1st Cycle
L
H→L
H→L
H→L
Mode ReadWrite
Hidden
2nd Cycle
Read
L
L→H→L
H→L
L
H→L
L
H→L
H
Refresh
-Only Refresh
CBR Refresh
Write
L→H→L
L H H X X ROW High-Z
H→L
L
L
L
L L X X High-Z 4
Notes:
1. These READ cycles may also be BYTE READ cycles (either
2. These WRITE cycles may also be BYTE READ cycles (either
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (
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L
X
ROW/COL
COL
ROW/COL
ROW/COL
L→H
L→H
or
or
or
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).
Data-Out,Data-In
Data-Out,Data-In
Data-Out
Data-In
active).
active).
1,2
1,2
1
2,3
G-LINK
RAS, UCAS
LCAS
RAS
RAS
UCAS
LCAS
RAS
UCAS
LCAS
CAS
RAS
RAS, UCAS
LCAS
RAS
UCAS
LCAS
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified.
GLT44016
Aug, 2000(Rev.3.1)
Sym. Parameter Test Conditions Access
Time
I
I
I
I
I
I
I
I
Input Leakage Current
LI
(any input pin)
Output Leakage Current
LO
(for High-Z State)
Operating Current,
CC1
Random READ/WRITE tRC = tRC (min.)
Standby Current,(TTL)
CC2
Refresh Current,
CC3
-Only
Operating Current,
CC4
EDO Page Mode
Refresh Current,
CC5
Before
Standby Current, (CMOS)
CC6
0V ≤ V
≤ 5.5V
IN
(All other pins not under
test=0V)
0V ≤ V
out
≤ 5.5V
Output is disabled (Hiz)
,
at V
other inputs ≥V
cycling,
at V
SS
,
IH
tRC = tRC (min.)
at VIL,
,
address cycling:tPC=tPC(min.)
,
address cycling:
tRC=tRC (min.)
≥VCC-0.2V,
≥VCC-0.2V,
t
= 25ns
RAC
t
= 28ns
RAC
t
= 30ns
RAC
t
= 35ns
RAC
t
= 40ns
RAC
t
= 50ns
RAC
IH
t
= 25ns
RAC
t
= 28ns
RAC
t
= 30ns
RAC
t
= 35ns
RAC
t
= 40ns
RAC
t
= 50ns
RAC
t
= 25ns
RAC
t
= 28ns
RAC
t
= 30ns
RAC
t
= 35ns
RAC
t
= 40ns
RAC
t
= 50ns
RAC
t
= 25ns
RAC
t
= 28ns
RAC
t
= 30ns
RAC
t
= 35ns
RAC
t
= 40ns
RAC
t
= 50ns
RAC
Min. Typ Max. Unit Notes
-10 +10
-10 +10
270
270
250
210
190
170
270
270
250
210
190
170
270
270
250
210
190
170
270
270
250
210
190
170
µA
µA
mA 1,2
4 mA
mA 2
mA 1,2
mA 1
2 mA
≥VCC-0.2V,
All other inputs V
V
V
V
V
Input Low Voltage -1 +0.8 V 3
IL
Input High Voltage 2.4 VCC+1 V 3
IH
Output Low Voltage IOL = 4.2mA 0.4 V
OL
Output High Voltage IOH = -5.0mA 2.4 V
OH
SS
Notes:
1.ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open.
2.ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle in
random Read/Write and EDO Fast Page Mode.
3.Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not to exceed 20ns. All AC
parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC.
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
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G-LINK
CAS
RAS
RAS
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
AC Characteristics
TA = 0°C to 70°C , VCC = 5 V ± 10%, VIH/VIL = 2.4/0.8 V, VOH/VOL = 2.0/0.8V
GLT44016
Aug, 2000(Rev.3.1)
An initial pause of 100 µs and 8
-before-
or
-only refresh cycles are required after power-up.
25 28 30 35 40 50
Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Read or Write Cycle Time t
Read Modify Write Cycle Time t
RAS Precharge Time
RAS Pulse Width
Access Time from RAS
Access Time from CAS
Access Time from Column Address t
CAS to Output Low-Z
CAS to Output High-Z
RAS Hold Time
RAS Hold Time Referenced to OE
CAS Hold Time
CAS Pulse Width
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Precharge Time
Row Address Set-Up Time t
Row Address Hold Time t
Column Address Set-Up Time t
Column Address Hold Time t
Column Address to RAS Lead Time t
Column Address Hold Time Referenced to RAS
Read Command Set-Up Time t
Read Command Hold Time Referenced to CAS
Read Command Hold Time Referenced to RAS
Write Command Set-Up Time t
Write Command Hold Time t
Write Command Pulse Width t
Write Command to RAS Lead Time
Write Command to CAS Lead Time
RC
RWC
t
RP
t
RAS
t
RAC
t
CAC
AA
t
CLZ
t
CEZ
t
RSH
t
ROH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
ASR
RAH
ASC
CAH
RAL
t
AR
RCS
t
RCH
t
RRH
WCS
WCH
WP
t
RWL
t
CWL
45 45 60 65 70 85 ns
67 67 79 86 91 106 ns
15 15 25 25 25 30 ns
25 100k 28 100k 30 100k 35 100k 40 100k 50 100k ns
25 28 30 35 40 50 ns 1,2,3
8 8 10 11 12 14 ns 1,5,10
13 13 16 18 20 25 ns 1,5,6
0 0 0 0 0 0 ns
0 5 0 5 3 7 3 8 3 8 3 8 ns
7 7 7 8 8 8 ns
4 4 7 8 8 8 ns
25 25 25 30 35 42 ns
4 4 4.5 5 6 8 ns
10 17 10 17 10 20 11 24 12 28 13 36 ns
8 12 8 12 8 14 9 17 10 20 11 25 ns 7
5 5 5 5 5 5 ns
0 0 0 0 0 0 ns
4 4 6 7 8 9 ns
0 0 0 0 0 0 ns
4 4 5 6 6 7 ns
13 13 16 18 20 25 ns
19 19 25 30 34 35 ns
0 0 0 0 0 0 ns
0 0 0 0 0 0 ns 4
0 0 0 0 0 0 ns 4
0 0 0 0 0 0 ns 8,9
4 4 5 6 6 6 ns
4 4 5 6 6 6 ns
7 7 7 8 8 8 ns
5 5 6 7 7 7 ns
G-Link Technology Corporation
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G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
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G-LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
AC Characteristics
25 28 30 35 40 50
Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Data Set-Up Time t
Data Hold Time t
Data Hold Time Referenced to RAS
RAS to WEE Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
RAS to CAS Precharge Time
Access Time from CAS Precharge
EDO Page Mode Cycle Time t
EDO Page Mode Read-Modify-Write Cycle Time t
CAS Precharge Time (EDO Page Mode)
RAS Pulse Width (EDO Page Mode Only)
Access Time from OE
OE to Data Delay Time
OE to Output High-Z
OE Command Hold Time
Data Output Hold after CAS low
RAS to Output High-Z
WE to Output High-Z
OE to CAS Hold Time
CAS Hold Time to OE
OE Precharge Time
CAS Set-Up Time for CAS -before-RAS Cycle
CAS Hold Time for CAS -before-RAS Cycle
Transition Time t
Refresh Period
DS
DH
t
DHR
t
RWD
t
CWD
t
AWD
t
RPC
t
CPA
PC
PRWC
t
CP
t
RASP
t
OEA
t
OED
t
OEZ
t
OEH
t
DOH
t
REZ
t
WEZ
t
OCH
t
CHO
t
OEP
t
CSR
t
CHR
T
t
REF
0 0 0 0 0 0 0 0 ns
4 4 7 8 8 8 ns
19 19 27 32 36 37 ns
36 36 43 49 54 64 ns
19 19 21 23 24 26 ns
24 24 27 30 32 37 ns
0 0 0 0 0 0 ns
15 15 18 20 22 27 ns
10 10 12 13 15 20 ns
35 35 39 43 45 50 ns
3 3 4.5 5 6 8 ns
25 100k 28 100k 30 100K 35 100k 40 100k 50 100k ns
8 8 10 11 12 14 ns
5 5 7 8 8 8 ns
3 7 3 7 3 7 3 8 3 8 0 8 ns
5 5 6 6 7 7 ns
4 4 5 5 5 5 ns
3 7 3 7 3 7 3 8 3 8 3 8 ns
3 10 3 10 3 10 3 10 3 10 3 12 ns
8 8 8 8 8 8 ns
8 8 8 8 8 8 ns
8 8 8 8 8 8 ns
5 5 10 10 10 10 ns
6 6 7 8 8 10 ns
1.5 50 1.5 50 1.5 50 1.5 50 1.5 50 2 50 ns
8 8 8 8 8 8 ms
G-Link Technology Corporation
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Industrial Park, Hsin Chu, Taiwan.
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G-LINK
CAS
WE
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Notes:
1. Measure with a load equivalent to one TTL inputs and 50 pF.
2. Assumes that t
dominant.
3. Assumes that t
controlled by t
4. Either t
RRH
or t
5. Access time is determined by the longest of t
6. Assumes that t
7. Operation within the t
is specified as a reference point only. If t
limit, the access time is controlled by t
8. t
9. t
, t
WCS
WCS
, t
RWD
AWD
(min.) must be satisfied in an Early Write Cycle.
10. tDS and tDH are referenced to the latter occurrence of
tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 1.5 ns.
≤ t
RCD
≤ t
RAD
.
CAC
must be satisfied for a Read Cycle.
RCH
≥ t
RAD
and t
(max.). If t
RCD
(max.). If t
RAD
(max.).
RAD
(max.) limit ensures that t
RAD
are not restrictive operating parameters.
CWD
is greater than t
RCD
is greater than t
RAD
CAA
is greater than the specified t
RAD
and t
CAA
, t
CAC
(max.), access time will be t
RCD
(max.), access time will be
RCD
and t
CAC
(max.) can be met. t
RAC
CPA
.
.
of
.
GLT44016
Aug, 2000(Rev.3.1)
(max.)
RAD
(max.)
RAD
AA
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G-LINK
t
t
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Read Cycle
VIH-
RAS
VIL-
VIH-
CAS
VIL-
WE
OE
DQ
VIH-
VIL-
VIH-
VIL-
VIH-
VIL-
VOH-
VOL-
Address
Early Write Cycle NOTE : D
VIH-
RAS
VIL-
tCRP
tASR tRAH
ROW
ADDRESS
= Open
OUT
tRAS
tCSH
tRCD tRSH
tRAD
tRCS
tASC
tAR
tCAH
COLUMN
ADDRESS
tRAC
tRAS
tAA
tCLZ
tRAL
t
tCAC
RC
OEA
RC
tCAS
tOEZ
DATA-OUT
tRP
tRP
tRRH
tCRP
tRCH
t
CEZ
Don't Care
VIH-
CAS
VIL-
DQ
WE
OE
VIH-
VIL-
VIH-
VIL-
VIH-
VIL-
VIH-
VIL-
Address
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tCRP
tASR
tRAH
ROW
ADDRESS
tCSH
tRCD tRSH
tRAD
tASC
tWCS
tDHR
tDS tDH
COLUMN
ADDRESS
tAR
DATA - IN
tCAH
tCWL
tWCR
- 9 -
tCRP
tCAS
tRAL
tRWL
tWCH
tWP
Don't Care
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G-LINK
t
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Late Write Cycle ( OE Controlled Write) NOTE : D
V
IH-
RAS
V
IL-
t
CAS
Address
WE
OE
CRP
IH-
V
V
IL-
t
ASR
t
V
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
RAH
ROW
ADDRESS
t
RAD
t
t
RCS
ASC
t
RCD
t
OED
t
V
IH-
DQ
V
IL-
Read - Modify - Write Cycle
V
IH-
RAS
V
IL-
= Open
OUT
t
t
CSH
COLUMN
ADDRESS
DS
COLUMN
ADDRESS
RAS
t
RC
t
RSH
t
CAS
t
RAL
t
CAH
t
CWL
t
RWL
t
WP
t
OEH
t
DH
RC
t
RAS
t
RP
t
CRP
Don't Care
t
RP
V
IH-
CAS
V
IL-
V
DQ
WE
OE
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
V
I/OH-
V
I/OL-
Address
G-Link Technology Corporation
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t
CRPtRCD
t
RAD
t
ASR
ASC
t
t
RAH
ROW
ADDR.
COLUMN
ADDRESS
t
AA
t
RAC
t
t
RSH
t
CAS
t
CSH
CAH
t
t
AWD
t
CWD
t
OEA
t
t
CAC
VALID
DATA-OUT
OED
t
t
OEZ
t
CLZ
DS
t
t
DH
VALID
DATA-IN
t
RWL
t
CWL
WP
CRP
Don't Care
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G-LINK
t
t
t
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Fast Page Read Cycle
VIH-
RAS
VIL-
tCRP
VIH-
CAS
VIL-
tASR
WE
OE
DQ
VIH-
VIL-
VIH-
VIL-
VIH-
VIL-
V
VIL-
ADDR.
IH-
Address
Fast Page Write Cycle NOTE : D
VIH-
RAS
VIL-
tCRP tRCD tCAS
VIH-
CAS
VIL-
tASR
Address
WE
OE
VIH-
VIL-
VIH-
V
VIH-
VIL-
IL-
ROW
ADDR.
ROW
OUT
tRCD tCAS
tRAD
tRAH
tASC
ADDRESS
tRCS
tRAC
tCLZ
= Open
tRAD
tRAH
tASC
COLUMN
ADDRESS
tWCS
tDS tDS tDStDH
tPC tPC
tCP tCP
tCSH
tCAH
COLUMN
tRCH
ASC
t
COLUMN
ADDRESS
tRCS tRCS
tCAC
tOEA
AA
t
DATA-UOT
VALID
tOFF
tOEZ
tAA
tPC
tCP tCP
tCSH
tCAH
tASC tASC
COLUMN
ADDRESS
tWCH tWCS tWCStWCH
tWP
tWP tWP
tCWL
RASP
tCAS
tCAS
tCAH tCAH
tASC
COLUMN
ADDRESS
tCAC
tOEA
tAA
CLZ
t
RASP
VALID
DATA-UOT
tCLZ
OEZ
t
tRHCP
tPC
tCAS
tCAS
tCAH tCAH
COLUMN
ADDRESS
tWCH
tCWL tCWL
tDS
tDS
tRSH
VALID
DATA-UOT
tRSH
OEZtOFF
t
tRWL
t
tRCH
OFF
tRP
tRRH
Don't Care
RP
VIH-
DQ
VIL-
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
Don't Care
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 11 -
G-LINK
t
t
t
t
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Fast Page Mode Late Write Cycle
VIH-
RAS
VIL-
tCRP tRCD tCAS
VIH-
CAS
VIL-
tRAD
tASR tRAH
Address
VIH-
VIL-
ROW
ADDR.
tRCS
VIH-
WE
V
IL-
VIH-
OE
VIL-
tOED
DQ
VIH-
VIL-
Hi-Z Hi-Z Hi-Z
Fast Page Read - Modify - Write Cycle
VIH-
RAS
VIL-
tRCD tCAS tCP tCAS
tRAD
tRAH
tCAH
tASC
ROW
ADDR.
COL.
ADDR.
tRCS
tRWD
tOEA
tCAC
tAA
tRAC
tCLZ tCLZ
CAS
Address
WE
OE
DQ
VIH-
VIL-
tASR
VIH-
VIL-
VIH-
VIL-
VIH-
VIL-
VI/OH-
VI/OL-
RASP
tCSH
tCP tCP
tCAS
tCAH
tASC
COLUMN
ADDRESS
tCWL tCWL
tWP
tCAH tCAH
tASC tASC
COLUMN
ADDRESS
tRCS tRCS tRWL
tWP
tOEH tOEH tOEH
tDH
tOED
tDH tOED
VALID
DATA-IN
RASP
tDS
VALID
DATA-IN
tDS
tCSH
tASC
COL.
ADDR.
tCWL
tCWD
tWP
tAWD
tDH
tOED
tDS
tOEZ
VALID
DATA-OUT
VALID
DATA-IN
tPC
tCAH
tOEA
tCAC
tAA
COLUMN
ADDRESS
tAWD
tCPWD
tRHCP
tWP
tDS
tDH
VALID
DATA-IN
tRSH
tPRWC
RAL
t
tCWD
tOED
tOEZ
VALID
DATA-OUT
tCAS
tRAL
tRSH
tCWL
tWP
OEH
t
tDH
VALID
DATA-IN
RP
tCRP
Don't Care
RP
tCRP
tRWL
tCWL
tDS
Don't Care
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 12 -
G-LINK
tRCt
tRCt
t
t
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
CAS
Before
RAS
Refresh Cycle
RAS
VIH-
VIL-
tCSR tCSRtCHR tCHRtRPC tRPC tCRP
VIH-
CAS
VIL-
RAS -Only Refresh Cycle
V
IH-
RAS
V
IL-
V
IH-
CAS
V
IL-
V
Address
IH-
V
IL-
Hidden Refresh Cycle ( Read )
V
IH-
RAS
V
IL-
tRAS
RC
RC
tRAS tRAS
tRP
tCRP
t
ASR
ROW ROW
RC
t
RAS
tASRtRAH t
tRAStRP
tRP
tRP
tRPC tCRP
RAH
t
RP
t
RAS
RC
t
RP
V
IH-
CAS
V
IL-
t
V
WE
OE
DQ
IH-
IL-
V
V
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
Address
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
t
CRP
ASRtCAH
ROW
ADDRESS
t
RAD
OPEN
t
t
RCD
RCS
t
t
RAC
ASC
COLUMN
ADDRESS
t
CAH
t
t
RAL
t
AA
t
CLZ
- 13 -
RSH
t
t
CAC
OEA
t
CHR
t
WHR
t
t
OEZ
DATA-OUT
OFF
Don't Care
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
G-LINK
t
t
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
Hidden Refresh Cycle ( Write ) NOTE : D
V
IH-
RAS
V
IL-
t
CAS
Address
WE
OE
DQ
CRP
V
IH-
V
IL-
t
ASCtCAH
V
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
V
IH-
V
IL-
ROW
ADDRESS
t
t
RAD
RCD
OUT
t
t
WCS
ASC
t
=Open
RAS
t
COLUMN
ADDRESS
DS
t
DATA-IN
CAH
RC
t
RSH
t
WCH
t
WP
t
DH
t
RP
t
CHR
t
RAS
RC
Don't Care
RP
t
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 14 -
G-LINK
GLT44016
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Aug, 2000(Rev.3.1)
CAS
- Before
RAS
RAS
CAS
Address
Read Cycle
Write Cycle
Read-Modify-Write
DQ
Refresh Counter Test Cycle
VIH-
VIL-
t
CSR
t
WRPtWRH
t
WRP
t
WRH
WE
OE
DQ
WE
OE
DQ
WE
OE
V
VIL-
VIH-
V
VIH-
VIL-
VIH-
V
VOH-
VOL-
VIH-
VIL-
VIH-
VIL-
VIH-
VIL-
VIH-
VIL-
V
VIL-
VI/OH-
VI/OL-
IH-
IL-
IL-
IH-
t
OPEN
CHR
t
WCS
t
RAS
t
CPT
t
ASC
COLUMN
ADDRESS
t
DS
VALID DATA-IN
t
RCS
t
CLZ
t
AA
t
t
t
t
t
CLZ
AA
CAC
t
t
CAC
OEA
t
RCS
t
AWD
CAH
t
t
CAS
OEA
t
RWL
t
CWL
t
WCH
WP
t
DH
t
CWD
t
t
VALID
DATA-OUT
t
RSH
t
RAL
VALID DATA-OUT
t
OED
OEZ
t
DS
VALID
DATA-IN
t
RP
t
RRH
t
RCH
t
t
OEZ
t
CWL
t
RWL
t
WP
DH
CEZ
Don't Care
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 15 -
G-LINK
Part Number
SPEED
POWER
FEATURE
PACKAGE
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Ordering Information
GLT44016-25J4 25ns Normal EDO 40L 400mil SOJ
GLT44016-28J4 28ns Normal EDO 40L 400mil SOJ
GLT44016-30J4 30ns Normal EDO 40L 400mil SOJ
GLT44016-35J4 35ns Normal EDO 40L 400mil SOJ
GLT44016-40J4 40ns Normal EDO 40L 400mil SOJ
GLT44016-50J4 50ns Normal EDO 40L 400mil SOJ
GLT44016-25TC 25ns Normal EDO 44L 400mil TSOP
GLT44016-28TC 28ns Normal EDO 44L 400mil TSOP
GLT44016-30TC 30ns Normal EDO 44L 400mil TSOP
GLT44016-35TC 35ns Normal EDO 44L 400mil TSOP
GLT44016-40TC 40ns Normal EDO 44L 400mil TSOP
GLT44016-50TC 50ns Normal EDO 44L 400mil TSOP
Parts Numbers (Top Mark) Definition :
GLT44016
Aug, 2000(Rev.3.1)
GLT 4 40 16 - 40 J4
4 : DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)*
11 : 1M(C/FPM)*
12 : 1M(H/EDO)*
13 : 1M(H/FPM)*
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
*See note
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
VOLTAGE
Blank : 5V
L : 3.3V
M : Mix Voltage
SPEED
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
25 : 25ns
30 : 30ns
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
PACKAGE
T : PDIP(300mil)
TS : TSOP(Type I)
TC : TSOP(Type ll)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
TQ : TQFP
Note : CÙCDROM , HÙHDD.
Example :
1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type.
2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type.
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
- 16 -
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
G-LINK
256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Package Information
40/44 Lead Thin Small Outline Package SOJ
GLT44016
Aug, 2000(Rev.3.1)
40/44 Lead Thin Small Outline Package TSOP(Type II)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 17 -
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