G-LINK GLT4160L16-40TC, GLT4160L16-40J4, GLT4160L16-35TC, GLT4160L16-35J4, GLT4160L16-60TC Datasheet
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G-LINK
GLT4160L16
1M X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Mar 2000 (Rev.2.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 1 -
Features : Description :
∗ 1,048,576 words by 16 bits organization.
∗ Fast access time and cycle time.
∗ Dual
CAS
Input.
∗ Low power dissipation.
∗ Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh, Hidden
Refresh and Test Mode Capability.
∗ 1024 refresh cycles per 16ms.
∗ Available in 400 mil SOJ / TSOPII
Packages.
∗ Single 3.3V±0.3V Power Supply.
∗ All inputs and Outputs are TTL
compatible.
∗ Extended Data-Out(EDO) Page Mode
operation.
∗ Self – refresh capability. (S-Version).
The GLT4160L16 is a 1,048,576 x 16 bit
high-performance CMOS dynamic random
access memory. The GLT4160L16 offers
Fast Page mode with Extended Data Output,
and has both BYTE WRITE and WORD
WRITE access cycles via two
CAS
pins. The
GLT4160L16 has symmetric address and
accepts 1024-cycle refresh in 16ms interval.
All inputs are TTL compatible. EDO
Page Mode operation allows random access
up to 1024 x 16 bits within a page, with cycle
times as short as 13ns.
The GLT4160L16 is best suited for
graphics, and DSP applications requiring
high performance memories.
HIGH PERFORMANCE 35 40 50
60
Max.
RAS
Access Time, (t
RAC
)
35 ns 40 ns 50 ns
60 ns
Max. Column Address Access Time, (t
CAA
) 18 ns 20 ns 25 ns
30 ns
Min. Extended Data Out Page Mode Cycle Time, (tPC) 13 ns 15 ns 20 ns
25 ns
Min. Read/Write Cycle Time, (tRC) 65 ns 70 ns 85 ns
104 ns
Max.
CAS
Access Time (t
CAC
)
11 ns 12 ns 14 ns
15 ns
G-LINK
GLT4160L16
1M X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Mar 2000 (Rev.2.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 2 -
Pin Configuration :
Vcc
DQ0
A0
A1
1
2
3
4
5
6
7
9
10
11
12
13
NC
OE
LCAS
VSS
DQ15
DQ1
WE
RAS
NC
A9
A8
8
14
15
16
17
18
19
20 23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DQ2
DQ
3
Vcc
DQ4
DQ5
DQ6
DQ7
NC
A2
DQ14
DQ13
DQ
12
VSS
DQ11
DQ10
DQ9
DQ8
UCAS
A7
A6
A
5
GLT416016
SOJ Top View
VCC 21 VSS22
NC
NC
A3 A
4
Vcc
DQ0
A0
A1
1
2
3
4
5
6
7
9
10
12
13
14
NC
OE
LCAS
VSS
DQ15
DQ1
WE
RAS
NC
A9
A8
8
15
16
17
18
19
20
21 24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
NC
A2
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
UCAS
A7
A6
A5
TSOP(Type II)
Top View
VCC 22 23 VSS
3411NC
NC
NC
A3
NC
A4
Pin Descriptions:
Name Function
A0 - A
9
Address Inputs
RAS
Row Address Strobe
UCAS
Column Address Strobe/Upper Byte Control
LCAS
Column Address Strobe/Lower Byte Control
WE
Write Enable
OE
Output Enable
DQ0 - DQ
15
Data Inputs / Outputs
V
CC
+3.3V Power Supply
V
SS
Ground
NC No Connection
G-LINK
GLT4160L16
1M X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Mar 2000 (Rev.2.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 3 -
Absolute Maximum Ratings* Capacitance*
TA=25°C, VCC=3.3V±0.3V, VSS=0V
Operating Temperature, TA (ambient)
.....................................…0°C to +70°C
Storage Temperature(plastic)....-55°C to +150°C
Voltage Relative to VSS...............-1.0V to + 4.6V
Short Circuit Output Current......................50mA
Power Dissipation......................................1.0W
Symbol
C
IN1
C
IN2
C
OUT
Parameter
Address Input
RAS,LCAS
,
UCAS
,WE,
OE
Data Input/Output
Max.
5
7
7
Unit
pF
pF
pF
*Note:Operation above Absolute Maximum Ratings can
abversely affect device reliability.
*Note: Capacitance is sampled and not 100% tested
Electrical Specifications
l
CAS
means
UCAS
and
LCAS
.
l All voltages are referenced to GND.
l After power up, wait more than 100µs and then, execute eight
CAS
-before-
RAS
or
RAS
-only
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
Memory
Array
1024X1024X16
Upper
Byte
Control
Sense Amplifier
Column Decoder
Row
Address
Buffer
Column
Address
Buffer
...1024X16...
...1024...
....1024....
Lower
Byte
Control
Row Decoder
Data
Output
Buffer
Data
Input
Buffer
Data
Output
Buffer
Data
Input
Buffer
CAS before
RAS Counter
Clock
Generator
A0
|
A9
X0..X9
Y0..Y9
DQ8
|
DQ15
DQ0
|
DQ7
RAS
LCAS
UCAS
WE
Vcc
GND
OE
X8
X8
X8
X8
X8
X1
6
X8
X8
X8
DC and Operating Characteristics (1-2)
G-LINK
GLT4160L16
1M X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Mar 2000 (Rev.2.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 4 -
TA = 0°C to 70°C, VCC=3.3V±0.3V, VSS=0V, unless otherwise specified.
Sym. Parameter Test Conditions Access
Time
Min. Typ Max. Unit Notes
I
LI
Input Leakage Current
(any input pin)
0V ≤ V
IN
≤ Vcc+0.3V
(All other pins not under test=0V)
-5 +5
µA
I
LO
Output Leakage Current
(for High-Z State)
0V ≤ V
out
≤ Vcc
Output is disabled (Hiz)
-5 +5
µA
I
CC1
Operating Current,
Random READ/WRITE tRC = tRC (min.)
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
170
160
150
140
mA 1,2
I
CC2
Standby Current,(TTL)
RAS, UCAS
,
LCAS
at V
IH
other inputs ≥V
SS
1 mA
I
CC3
Refresh Current,
RAS
-Only
RAS
cycling,
UCAS
,
LCAS
at V
IH
tRC = tRC (min.)
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
170
160
150
140
mA 2
I
CC4
Operating Current,
EDO Page Mode
RAS
at VIL,
UCAS
,
LCAS
address
cycling:tPC=tPC(min.)
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
170
160
150
140
mA 1,2
I
CC5
Refresh Current,
CAS
Before
RAS
RAS, UCAS
,
LCAS
address cycling:
tRC=tRC (min.)
t
RAC
= 35ns
t
RAC
= 40ns
t
RAC
= 50ns
t
RAC
= 60ns
170
160
150
140
mA 1
0.5 mA 1I
CC6
Standby Current,
(CMOS)
RAS
≥VCC-0.2V,
UCAS
≥VCC-0.2V,
LCAS
≥VCC-0.2V,
All other inputs V
SS
200
µA
1,5
I
CC7
Self Refresh Current
RAS =
UCAS = LCAS =V
IL
WE = OE =A0~A9=VCC-0.2V or 0.2V
DQ0~DQ15=VCC-0.2V,0.2V or Open
200
µA
V
IL
Input Low Voltage -0.3 +0.8 V 3
V
IH
Input High Voltage 2.0 VCC+0.3 V 3
V
OL
Output Low Voltage IOL = 2mA 0.4 V
V
OH
Output High Voltage IOH = -2mA 2.4 V
Notes:
1.ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open.
2.ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle in
random Read/Write and EDO Fast Page Mode.
3.Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not to exceed 15ns. All AC
parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC.
4.Specified VIH(max.) is steady state operation. During transitions VIH(max.) may undershoot to +1.0V for a period not to exceed 15ns. All AC
parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC.
5.S-Version.
G-LINK
GLT4160L16
1M X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT
Mar 2000 (Rev.2.0)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 5 -
AC Characteristics
TA = 0°C to 70°C , VCC = 3V ±0.3V, VIH / VIL = 3.0/0 V, VOH/VOL = 2.0/0.8V
An initial pause of 100 µs and 8
CAS
-before-
RAS
or
RAS
-only refresh cycles are required after power-up.
35 40 50 60
Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes
Read or Write Cycle Time
t
RC
65 70 85 104 ns
Read Modify Write Cycle Time
t
RWC
86 91 106 133 ns
RAS Precharge Time
t
RP
25 25 30 40 ns
RAS Pulse Width
t
RAS
35 100K 40 100K 50 100K 60 100k ns
Access Time from RAS
t
RAC
35 40 50 60 ns 1,2,3
Access Time from CAS
t
CAC
11 12 14 15 ns 1,5,10
Access Time from Column Address
t
AA
18 20 25 30 ns 1,5,6
CAS to Output Low-Z
t
CLZ
0 0 0 0 ns
CAS to Output High-Z
t
CEZ
3 8 3 8 3 8 3 10 ns
RAS Hold Time
t
RSH
12 12 14 13 ns
RAS Hold Time Referenced to OE
t
ROH
8 8 9 10 ns
CAS Hold Time
t
CSH
30 34 45 40 ns
CAS Pulse Width
t
CAS
6 10k 6 10k 8 10k 12 10k ns
RAS to CAS Delay Time
t
RCD
17 24 18 28 19 37 18 45 ns
RAS to Column Address Delay Time
t
RAD
12 17 13 20 14 25 13 30 ns 7
CAS to RAS Precharge Time
t
CRP
5 5 5 5 ns
Row Address Set-Up Time
t
ASR
0 0 0 0 ns
Row Address Hold Time
t
RAH
7 8 9 10 ns
Column Address Set-Up Time
t
ASC
0 0 0 0 ns
Column Address Hold Time
t
CAH
6 6 7 10 ns
Column Address to RAS Lead Time
t
RAL
18 20 25 30 ns
Column Address Hold Time Referenced to RAS
t
AR
30 34 44 55 ns
Read Command Set-Up Time
t
RCS
0 0 0 0 ns
Read Command Hold Time Referenced to CAS
t
RCH
0 0 0 0 ns 4
Read Command Hold Time Referenced to RAS
t
RRH
0 0 0 0 ns 4
Write Command Set-Up Time
t
WCS
0 0 0 0 ns 8,9
Write Command Hold Time
t
WCH
6 6 6 10 ns
Write Command Pulse Width
t
WP
6 6 6 10 ns
Write Command to RAS Lead Time
t
RWL
11 12 13 13 ns
Write Command to CAS Lead Time
t
CWL
11 12 13 13 ns
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