G-LINK GLT41316-45TC, GLT41316-45J4, GLT41316-40TC, GLT41316-40J4, GLT41316-35TC Datasheet

G-LINK

WE

RAS

CAS

RAS

WE

RAS

CAS

64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

Features : Description :

GLT41316

June 1998 (Rev 2)

∗ 65,536 words by 16 bits organization.
∗ Fast access time and cycle time.

∗ Dual

Input.

∗ Low power dissipation.
∗ Read-Modify-Write,

-Before-

Refresh and Test Mode Capability.

Refresh, Hidden

-Only Refresh,

∗ 256 refresh cycles per 4ms.
∗ Available in 40-pin 400 mil SOJ,and 40/44

pin TSOP (II).

∗ Single 5.0V±10% Power Supply.
∗ All inputs and Outputs are TTL

compatible. ∗ Fast Page Mode operation.

The GLT41316 is a 65,536 x 16 bit high­performance CMOS dynamic random access
memory. The GLT41316 offers Fast Page
mode ,and has both BYTE WRITE and

WORD WRITE access cycles via two
pins. The GLT41316 has symmetric address
and accepts 256-cycle refresh in 4ms
interval.

All inputs are TTL compatible. Fast
Page Mode operation allows random access
up to 256x16 bits, within a page, with cycle
times as short as 18ns.

The GLT41316 is best suited for
graphics, and DSP applications requiring
high performance memories.

HIGH PERFORMANCE 30 35 40 45

Max.

Access Time, (t

RAC

)

30 ns 35 ns 40 ns 45 ns

Max. Column Address Access Time, (tAA) 15 ns 18 ns 20 ns 22 ns
Min. Fast Page Mode Cycle Time, (tPC) 18 ns 21 ns 23 ns 25 ns
Min. Read/Write Cycle Time, (tRC) 65 ns 70 ns 75 ns 80 ns

Max.

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

Access Time (t

CAC

)

10 ns 11 ns 12 ns 12 ns

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2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.

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UW

LW

OE

Pin Configuration :

GLT41316

64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

June 1998 (Rev 2)

Pin Descriptions:

GLT41316

SOJ Top View

TSOP(Type II)

Top View

Name Function

A0 - A

DQ0 - DQ
V
V

7

15
CC
SS

NC No Connection

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

Address Inputs
Row Address Strobe

Column Address Strobe
Read / Upper Byte Write Enable
Read / Lower Byte Write Enable
Output Enable
Data Inputs / Outputs

+5V Power Supply
Ground

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2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.

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G-LINK

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WE

UW

CAS

RAS

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64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

Absolute Maximum Ratings* Capacitance*

TA=25°C, VCC=5V±10%, VSS=0V

GLT41316

June 1998 (Rev 2)

Operating Temperature, TA (ambient)

Symbol

.......................................-0°C to +70°C

C

Storage Temperature(plastic)....-55°C to +150°C

Voltage Relative to VSS...............-1.0V to + 7.0V

IN1

C

IN2

Short Circuit Output Current......................50mA

C

Power Dissipation......................................1.0W

*Note: Operation above Absolute Maximum Ratings

can adversely affect device reliability.

OUT

*Note: Capacitance is sampled and not 100% tested

Electrical Specifications

l

l All voltages are referenced to GND.
l After power up, wait more than 100µs and then, execute eight

means

and LW.

refresh cycles as dummy cycles to initialize internal circuit.

Block Diagram :

Parameter

Address Input

Data Input/Output

-before-

or

Max.

5
7
7

Unit

pF
pF
pF

-only

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.

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UWLWOE

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UW

Truth Table: GLT41316

GLT41316

64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

June 1998 (Rev 2)

Function

Standby H
Read: Word L L H H L ROW/COL Data Out

Write: Word(Early Write) L L L L X ROW/COL Data-In
Write: Lower Byte (Early) L L H L X ROW/COL Lower Byte,Data-In

Write: Upper Byte (Early) L L L H X ROW/COL Lower Byte,High-Z

Read Write L L
Fast-Page­Mode Read

Fast-Page­Mode Write

Fast-Page­Mode Read­Write

1st Cycle
2nd Cycle

1st Cycle
2nd Cycle

1st Cycle

2nd Cycle

L
L

L
L

L

L

H→X

H→L
H→L
H→L
H→L
H→L

H→L

X X X High-Z

H→L H→L L→H

H H

H

L
L

H→L

H→L

L
L

H→L

H→L

L→H

L→H

ADDRESS DQs Note

Upper Byte,High-Z

Upper Byte,Data-In

ROW/COL Data-Out,Data-In 1,2
L
L

X
X

ROW/COL

COL

ROW/COL

COL

ROW/COL

COL

Data-Out
Data-Out

Data-In
Data-In

Data-Out,Data-In

Data-Out,Data-In

s

1
1

2
2

1,2

1,2

Hidden
Refresh

-Only Refresh

CBR Refresh

Read

Write

L→H→L

L→H→L

L H X X X ROW High-Z

H→L

L

L

L X X X High-Z

H

L

H

L

Notes:

1. These READ cycles are always WORD READ cycles .

2. These WRITE cycles may also be BYTE READ cycles (either

3. EARLY WRITE only.

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L

ROW/COL

X

ROW/COL

or LW active).

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2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.

Data-Out

Data-In

1

2,3

G-LINK

RAC

RAC

RAC

RAC

RAS, CAS

RAS

CAS

RAC

RAC

RAC

RAC

RAS

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RAC

RAC

RAC

RAC

RAS, CAS

RAC

RAC

RAC

RAC

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64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

DC and Operating Characteristics (1-2)

TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified.

GLT41316

June 1998 (Rev 2)

Sym. Parameter Test Conditions Access

Time

I

I

I

I

I

I

I

I

V
V
V
V

Input Leakage Current

LI

(any input pin)

0V ≤ V

≤ 5.5V

IN

(All other pins not under
test=0V)

Output Leakage Current

LO

(for High-Z State)
Operating Current,

CC1

Random READ/WRITE tRC = tRC (min.)

Standby Current,(TTL)

CC2

Refresh Current,

CC3

RAS-Only

Operating Current,

CC4

EDO Page Mode

Refresh Current,

CC5

CAS Before RAS

Standby Current, (CMOS)

CC6

0V ≤ V

out

≤ 5.5V

Output is disabled (Hiz)

at V

IH

other inputs ≥V

cycling,

V

IH

SS

at

tRC = tRC (min.)

at VIL,

address cycling: t

,

PC

=

tPC(min.)

,
address cycling:
t

= tRC (min.)

RC

≥VCC-0.2V,

t
t
t
t

t
t
t
t
t
t
t
t
t
t
t
t

= 30ns
= 35ns
= 40ns
= 45ns

= 30ns
= 35ns
= 40ns
= 45ns
= 30ns
= 35ns
= 40ns
= 45ns
= 30ns
= 35ns
= 40ns
= 45ns

≥VCC-0.2V,

All other inputs ≥V

Input Low Voltage -1 +0.8 V 3

IL

Input High Voltage 2.4 VCC+1 V 3

IH

Output Low Voltage IOL = 4.2mA 0.4 V

OL

Output High Voltage IOH = -5mA 2.4 V

OH

SS

Notes:

1. I

is dependent on output loading when the device output is selected. Specified I

CC

output open.

2. ICC is dependent upon the number of address transitions specified I
one transition per address cycle in random Read/Write and Fast Page Mode.

3. Specified V
to exceed 20ns. All AC parameters are measured with V

is steady state operation. During transitions V

IL(min.)

IL(min.)≥VSS

CC(max.)

may undershoot to -1.0V for a period not

IL(min.)

and V

Min. Typ Max. Unit Notes

-10 +10

-10 +10

180
170
160
150

180
170
160
150
180
170
160
150
180
170
160
150

is measured with the

CC(max.)

is measured with a maximum of

IH(max.)≤VCC

.

µA

µA

mA 1,2

4 mA

mA 2

mA 1,2

mA 1

2 mA

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.

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G-LINK

RAC

RAC

RAC

RAC

RAS

CAS

CAS

CAS

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RAS

RAS

CAS

CAS

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CAS

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CAS

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64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

AC Characteristics (0°°C ≤≤ TA ≤≤ 70°°C, See note 1,2)

Test condition:VCC=5.0V±10%, VIH/VIL=2.4V/0.8V,VOH/VOL=2.4V/0.4V

Parameter t

SymbolMIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Unit Notes

= 30 ns t

= 35 ns t

= 40 ns t

GLT41316

June 1998 (Rev 2)

= 45 ns

Read/Write Cycle Time t
Read Midify Write Cycle Time t

Access Time from
Access Time from

Access Time from Column Address t

to Output in Low-Z

Output Buffer Turn-off Delay from
Transition Time(Rise and Fall) t

Precharge Time
Pulse Width
Hold Time
Hold Time
Pulse Width
to

Delay Time
to Column Address Delay Time
to

Precharge Time

Row Address Setup Time t
Row Address Hold Time t
Column Address Setup Time t
Column Address Hold Time t
Column Address Hold Time Referenced

to
Column Address Lead Time Referenced

to
Read Command Setup Time t
Read Command Hold Time Referenced

to
Read Command Hold Time Referenced

to

Hold Time Referenced to

Write Command Hold Time Referenced
to

Pulse Width

RC
RWC

t

RAC

t

CAC

AA

t

CLZ

t

OFF

T

t

RP

t

RAS

t

RSH

t

CSH

t

CAS

t

RCD

t

RAD

t

CRP

ASR
RAH
ASC
CAH

t

AR

t

RAL

RCS

t

RRH

t

RCH

t

WCH

t

WCR

t

WP

65 - 70 - 75 - 80 - ns
80 - 99 - 105 - 110 - ns

- 30 - 35 - 40 - 45 ns 3,4

- 10 - 11 - 12 - 12 ns 3,4

- 15 - 18 - 20 - 22 ns 3,4

0 0 - 0 - 0 - ns 3
3 8 3 8 3 8 3 8 ns 7
3 50 3 50 3 50 3 50 ns 2

25 - 25 - 25 - 25 - ns
30 100k 35 100k 40 100K 45 100K ns
10 - 12 - 12 - 13 - ns
30 - 36 - 40 - 46 - ns
10 10000 12 10000 12 10000 13 10000 ns
13 20 17 24 18 28 18 33 ns 4
10 15 12 17 13 20 13 23 ns 4

5 - 5 - 5 - 5 - ns 8
0 - 0 - 0 - 0 - ns

7 - 7 - 8 - 8 - ns
0 - 0 - 0 - 0 - ns
6 - 6 - 6 - 6 - ns

26 - 30 - 34 - 39 - ns

15 - 18 - 20 - 23 - ns

0 - 0 - 0 - 0 - ns
0 - 0 - 0 - 0 - ns 9

0 - 0 - 0 - 0 - ns 9

6 - 6 - 6 - 6 - ns 10

26 - 30 - 34 - 39 - ns 5

6 - 6 - 6 - 6 - ns 10

G-Link Technology Corporation

2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.

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G-LINK

RAC

RAC

RAC

RAC

WE

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WE

CAS

RAS

WE

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CAS

CAS

CAS

RAS

CAS

CAS

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RAS

CAS

CAS

CAS

CAS

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RAS

CAS

OE

OE

OE

OE

WE

GLT41316

64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

June 1998 (Rev 2)

Parameter t

Lead Time Referenced to

Lead Time Referenced to
Data-In Setup Time t
Data-In Hold Time t

Data Hold Time Referenced to

Setup Time

toWE Delay Time
to WE Delay Time

Column Address to WE Delay Time

Setup Time(

Refresh)

Hold Time(

Refresh)

to

Precharge Time

Precharge Time(CBR Counter Test

Cycle)
Access Time from

Fast Page mode Read/Write Cycle Time
Fast Page mode Read Modify Write

Cycle Time

Precharge Time(Fast Page mode)
Pulse Width(Fast Page mode)
Hold Time from

Access Time from

to Delay Time

Output Buffer Turn-off Delay Time from

before

before

Precharge

Precharge

= 30 ns t

= 35 ns t

= 40 ns t

= 45 ns

SymbolMIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Unit Notes

t

RWL

t

CWL

DS
DH

t

DHR

t

WCS

t

RWD

t

CWD

t

AWD

t

CSR

t

CHR

t

RPC

t

CPT

t

CPA

t

PC

t

PRWC

t

CP

t

RASP

t

RHCP

t

OEA

t

OED

t

OEZ

10 - 11 - 12 - 12 - ns
10 - 11 - 12 - 12 - ns

0 - 0 - 0 - 0 - ns 11
7 - 7 - 8 - 8 - ns 11

27 - 31 - 36 - 41 - ns 6

0 - 0 - 0 - 0 - ns 5
47 - 58 - 63 - 68 - ns 5
24 - 29 - 30 - 30 - ns 5
29 - 36 - 38 - 40 - ns 5

5 - 5 - 5 - 5 - ns

10 - 10 - 10 - 10 - ns

5 - 5 - 5 - 5 - ns
20 - 20 - 20 - 20 - ns

- 18 - 21 - 23 - 25 ns 3

18 - 21 - 23 - 25 - ns
48 - 60 - 63 - 65 - ns

5.5 - 6 - 7 - 7 - ns
30 100k 35 100k 40

100K

45

100K

ns

25 - 25 - 25 - 30 - ns

- 10 - 11 - 12 - 12 ns
8 - 8 - 8 - 8 - ns
3 8 3 8 3 8 3 8 ns 7

Hold Time

Hold Time(Hidden Refresh Cycle)

Refresh Time(256cycles)

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t

OEH

t

WHR

t

REF

6 - 6 - 7 - 7 - ns

15 - 15 - 15 - 15 - ns

- 4 - 4 - 4 - 4 ms

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2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.

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