G-LINK GLT41016-35J4, GLT41016-30TC, GLT41016-30J4, GLT41016-45J4, GLT41016-40J4 Datasheet

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64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

Features : Description :

GLT41016

Dec 1998 (Rev 2.1)

∗ 65,536 words by 16 bits organization.
∗ Fast access time and cycle time.

∗ Dual

Input.

∗ Low power dissipation.
∗ Read-Modify-Write,

-Before-

Refresh and Test Mode Capability.

Refresh, Hidden

-Only Refresh,

∗ 256 refresh cycles per 4ms.
∗ Available in 40-pin 400 mil SOJ and 40/44

pin TSOP (II).

∗ Single 5.0V±10% Power Supply.
∗ All inputs and Outputs are TTL

compatible.

∗ Extended Data-Out(EDO) Page Mode

operation.

The GLT41016 is a 65,536 x 16 bit high­performance CMOS dynamic random access
memory. The GLT41016 offers Fast Page
mode with Extended Data Output, and has
both BYTE WRITE and WORD WRITE

access cycles via two

pins. The
GLT41016 accepts 256-cycle refresh in 4ms
interval.

All inputs are TTL compatible. EDO
Page Mode operation allows random access
up to 256 x 16 bits, within a page, with cycle
times as short as 12ns.

The GLT41016 is best suited for
graphics, and DSP applications requiring
high performance memories.

HIGH PERFORMANCE 30 35 40 45

Max.

Access Time, (t

RAC

)

30 ns 35 ns 40 ns 45 ns

Max. Column Address Access Time, (tAA) 15 ns 18 ns 20 ns 22 ns
Min. Extended Data Out Page Mode Cycle Time, (tPC) 12 ns 13 ns 15 ns 18 ns
Min. Read/Write Cycle Time, (tRC) 65 ns 70 ns 75 ns 80 ns

Max.

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Access Time (t

CAC

)

10 ns 11 ns 12 ns 12 ns

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Pin Configuration :

GLT41016

64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

Dec 1998 (Rev 2.1)

Pin Descriptions:

GLT41016

SOJ Top View

TSOP(Type II)

Top View

Name Function

A0 - A

DQ0 - DQ
V
V

7

15
CC
SS

NC No Connection

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2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

Address Inputs
Row Address Strobe

Column Address Strobe/Upper Byte Control
Column Address Strobe/Lower Byte Control
Write Enable
Output Enable
Data Inputs / Outputs

+5V Power Supply
Ground

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64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

Absolute Maximum Ratings* Capacitance*

TA=25°C, VCC=5V±10%, VSS=0V

GLT41016

Dec 1998 (Rev 2.1)

Operating Temperature, TA (ambient)

Symbol

.......................................-0°C to +70°C

C

Storage Temperature(plastic)....-55°C to +150°C

Voltage Relative to VSS...............-1.0V to + 7.0V

IN1

C

IN2

Short Circuit Output Current......................50mA

C

Power Dissipation......................................1.0W

*Note: Operation above Absolute Maximum Ratings

can adversely affect device reliability.

OUT

*Note: Capacitance is sampled and not 100% tested

Electrical Specifications

l

l All voltages are referenced to GND.
l After power up, wait more than 100µs and then, execute eight

means

and

.

refresh cycles as dummy cycles to initialize internal circuit.

Block Diagram :

Parameter

Address Input

,

Data Input/ Output

,

-before-

Max.

,

or

Unit

5

pF

7

pF

7

pF

-only

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2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.

G-Link Technology Corporation, Taiwan

2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.

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64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

GLT41016

Dec 1998 (Rev 2.1)

Extended Data Output (EDO) Page Mode

The EDO page mode is a kind of page mode with enhanced features. The two major features
of the EDO page mode are as follows.

1. Data output time is extended.
In the EDO page mode, the output data is held to the next

cycle‘s falling edge,
instead of the rising edge. For this reason, valid data output time in the EDO page mode is
extended compared with the fast page mode (=data extend function). In the fast page mode,

the data output time becomes shorter as the

cycle time becomes shorter. Therefore, in

the EDO page mode, the timing margin in read cycle is larger than of the fast page mode
even if the

2. The

In the EDO page mode, due to the data extend function, the

cycle time becomes shorter.

cycle time in the EDO page mode is shorter than that in the fast page mode.

cycle time can be

shorter than in the fast page mode if the timing margin is the same.

Taking a device whose t

is 60ns as an example, the

RAC

cycle time in the EDO page

mode is 25ns while that in the fast page mode is 40ns.

In the EDO page mode, read (data out) and write (data in) cycles can be executed

repeatedly during one

cycle. The EDO page mode allows both read and write
operations during one cycle, but the performance is equivalent to that of the fast page mode
in that case.

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2701Northwestern Parkway
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Hsin Chu, Taiwan, R.O.C.

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Truth Table: GLT41016

GLT41016

64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

Dec 1998 (Rev 2.1)

Function

Standby H
Read: Word L L L H L ROW/COL Data Out

Read: Lower Byte L L H H L ROW/COL Lower Byte,Data-

Read: Upper Byte L H L H L ROW/COL Lower Byte,High-Z

Write: Word(Early Write) L L L L X ROW/COL Data-In
Write: Lower Byte (Early) L L H L X ROW/COL Lower Byte,Data-In

Write: Upper Byte (Early) L H L L X ROW/COL Lower Byte,High-Z

Read Write L L L
EDO-Page­Mode Read

EDO-Page­Mode Write

1st Cycle
2nd Cycle

1st Cycle
2nd Cycle

L
L

L
L

H→X H→X

H→L
H→L
H→L
H→L

H→L
H→L
H→L
H→L

X X High-Z

H→L L→H

H
H

L
L

ADDRESS DQs Notes

Out
Upper Byte,High-Z

Upper Byte,Data­Out

Upper Byte,High-Z

Upper Byte,Data-In

ROW/COL Data-Out,Data-In 1,2
L
L

X
X

ROW/COL

COL

ROW/COL

COL

Data-Out
Data-Out

Data-In
Data-In

1
1

2
2

EDO-Page­Mode Read­Write

Hidden
Refresh

-Only Refresh

CBR Refresh

1st Cycle

2nd Cycle
Read

Write

L

L

L→H→L

L→H→L

L H H X X ROW High-Z

H→L

H→L

H→L

H→L

H→L

L

L

L L X X High-Z 4

H→L

H→L

L

L

H

L

Notes:

1. These READ cycles may also be BYTE READ cycles (either

2. These WRITE cycles may also be BYTE READ cycles (either

3. EARLY WRITE only.

4. At least one of the two CAS signals must be active (

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L→H

L→H

or

ROW/COL

COL

L

ROW/COL

X

ROW/COL

or

or

).

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Data-Out,Data-In

Data-Out,Data-In
Data-Out

Data-In

active).

active).

1,2

1,2

1

2,3

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CC1

CC2

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CC3

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CC4

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CC5

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CC6

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64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

DC and Operating Characteristics (1-2)

TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified.

GLT41016

Dec 1998 (Rev 2.1)

Sym

Parameter Test Conditions Access

.

I

Input Leakage Current

LI

(any input pin)

I

Output Leakage Current

LO

(for High-Z State)

I

Operating Current,
Random READ/WRITE tRC = tRC (min.)

I

Standby Current,(TTL)

I

Refresh Current,

-Only

I

Operating Current,
EDO Page Mode

I

Refresh Current,
CAS Before

I

Standby Current, (CMOS)

0V ≤ V

≤ 5.5V

IN

(All other pins not under
test=0V)

0V ≤ V

out

≤ 5.5V

Output is disabled (Hiz)

,

V

other inputs ≥V

IH

cycling,

at V

,

at

SS

,

IH

tRC = tRC (min.)

at VIL,

,

cycling: t

,

address

= tPC(min.)

PC

,
address cycling:
t

= tRC (min.)

RC

≥VCC-0.2V,

≥VCC-0.2V,

t

RAC

t

RAC

t

RAC

t

RAC

t

RAC

t

RAC

t

RAC

t

RAC

t

RAC

t

RAC

t

RAC

t

RAC

t

RAC

t

RAC

t

RAC

t

RAC

Time

= 30ns
= 35ns
= 40ns
= 45ns

= 30ns
= 35ns
= 40ns
= 45ns
= 30ns
= 35ns
= 40ns
= 45ns
= 30ns
= 35ns
= 40ns
= 45ns

Min. Typ Max. Unit Notes

-10 +10

-10 +10

180
170
160
150

4 mA

180
170
160
150
180
170
160
150
180
170
160
150

2 mA

µA

µA

mA 1,2

mA 2

mA 1,2

mA 1

≥VCC-0.2V,

All other inputs V

SS

VILInput Low Voltage -1 +0.8 V 3
VIHInput High Voltage 2.4 VCC+1 V 3
VOLOutput Low Voltage IOL = 4.2mA 0.4 V
VOHOutput High Voltage IOH = -5mA 2.4 V

Notes:

1. ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output
open.

2. ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one
transition per address cycle in random Read/Write and EDO Fast Page Mode.

3. Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not to
exceed 20ns. All AC parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC.

G-Link Technology Corporation

2701Northwestern Parkway
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64K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

AC Characteristics

TA = 0°C to 70°C , VCC = 5 V ± 10%, VIH/VIL = 2.4/0.8 V, VOH/VOL = 2.0/0.8V

GLT41016

Dec 1998 (Rev 2.1)

An initial pause of 100 µs and 8

-before-

or

-only refresh cycles are required after power-up.

30 35 40 45

Parameter Symbol Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes

Read or Write Cycle Time
Read Modify Write Cycle Time

Precharge Time

Pulse Width
Access Time from
Access Time from

Access Time from Column Address

to Output Low-Z

to Output High-Z

Hold Time

Hold Time Referenced to

Hold Time

Pulse Width

to CAS Delay Time

to Column Address Delay Time

to

Precharge Time

Row Address Set-Up Time
Row Address Hold Time
Column Address Set-Up Time
Column Address Hold Time

Column Address to

Lead Time

Column Address Hold Time Referenced to

t

RC

t

RWC

t

RP

t

RAS

t

RAC

t

CAC

t

AA

t

CLZ

t

CEZ

t

RSH

t

ROH

t

CSH

t

CAS

t

RCD

t

RAD

t

CRP

t

ASR

t

RAH

t

ASC

t

CAH

t

RAL

t

AR

65 70 75 80 ns
90 95 100 103 ns
25 25 25 30 ns

30 100k 35 100k 40 100k 45 100k ns

30 35 40 45 ns 1,2,3
10 11 12 12 ns 1,5,10
15 18 20 22 ns 1,5,6

0 0 0 0 ns
3 8 3 8 3 8 3 8 ns

10 12 12 13 ns

7 8 8 9 ns

25 30 34 40 ns

6 10k 6 10k 6 10K 7 10K ns
13 20 17 24 18 28 18 33 ns
10 15 12 17 13 20 13 23 ns 7

5 5 5 5 ns

0 0 0 0 ns

6 7 8 8 ns

0 0 0 0 ns

6 6 6 6 ns
15 18 20 23 ns

26 30 34 39 ns

Read Command Set-Up Time
Read Command Hold Time Referenced to

Read Command Hold Time Referenced to
Write Command Set-Up Time

Write Command Hold Time
Write Command Pulse Width

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t

RCS

t

RCH

t

RRH

t

WCS

t

WCH

t

WP

0 0 0 0 ns

0 0 0 0 ns 4

0 0 0 0 ns 4

0 0 0 0 ns 8,9

6 6 6 6 ns

6 6 6 6 ns

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