GD32VF103 User Manual
GigaDevice Semiconductor Inc.
GD32VF103
RISC-V 32-bit MCU
User Manual
Revision 1.0
( Jun. 2019 )
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GD32VF103 User Manual
Table of Contents
Table of Contents ............................................................................................................... 2
List of Figures ................................................................................................................... 14
List of Tables ..................................................................................................................... 20
1. System and memory architecture ........................................................................... 22
1.1. RISC-V CPU ......................................................................................................................... 22
1.2. System architecture ............................................................................................................ 22
1.3. Memory map ..................................................................................................................... 24
1.3.1. On-chip SRAM memory ................................................................................................................... 28
1.3.2. On-chip flash memory overview ..................................................................................................... 28
1.4. Boot configuration ............................................................................................................. 29
1.5. Device electronic signature ................................................................................................. 29
1.5.1. Memory density information ............................................................................................................ 30
1.5.2. Unique device ID (96 bits) ............................................................................................................... 30
2. Flash memory controller (FMC) ............................................................................... 32
2.1. Overview ........................................................................................................................... 32
2.2. Characteristics .................................................................................................................... 32
2.3. Function overview .............................................................................................................. 32
2.3.1. Flash memory architecture .............................................................................................................. 32
2.3.2. Read operations ................................................................................................................................ 33
2.3.3. Unlock the FMC_CTL registers ...................................................................................................... 33
2.3.4. Page erase ........................................................................................................................................ 33
2.3.5. Mass erase ........................................................................................................................................ 34
2.3.6. Main flash programming .................................................................................................................. 35
2.3.7. Option bytes Erase ........................................................................................................................... 37
2.3.8. Option bytes modify .......................................................................................................................... 38
2.3.9. Option bytes description .................................................................................................................. 38
2.3.10. Page erase/program protection ...................................................................................................... 39
2.3.11. Security protection ............................................................................................................................ 40
2.4. Register definition .............................................................................................................. 41
2.4.1. Wait state register (FMC_WS) ........................................................................................................ 41
2.4.2. Unlock key register (FMC_KEY)..................................................................................................... 41
2.4.3. Option byte unlock key register (FMC_OBKEY) .......................................................................... 42
2.4.4. Status register (FMC_STAT) ........................................................................................................... 42
2.4.5. Control register (FMC_CTL) ............................................................................................................ 43
2.4.6. Address register (FMC_ADDR) ...................................................................................................... 44
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2.4.7. Option byte status register (FMC_OBSTAT) ................................................................................. 45
2.4.8. Erase/Program Protection register (FMC_WP) ............................................................................ 45
2.4.9. Product ID register (FMC_PID) ...................................................................................................... 46
3. Power management unit (PMU) ............................................................................... 47
3.1. Overview ........................................................................................................................... 47
3.2. Characteristics .................................................................................................................... 47
3.3. Function overview .............................................................................................................. 47
3.3.1. Battery backup domain .................................................................................................................... 48
3.3.2. VDD/V
3.3.3. 1.2V power domain ........................................................................................................................... 51
3.3.4. Power saving modes ........................................................................................................................ 51
power domain ................................................................................................................... 49
DDA
3.4. Register definition .............................................................................................................. 54
3.4.1. Control register (PMU_CTL) ........................................................................................................... 54
3.4.2. Control and status register (PMU_CS) .......................................................................................... 55
4. Backup registers (BKP) ............................................................................................ 57
4.1. Overview ........................................................................................................................... 57
4.2. Characteristics .................................................................................................................... 57
4.3. Function overview .............................................................................................................. 57
4.3.1. RTC clock calibration ....................................................................................................................... 57
4.3.2. Tamper detection .............................................................................................................................. 58
4.4. Register definition .............................................................................................................. 59
4.4.1. Backup data register x (BKP_DATAx) (x= 0..41) ......................................................................... 59
4.4.2. RTC signal output control register (BKP_OCTL) ......................................................................... 59
4.4.3. Tamper pin control register (BKP_TPCTL) ................................................................................... 60
4.4.4. Tamper control and status register (BKP_TPCS) ........................................................................ 60
5. Reset and clock unit (RCU) ...................................................................................... 62
5.1. Reset control unit (RCTL) .................................................................................................... 62
5.1.1. Overview ............................................................................................................................................ 62
5.1.2. Function overview ............................................................................................................................. 62
5.2. Clock control unit (CCTL) ..................................................................................................... 63
5.2.1. Overview ............................................................................................................................................ 63
5.2.2. Characteristics................................................................................................................................... 65
5.2.3. Function overview ............................................................................................................................. 65
5.3. Register definition .............................................................................................................. 69
5.3.1. Control register (RCU_CTL) ............................................................................................................ 69
5.3.2. Clock configuration register 0 (RCU_CFG0) ................................................................................ 71
5.3.3. Clock interrupt register (RCU_INT) ................................................................................................ 74
5.3.4. APB2 reset register (RCU_APB2RST) .......................................................................................... 77
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5.3.5. APB1 reset register (RCU_APB1RST) .......................................................................................... 79
5.3.6. AHB enable register (RCU_AHBEN) ............................................................................................. 82
5.3.7. APB2 enable register (RCU_APB2EN) ......................................................................................... 83
5.3.8. APB1 enable register (RCU_APB1EN) ......................................................................................... 85
5.3.9. Backup domain control register (RCU_BDCTL) .......................................................................... 87
5.3.10. Reset source/clock register (RCU_RSTSCK) .............................................................................. 88
5.3.11. AHB reset register (RCU_AHBRST) .............................................................................................. 90
5.3.12. Clock configuration register 1 (RCU_CFG1) ................................................................................ 91
5.3.13. Deep-sleep mode voltage register (RCU_DSV) .......................................................................... 93
6. Interrupt/event controller (EXTI) .............................................................................. 94
6.1. Overview ........................................................................................................................... 94
6.2. Characteristics .................................................................................................................... 94
6.3. Function overview .............................................................................................................. 94
6.4. External interrupt and event (EXTI) block diagram ............................................................... 97
6.5. External Interrupt and Event function overview .................................................................. 97
6.6. Register definition .............................................................................................................. 99
6.6.1. Interrupt enable register (EXTI_INTEN) ........................................................................................ 99
6.6.2. Event enable register (EXTI_EVEN) .............................................................................................. 99
6.6.3. Rising edge trigger enable register (EXTI_RTEN) ..................................................................... 100
6.6.4. Falling edge trigger enable register (EXTI_FTEN) .................................................................... 100
6.6.5. Software interrupt event register (EXTI_SWIEV) ....................................................................... 101
6.6.6. Pending register (EXTI_PD) .......................................................................................................... 101
7. General-purpose and alternate-function I/Os (GPIO and AFIO) ........................ 102
7.1. Overview ......................................................................................................................... 102
7.2. Characteristics .................................................................................................................. 102
7.3. Function overview ............................................................................................................ 102
7.3.1. GPIO pin configuration ................................................................................................................... 103
7.3.2. External interrupt/event lines ........................................................................................................ 104
7.3.3. Alternate functions (AF) ................................................................................................................. 104
7.3.4. Input configuration .......................................................................................................................... 104
7.3.5. Output configuration ....................................................................................................................... 105
7.3.6. Analog configuration ....................................................................................................................... 106
7.3.7. Alternate function (AF) configuration ........................................................................................... 106
7.3.8. IO pin function selection ................................................................................................................ 107
7.3.9. GPIO locking function .................................................................................................................... 107
7.4. Remapping function I/O and debug configuration ............................................................. 108
7.4.1. Introduction ...................................................................................................................................... 108
7.4.2. Main features ................................................................................................................................... 108
7.4.3. JTAG alternate function remapping ............................................................................................. 108
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7.4.4. TIMER AF remapping ..................................................................................................................... 109
7.4.5. USART AF remapping .................................................................................................................... 110
7.4.6. I2C0 AF remapping ......................................................................................................................... 110
7.4.7. SPI0 AF remapping ........................................................................................................................ 111
7.4.8. SPI2/I2S2 AF remapping ............................................................................................................... 111
7.4.9. CAN0 AF remapping ...................................................................................................................... 111
7.4.10. CAN1 AF remapping ...................................................................................................................... 111
7.4.11. CLK pins AF remapping ................................................................................................................. 112
7.5. Register definition ............................................................................................................ 113
7.5.1. Port control register 0 (GPIOx_CTL0, x=A..E) ........................................................................... 113
7.5.2. Port control register 1 (GPIOx_CTL1, x=A..E) ........................................................................... 115
7.5.3. Port input status register (GPIOx_ISTAT, x=A..E) ...................................................................... 116
7.5.4. Port output control register (GPIOx_OCTL, x=A..E) .................................................................. 117
7.5.5. Port bit operate register (GPIOx_BOP, x=A..E).......................................................................... 117
7.5.6. Port bit clear register (GPIOx_BC, x=A..E) ................................................................................. 118
7.5.7. Port configuration lock register (GPIOx_LOCK, x=A..E) .......................................................... 118
7.5.8. Event control register (AFIO_EC)................................................................................................. 119
7.5.9. AFIO port configuration register 0 (AFIO_PCF0) ....................................................................... 120
7.5.10. EXTI sources selection register 0 (AFIO_EXTISS0) ................................................................. 123
7.5.11. EXTI sources selection register 1 (AFIO_EXTISS1) ................................................................. 124
7.5.12. EXTI sources selection register 2 (AFIO_EXTISS2) ................................................................. 125
7.5.13. EXTI sources selection register 3 (AFIO_EXTISS3) ................................................................. 126
7.5.14. AFIO port configuration register 1 (AFIO_PCF1) ....................................................................... 127
8. CRC calculation unit (CRC) .................................................................................... 129
8.1. Overview ......................................................................................................................... 129
8.2. Characteristics .................................................................................................................. 129
8.3. Function overview ............................................................................................................ 130
8.4. Register definition ............................................................................................................ 131
8.4.1. Data register (CRC_DATA) ........................................................................................................... 131
8.4.2. Free data register (CRC_FDATA) ................................................................................................ 131
8.4.3. Control register (CRC_CTL) .......................................................................................................... 132
9. Direct memory access controller (DMA) .............................................................. 133
9.1. Overview ......................................................................................................................... 133
9.2. Characteristics .................................................................................................................. 133
9.3. Block diagram .................................................................................................................. 134
9.4. Function overview ............................................................................................................ 134
9.4.1. DMA operation................................................................................................................................. 134
9.4.2. Peripheral handshake .................................................................................................................... 136
9.4.3. Arbitration ......................................................................................................................................... 136
9.4.4. Address generation ........................................................................................................................ 137
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9.4.5. Circular mode .................................................................................................................................. 137
9.4.6. Memory to memory mode .............................................................................................................. 137
9.4.7. Channel configuration .................................................................................................................... 137
9.4.8. Interrupt ............................................................................................................................................ 138
9.4.9. DMA request mapping ................................................................................................................... 139
9.5. Register definition ............................................................................................................ 142
9.5.1. Interrupt flag register (DMA_INTF) ............................................................................................... 142
9.5.2. Interrupt flag clear register (DMA_INTC) .................................................................................... 143
9.5.3. Channel x control register (DMA_CHxCTL)................................................................................ 143
9.5.4. Channel x counter register (DMA_CHxCNT) .............................................................................. 145
9.5.5. Channel x peripheral base address register (DMA_CHxPADDR) ........................................... 146
9.5.6. Channel x memory base address register (DMA_CHxMADDR) ............................................. 146
10. Debug (DBG) ......................................................................................................... 148
10.1. Overview ...................................................................................................................... 148
10.2. JTAG function overview................................................................................................. 148
10.2.1. Pin assignment ................................................................................................................................ 148
10.2.2. JTAG daisy chained structure ....................................................................................................... 148
10.2.3. Debug reset ..................................................................................................................................... 149
10.3. Debug hold function overview ...................................................................................... 149
10.3.1. Debug support for power saving mode ....................................................................................... 149
10.3.2. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN .................................................. 149
10.4. Register definition ........................................................................................................ 150
10.4.1. ID code register (DBG_ID) ............................................................................................................ 150
10.4.2. Control register (DBG_CTL) .......................................................................................................... 150
11. Analog-to-digital converter (ADC) ...................................................................... 153
11.1. Introduction ................................................................................................................. 153
11.2. Main features ............................................................................................................... 153
11.3. Pins and internal signals ................................................................................................ 154
11.4. Functional description .................................................................................................. 154
11.4.1. Calibration (CLB) ............................................................................................................................ 155
11.4.2. ADC clock ........................................................................................................................................ 156
11.4.3. ADCON switch ................................................................................................................................ 156
11.4.4. Regular and inserted channel groups .......................................................................................... 156
11.4.5. Conversion modes .......................................................................................................................... 156
11.4.6. Inserted channel management ..................................................................................................... 160
11.4.7. Data alignment ................................................................................................................................ 161
11.4.8. Programmable sample time .......................................................................................................... 162
11.4.9. External trigger ................................................................................................................................ 163
11.4.10. DMA request ................................................................................................................................ 163
11.4.11. Temperature sensor, and internal reference voltage V
................................................ 163
REFINT
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11.4.12. Programmable resolution (DRES) - fast conversion mode .................................................. 164
11.4.13. On-chip hardware oversampling .............................................................................................. 165
11.5. ADC sync mode ............................................................................................................. 166
11.6. Free mode .................................................................................................................... 167
11.6.1. Regular parallel mode .................................................................................................................... 168
11.6.2. Inserted parallel mode ................................................................................................................... 168
11.6.3. Follow-up fast mode ....................................................................................................................... 169
11.6.4. Follow-up slow mode ..................................................................................................................... 169
11.6.5. Trigger rotation mode ..................................................................................................................... 170
11.6.6. Combined regular parallel & inserted parallel mode ................................................................. 171
11.6.7. Combined regular parallel & trigger rotation mode .................................................................... 171
11.6.8. Combined inserted parallel & follow-up mode ............................................................................ 172
11.7. ADC interrupts .............................................................................................................. 173
11.8. ADC registers ................................................................................................................ 174
11.8.1. Status register (ADC_STAT) ......................................................................................................... 174
11.8.2. Control register 0 (ADC_CTL0) .................................................................................................... 175
11.8.3. Control register 1 (ADC_CTL1) .................................................................................................... 177
11.8.4. Sample time register 0 (ADC_SAMPT0) ..................................................................................... 179
11.8.5. Sample time register 1 (ADC_SAMPT1) ..................................................................................... 180
11.8.6. Inserted channel data offset register x (ADC_IOFFx) (x=0..3) ................................................ 181
11.8.7. Watchdog high threshold register (ADC_WDHT) ...................................................................... 181
11.8.8. Watchdog low threshold register (ADC_WDLT) ......................................................................... 182
11.8.9. Regular sequence register 0 (ADC_RSQ0) ................................................................................ 182
11.8.10. Regular sequence register 1 (ADC_RSQ1) ............................................................................ 183
11.8.11. Regular sequence register 2 (ADC_RSQ2) ............................................................................ 183
11.8.12. Inserted sequence register (ADC_ISQ) .................................................................................. 184
11.8.13. Inserted data register x (ADC_IDATAx) (x= 0..3) ................................................................... 185
11.8.14. Regular data register (ADC_RDATA) ...................................................................................... 185
11.8.15. Oversample control register (ADC_OVSAMPCTL) ............................................................... 186
12. Digital-to-analog converter (DAC) ...................................................................... 188
12.1. Overview ...................................................................................................................... 188
12.2. Characteristics .............................................................................................................. 188
12.3. Function overview ........................................................................................................ 189
12.3.1. DAC enable ..................................................................................................................................... 189
12.3.2. DAC output buffer ........................................................................................................................... 190
12.3.3. DAC data configuration .................................................................................................................. 190
12.3.4. DAC trigger ...................................................................................................................................... 190
12.3.5. DAC conversion .............................................................................................................................. 190
12.3.6. DAC noise wave ............................................................................................................................. 191
12.3.7. DAC output voltage ........................................................................................................................ 192
12.3.8. DMA request .................................................................................................................................... 192
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12.3.9. DAC concurrent conversion .......................................................................................................... 192
12.4. Register definition ........................................................................................................ 193
12.4.1. Control register (DAC_CTL) .......................................................................................................... 193
12.4.2. Software trigger register (DAC_SWT) ......................................................................................... 195
12.4.3. DAC0 12-bit right-aligned data holding register (DAC0_R12DH) ............................................ 196
12.4.4. DAC0 12-bit left-aligned data holding register (DAC0_L12DH) ............................................... 196
12.4.5. DAC0 8-bit right-aligned data holding register (DAC0_R8DH) ................................................ 197
12.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH) ............................................ 197
12.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) ............................................... 198
12.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH) ................................................ 198
12.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) .............. 199
12.4.10. DAC concurrent mode 12-bit left-aligned data holding register (DACC_L12DH) ............. 199
12.4.11. DAC concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) .............. 200
12.4.12. DAC0 data output register (DAC0_DO) .................................................................................. 200
12.4.13. DAC1 data output register (DAC1_DO) .................................................................................. 201
13. Watchdog timer (WDGT) ...................................................................................... 202
13.1. Free watchdog timer (FWDGT) ...................................................................................... 202
13.1.1. Overview .......................................................................................................................................... 202
13.1.2. Characteristics................................................................................................................................. 202
13.1.3. Function overview ........................................................................................................................... 202
13.1.4. Register definition ........................................................................................................................... 205
13.2. Window watchdog timer (WWDGT) .............................................................................. 208
13.2.1. Overview .......................................................................................................................................... 208
13.2.2. Characteristics................................................................................................................................. 208
13.2.3. Function overview ........................................................................................................................... 208
13.2.4. Register definition ........................................................................................................................... 211
14. Real-time Clock (RTC) .......................................................................................... 213
14.1. Overview ...................................................................................................................... 213
14.2. Characteristics .............................................................................................................. 213
14.3. Function overview ........................................................................................................ 213
14.3.1. RTC reset ......................................................................................................................................... 214
14.3.2. RTC reading .................................................................................................................................... 214
14.3.3. RTC configuration ........................................................................................................................... 215
14.3.4. RTC flag assertion .......................................................................................................................... 215
14.4. Register definition ........................................................................................................ 217
14.4.1. RTC interrupt enable register(RTC_INTEN) ............................................................................... 217
14.4.2. RTC control register(RTC_CTL) ................................................................................................... 217
14.4.3. RTC prescaler high register (RTC_PSCH) ................................................................................. 218
14.4.4. RTC prescaler low register (RTC_PSCL) ................................................................................... 219
14.4.5. RTC divider high register (RTC_DIVH) ....................................................................................... 219
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14.4.6. RTC divider low register (RTC_DIVL) .......................................................................................... 219
14.4.7. RTC counter high register (RTC_CNTH) .................................................................................... 220
14.4.8. RTC counter low register (RTC_CNTL)....................................................................................... 220
14.4.9. RTC alarm high register (RTC_ALRMH) ..................................................................................... 221
14.4.10. RTC alarm low register (RTC_ALRML) ................................................................................... 221
15. Timer(TIMERx) ...................................................................................................... 222
15.1. Advanced timer (TIMERx, x=0) ...................................................................................... 223
15.1.1. Overview .......................................................................................................................................... 223
15.1.2. Characteristics................................................................................................................................. 223
15.1.3. Block diagram .................................................................................................................................. 224
15.1.4. Function overview ........................................................................................................................... 224
15.1.5. TIMERx registers(x=0) ................................................................................................................... 254
15.2. General level0 timer (TIMERx, x=1, 2, 3, 4) ..................................................................... 279
15.2.1. Overview .......................................................................................................................................... 279
15.2.2. Characteristics................................................................................................................................. 279
15.2.3. Block diagram .................................................................................................................................. 279
15.2.4. Function overview ........................................................................................................................... 280
15.2.5. TIMERx registers(x=1,2,3,4) ......................................................................................................... 297
15.3. Basic timer (TIMERx, x=5, 6) .......................................................................................... 318
15.3.1. Overview .......................................................................................................................................... 318
15.3.2. Characteristics................................................................................................................................. 318
15.3.3. Block diagram .................................................................................................................................. 318
15.3.4. Function overview ........................................................................................................................... 318
15.3.5. TIMERx registers(x=5,6) ................................................................................................................ 323
16. Universal synchronous/asynchronous receiver /transmitter (USART) ........ 328
16.1. Overview ...................................................................................................................... 328
16.2. Characteristics .............................................................................................................. 328
16.3. Function overview ........................................................................................................ 329
16.3.1. USART frame format ...................................................................................................................... 330
16.3.2. Baud rate generation ...................................................................................................................... 331
16.3.3. USART transmitter .......................................................................................................................... 331
16.3.4. USART receiver .............................................................................................................................. 333
16.3.5. Use DMA for data buffer access ................................................................................................... 334
16.3.6. Hardware flow control .................................................................................................................... 335
16.3.7. Multi-processor communication .................................................................................................... 336
16.3.8. LIN mode .......................................................................................................................................... 337
16.3.9. Synchronous mode ......................................................................................................................... 338
16.3.10. IrDA SIR ENDEC mode ............................................................................................................. 339
16.3.11. Half-duplex communication mode ............................................................................................ 341
16.3.12. Smartcard (ISO7816-3) mode .................................................................................................. 341
16.3.13. USART interrupts ........................................................................................................................ 342
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16.4. Register definition ........................................................................................................ 344
16.4.1. Status register (USART_STAT) .................................................................................................... 344
16.4.2. Data register (USART_DATA) ....................................................................................................... 346
16.4.3. Baud rate register (USART_BAUD) ............................................................................................. 346
16.4.4. Control register 0 (USART_CTL0) ............................................................................................... 347
16.4.5. Control register 1 (USART_CTL1) ............................................................................................... 349
16.4.6. Control register 2 (USART_CTL2) ............................................................................................... 350
16.4.7. Guard time and prescaler register (USART_GP) ....................................................................... 352
17. Inter-integrated circuit interface (I2C) ............................................................... 354
17.1. Overview ...................................................................................................................... 354
17.2. Characteristics .............................................................................................................. 354
17.3. Function overview ........................................................................................................ 354
17.3.1. SDA and SCL lines ......................................................................................................................... 355
17.3.2. Data validation................................................................................................................................. 356
17.3.3. START and STOP condition .......................................................................................................... 356
17.3.4. Clock synchronization .................................................................................................................... 356
17.3.5. Arbitration ......................................................................................................................................... 357
17.3.6. I2C communication flow ................................................................................................................. 357
17.3.7. Programming model ....................................................................................................................... 358
17.3.8. SCL line stretching .......................................................................................................................... 367
17.3.9. Use DMA for data transfer ............................................................................................................. 368
17.3.10. Packet error checking ................................................................................................................ 368
17.3.11. SMBus support ........................................................................................................................... 368
17.3.12. Status, errors and interrupts ..................................................................................................... 370
17.4. Register definition ........................................................................................................ 371
17.4.1. Control register 0 (I2C_CTL0)....................................................................................................... 371
17.4.2. Control register 1 (I2C_CTL1)....................................................................................................... 373
17.4.3. Slave address register 0 (I2C_SADDR0) .................................................................................... 374
17.4.4. Slave address register 1 (I2C_SADDR1) .................................................................................... 374
17.4.5. Transfer buffer register (I2C_DATA)............................................................................................. 375
17.4.6. Transfer status register 0 (I2C_STAT0) ....................................................................................... 375
17.4.7. Transfer status register 1 (I2C_STAT1) ....................................................................................... 377
17.4.8. Clock configure register (I2C_CKCFG) ....................................................................................... 378
17.4.9. Rise time register (I2C_RT)........................................................................................................... 379
18. Serial peripheral interface/Inter-IC sound (SPI/I2S) ......................................... 380
18.1. Overview ...................................................................................................................... 380
18.2. Characteristics .............................................................................................................. 380
18.2.1. SPI characteristics .......................................................................................................................... 380
18.2.2. I2S characteristics .......................................................................................................................... 380
18.3. SPI block diagram ......................................................................................................... 381
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18.4. SPI signal description .................................................................................................... 381
18.4.1. Normal configuration ...................................................................................................................... 381
18.5. SPI function overview ................................................................................................... 382
18.5.1. SPI clock timing and data format .................................................................................................. 382
18.5.2. NSS function .................................................................................................................................... 382
18.5.3. SPI operating modes ...................................................................................................................... 383
18.5.4. DMA function ................................................................................................................................... 389
18.5.5. CRC function ................................................................................................................................... 389
18.6. SPI interrupts ............................................................................................................... 389
18.6.1. Status flags ...................................................................................................................................... 389
18.6.2. Error flags ........................................................................................................................................ 390
18.7. I2S block diagram ......................................................................................................... 391
18.8. I2S signal description .................................................................................................... 391
18.9. I2S function overview ................................................................................................... 392
18.9.1. I2S audio standards ....................................................................................................................... 392
18.9.2. I2S clock ........................................................................................................................................... 400
18.9.3. Operation ......................................................................................................................................... 401
18.9.4. DMA function ................................................................................................................................... 403
18.10. I2S interrupts................................................................................................................ 404
18.10.1. Status flags .................................................................................................................................. 404
18.10.2. Error flags .................................................................................................................................... 404
18.11. Register definition ........................................................................................................ 406
18.11.1. Control register 0 (SPI_CTL0) .................................................................................................. 406
18.11.2. Control register 1 (SPI_CTL1) .................................................................................................. 408
18.11.3. Status register (SPI_STAT) ....................................................................................................... 409
18.11.4. Data register (SPI_DATA).......................................................................................................... 410
18.11.5. CRC polynomial register (SPI_CRCPOLY) ............................................................................ 411
18.11.6. RX CRC register (SPI_RCRC) ................................................................................................. 411
18.11.7. TX CRC register (SPI_TCRC) .................................................................................................. 412
18.11.8. I2S control register (SPI_I2SCTL) ........................................................................................... 413
18.11.9. I2S clock prescaler register (SPI_I2SPSC) ............................................................................ 414
19. External memory controller (EXMC) .................................................................. 416
19.1. Overview .................................................................................................................... 416
19.2. Characteristics .......................................................................................................... 416
19.3. Function overview .................................................................................................... 416
19.3.1. Block diagram .................................................................................................................................. 416
19.3.2. Basic regulation of EXMC access ................................................................................................ 417
19.3.3. External device address mapping ................................................................................................ 418
19.3.4. NOR/PSRAM controller ................................................................................................................. 418
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19.4. Register definition .................................................................................................... 424
19.4.1. NOR/PSRAM controller registers ................................................................................................. 424
20. Controller area network (CAN) ........................................................................... 427
20.1. Overview .................................................................................................................... 427
20.2. Characteristics .......................................................................................................... 427
20.3. Function overview .................................................................................................... 428
20.3.1. Working mode ................................................................................................................................. 428
20.3.2. Communication modes .................................................................................................................. 429
20.3.3. Data transmission ........................................................................................................................... 430
20.3.4. Data reception ................................................................................................................................. 432
20.3.5. Filtering function .............................................................................................................................. 433
20.3.6. Time-triggered communication ..................................................................................................... 436
20.3.7. Communication parameters .......................................................................................................... 437
20.3.8. Error flags ........................................................................................................................................ 438
20.3.9. CAN interrupts ................................................................................................................................. 439
20.4. Register definition .................................................................................................... 441
20.4.1. Control register (CAN_CTL) .......................................................................................................... 441
20.4.2. Status register (CAN_STAT) ......................................................................................................... 442
20.4.3. Transmit status register (CAN_TSTAT) ....................................................................................... 444
20.4.4. Receive message FIFO0 register (CAN_RFIFO0) .................................................................... 447
20.4.5. Receive message FIFO1 register (CAN_RFIFO1) .................................................................... 447
20.4.6. Interrupt enable register (CAN_INTEN) ...................................................................................... 448
20.4.7. Error register (CAN_ERR) ............................................................................................................. 450
20.4.8. Bit timing register (CAN_BT) ......................................................................................................... 451
20.4.9. Transmit mailbox identifier register (CAN_TMIx) (x=0..2) ........................................................ 452
20.4.10. Transmit mailbox property register (CAN_TMPx) (x=0..2) ................................................... 453
20.4.11. Transmit mailbox data0 register (CAN_TMDATA0x) (x=0..2) .............................................. 453
20.4.12. Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2) .............................................. 454
20.4.13. Receive FIFO mailbox identifier register (CAN_RFIFOMIx) (x=0,1) ................................... 454
20.4.14. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x=0,1) .................................. 455
20.4.15. Receive FIFO mailbox data0 register (CAN_RFIFOMDATA0x) (x=0,1) ............................. 456
20.4.16. Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x=0,1) ............................. 456
20.4.17. Filter control register (CAN_FCTL) .......................................................................................... 457
20.4.18. Filter mode configuration register (CAN_FMCFG) ................................................................ 457
20.4.19. Filter scale configuration register (CAN_FSCFG) ................................................................. 458
20.4.20. Filter associated FIFO register (CAN_FAFIFO) ..................................................................... 458
20.4.21. Filter working register (CAN_FW) ............................................................................................ 459
20.4.22. Filter x data y register (CAN_FxDATAy) (x=0..27, y=0,1) ..................................................... 459
21. Universal serial bus full-speed interface (USBFS) .......................................... 461
21.1. Overview ...................................................................................................................... 461
21.2. Characteristics .............................................................................................................. 461
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21.3. Block diagram ............................................................................................................... 462
21.4. Signal description ......................................................................................................... 462
21.5. Function overview ........................................................................................................ 462
21.5.1. USBFS clocks and working modes .............................................................................................. 462
21.5.2. USB host function ........................................................................................................................... 464
21.5.3. USB device function ....................................................................................................................... 466
21.5.4. OTG function overview .................................................................................................................. 467
21.5.5. Data FIFO ........................................................................................................................................ 468
21.5.6. Operation guide............................................................................................................................... 471
21.6. Interrupts ..................................................................................................................... 475
21.7. Register definition ........................................................................................................ 477
21.7.1. Global control and status registers ............................................................................................... 477
21.7.2. Host control and status registers .................................................................................................. 498
21.7.3. Device control and status registers .............................................................................................. 510
21.7.4. Power and clock control register (USBFS_PWRCLKCTL) ....................................................... 534
22. Revision history .................................................................................................... 535
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List of Figures
Figure 1-1. GD32VF103 system architecture ............................................................................................... 24
Figure 2-1. Process of page erase operation .............................................................................................. 34
Figure 2-2. Process of mass erase operation ............................................................................................. 35
Figure 2-3. Process of word program operation ........................................................................................ 37
Figure 3-1. Power supply overview ............................................................................................................... 48
Figure 3-2. Waveform of the POR/PDR ......................................................................................................... 50
Figure 3-3. Waveform of the LVD threshold ................................................................................................ 50
Figure 5-1. The system reset circuit ............................................................................................................. 63
Figure 5-2. Clock tree ...................................................................................................................................... 64
Figure 5-3. HXTAL clock source .................................................................................................................... 65
Figure 6-1. Block diagram of EXTI ................................................................................................................ 97
Figure 7.1. Basic structure of a standard I/O port bit .............................................................................. 103
Figure 7.2. Input configuration .................................................................................................................... 104
Figure 7.3. Output configuration ................................................................................................................. 105
Figure 7.4. Analog configuration ................................................................................................................. 106
Figure 7.5. Alternate function configuration ............................................................................................. 106
Figure 8-1. Block diagram of CRC calculation unit .................................................................................. 129
Figure 9-1. Block diagram of DMA .............................................................................................................. 134
Figure 9-2. Handshake mechanism ............................................................................................................. 136
Figure 9-3. DMA interrupt logic .................................................................................................................... 138
Figure 9-4. DMA0 request mapping ............................................................................................................ 139
Figure 9-5. DMA1 request mapping ............................................................................................................ 140
Figure 11-1. ADC module block diagram ................................................................................................... 154
Figure 11-2. Single conversion mode ......................................................................................................... 156
Figure 11-3. Continuous conversion mode ............................................................................................... 157
Figure 11-4. Scan conversion mode, continuous disable ...................................................................... 158
Figure 11-5. Scan conversion mode, continuous enable ....................................................................... 159
Figure 11-6. Discontinuous conversion mode .......................................................................................... 160
Figure 11-7. Auto-insertion, CNT = 1 .......................................................................................................... 161
Figure 11-8. Triggered insertion .................................................................................................................. 161
Figure 11-9. 12-bit Data alignment .............................................................................................................. 162
Figure 11-10. 6-bit Data alignment .............................................................................................................. 162
Figure 11-11. 20-bit to 16-bit result truncation .......................................................................................... 165
Figure 11-12. Numerical example with 5-bits shift and rounding .......................................................... 166
Figure 11-13. ADC sync block diagram ...................................................................................................... 167
Figure 11-14. Regular parallel mode on 16 channels............................................................................... 168
Figure 11-15. Inserted parallel mode on 4 channels ................................................................................ 169
Figure 11-16. Follow-up fast mode on 1 channel in continuous conversion mode ........................... 169
Figure 11-17. Follow-up slow mode on 1 channel .................................................................................... 170
Figure 11-18. Trigger rotation: inserted channel group .......................................................................... 171
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Figure 11-19. Trigger rotation: inserted channels in discontinuous mode ......................................... 171
Figure 11-20. Regular parallel & trigger rotation mode ........................................................................... 172
Figure 11-21. Trigger occurs during inserted conversion ...................................................................... 172
Figure 11-22 Follow-up single channel with inserted sequence CH1, CH2 ......................................... 173
Figure 12-1. DAC block diagram .................................................................................................................. 189
Figure 12-2. DAC LFSR algorithm ............................................................................................................... 191
Figure 12-3. DAC triangle noise wave ........................................................................................................ 191
Figure 13.1. Free watchdog block diagram ............................................................................................... 203
Figure 13.2. Window watchdog timer block diagram .............................................................................. 209
Figure 13.3. Window watchdog timing diagram ....................................................................................... 210
Figure 14.1. Block diagram of RTC ............................................................................................................. 214
Figure 14.2. RTC second and alarm waveform example (RTC_PSC = 3, RTC_ALRM = 2) ................ 215
Figure 14.3. RTC second and overflow waveform example (RTC_PSC= 3) ......................................... 216
Figure 15-1. Advanced timer block diagram ............................................................................................. 224
Figure 15-2. Normal mode, internal clock divided by 1 ........................................................................... 225
Figure 15-3. Counter timing diagram with prescaler division change from 1 to 2 ............................. 226
Figure 15-4. Timing chart of up counting mode, PSC=0/1 ...................................................................... 227
Figure 15-5. Timing chart of up counting mode, change TIMERx_CAR ongoing ............................... 228
Figure 15-6. Timing chart of down counting mode, PSC=0/1 ................................................................. 229
Figure 15-7. Timing chart of down counting mode, change TIMERx_CAR ongoing ......................... 230
Figure 15-8. Timing chart of center-aligned counting mode .................................................................. 231
Figure 15-9. Repetition counter timing chart of center-aligned counting mode ................................. 232
Figure 15-10. Repetition counter timing chart of up counting mode .................................................... 232
Figure 15-11. Repetition counter timing chart of down counting mode ............................................... 233
Figure 15-12. Input capture logic ................................................................................................................. 234
Figure 15-13. Output compare logic (with complementary output, x=0,1,2) ....................................... 235
Figure 15-14. Output compare logic (CH3_O) ........................................................................................... 235
Figure 15-15. Output-compare in three modes ......................................................................................... 237
Figure 15-16. Timing chart of EAPWM ........................................................................................................ 238
Figure 15-17. Timing chart of CAPWM ....................................................................................................... 238
Figure 15-18. Complementary output with dead time insertion ............................................................. 241
Figure 15-19. Output behavior of the channel in response to a break (the break high active) ........ 242
Figure 15-20. Example of counter operation in encoder interface mode ............................................. 243
Figure 15-21. Example of encoder interface mode with CI0FE0 polarity inverted ............................. 243
Figure 15-22. Hall sensor is used to BLDC motor .................................................................................... 244
Figure 15-23. Hall sensor timing between two timers ............................................................................. 245
Figure 15-24. Restart mode .......................................................................................................................... 246
Figure 15-25. Pause mode ............................................................................................................................ 246
Figure 15-26. Event mode ............................................................................................................................. 247
Figure 15-27. Single pulse mode TIMERx_CHxCV=0x04, TIMERx_CAR=0x60.................................... 248
Figure 15-28. TIMER0 Master/Slave mode timer example ....................................................................... 248
Figure 15-29. Triggering TIMER0 with enable signal of TIMER2 ............................................................ 249
Figure 15-30. Triggering TIMER0 with update signal of TIMER2 ........................................................... 250
Figure 15-31. Pause TIMER0 with enable signal of TIMER2 ................................................................... 251
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Figure 15-32. Pause TIMER0 with O0CPREF signal of Timer2 ............................................................... 251
Figure 15-33. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input .............................................. 252
Figure 15-34. General Level 0 timer block diagram ................................................................................. 280
Figure 15-35. Normal mode, internal clock divided by 1 ......................................................................... 281
Figure 15-36. Counter timing diagram with prescaler division change from 1 to 2 ........................... 282
Figure 15-37. Timing chart of up counting mode, PSC=0/1 .................................................................... 283
Figure 15-38. Timing chart of up counting mode, change TIMERx_CAR ongoing ............................. 284
Figure 15-39. Timing chart of down counting mode, PSC=0/1 ............................................................... 285
Figure 15-40. Timing chart of down counting mode, change TIMERx_CAR. ...................................... 286
Figure 15-41. Timing chart of center-aligned counting mode ................................................................ 287
Figure 15-42. Input capture logic ................................................................................................................. 288
Figure 15-43. Output-compare in three modes ......................................................................................... 290
Figure 15-44. EAPWM timechart .................................................................................................................. 291
Figure 15-45. CAPWM timechart .................................................................................................................. 291
Figure 15-46. Example of counter operation in encoder interface mode ............................................. 293
Figure 15-47. Example of encoder interface mode with CI0FE0 polarity inverted ............................. 293
Figure 15-48. Restart mode .......................................................................................................................... 294
Figure 15-49. Pause mode ............................................................................................................................ 295
Figure 15-50. Event mode ............................................................................................................................. 295
Figure 15-51. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 .................................. 296
Figure 15-52. Basic timer block diagram ................................................................................................... 318
Figure 15-53. Normal mode, internal clock divided by 1 ......................................................................... 319
Figure 15-54. Counter timing diagram with prescaler division change from 1 to 2 ........................... 320
Figure 15-55. Timing chart of up counting mode, PSC=0/1 .................................................................... 321
Figure 15-56. Timing chart of up counting mode, change TIMERx_CAR ongoing ............................. 322
Figure 16-1. USART module block diagram .............................................................................................. 330
Figure 16-2. USART character frame (8 bits data and 1 stop bit) .......................................................... 330
Figure 16-3. USART transmit procedure .................................................................................................... 332
Figure 16-4. Receiving a frame bit by oversampling method ................................................................. 333
Figure 16-5. Configuration steps when using DMA for USART transmission ..................................... 334
Figure 16-6. Configuration steps when using DMA for USART reception ........................................... 335
Figure 16-7. Hardware flow control between two USARTs ..................................................................... 336
Figure 16-8. Hardware flow control ............................................................................................................. 336
Figure 16-9. Break frame occurs during idle state ................................................................................... 338
Figure 16-10. Break frame occurs during a frame .................................................................................... 338
Figure 16-11. Example of USART in synchronous mode ........................................................................ 339
Figure 16-12. 8-bit format USART synchronous waveform (CLEN=1) .................................................. 339
Figure 16-13. IrDA SIR ENDEC module ...................................................................................................... 340
Figure 16-14. IrDA data modulation ............................................................................................................ 340
Figure 16-15. ISO7816-3 frame format ........................................................................................................ 341
Figure 16-16. USART interrupt mapping diagram .................................................................................... 343
Figure 17-1. I2C module block diagram ..................................................................................................... 355
Figure 17-2. Data validation .......................................................................................................................... 356
Figure 17-3. START and STOP condition ................................................................................................... 356
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Figure 17-4. Clock synchronization ............................................................................................................ 357
Figure 17-5. SDA Line arbitration ................................................................................................................ 357
Figure 17-6. I2C communication flow with 7-bit address ........................................................................ 358
Figure 17-7. I2C communication flow with 10-bit address (Master Transmit) ..................................... 358
Figure 17-8. I2C communication flow with 10-bit address (Master Receive) ...................................... 358
Figure 17-9. Programming model for slave transmitting(10-bit address mode) ................................. 360
Figure 17-10. Programming model for slave receiving(10-bit address mode) .................................... 361
Figure 17-11. Programming model for master transmitting(10-bit address mode) ............................ 363
Figure 17-12. Programming model for master receiving using Solution A(10-bit address mode) .. 365
Figure 17-13. Programming model for master receiving using solution B(10-bit address mode) .. 367
Figure 18-1. Block diagram of SPI ............................................................................................................... 381
Figure 18-2. SPI timing diagram in normal mode ..................................................................................... 382
Figure 18-3. A typical full-duplex connection ........................................................................................... 384
Figure 18-4. A typical simplex connection (Master: Receive, Slave: Transmit) .................................. 384
Figure 18-5. A typical simplex connection (Master: Transmit only, Slave: Receive) ......................... 384
Figure 18-6. A typical bidirectional connection ........................................................................................ 385
Figure 18-7. Timing diagram of TI master mode with discontinuous transfer..................................... 386
Figure 18-8. Timing diagram of TI master mode with continuous transfer .......................................... 387
Figure 18-9. Timing diagram of TI slave mode .......................................................................................... 387
Figure 18-10. Timing diagram of NSS pulse with continuous transmission ....................................... 388
Figure 18-11. Block diagram of I2S .............................................................................................................. 391
Figure 18-12. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ....................... 392
Figure 18-13. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ....................... 392
Figure 18-14. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0)........................................... 393
Figure 18-15. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ....................... 393
Figure 18-16. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ...................... 393
Figure 18-17. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ...................... 393
Figure 18-18. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ...................... 394
Figure 18-19. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ...................... 394
Figure 18-20. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ................... 394
Figure 18-21. MSB justified standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ................... 394
Figure 18-22. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ................... 394
Figure 18-23. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ................... 395
Figure 18-24. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ................... 395
Figure 18-25. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ................... 395
Figure 18-26. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) .................. 395
Figure 18-27. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) .................. 395
Figure 18-28. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ................... 396
Figure 18-29. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ................... 396
Figure 18-30. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) .................... 396
Figure 18-31. LSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) .................... 396
Figure 18-32. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=0) ................................................................................................................................ 397
Figure 18-33. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
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CHLEN=0, CKPL=1) ................................................................................................................................ 397
Figure 18-34. PCM standard short frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0) ................................................................................................................................ 397
Figure 18-35. PCM standard short frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1) ................................................................................................................................ 397
Figure 18-36. PCM standard short frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0) ................................................................................................................................ 397
Figure 18-37. PCM standard short frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=1) ................................................................................................................................ 397
Figure 18-38. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=0) ................................................................................................................................ 398
Figure 18-39. PCM standard short frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1) ................................................................................................................................ 398
Figure 18-40. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=0) ................................................................................................................................ 398
Figure 18-41. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=0, CKPL=1) ................................................................................................................................ 398
Figure 18-42. PCM standard long frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=0) ................................................................................................................................ 398
Figure 18-43. PCM standard long frame synchronization mode timing diagram (DTLEN=10,
CHLEN=1, CKPL=1) ................................................................................................................................ 399
Figure 18-44. PCM standard long frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=0) ................................................................................................................................ 399
Figure 18-45. PCM standard long frame synchronization mode timing diagram (DTLEN=01,
CHLEN=1, CKPL=1) ................................................................................................................................ 399
Figure 18-46. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=0) ................................................................................................................................ 399
Figure 18-47. PCM standard long frame synchronization mode timing diagram (DTLEN=00,
CHLEN=1, CKPL=1) ................................................................................................................................ 399
Figure 18-48. Block diagram of I2S clock generator ................................................................................ 400
Figure 19-1. The EXMC block diagram ....................................................................................................... 417
Figure 19-2. EXMC memory banks .............................................................................................................. 418
Figure 19-3. Region of bank0 address mapping ....................................................................................... 418
Figure 19-4. Multiplex mode read access .................................................................................................. 421
Figure 19-5. Multiplex mode write access ................................................................................................. 421
Figure 19-6. Read access timing diagram under async-wait signal assertion.................................... 423
Figure 19-7. Write access timing diagram under async-wait signal assertion ................................... 423
Figure 20-1. CAN module block diagram ................................................................................................... 428
Figure 20-2. Transmission register ............................................................................................................. 430
Figure 20-3. State of transmission mailbox ............................................................................................... 431
Figure 20-4. Reception register ................................................................................................................... 432
Figure 20-5. 32-bit filter ................................................................................................................................. 434
Figure 20-6. 16-bit filter ................................................................................................................................. 434
Figure 20-7. 32-bit mask mode filter ........................................................................................................... 434
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Figure 20-8. 16-bit mask mode filter ........................................................................................................... 434
Figure 20-9. 32-bit list mode filter................................................................................................................ 434
Figure 20-10. 16-bit list mode filter ............................................................................................................. 434
Figure 20-11. The bit time ............................................................................................................................. 438
Figure 21-1. USBFS block diagram ............................................................................................................. 462
Figure 21-2. Connection with host or device mode ................................................................................. 463
Figure 21-3. Connection with OTG mode ................................................................................................... 464
Figure 21-4. State transition diagram of host port ................................................................................... 464
Figure 21-5. HOST mode FIFO space in SRAM ......................................................................................... 469
Figure 21-6. Host mode FIFO access register map .................................................................................. 469
Figure 21-7. Device mode FIFO space in SRAM ....................................................................................... 470
Figure 21-8. Device mode FIFO access register map .............................................................................. 471
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List of Tables
Table 1-1. The interconnection relationship of the AHB interconnect matrix ....................................... 23
Table 1-2. Memory map of GD32VF103 devices ......................................................................................... 25
Table 1-3. Boot modes .................................................................................................................................... 29
Table 2-1. Base address and size for flash memory .................................................................................. 32
Table 2-2. Option byte ...................................................................................................................................... 38
Table 3-1. Power saving mode summary ..................................................................................................... 52
Table 5-1. Clock output 0 source select ....................................................................................................... 68
Table 5-2. 1.2V domain voltage selected in deep-sleep mode ................................................................. 68
Table 6-1. Interrupt vector table .................................................................................................................... 95
Table 6-2. EXTI source .................................................................................................................................... 98
Table 7.1. GPIO configuration table ............................................................................................................ 102
Table 7.2. Debug interface signals .............................................................................................................. 108
Table 7.3. Debug port mapping.................................................................................................................... 108
Table 7.4. TIMER0 alternate function remapping ...................................................................................... 109
Table 7.5. TIMER1 alternate function remapping ...................................................................................... 109
Table 7.6. TIMER2 alternate function remapping ...................................................................................... 109
Table 7.7. TIMER3 alternate function remapping ...................................................................................... 109
Table 7.8. TIMER4 alternate function remapping ...................................................................................... 110
Table 7.9. USART0 alternate function remapping ..................................................................................... 110
Table 7.10. USART1 alternate function remapping ................................................................................... 110
Table 7.11. USART2 alternate function remapping ................................................................................... 110
Table 7.12. I2C0 alternate function remapping .......................................................................................... 110
Table 7.13. SPI0 alternate function remapping .......................................................................................... 111
Table 7.14. SPI2/I2S2 alternate function remapping ................................................................................. 111
Table 7.15. CAN0 alternate function remapping ....................................................................................... 111
Table 7.16. CAN1 alternate function remapping ....................................................................................... 111
Table 7.17. OSC32 pins configuration......................................................................................................... 112
Table 7.18. OSC pins configuration ............................................................................................................. 112
Table 9-1. DMA transfer operation .............................................................................................................. 135
Table 9-2. Interrupt events ............................................................................................................................ 138
Table 9-3. DMA0 requests for each channel .............................................................................................. 140
Table 9-4. DMA1 requests for each channel .............................................................................................. 141
Table 11-1. ADC internal signals ................................................................................................................. 154
Table 11-2. ADC pins definition ................................................................................................................... 154
Table 11-3. External trigger for regular channels for ADC0 and ADC1 ................................................. 163
Table 11-4. External trigger for inserted channels for ADC0 and ADC1 ............................................... 163
Table 11-5. t
Table 11-6. Maximum output results vs N and M (Grayed values indicates truncation) ................... 166
Table 12-1. DAC pins ..................................................................................................................................... 189
Table 12-2. External triggers of DAC........................................................................................................... 190
timings depending on resolution .................................................................................. 164
CONV
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Table 13.1. Min/max FWDGT timeout period at 40 kHz (IRC40K) .......................................................... 203
Table 13.2. Min/max timeout value at 54 MHz (f
) .............................................................................. 210
PCLK1
Table 15-1. Timers (TIMERx) are devided into three sorts ...................................................................... 222
Table 15-2. Complementary outputs controlled by parameters ............................................................ 240
Table 15-3. Counting direction versus encoder signals ......................................................................... 243
Table 15-4. Slave mode example table ....................................................................................................... 245
Table 15-5. Counting direction versus encoder signals ......................................................................... 292
Table 15-6. Slave controller examples ........................................................................................................ 294
Table 16-1. Description of USART important pins .................................................................................... 329
Table 16-2. Stop bits configuration ............................................................................................................. 330
Table 16-3. USART interrupt requests ........................................................................................................ 342
Table 17-1. Definition of I2C-bus terminology (refer to the I2C specification of philips
semiconductors) .................................................................................................................................... 355
Table17-2. Event status flags ....................................................................................................................... 370
Table17-3. I2C error flags .............................................................................................................................. 370
Table 18-1. SPI signal description ............................................................................................................... 381
Table 18-2. SPI operating modes ................................................................................................................. 383
Table 18-3. SPI interrupt requests ............................................................................................................... 390
Table 18-4. I2S bitrate calculation formulas .............................................................................................. 400
Table 18-5. Audio sampling frequency calculation formulas ................................................................. 400
Table 18-6. Direction of I2S interface signals for each operation mode .............................................. 401
Table 18-7. I2S interrupt ................................................................................................................................ 405
Table 19-1. NOR Flash interface signals description .............................................................................. 419
Table 19-2. PSRAM muxed signal description .......................................................................................... 419
Table 19-3. EXMC bank 0 supports all transactions ................................................................................ 419
Table 19-4. NOR / PSRAM controller timing parameters ......................................................................... 420
Table 19-5. EXMC_timing models................................................................................................................ 421
Table 19-6. Multiplex mode related registers configuration ................................................................... 422
Table 20-1. 32-bit filter number .................................................................................................................... 435
Table 20-2. Filtering index ............................................................................................................................. 435
Table 21-1. USBFS signal description ........................................................................................................ 462
Table 21-2. USBFS global interrupt ............................................................................................................. 475
Table 22-1. Revision history ......................................................................................................................... 535
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GD32VF103 User Manual
1. System and memory architecture
The devices of GD32VF103 series are 32-bit general-purpose microcontrollers based on the
32bit RISC-V processor. The RISC-V processor includes three AHB buses known as I-Code
bus, D-Code bus and System buse. All memory accesses of the RISC-V processor are
executed on the three buses according to the different purposes and the target memory
spaces. The memory organization uses a Harvard architecture, pre-defined memory map and
up to 4 GB of memory space, making the system flexible and extendable.
1.1. RISC-V CPU
RISC-V CPU target for embedded applications that require low energy consumption and small
area, which is compliant to RISC-V architecture with several efficient micro-architecture
features, including simple dynamic branch prediction, instruction pre-fetch buffers and local
memories. It supports 32 general purpose registers (GPRs) and fast multiplier for
performance/area tradeoff:
RISC-V compliant little-endian RV32IMAC (32GPRs) ;
Configurable 2-stage pipeline optimized for low gate-count and high frequency;
Machine (M) and User (U) Privilege levels support;
Single-cycle hardware multiplier and Multi-cycles hardware divider support;
Misaligned load/store hardware support;
Atomic instructions hardware support;
Non-maskable interrupt (NMI) support;
Dynamic Branch Prediction and instruction pre-fetch buffers to speed up control code;
State-of-the-art micro-architecture design to tradeoff area and performance
requirements;
WFI (Wait for Interrupt) support;
WFE (Wait for Event) support;
Interrupt priority levels configurable and programmable;
Enhancement of vectored interrupt handling for real-time performance;
Support interrupt preemption with priority ;
Support interrupt tail chaining;
Standard 4-wire JTAG debug port
Support interactive debug functionalities
Support 4 triggers for hardware breakpoint
1.2. System architecture
A 32-bit multilayer bus is implemented in the GD32VF103 devices, which makes the parallel
access paths between multiple masters and slaves in the system possible The multilayer bus
consists of an AHB interconnect matrix, one AHB bus and two APB buses. The
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GD32VF103 User Manual
IBUS
DBUS
SBUS
DMA0
DMA1
FMC-I
1
FMC-D
1 1 1
SRAM
1 1 1 1 1
EXMC
1 1 1 1 1
AHB
1 1
1
APB1
1 1
1
APB2
1 1
1
interconnection relationship of the AHB interconnect matrix is shown below. In Table 1-1. The
interconnection relationship of the AHB interconnect matrix, “1” indicates the
corresponding master is able to access the corresponding slave through the AHB
interconnect matrix, the blank indicates the corresponding master cannot access the
corresponding slave through the AHB interconnect matrix.
Table 1-1. The interconnection relationship of the AHB interconnect matrix
As is shown above, there are several masters connected with the AHB interconnect matrix,
including IBUS, DBUS, SBUS, DMA0 and DMA1. IBUS is the instruction bus of the RISC-V
core, which is used for fetching instruction/vector from the Code region (0x0000 0000 ~
0x1FFF FFFF). DBUS is the data bus of the RISC-V core, which is used for loading/storing
data and also for debugging access of the Code region. Similarly, SBUS is the system bus of
the RISC-V core, which is used for fetching instruction/vector, loading/storing data and
debugging access of the system regions. The System regions include the internal SRAM
region and the Peripheral region. DMA0 and DMA1 are the buses of DMA0 and DMA1
respectively.
There are also several slaves connected with the AHB interconnect matrix, including FMC-I,
FMC-D, SRAM, EXMC, AHB, APB1 and APB2. FMC-I is the instruction bus of the flash
memory controller, FMC-D is the data bus of the flash memory controller. SRAM is on-chip
static random access memories. EXMC is the external memory controller. AHB is the AHB
bus connected with all AHB slaves, APB1 and APB2 connected with all APB slaves and all
APB peripherals. APB1 is limited to 54 MHz, APB2 operates at full speed (up to 108MHz
depending on the device).
As shown in the following figure, these are interconnected using the multilayer AHB bus
architecture.
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GD32VF103 User Manual
ECLIC
Flash
Memory
Controller
Flash
Memory
SRAM
Controller
SRAM
AHB to APB
Bridge 2
AHB to APB
Bridge 1
USART0
SPI0
EXTI
GPIOA
GPIOB
USART1~2
SPI1~2
TIMER1~3
WWDGT
CAN0
Slave
Slave
Slave
Slave Slave
Master
Ibus
Dbus
Interrput request
POR/PDR
PLL
Fmax: 108MHz
LDO
1.2V
IRC
8MHz
HXTAL
3-25MHz
LVD
Powered By VDDA
Master
I2C0
I2C1
FWDGT
RTC
DAC
TIMER4~6
GPIOC
GPIOD
GPIOE
TIMER0
USART3~5
CAN1
ADC0~1
AHB Peripherals
FMC
USB
FS
CRC RCU
GP DMA0
Slave
EXMC
12-bit
SAR ADC
Powered By VDDA
RISC_V
CPU
Fmax:108MHz
JTAG
System
DCode
ICode
AHB Matrix
APB2: Fmax = 108MHz
APB1: Fmax = 54MHZ
Master
GP DMA1
Figure 1-1. GD32VF103 system architecture
1.3. Memory map
The RISC-V processor is structured using a Harvard architecture which uses separate buses
to fetch instructions and load/store data. The instruction code and data are both located in
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GD32VF103 User Manual
Pre-defined
Regions
Bus
Address
Peripherals
External
device
AHB
0xA000 0000 - 0xA000 0FFF
EXMC - SWREG
External RAM
0x9000 0000 - 0x9FFF FFFF
Reserved
0x7000 0000 - 0x8FFF FFFF
Reserved
0x6000 0000 - 0x6FFF FFFF
EXMC -
NOR/PSRAM/SRA
M
Peripheral
AHB
0x5000 0000 - 0x5003 FFFF
USBFS
0x4008 0000 - 0x4FFF FFFF
Reserved
0x4004 0000 - 0x4007 FFFF
Reserved
0x4002 BC00 - 0x4003 FFFF
Reserved
0x4002 B000 - 0x4002 BBFF
Reserved
0x4002 A000 - 0x4002 AFFF
Reserved
0x4002 8000 - 0x4002 9FFF
Reserved
0x4002 6800 - 0x4002 7FFF
Reserved
0x4002 6400 - 0x4002 67FF
Reserved
0x4002 6000 - 0x4002 63FF
Reserved
0x4002 5000 - 0x4002 5FFF
Reserved
0x4002 4000 - 0x4002 4FFF
Reserved
0x4002 3C00 - 0x4002 3FFF
Reserved
0x4002 3800 - 0x4002 3BFF
Reserved
0x4002 3400 - 0x4002 37FF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2C00 - 0x4002 2FFF
Reserved
0x4002 2800 - 0x4002 2BFF
Reserved
0x4002 2400 - 0x4002 27FF
Reserved
0x4002 2000 - 0x4002 23FF
FMC
0x4002 1C00 - 0x4002 1FFF
Reserved
0x4002 1800 - 0x4002 1BFF
Reserved
the same memory address space but in different address ranges. Program memory, data
memory, registers and I/O ports are organized within the same linear 4-Gbyte address
space .The maximum address range of the RISC-V is 4-Gbyte due to its 32-bit bus address
width. Additionally, a pre-defined memory map is provided by the RISC-V processor to reduce
the software complexity of repeated implementation for different device vendors. In the map,
some regions are used by the RISC-V system peripherals which can not be modified.
However, the other regions are available to the vendors. Table 1-2. Memory map of
GD32VF103 devices shows the memory map of the GD32VF103 series devices, including
Code, SRAM, peripheral, and other pre-defined regions. Almost each peripheral is allocated
1KB of space. This allows simplifying the address decoding for each peripheral.
Table 1-2. Memory map of GD32VF103 devices
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GD32VF103 User Manual
Pre-defined
Regions
Bus
Address
Peripherals
0x4002 1400 - 0x4002 17FF
Reserved
0x4002 1000 - 0x4002 13FF
RCU
0x4002 0C00 - 0x4002 0FFF
Reserved
0x4002 0800 - 0x4002 0BFF
Reserved
0x4002 0400 - 0x4002 07FF
DMA1
0x4002 0000 - 0x4002 03FF
DMA0
0x4001 8400 - 0x4001 FFFF
Reserved
0x4001 8000 - 0x4001 83FF
Reserved
APB2
0x4001 7C00 - 0x4001 7FFF
Reserved
0x4001 7800 - 0x4001 7BFF
Reserved
0x4001 7400 - 0x4001 77FF
Reserved
0x4001 7000 - 0x4001 73FF
Reserved
0x4001 6C00 - 0x4001 6FFF
Reserved
0x4001 6800 - 0x4001 6BFF
Reserved
0x4001 5C00 - 0x4001 67FF
Reserved
0x4001 5800 - 0x4001 5BFF
Reserved
0x4001 5400 - 0x4001 57FF
Reserved
0x4001 5000 - 0x4001 53FF
Reserved
0x4001 4C00 - 0x4001 4FFF
Reserved
0x4001 4800 - 0x4001 4BFF
Reserved
0x4001 4400 - 0x4001 47FF
Reserved
0x4001 4000 - 0x4001 43FF
Reserved
0x4001 3C00 - 0x4001 3FFF
Reserved
0x4001 3800 - 0x4001 3BFF
USART0
0x4001 3400 - 0x4001 37FF
Reserved
0x4001 3000 - 0x4001 33FF
SPI0
0x4001 2C00 - 0x4001 2FFF
TIMER0
0x4001 2800 - 0x4001 2BFF
ADC1
0x4001 2400 - 0x4001 27FF
ADC0
0x4001 2000 - 0x4001 23FF
Reserved
0x4001 1C00 - 0x4001 1FFF
Reserved
0x4001 1800 - 0x4001 1BFF
GPIOE
0x4001 1400 - 0x4001 17FF
GPIOD
0x4001 1000 - 0x4001 13FF
GPIOC
0x4001 0C00 - 0x4001 0FFF
GPIOB
0x4001 0800 - 0x4001 0BFF
GPIOA
0x4001 0400 - 0x4001 07FF
EXTI
0x4001 0000 - 0x4001 03FF
AFIO
APB1
0x4000 CC00 - 0x4000 FFFF
Reserved
0x4000 C800 - 0x4000 CBFF
Reserved
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GD32VF103 User Manual
Pre-defined
Regions
Bus
Address
Peripherals
0x4000 C400 - 0x4000 C7FF
Reserved
0x4000 C000 - 0x4000 C3FF
Reserved
0x4000 8000 - 0x4000 BFFF
Reserved
0x4000 7C00 - 0x4000 7FFF
Reserved
0x4000 7800 - 0x4000 7BFF
Reserved
0x4000 7400 - 0x4000 77FF
DAC
0x4000 7000 - 0x4000 73FF
PMU
0x4000 6C00 - 0x4000 6FFF
BKP
0x4000 6800 - 0x4000 6BFF
CAN1
0x4000 6400 - 0x4000 67FF
CAN0
0x4000 6000 - 0x4000 63FF
Shared USB/CAN
SRAM 512 bytes
0x4000 5C00 - 0x4000 5FFF
USB device FS
registers
0x4000 5800 - 0x4000 5BFF
I2C1
0x4000 5400 - 0x4000 57FF
I2C0
0x4000 5000 - 0x4000 53FF
UART4
0x4000 4C00 - 0x4000 4FFF
UART3
0x4000 4800 - 0x4000 4BFF
USART2
0x4000 4400 - 0x4000 47FF
USART1
0x4000 4000 - 0x4000 43FF
Reserved
0x4000 3C00 - 0x4000 3FFF
SPI2/I2S2
0x4000 3800 - 0x4000 3BFF
SPI1/I2S1
0x4000 3400 - 0x4000 37FF
Reserved
0x4000 3000 - 0x4000 33FF
FWDGT
0x4000 2C00 - 0x4000 2FFF
WWDGT
0x4000 2800 - 0x4000 2BFF
RTC
0x4000 2400 - 0x4000 27FF
Reserved
0x4000 2000 - 0x4000 23FF
Reserved
0x4000 1C00 - 0x4000 1FFF
Reserved
0x4000 1800 - 0x4000 1BFF
Reserved
0x4000 1400 - 0x4000 17FF
TIMER6
0x4000 1000 - 0x4000 13FF
TIMER5
0x4000 0C00 - 0x4000 0FFF
TIMER4
0x4000 0800 - 0x4000 0BFF
TIMER3
0x4000 0400 - 0x4000 07FF
TIMER2
0x4000 0000 - 0x4000 03FF
TIMER1
SRAM
AHB
0x2007 0000 - 0x3FFF FFFF
Reserved
0x2006 0000 - 0x2006 FFFF
Reserved
0x2003 0000 - 0x2005 FFFF
Reserved
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GD32VF103 User Manual
Pre-defined
Regions
Bus
Address
Peripherals
0x2002 0000 - 0x2002 FFFF
Reserved
0x2001 C000 - 0x2001 FFFF
Reserved
0x2001 8000 - 0x2001 BFFF
Reserved
0x2000 5000 - 0x2001 7FFF
SRAM
0x2000 0000 - 0x2000 4FFF
Code
AHB
0x1FFF F810 - 0x1FFF FFFF
Reserved
0x1FFF F800 - 0x1FFF F80F
Option Bytes
0x1FFF B000 - 0x1FFF F7FF
Boot loader
0x1FFF 7A10 - 0x1FFF AFFF
Reserved
0x1FFF 7800 - 0x1FFF 7A0F
Reserved
0x1FFF 0000 - 0x1FFF 77FF
Reserved
0x1FFE C010 - 0x1FFE FFFF
Reserved
0x1FFE C000 - 0x1FFE C00F
Reserved
0x1001 0000 - 0x1FFE BFFF
Reserved
0x1000 0000 - 0x1000 FFFF
Reserved
0x083C 0000 - 0x0FFF FFFF
Reserved
0x0802 0000 - 0x083B FFFF
Reserved
0x0800 0000 - 0x0801 FFFF
Main Flash
0x0030 0000 - 0x07FF FFFF
Reserved
0x0010 0000 - 0x002F FFFF
Aliased to Main
Flash or Boot loader
0x0002 0000 - 0x000F FFFF
0x0000 0000 - 0x0001 FFFF
1.3.1. On-chip SRAM memory
1.3.2. On-chip flash memory overview
The GD32VF103 series of devices contain up to 32 KB of on-chip SRAM which address starts
at 0x2000 0000. It supports byte, half-word (16 bits), and word (32 bits) accesses.
The devices provide high density on-chip flash memory, which is organized as follows:
Up to 128KB of main flash memory.
Up to 18KB of information blocks for the boot loader.
Option bytes to configure the device.
Refer to Flash memory controller (FMC) Chapter for more details.
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GD32VF103 User Manual
Selected boot source
Boot mode selection pins
Boot1
Boot0
Main Flash Memory
x
0
Boot loader
0 1 On-chip SRAM
1
1
1.4. Boot configuration
The GD32VF103 devices provide three kinds of boot sources which can be selected by the
BOOT0 and BOOT1 pins. The details are shown in the following table. The value on the two
pins is latched on the 4th rising edge of CK_SYS after a reset. User can select the required
boot source by set the BOOT0 and BOOT1 pins after a power-on reset or a system reset.
Once the two pins have been sampled, they are free and can be used for other purposes.
Table 1-3. Boot modes
Note: When the boot source is hoped to be set as “Main Flash Memory”, the Boot0 pin has
to be connected with GND definitely and can not be floating.
The embedded boot loader is located in the System memory, which is used to reprogram the
Flash memory. In GD32VF103 devices, the boot loader can be activated through the USART0
(PA9 and PA10), USART1 (PD5 and PD6), USBFS in device mode (PA9, PA11 and PA12)
interface.
1.5. Device electronic signature
The device electronic signature contains memory size information and the 96-bit unique
device ID. It is stored in the information block of the Flash memory. The 96-bit unique device
ID is unique for any device. It can be used as serial numbers, or part of security keys, etc.
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GD32VF103 User Manual
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SRAM_DENSITY[15:0]
r
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
FLASH_DENSITY[15:0]
r
Bits
Fields
Descriptions
31:16
SRAM_DENSITY
[15:0]
SRAM density
The value indicates the on-chip SRAM density of the device in Kbytes.
Example: 0x0008 indicates 8 Kbytes.
15:0
FLASH_DENSITY
[15:0]
Flash memory density
The value indicates the Flash memory density of the device in Kbytes.
Example: 0x0020 indicates 32 Kbytes.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
UNIQUE_ID[31:16]
r
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
UNIQUE_ID[15:0]
r
Bits
Fields
Descriptions
31:0
UNIQUE_ID[31:0]
Unique device ID
1.5.1. Memory density information
Base address: 0x1FFF F7E0
The value is factory programmed and can never be altered by user.
1.5.2. Unique device ID (96 bits)
Base address: 0x1FFF F7E8
The value is factory programmed and can never be altered by user.
Base address: 0x1FFF F7EC
The value is factory programmed and can never be altered by user.
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GD32VF103 User Manual
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
UNIQUE_ID[63:48]
r
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
UNIQUE_ID[47:32]
r
Bits
Fields
Descriptions
31:0
UNIQUE_ID[63:32]
Unique device ID
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
UNIQUE_ID[95:80]
r
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
UNIQUE_ID[79:64]
r
Bits
Fields
Descriptions
31:0
UNIQUE_ID[95:64]
Unique device ID
Base address: 0x1FFF F7F0
The value is factory programmed and can never be altered by user.
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GD32VF103 User Manual
Block
Name
Address Range
size
(bytes)
Main Flash Block
Page 0
0x0800 0000 - 0x0800 03FF
1KB
Page 1
0x0800 0400 - 0x0800 07FF
1KB
Page 2
0x0800 0800 - 0x0800 0BFF
1KB
…
…
…
Page 127
0x0801 FC00 - 0x0801 FFFF
1KB
Information Block
Boot loader area
0x1FFF B000- 0x1FFF F7FF
18KB
Option bytes Block
Option bytes
0x1FFF F800 - 0x1FFF F80F
16B
2. Flash memory controller (FMC)
2.1. Overview
The flash memory controller, FMC, provides all the necessary functions for the on-chip flash
memory. There is no waiting time while CPU executes instructions stored in the flash. It also
provides page erase, mass erase, and word/half-word program operations for flash memory.
2.2. Characteristics
Up to 128KB of on-chip flash memory for instruction and data.
No waiting time when CPU executes instructions.
The flash page size is 1KB for all series.
Word/half-word programming, page erase and mass erase operation.
16B option bytes block for user application requirements.
Option bytes are uploaded to the option byte control registers on every system reset.
Flash security protection to prevent illegal code/data access.
Page erase/program protection to prevent unexpected operation.
2.3. Function overview
2.3.1. Flash memory architecture
The flash memory consists of up to 128 KB main flash organized into 128 pages with 1 KB
capacity per page and a 18 KB Information Block for the Boot Loader. The main flash memory
contains a total of up to 128 pages which can be erased individually. The Table 2-1. Base
address and size for flash memory shows the details of flash organization.
Table 2-1. Base address and size for flash memory
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GD32VF103 User Manual
Note: The Information Block stores the boot loader. This block cannot be programmed or
erased by user.
2.3.2. Read operations
The flash can be addressed directly as a common memory space. Any instruction fetch and
the data access from the flash are through the IBUS or DBUS from the CPU.
2.3.3. Unlock the FMC_CTL registers
After reset, the FMC_CTL registers are not accessible in write mode, and the LK bit in
FMC_CTL register is 1. An unlocking sequence consists of two write operations to the
FMC_KEY register to open the access to the FMC_CTL register. The two write operations are
writing 0x45670123 and 0xCDEF89AB to the FMC_KEY register. After the two write
operations, the LK bit in FMC_CTL register is reset to 0 by hardware. The software can lock
the FMC_CTL again by setting the LK bit in FMC_CTL register to 1. Any wrong operations to
the FMC_KEY will set the LK bit to 1, and lock FMC_CTL register, and lead to a bus error.
The OBPG bit and OBER bit in FMC_CTL are still protected even the FMC_CTL is unlocked.
The unlocking sequence is two write operations, which are writing 0x45670123 and
0xCDEF89AB to FMC_OBKEY register. And then the hardware sets the OBWEN bit in
FMC_CTL register to 1. The software can reset OBWEN bit to 0 to protect the OBPG bit and
OBER bit in FMC_CTL register again.
2.3.4. Page erase
The FMC provides a page erase function which is used to initialize the contents of a main
flash memory page to a high state. Each page can be erased independently without affecting
the contents of other pages. The following steps show the access sequence of the registers
for a page erase operation.
Unlock the FMC_CTL registers if necessary.
Check the BUSY bit in FMC_STAT registers to confirm that no flash memory operation
is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished.
Set the PER bit in FMC_CTL registers.
Write the page absolute address (0x08XX XXXX) into the FMC_ADDR registers.
Send the page erase command to the FMC by setting the START bit in FMC_CTL
registers.
Wait until all the operations have finished by checking the value of the BUSY bit in
FMC_STAT registers.
Read and verify the page if required using a DBUS access.
When the operation is executed successfully, the ENDF in FMC_STAT registers is set, and
an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL registers is set. Note
that a correct target page address must be confirmed. Or the software may run out of control
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GD32VF103 User Manual
Set the PER bit,
Write
FMC_ADDR
Is the LK bit is 0
Send the command
to FMC by setting
START bit
Start
Yes
No
Unlock the
FMC_CTL
Is the BUSY bit is 0
Yes
No
Is the BUSY bit is 0
Yes
No
Finish
if the target erase page is being used to fetch codes or to access data. The FMC will not
provide any notification when this occurs. Additionally, the page erase operation will be
ignored on erase/program protected pages. In this condition, a flash operation error interrupt
will be triggered by the FMC if the ERRIE bit in the FMC_CTL registers is set. The software
can check the WPERR bit in the FMC_STAT registers to detect this condition in the interrupt
handler. Figure 2-1. Process of page erase operation shows the page erase operation flow.
Figure 2-1. Process of page erase operation
2.3.5. Mass erase
The FMC provides a complete erase function which is used to initialize the main flash block
contents. This erase can affect by setting MER bit to 1 in the FMC_CTL register. The following
steps show the mass erase register access sequence.
Unlock the FMC_CTL registers if necessary.
Check the BUSY bit in FMC_STAT registers to confirm that no flash memory operation
is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished.
Set MER bit in FMC_CTL register
Send the mass erase command to the FMC by setting the START bit in FMC_CTL
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GD32VF103 User Manual
Set the MER bit
Is the LK bit is 0
Send the command
to FMC by setting
START bit
Start
Yes
No
Unlock the
FMC_CTL
Is the BUSY bit is 0
Yes
No
Is the BUSY bit is 0
Yes
No
Finish
registers.
Wait until all the operations have been finished by checking the value of the BUSY bit in
FMC_STAT registers.
Read and verify the flash memory if required using a DBUS access.
When the operation is executed successfully, the ENDF in FMC_STAT registers is set, and
an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL registers is set. Since
all flash data will be modified to a value of 0xFFFF_FFFF, the mass erase operation can be
implemented using a program that runs in SRAM or by using the debugging tool that accesses
the FMC registers directly.
The following figure indicates the mass erase operation flow.
Figure 2-2. Process of mass erase operation
2.3.6. Main flash programming
The FMC provides a 32-bit word/16-bit half word programming function which is used to
modify the main flash memory contents. The following steps show the register access
sequence of the word programming operation.
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GD32VF103 User Manual
Unlock the FMC_CTL registers if necessary.
Check the BUSY bit in FMC_STAT registers to confirm that no flash memory operation
is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished.
Set the PG bit in FMC_CTL registers.
Write a 32-bit word/16-bit half word to desired absolute address (0x08XX XXXX) by
DBUS.
Wait until all the operations have been finished by checking the value of the BUSY bit in
FMC_STAT registers.
Read and verify the Flash memory if required using a DBUS access.
When the operation is executed successfully, the ENDF in FMC_STAT registers is set, and
an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL registers is set. Note
that the word/half word programming operation checks the address if it has been erased. If
the address has not been erased, PGERR bit in the FMC_STAT registers will be set when
programming the address except 0x0. Note that the PG bit must be set before the word/half
word programming operation. Additionally, the program operation will be ignored on
erase/program protected pages and WPERR bit in FMC_STAT is set. In these conditions, a
flash operation error interrupt will be triggered by the FMC if the ERRIE bit in the FMC_CTL
registers is set. The software can check the PGERR bit or WPERR bit in the FMC_STAT
registers to detect which condition occurred in the interrupt handler. Figure 2-3. Process of
word program operation displays the word programming operation flow.
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GD32VF103 User Manual
Set the PG bit
Is the LK bit is 0
Perform word/half
word write by DBUS
Start
Yes
No
Unlock the
FMC_CTL
Is the BUSY bit is 0
Yes
No
Is the BUSY bit is 0
Yes
No
Finish
Figure 2-3. Process of word program operation
Note: Reading the flash should be avoided when a program/erase operation is ongoing in the
same bank. And flash memory accesses failed if the CPU enters the power saving modes.
2.3.7. Option bytes Erase
The FMC provides an erase function which is used to initialize the option bytes block in flash.
The following steps show the erase sequence.
Unlock the FMC_CTL register if necessary.
Check the BUSY bit in FMC_STAT register to confirm that no Flash memory operation
is in progress (BUSY equal to 0). Otherwise, wait until the operation has finished.
Unlock the option bytes operation bits in FMC_CTL register if necessary.
Wait until OBWEN bit is set in FMC_CTL register.
Set OBER bit in FMC_CTL register.
Send the option bytes erase command to the FMC by setting the START bit in FMC_CTL
register.
Wait until all the operations have been finished by checking the value of the BUSY bit in
FMC_STAT register.
Read and verify the Flash memory if required using a DBUS access.
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GD32VF103 User Manual
Address
Name
Description
0x1fff f800
SPC
option byte Security Protection value
0xA5 : no security protection
any value except 0xA5 : under security protection
0x1fff f801
SPC_N
SPC complement value
0x1fff f802
USER
[7:4]: reserved
[3]: BB
When the operation is executed successful, the ENDF in FMC_STAT register is set, and an
interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set.
2.3.8. Option bytes modify
The FMC provides an erase and then program function which is used to modify the option
bytes block in flash. There are 8 pair option bytes. The MSB is the complement of the LSB in
each pair. And when the option bytes are modified, the MSB is generated by FMC
automatically, not the value of input data. The following steps show the erase sequence.
Unlock the FMC_CTL register if necessary.
Check the BUSY bit in FMC_STAT register to confirm that no Flash memory operation
is in progress (BUSY equals to 0). Otherwise, wait until the operation has finished.
Unlock the option bytes operation bits in FMC_CTL register if necessary.
Wait until OBWEN bit is set in FMC_CTL register.
Set the OBPG bit in FMC_CTL register.
A 32-bit word/16-bit half word write at desired address by DBUS.
Wait until all the operations have been finished by checking the value of the BUSY bit in
FMC_STAT register.
Read and verify the Flash memory if required using a DBUS access.
When the operation is executed successfully, the ENDF in FMC_STAT register is set, and an
interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set. Note that
the word/half word programming operation checks the address if it has been erased. If the
address has not been erased, PGERR bit in the FMC_STAT register will set when program
the address except programming 0x0.
The modified option bytes only take effect after a system reset is generated.
2.3.9. Option bytes description
The option bytes block is reloaded to FMC_OBSTAT and FMC_WP registers after each
system reset, and the option bytes take effect. The complement option bytes are the opposite
of option bytes. When option bytes reload, if the complement option byte and option byte do
not match, the OBERR bit in FMC_OBSTAT register is set, and the option byte is set to 0xFF.
The OBERR bit is not set if both the option byte and its complement byte are 0xFF.Table 2-2.
Option byte shows the detail of option bytes.
Table 2-2. Option byte
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GD32VF103 User Manual
Address
Name
Description
0: boot from bank1 or bank0 if bank1 is void, when
configured boot from main memory
1: boot from bank0, when configured boot from main
memory
[2]: nRST_STDBY
0: generate a reset instead of entering standby mode
1: no reset when entering standby mode
[1]: nRST_DPSLP
0: generate a reset instead of entering Deep-sleep mode
1: no reset when entering Deep-sleep mode
[0]: nWDG_HW
0: hardware free watchdog
1: software free watchdog
0x1fff f803
USER_N
USER complement value
0x1fff f804
DATA[7:0]
user defined data bit 7 to 0
0x1fff f805
DATA_N[7:0]
DATA complement value bit 7 to 0
0x1fff f806
DATA[15:8]
user defined data bit 15 to 8
0x1fff f807
DATA_N[15:8]
DATA complement value bit 15 to 8
0x1fff f808
WP[7:0]
Page Erase/Program Protection bit 7 to 0
0: protection active
1: unprotected
0x1fff f809
WP_N[7:0]
WP complement value bit 7 to 0
0x1fff f80a
WP[15:8]
Page Erase/Program Protection bit 15 to 8
0x1fff f80b
WP_N[15:8]
WP complement value bit 15 to 8
0x1fff f80c
WP[23:16]
Page Erase/Program Protection bit 23 to 16
0x1fff f80d
WP_N[23:16]
WP complement value bit 23 to 16
0x1fff f80e
WP[31:24]
Page Erase/Program Protection bit 31 to 24
WP[30:24]: Each bit is related to 4KB flash protection, that
means 4 pages for GD32VF103. Bit 0 configures the first
4KB flash protection, and so on.
0x1fff f80f
WP_N[31:24]
WP complement value bit 31 to 24
2.3.10. Page erase/program protection
The FMC provides page erase/program protection functions to prevent inadvertent operations
on the Flash memory. The page erase or program will not be accepted by the FMC on
protected pages. If the page erase or program command is sent to the FMC on a protected
page, the WPERR bit in the FMC_STAT registers will then be set by the FMC. If the WPERR
bit is set and the ERRIE bit is also set to 1 to enable the corresponding interrupt, then the
Flash operation error interrupt will be triggered by the FMC to draw the attention of the CPU.
The page protection function can be individually enabled by configuring the WP [31:0] bit field
to 0 in the option bytes. If a page erase operation is executed on the option bytes block, all
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GD32VF103 User Manual
the Flash Memory page protection functions will be disabled. When WP in the option bytes is
modified, a system reset followed is necessary.
2.3.11. Security protection
The FMC provides a security protection function to prevent illegal code/data access on the
Flash memory. This function is useful for protecting the software/firmware from illegal users.
No protection: when setting SPC byte and its complement value to 0x5AA5, no protection
performed. The main flash and option bytes block are accessible by all operations.
Under protection: when setting SPC byte and its complement value to any value except
0x5AA5, the security protection is performed. Note that a power reset should be followed
instead of a system reset if the SPC modification is performed while the debug module is still
connected to JTAG device. Under the security protection, the main flash can only be accessed
by user code and the first 4KB flash is under erase/program protection. In debug mode, boot
from SRAM or boot from boot loader mode, all operations to main flash is forbidden. If a read
operation to main flash in debug, boot from SRAM or boot from boot loader mode, a bus error
will be generated. If a program/erase operation to main flash in debug mode, boot from SRAM
or boot from boot loader mode, the WPERR bit in FMC_STAT registers will be set. Option
bytes block are accessible by all operations, which can be used to disable the security
protection. If program back to no protection level by setting SPC byte and its complement
value to 0x5AA5, a mass erase for main flash will be performed.
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GD32VF103 User Manual
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Reserved
WSCNT[2:0]
rw
Bits
Fields
Descriptions
31:3
Reserved
Must be kept at reset value.
2:0
WSCNT[2:0]
Wait state counter
These bits is set and reset by software. The WSCNT valid when WSEN bit in
FMC_WSEN is set.
000: 0 wait state added
001: 1 wait state added
010: 2 wait state added
011~111:reserved
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
KEY[31:16]
w
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
KEY[15:0]
w
2.4. Register definition
FMC base address: 0x4002 2000
2.4.1. Wait state register (FMC_WS)
Address offset: 0x00
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
2.4.2. Unlock key register (FMC_KEY)
Address offset: 0x04
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
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GD32VF103 User Manual
Bits
Fields
Descriptions
31:0
KEY[31:0]
FMC_CTL unlock key
These bits are only be written by software. Write KEY[31:0] with keys to unlock
FMC_CTL register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OBKEY[31:16]
w
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
OBKEY[15:0]
w
Bits
Fields
Descriptions
31:0
OBKEY[31:0]
FMC_CTL option bytes operation unlock key
These bits are only be written by software. Write OBKEY[31:0] with keys to unlock
option bytes command in FMC_CTL register.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Reserved
ENDF
WPERR
Reserved
PGERR
Reserved
BUSY rc_w1
rc_w1 rc_w1 r
Bits
Fields
Descriptions
31:6
Reserved
Must be kept at reset value.
5
ENDF
End of operation flag bit
When the operation executed successfully, this bit is set by hardware. The software
can clear it by writing 1.
4
WPERR
Erase/Program protection error flag bit
2.4.3. Option byte unlock key register (FMC_OBKEY)
Address offset: 0x08
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
2.4.4. Status register (FMC_STAT)
Address offset: 0x0C
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
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GD32VF103 User Manual
When erase/program on protected pages, this bit is set by hardware. The software
can clear it by writing 1.
3
Reserved
Must be kept at reset value.
2
PGERR
Program error flag bit
When program to the flash while it is not 0xFFFF, this bit is set by hardware. The
software can clear it by writing 1.
1
Reserved
Must be kept at reset value.
0
BUSY
The flash busy bit
When the operation is in progress, this bit is set to 1. When the operation is end or
an error is generated, this bit is cleared.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Reserved
ENDIE
Reserved
ERRIE
OBWEN
Reserved
LK
START
OBER
OBPG
Reserved
MER
PER
PG rw rw
rw rs
rs
rw
rw rw
rw
rw
Bits
Fields
Descriptions
31:13
Reserved
Must be kept at reset value.
12
ENDIE
End of operation interrupt enable bit
This bit is set or cleared by software
0: no interrupt generated by hardware.
1: end of operation interrupt enable
11
Reserved
Must be kept at reset value.
10
ERRIE
Error interrupt enable bit
This bit is set or cleared by software
0: no interrupt generated by hardware.
1: error interrupt enable
9
OBWEN
Option byte erase/program enable bit
This bit is set by hardware when right sequence written to FMC_OBKEY register.
This bit can be cleared by software.
2.4.5. Control register (FMC_CTL)
Address offset: 0x10
Reset value: 0x0000 0080
This register has to be accessed by word (32-bit)
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GD32VF103 User Manual
8
Reserved
Must be kept at reset value.
7
LK
FMC_CTL lock bit
This bit is cleared by hardware when right sequence written to FMC_KEY register.
This bit can be set by software.
6
START
Send erase command to FMC bit
This bit is set by software to send erase command to FMC. This bit is cleared by
hardware when the BUSY bit is cleared.
5
OBER
Option bytes erase command bit
This bit is set or clear by software
0: no effect
1: option byte erase command
4
OBPG
Option bytes program command bit
This bit is set or clear by software
0: no effect
1: option bytes program command
3
Reserved
Must be kept at reset value.
2
MER
Main flash mass erase for bank0 command bit
This bit is set or cleared by software
0: no effect
1: main flash mass erase command for bank0
1
PER
Main flash page erase for bank0 command bit
This bit is set or clear by software
0: no effect
1: main flash page erase command for bank0
0
PG
Main flash program for bank0 command bit
This bit is set or clear by software
0: no effect
1: main flash program command for bank0
Note: This register should be reset after the corresponding flash operation completed.
2.4.6. Address register (FMC_ADDR)
Address offset: 0x14
Reset value: 0x0000 0000
This register has to be accessed by word (32-bit)
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GD32VF103 User Manual
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDR[31:16]
w
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
ADDR[15:0]
w
Bits
Fields
Descriptions
31:0
ADDR[31:0]
Flash erase/program command address bits
These bits are configured by software.
ADDR bits are the address of flash erase/program command
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
DATA[15:6] r
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
DATA[5:0]
USER[7:0]
SPC
OBERR
r
r
r
r
Bits
Fields
Descriptions
31:26
Reserved
Must be kept at reset value.
25:10
DATA[15:0]
Store DATA of option bytes block after system reset.
9:2
USER[7:0]
Store USER of option bytes block after system reset.
1
SPC
Option bytes security protection code
0: no protection
1: protection
0
OBERR
Option bytes read error bit.
This bit is set by hardware when the option bytes and its complement byte do not
match, then the option bytes is set to 0xFF.
2.4.7. Option byte status register (FMC_OBSTAT)
Address offset: 0x1C
Reset value: 0x0XXX XXXX.
This register has to be accessed by word (32-bit)
2.4.8. Erase/Program Protection register (FMC_WP)
Address offset: 0x20
Reset value: 0xXXXX XXXX
This register has to be accessed by word (32-bit)
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GD32VF103 User Manual
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
WP[31:16]
r
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
WP[1
r
Bits
Fields
Descriptions
31:0
WP[31:0]
Store WP of option bytes block after system reset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PID[31:16]
r
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
PID[15:0]
r
Bits
Fields
Descriptions
31:0
PID[31:0]
Product reserved ID code register 0
These bits are read only by software.
These bits are unchanged constant after power on. These bits are one time program
when the chip produced.
2.4.9. Product ID register (FMC_PID)
Address offset: 0x100
Reset value: 0xXXXX XXXX
This register has to be accessed by word(32-bit)
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3. Power management unit (PMU)
3.1. Overview
The power consumption is regarded as one of the most important issues for the devices of
GD32VF103 series. According to the Power management unit (PMU), provides three types
of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes
reduce the power consumption and allow the application to achieve the best tradeoff among
the conflicting demands of CPU operating time, speed and power consumption. For
GD32VF103 devices, there are three power domains, including VDD/V
domain, and Backup domain, as is shown in Figure 3-1. Power supply overview. The power
of the VDD domain is supplied directly by VDD. An embedded LDO in the VDD/V
used to supply the 1.2V domain power. A power switch is implemented for the Backup domain.
It can be powered from the V
3.2. Characteristics
voltage when the main V
BAT
supply is shut down.
DD
domain, 1.2V
DDA
domain is
DDA
Three power domains: V
Three power saving modes: Sleep, Deep-sleep and Standby modes.
Internal Voltage regulator (LDO) supplies around 1.2V voltage source for 1.2V domain.
Low Voltage Detector can issue an interrupt or event when the power is lower than a
programmed threshold.
Battery power (V
) for Backup domain when VDD is shut down.
BAT
LDO output voltage select for power saving.
3.3. Function overview
Figure 3-1. Power supply overview provides details on the internal configuration of the PMU
and the relevant power domains.
BAK
, VDD/V
and 1.2V power domains.
DDA
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GD32VF103 User Manual
PMU
CTL
FWDGT
IRC40K
LDO
LXTAL
RTC
WKUP3
IRC8M
HXTAL
PLLs
POR/PDR
BPOR
ADC
Backup Domain
NRST
PA0
VDD Domain
WKUP1 WKUP4
VDD
VBAT
Power Switch
3.3V
VBAK
RISC-V
AHB IPs
1.2V Domain
APB IPs
SLEEPING
SLEEPDEEP
1.2V
LVD: Low Voltage Detector LDO: Voltage Regulator
POR: Power On Reset PDR: Power Down Reset
BPOR: VBAK Power On Reset
WKUP2
LVD DAC
VDDA
3.3V
VDDA Domain
BREG
BREG: Backup registers
Figure 3-1. Power supply overview
3.3.1. Battery backup domain
The Backup domain is powered by the VDD or the battery power source (V
internal power switch, and the V
unit, LXTAL oscillator, BPOR and BREG，and three pads, including PC13 to PC15. In order
to ensure the content of the Backup domain registers and the RTC supply, when V
is shut down, V
or by another source. The power switch is controlled by the Power Down Reset circuit in the
VDD/V
connect V
The Backup domain reset sources include the Backup domain power-on-reset (BPOR) and
the Backup Domain software reset. The BPOR signal forces the device to stay in the reset
mode until V
Backup domain software reset by setting the BKPRST bit in the RCU_BDCTL register to reset
the Backup domain.
The clock source of the Real Time Clock (RTC) circuit can be derived from the Internal 40KHz
RC oscillator (IRC40K) or the Low Speed Crystal oscillator (LXTAL), or HXTAL clock divided
by 128. When VDD is shut down, only LXTAL is valid for RTC. Before entering the power saving
mode by executing the WFI/WFE instruction, the RISC-V can setup the RTC register with an
expected wakeup time and enable the wakeup function to achieve the RTC timer wakeup
domain. If no external battery is used in the application, it is recommended to
DDA
BAT
pin can be connected to an optional standby voltage supplied by a battery
BAT
pin externally to V
is completely powered up. Also the application software can trigger the
BAK
) selected by the
BAT
pin which drives Backup Domain, supplies power for RTC
BAK
DD
pin with a 100nF external ceramic decoupling capacitor.
DD
supply
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GD32VF103 User Manual
event. After entering the power saving mode for a certain amount of time, the RTC will wake
up the device when the time match event occurs. The details of the RTC configuration and
operation will be described in theReal-time Clock (RTC).
When the Backup domain is supplied by V
functions are available:
PC13 can be used as GPIO or RTC function pin described in theReal-time Clock (RTC)..
PC14 and PC15 can be used as either GPIO or LXTAL Crystal oscillator pins.
When the Backup domain is supplied by V
functions are available:
PC13 can be used as RTC function pin described in the Real-time Clock (RTC)..
PC14 and PC15 can be used as LXTAL Crystal oscillator pins only.
Note: Since PC13, PC14, PC15 are supplied through the Power Switch, which can only be
obtained by a small current, the speed of GPIOs PC13 to PC15 should not exceed 2MHz
when they are in output mode(maximum load: 30pF).
3.3.2. VDD/V
VDD/V
HXTAL (High Speed Crystal oscillator), LDO (Voltage Regulator), POR/PDR (Power On/Down
Reset), FWDGT (Free Watchdog Timer), all pads except PC13/PC14/PC15, etc. V
includes ADC/DAC (AD/DA Converter), IRC8M (Internal 8MHz RC oscillator), IRC40K
(Internal 40KHz RC oscillator), PLLs (Phase Locking Loop), LVD (Low Voltage Detector), etc.
DD (VBAK
BAT (VBAK
power domain
DDA
domain includes two parts: VDD domain and V
DDA
pin is connected to VDD), the following
pin is connected to V
domain. VDD domain includes
DDA
), the following
BAT
domain
DDA
VDD domain
The LDO, which is implemented to supply power for the 1.2V domain, is always enabled after
reset. It can be configured to operate in three different status, including in the Sleep mode
(full power on), in the Deep-sleep mode (on or low power), and in the Standby mode (power
off).
The POR/PDR circuit is implemented to detect VDD/V
which resets the whole chip except the Backup domain when the supply voltage is lower than
the specified threshold. Figure 3-2. Waveform of the POR/PDR shows the relationship
between the supply voltage and the power reset signal. V
indicates the threshold of power on reset, while V
PDR
threshold of power down reset. The hysteresis voltage (V
and generate the power reset signal
DDA
, which typical value is 2.40V,
POR
, which typical value is 2.35V, means the
) is around 50mV.
hyst
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GD32VF103 User Manual
VDD/VDDA
VPOR
tRSTTEMPO
2ms
Power Reset (Active Low)
t
VPDR
50mV
Vhyst
VDD/VDDA
LVD output
t
LVD
threshold
100mV
Vhyst
Figure 3-2. Waveform of the POR/PDR
V
domain
DDA
The LVD is used to detect whether the VDD/V
supply voltage is lower than a programmed
DDA
threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL). The LVD
is enabled by setting the LVDEN bit, and LVDF bit, which in the Power status register
(PMU_CS), indicates if VDD/V
is higher or lower than the LVD threshold. This event is
DDA
internally connected to the EXTI line 16 and can generate an interrupt if it is enabled through
the EXTI registers. Figure 3-3. Waveform of the LVD threshold shows the relationship
between the LVD threshold and the LVD output (LVD interrupt signal depends on EXTI line
16 rising or falling edge configuration). The following figure shows the relationship between
the supply voltage and the LVD signal. The hysteresis voltage (V
) is 100mV.
hyst
Figure 3-3. Waveform of the LVD threshold
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GD32VF103 User Manual
Generally, digital circuits are powered by VDD, while most of analog circuits are powered by
V
. To improve the ADC and DAC conversion accuracy, the independent power supply V
DDA
is implemented to achieve better performance of analog circuits. V
connected to VDD through the external filtering circuit that avoids noise on V
should be connected to V
different from VDD, V
must always be higher, but the voltage difference should not exceed
DDA
0.2V.
To ensure a high accuracy on low voltage ADC and DAC, the separate external reference
voltage on V
V
pin must be connected to V
REF+
should be connected to ADC/DAC pins. According to the different packages,
REF
pin is only available on no less than 100-pin packages, or else the V
and internally connected to V
packages, or else the V
REF-
3.3.3. 1.2V power domain
The main functions that include RISC-V logic, AHB/APB peripherals, the APB interfaces for
the Backup domain and the VDD/V
1.2V is powered up, the POR will generate a reset sequence on the 1.2V power domain. If
need to enter the expected power saving mode, the associated control bits must be
configured. Then, once a WFI (Wait for Interrupt) or WFE (Wait for Event) instruction is
executed, the device will enter an expected power saving mode which will be discussed in
the following section.
can be externally
DDA
DDA
through the specific circuit independently. Otherwise, if V
SS
pin, V
DDA
The V
DDA.
pin is not available and internally connected to V
domain, etc, are located in this power domain. Once the
DDA
pin must be connected to V
REF-
REF+
pin is only available on no less than 100-pin
REF-
pin. The V
SSA
pin is not available
.
SSA
, and V
DDA
DDA
SSA
is
REF+
3.3.4. Power saving modes
After a system reset or a power reset, the GD32VF103 MCU operates at full function and all
power domains are active. Users can achieve lower power consumption through slowing
down the system clocks (HCLK, PCLK1, PCLK2) or gating the clocks of the unused
peripherals. Besides, three power saving modes are provided to achieve even lower power
consumption, they are Sleep mode, Deep-sleep mode, and Standby mode.
Sleep mode
The Sleep mode is corresponding to the SLEEPING mode of the RISC-V. In Sleep mode,
only clock of RISC-V is off. To enter the Sleep mode, it is only necessary to clear the
CSR_SLEEPVALUE bit in the RISC-V System Control Register, and execute a WFI or WFE
instruction. If the Sleep mode is entered by executing a WFI instruction, any interrupt can
wake up the system. If it is entered by executing a WFE instruction, any wakeup event can
wake up the system. The mode offers the lowest wakeup time as no time is wasted in interrupt
entry or exit.
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GD32VF103 User Manual
Mode
Sleep
Deep-sleep
Standby
Description
Only CPU clock is off
All clocks in the 1.2V
domain are off
Disable IRC8M, HXTAL and
PLL
The 1.2V domain is power
off
Disable IRC8M, HXTAL
and PLL
LDO Status
On
On or in low power mode
Off
Configuration
CSR_SLEEPVALUE =
0
CSR_SLEEPVALUE = 1
STBMOD = 0
CSR_SLEEPVALUE = 1
STBMOD = 1, WURST=1
Entry
WFI or WFE
WFI or WFE
WFI or WFE
Deep-sleep mode
The Deep-sleep mode is based on the SLEEPDEEP mode of the RISC-V. In Deep-sleep
mode, all clocks in the 1.2V domain are off, and all of IRC8M, HXTAL and PLLs are disabled.
The contents of SRAM and registers are preserved. The LDO can operate normally or in low
power mode depending on the LDOLP bit in the PMU_CTL register. Before entering the Deepsleep mode, it is necessary to set the CSR_SLEEPVALUE bit in the RISC-V System Control
Register, and clear the STBMOD bit in the PMU_CTL register. Then, the device enters the
Deep-sleep mode after a WFI or WFE instruction is executed. If the Deep-sleep mode is
entered by executing a WFI instruction, any interrupt from EXTI lines can wake up the system.
If it is entered by executing a WFE instruction, any wakeup event from EXTI lines can wake
up the system. When exiting the Deep-sleep mode, the IRC8M is selected as the system
clock. Notice that an additional wakeup delay will be incurred if the LDO operates in low power
mode.
Note: In order to enter Deep-sleep mode smoothly, all EXTI line pending status (in the
EXTI_PD register) and RTC alarm/time stamp/tamper flag must be reset. If not, the program
will skip the entry process of Deep-sleep mode to continue to execute the following procedure.
Standby mode
The Standby mode is based on the SLEEPDEEP mode of the RISC-V, too. In Standby mode,
the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and
PLLs are disabled. Before entering the Standby mode, it is necessary to set the
CSR_SLEEPVALUE bit in the RISC-V System Control Register, and set the STBMOD bit in
the PMU_CTL register, and clear WUF bit in the PMU_CS register. Then, the device enters
the Standby mode after a WFI or WFE instruction is executed, and the STBF status flag in
the PMU_CS register indicates that the MCU has been in Standby mode. There are four
wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC
alarm/time stamp/tamper events, the FWDGT reset, and the rising edge on WKUP pin. The
Standby mode achieves the lowest power consumption, but spends longest time to wake up.
Besides, the contents of SRAM and registers in 1.2V power domain are lost in Standby mode.
When exiting from the Standby mode, a power-on reset occurs and the RISC-V will execute
instruction code from the 0x00000000 address.
Table 3-1. Power saving mode summary
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Mode
Sleep
Deep-sleep
Standby
Wakeup
Any interrupt for WFI
Any event (or interrupt)
for WFE(WFI)
Any interrupt from EXTI
lines for WFI
Any event(or interrupt) from
EXTI for WFE(WFI)
NRST pin
WKUP pin
FWDGT reset
RTC
Wakeup
Latency
None
IRC8M wakeup time,
LDO wakeup time added if
LDO is in low power mode
Power on sequence
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31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Reserved
BKPWEN
LVDT[2:0]
LVDEN
STBRST
WURST
STBMOD
LDOLP
rw
rw
rw
rc_w1
rc_w1
rw
rw
Bits
Fields
Descriptions
31:9
Reserved
Must be kept at reset value.
8
BKPWEN
Backup Domain Write Enable
0: Disable write access to the registers in Backup domain
1: Enable write access to the registers in Backup domain
After reset, any write access to the registers in Backup domain is ignored. This bit
has to be set to enable write access to these registers.
7:5
LVDT[2:0]
Low Voltage Detector Threshold
000: 2.2V
001: 2.3V
010: 2.4V
011: 2.5V
100: 2.6V
101: 2.7V
110: 2.8V
111: 2.9V
4
LVDEN
Low Voltage Detector Enable
0: Disable Low Voltage Detector
1: Enable Low Voltage Detector
3
STBRST
Standby Flag Reset
0: No effect
1: Reset the standby flag
This bit is always read as 0.
3.4. Register definition
PMU base address: 0x4000 7000
3.4.1. Control register (PMU_CTL)
Address offset: 0x00
Reset value: 0x0000 0000 (reset by wakeup from Standby mode)
This register can be accessed by half-word(16-bit) or word(32-bit)
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2
WURST
Wakeup Flag Reset
0: No effect
1: Reset the wakeup flag
This bit is always read as 0.
1
STBMOD
Standby Mode
0: Enter the Deep-sleep mode when the RISC-V enters SLEEPDEEP mode
1: Enter the Standby mode when the RISC-V enters SLEEPDEEP mode
0
LDOLP
LDO Low Power Mode
0: The LDO operates normally during the Deep-sleep mode
1: The LDO is in low power mode during the Deep-sleep mode
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
WUPEN
Reserved
LVDF
STBF
WUF rw r r r
Bits
Fields
Descriptions
31:9
Reserved
Must be kept at reset value.
8
WUPEN
WKUP Pin Enable
0: Disable WKUP pin function
1: Enable WKUP pin function
If WUPEN is set before entering the power saving mode, a rising edge on the WKUP
pin wakes up the system from the power saving mode. As the WKUP pin is active
high, the WKUP pin is internally configured to input pull down mode. And set this bit
will trigger a wakup event when the input changes to high.
7:3
Reserved
Must be kept at reset value.
2
LVDF
Low Voltage Detector Status Flag
0: Low Voltage event has not occurred (VDD is higher than the specified LVD
threshold)
1: Low Voltage event occurred (VDD is equal to or lower than the specified LVD
threshold)
Note: The LVD function is stopped in Standby mode.
3.4.2. Control and status register (PMU_CS)
Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
This register can be accessed by half-word(16-bit) or word(32-bit).
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1
STBF
Standby Flag
0: The device has not entered the Standby mode
1: The device has been in the Standby mode
This bit is cleared only by a POR/PDR or by setting the STBRST bit in the PMU_CTL
register.
0
WUF
Wakeup Flag
0: No wakeup event has been received
1: Wakeup event occurred from the WKUP pin or the RTC wakeup event including
RTC Tamper event, RTC alarm event, or RTC Time Stamp event.
This bit is cleared only by a POR/PDR or by setting the WURST bit in the PMU_CTL
register.
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4. Backup registers (BKP)
4.1. Overview
The Backup registers are located in the Backup domain that remains powered-on by V
even if VDD power is shut down, they are forty-two 16-bit (84 bytes) registers for data
protection of user application data, and the wake-up action from Standby mode or system
reset do not affect these registers.
In addition, the BKP registers can be used to implement the tamper detection and RTC
calibration function.
After reset, any writing access to the registers in Backup domain is disabled, that is, the
Backup registers and RTC cannot be written to access. In order to enable access to the
Backup registers and RTC, the Power and Backup interface clocks should be enabled firstly
by setting the PMUEN and BKPIEN bits in the RCU_APB1EN register, and writing access to
the registers in Backup domain should be enabled by setting the BKPWEN bit in the
PMU_CTL register.
4.2. Characteristics
84 bytes Backup registers which can keep data under power saving mode. If tamper
event is detected, Backup registers will be reset.
The active level of Tamper source (PC13) can be configured.
RTC Clock Calibration register provides RTC alarm and second output selection, and
the calibration value configuration.
Tamper control and status register (BKP_TPCS) can control tamper detection with
interrupt or event capability.
BAT
4.3. Function overview
4.3.1. RTC clock calibration
In order to improve the RTC clock accuracy, the MCU provides the RTC output for calibration
function. The clock with the frequency f
setting the COEN bit in the BKP_OCTL register.
The calibration value is set by RCCV[6:0] in the BKP_OCTL register, and the calibration
function can slow down the RTC clock by steps of 1000000/2^20 ppm.
/64 can be output on the PC13. It is enabled by
RTCCLK
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4.3.2. Tamper detection
In order to protect the important user data, the MCU provides the tamper detection function,
and it can be independently enabled on TAMPER pin by setting corresponding TPEN bit in
the BKP_TPCTL register. To prevent the tamper event from losing, the edge detection is
logically ANDed with the TPEN bit, used for tamper detection signal. So the tamper detection
configuration should be set before enable TAMPER pin. When the tamper event is detected,
the corresponding TEF bit in the BKP_TPCS register will be set. Tamper event can generate
an interrupt if tamper interrupt is enabled. Any tamper event will reset all Backup data registers.
Note: When TPAL=0/1, if the TAMPER pin is already high/low before it is enabled(by setting
TPEN bit), an extra tamper event is detected, while there was no rising/falling edge on the
TAMPER pin after TPEN bit was set.
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15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
DATA [15:0]
rw
Bits
Fields
Descriptions
15:0
DATA[15:0]
Backup data
These bits are used for general purpose data storage. The contents of the
BKP_DATAx register will remain even if the wake-up action from Standby mode or
system reset or power reset occurs.
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Reserved
ROSEL
ASOEN
COEN
RCCV[6:0]
rw
rw
rw
rw
Bits
Fields
Descriptions
15:10
Reserved
Must be kept at reset value.
9
ROSEL
RTC output selection
0: RTC alarm pulse is selected as the RTC output
1: RTC second pulse is selected as the RTC output
8
ASOEN
RTC alarm or second signal output enable
0: Disable RTC alarm or second output
1: Enable RTC alarm or second output
When enable, the TAMPER pin will output the RTC output.
7
COEN
RTC clock calibration output enable
0: Disable RTC clock calibration output
4.4. Register definition
BKP base address: 0x4000 6C00
4.4.1. Backup data register x (BKP_DATAx) (x= 0..41)
Address offset: 0x04 to 0x28, 0x40 to 0xBC
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit)
4.4.2. RTC signal output control register (BKP_OCTL)
Address offset: 0x2C
Reset value: 0x0000(bit [6:0], bit 8, bit 9 reset by a Backup domain reset, bit 7 reset by a POR/PDR)
This register can be accessed by half-word(16-bit) or word(32-bit)
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1: Enable RTC clock calibration output
When enable, the TAMPER pin will output a clock with the frequency f
RTCCLK
/64.
ASOEN has the priority over COEN. When ASOEN is set, the TAMPER pin will
output the RTC alarm or second signal whether COEN is set or not.
6:0
RCCV[6:0]
RTC clock calibration value
The value indicates how many clock pulses are ignored or added every 2^20 RTC
clock pulses.
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Reserved
TPAL
TPEN rw
rw
Bits
Fields
Descriptions
15:2
Reserved
Must be kept at reset value.
1
TPAL
TAMPER pin active level
0: The TAMPER pin is active high
1: The TAMPER pin is active low
0
TPEN
TAMPER detection enable
0: The TAMPER pin is free for GPIO functions
1: The TAMPER pin is dedicated for the Backup Reset function. The active level on
the TAMPER pin resets all data of the BKP_DATAx registers.
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Reserved
TIF
TEF
Reserved
TPIE
TIR
TER r
r rw w w
Bits
Fields
Descriptions
15:10
Reserved
Must be kept at reset value.
4.4.3. Tamper pin control register (BKP_TPCTL)
Address offset: 0x30
Reset value: 0x0000
This register can be accessed by half-word (16-bit) or word (32-bit)
4.4.4. Tamper control and status register (BKP_TPCS)
Address offset: 0x34
Reset value: 0x0000(bit 2 reset by a system reset or the wake-up from Standby mode)
This register can be accessed by half-word (16-bit) or word (32-bit)
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9
TIF
Tamper interrupt flag
0: No tamper interrupt occurred
1: A tamper interrupt occurred
This bit is reset by writing 1 to the TIR bit or the TPIE bit being 0.
8
TEF
Tamper event flag
0: No tamper event occurred
1: A tamper event occurred
This bit is reset by writing 1 to the TER bit.
7:3
Reserved
Must be kept at reset value.
2
TPIE
Tamper interrupt enable
0: Disable the tamper interrupt
1: Enable the tamper interrupt
1
TIR
Tamper interrupt reset
0: No effect
1: Reset the TIF bit
This bit is always read as 0.
0
TER
Tamper event reset
0: No effect
1: Reset the TEF bit
This bit is always read as 0.
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5. Reset and clock unit (RCU)
5.1. Reset control unit (RCTL)
5.1.1. Overview
GD32VF103 Reset Control includes the control of three kinds of reset: power reset, system
reset and backup domain reset. The power reset, known as a cold reset, resets the full system
except the Backup domain. The system reset resets the processor core and peripheral IP
components except for the JTAG controller and the Backup domain. The backup domain reset
resets the Backup domain. The resets can be triggered by an external signal, internal events
and the reset generators. More information about these resets will be described in the
following sections.
5.1.2. Function overview
Power reset
The Power reset is generated by either an external reset as Power On and Power Down reset
(POR/PDR reset) or by the internal reset generator when exiting Standby mode. The power
reset sets all registers to their reset values except the Backup domain. The Power reset
whose active signal is low, it will be de-asserted when the internal LDO voltage regulator is
ready to provide 1.2V power. The RESET service routine vector is fixed at address 0x0000
0000 in the memory map.
System reset
A system reset is generated by the following events:
A power reset (POWER_RSTn).
An external pin reset (NRST).
A window watchdog timer reset (WWDGT_RSTn).
A free watchdog timer reset (FWDGT_RSTn).
The SYSRESETREQ bit in RISC-V Application Interrupt and Reset Control Register is
set (SW_RSTn).
Reset generated when entering Standby mode when resetting nRST_STDBY bit in User
Option Bytes (OB_STDBY_RSTn).
Reset generated when entering Deep-sleep mode when resetting nRST_DPSLP bit in
User Option Bytes (OB_DPSLP_RSTn).
A system reset resets the processor core and peripheral IP components except for the JTAG
controller and the Backup domain.
A system reset pulse generator guarantees low level pulse duration of 20 μs for each reset
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Filter
WWDGT_RSTn
FWDGT_RSTn
SW_RSTn
OB_STDBY_RSTn
OB_DPSLP_RSTn
POWER_RSTn
NRST
System Reset
min 20 us
pulse
generator
source (external or internal reset).
Figure 5-1. The system reset circuit
Backup domain reset
A backup domain reset is generated by setting the BKPRST bit in the Backup domain control
register or Backup domain power on reset (VDD or V
previously been powered off).
5.2. Clock control unit (CCTL)
power on, if both supplies have
BAT
5.2.1. Overview
The Clock Control unit provides a range of frequencies and clock functions. These include an
Internal 8M RC oscillator (IRC8M), a High Speed crystal oscillator (HXTAL), a Low Speed
Internal 40K RC oscillator (IRC40K), a Low Speed crystal oscillator (LXTAL), three Phase
Lock Loop (PLL), a HXTAL clock monitor, clock prescalers, clock multiplexers and clock
gating circuitry.
The clocks of the AHB, APB and RISC-V are derived from the system clock (CK_SYS) which
can source from the IRC8M, HXTAL or PLL. The maximum operating frequency of the system
clock (CK_SYS) can be up to 108 MHz. The Free Watchdog Timer has independent clock
source (IRC40K), and Real Time Clock (RTC) uses the IRC40K, LXTAL or HXTAL/128 as its
clock source.
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/2
3-25 MHz
HXTAL
8 MHz
IRC8M
×2,3,4
…,32
PLL
Clock
Monitor
PLLSEL PLLMF
0
1
00
01
10
CK_IRC8M
CK_HXTAL
CK_PLL CK_SYS
108 MHz max
AHB
Prescaler
÷1,2...512
CK_AHB
108 MHz max
APB1
Prescaler
÷1,2,4,8,16
TIMER1,2,3,4,5,6
if(APB1 prescale
=1)x1
else x 2
APB2
Prescaler
÷1,2,4,8,16
TIMER0 if(APB2
prescale =1)x1
else x 2
ADC
Prescaler
÷2,4,6,8,12,1
6
CK_APB2
108 MHz max
Peripheral enable
PCLK2
to APB2 peripherals
CK_APB1
54 MHz max
Peripheral enable
PCLK1
to APB1 peripherals
TIMERx
enable
CK_TIMERx
to TIMER0
TIMERx
enable
CK_TIMERx
to TIMER1,2,3,4, 5,6
CK_ADCx to ADC0, 1
14 MHz max
AHB enable
HCLK
(to AHB bus,CPU,SRAM,DMA)
EXMC enable
CK_EXMC
(to EXMC)
÷8
CK_CST
(to CPU SysTick)
FCLK
(free running clock)
USB OTG
Prescaler
1,1.5,2,2.5
CK_USBFS
(to USBFS)
32.768 KHz
LXTAL
11
10
01
40 KHz
IRC40K
CK_RTC
CK_FWDGT
(to RTC)
(to FWDGT)
/128
CK_OUT0
SCS[1:0]
RTCSRC[1:0]
PREDV0
0
1
CK_PLL
CK_HXTAL
CK_IRC8M
CK_SYS
/20111
00xx
NO CLK
0100
0101
0110
CKOUT0SEL[3:0]
48 MHz
EXT1
/2
1000
1001
1010
CK_PLL1
CK_PLL2
1011
CK_PLL2
/1,2,3…
15,16
PREDV1
×8,9,10…,
14,16,20
PLL1
PLL1MF
PLL2MF
×8,9,10…,
14,16,20
PLL2
CK_PLL1
CK_PLL2
/1,2,3…
15,16
x2
I2S1/2SEL
0
1
CK_I2S
1
EXT1 to
CK_OUT0
PREDV0SEL
CK_FMC
(to FMC)
Figure 5-2. Clock tree
The frequency of AHB, APB2 and the APB1 domains can be configured by each prescaler.
The maximum frequency of the AHB, APB2 and APB1 domains is 108 MHz/108 MHz/54 MHz.
The RISCV System Timer (SysTick) external clock is clocked with the AHB clock (HCLK)
divided by 8. The SysTick can work either with this clock or with the AHB clock (HCLK),
configurable in the SysTick Control and Status Register.
The ADCs are clocked by the clock of APB2 divided by 2, 4, 6, 8, 12, 16.
The TIMERs are clocked by the clock divided from CK_APB2 and CK_APB1. The frequency
of TIMERs clock is equal to CK_APBx(APB prescaler is 1), twice the CK_APBx(APB
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OSCIN OSCOUT
C1 C2
Crystal
prescaler is not 1).
The USBFS is clocked by the clock of CK_PLL as the clock source of 48MHz.
The I2S is clocked by the clock of CK_SYS or PLL2*2 which defined by I2SxSEL bit in
RCU_CFG1 register.
The RTC is clocked by LXTAL clock or IRC40K clock or HXTAL clock divided by 128 (defined
which select by RTCSRC bit in Backup Domain Control Register (RCU_BDCTL). After the
RTC select HXTAL clock divided by 128, the clock disappeared when the 1.2V core domain
power off. After the RTC select IRC40K, the clock disappeared when V
RTC select LXTAL, the clock disappeared when V
The FWDGT is clocked by IRC40K clock, which is forced on when FWDGT started.
The FMC is clocked by IRC8M clock, which is forced on when IRC8M started.
5.2.2. Characteristics
3 to 25 MHz High Speed crystal oscillator (HXTAL) .
Internal 8 MHz RC oscillator (IRC8M).
32,768 Hz Low Speed crystal oscillator (LXTAL).
Internal 40KHz RC oscillator (IRC40K).
PLL clock source can be HXTAL or IRC8M.
HXTAL clock monitor.
DD
and V
power off.
BAT
power off. After the
DD
5.2.3. Function overview
High speed crystal oscillator (HXTAL)
The high speed external crystal oscillator (HXTAL), which has a frequency from 3 to 25 MHz,
produces a highly accurate clock source for use as the system clock. A crystal with a specific
frequency must be connected and located close to the two HXTAL pins. The external resistor
and capacitor components connected to the crystal are necessary for proper oscillation.
Figure 5-3. HXTAL clock source
The HXTAL crystal oscillator can be switched on or off using the HXTALEN bit in the Control
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Register RCU_CTL. The HXTALSTB flag in Control Register RCU_CTL indicates if the highspeed external crystal oscillator is stable. When the HXTAL is powered up, it will not be
released for use until this HXTALSTB bit is set by the hardware. This specific delay period is
known as the oscillator “Start-up time”. As the HXTAL becomes stable, an interrupt will be
generated if the related interrupt enable bit HXTALSTBIE in the Interrupt Register RCU_INT
is set. At this point the HXTAL clock can be used directly as the system clock source or the
PLL input clock.
Select external clock bypass mode by setting the HXTALBPS and HXTALEN bits in the
Control Register RCU_CTL. The CK_HXTAL is equal to the external clock which drives the
OSCIN pin.
Internal 8M RC oscillators (IRC8M)
The internal 8M RC oscillator, IRC8M, has a fixed frequency of 8 MHz and is the default clock
source selection for the CPU when the device is powered up. The IRC8M oscillator provides
a lower cost type clock source as no external components are required. The IRC8M RC
oscillator can be switched on or off using the IRC8MEN bit in the Control Register RCU_CTL.
The IRC8MSTB flag in the Control Register RCU_CTL is used to indicate if the internal 8M
RC oscillator is stable. The start-up time of the IRC8M oscillator is shorter than the HXTAL
crystal oscillator. An interrupt can be generated if the related interrupt enable bit,
IRC8MSTBIE, in the Clock Interrupt Register, RCU_INT, is set when the IRC8M becomes
stable. The IRC8M clock can also be used as the system clock source or the PLL input clock.
The frequency accuracy of the IRC8M can be calibrated by the manufacturer, but its operating
frequency is still less accurate than HXTAL. The application requirements, environment and
cost will determine which oscillator type is selected.
If the HXTAL or PLL is the system clock source, to minimize the time required for the system
to recover from the Deep-sleep Mode, the hardware forces the IRC8M clock to be the system
clock when the system initially wakes-up.
Phase locked loop (PLL)
There are three internal Phase Locked Loop, including PLL, PLL1 and PLL2.
The PLL can be switched on or off by using the PLLEN bit in the RCU_CTL Register. The
PLLSTB flag in the RCU_CTL Register will indicate if the PLL clock is stable. An interrupt can
be generated if the related interrupt enable bit, PLLSTBIE, in the RCU_INT Register, is set
as the PLL becomes stable.
The PLL1 can be switched on or off by using the PLL1EN bit in the RCU_CTL Register. The
PLL1STB flag in the RCU_CTL Register will indicate if the PLL1 clock is stable. An interrupt
can be generated if the related interrupt enable bit, PLL1STBIE, in the RCU_INT Register, is
set as the PLL1 becomes stable.
The PLL2 can be switched on or off by using the PLL2EN bit in the RCU_CTL Register. The
PLL2STB flag in the RCU_CTL Register will indicate if the PLL2 clock is stable. An interrupt
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can be generated if the related interrupt enable bit, PLL2STBIE, in the RCU_INT Register, is
set as the PLL2 becomes stable.
The three PLLs are closed by hardware when entering the Deepsleep/Standby mode or
HXTAL monitor fail when HXTAL used as the source clock of the PLLs.
Low speed crystal oscillator (LXTAL)
The low speed external crystal or ceramic resonator oscillator, which has a frequency of
32,768 Hz, produces a low power but highly accurate clock source for the Real Time Clock
circuit. The LXTAL oscillator can be switched on or off using the LXTALEN bit in the Backup
Domain Control Register (RCU_BDCTL). The LXTALSTB flag in the Backup Domain Control
Register (RCU_BDCTL) will indicate if the LXTAL clock is stable. An interrupt can be
generated if the related interrupt enable bit, LXTALSTBIE, in the Interrupt Register RCU_INT
is set when the LXTAL becomes stable.
Select external clock bypass mode by setting the LXTALBPS and LXTALEN bits in the
Backup Domain Control Register (RCU_BDCTL). The CK_LXTAL is equal to the external
clock which drives the OSC32IN pin.
Internal 40K RC oscillator (IRC40K)
The internal RC oscillator has a frequency of about 40 kHz and is a low power clock source
for the Real Time Clock circuit or the Free Watchdog Timer. The IRC40K offers a low cost
clock source as no external components are required. The IRC40K RC oscillator can be
switched on or off by using the IRC40KEN bit in the Reset source/clock Register
(RCU_RSTSCK). The IRC40KSTB flag in the Reset source/clock Register RCU_RSTSCK
will indicate if the IRC40K clock is stable. An interrupt can be generated if the related interrupt
enable bit IRC40KSTBIE in the Clock Interrupt Register (RCU_INT) is set when the IRC40K
becomes stable.
The IRC40K can be trimmed by TIMER4_CH3, user can get the clocks frequency, and adjust
the RTC and FWDGT counter. Please refer to TIMER4CH3_IREMAP in AFIO_PCF0 register.
System clock (CK_SYS) selection
After the system reset, the default CK_SYS source will be IRC8M and can be switched to
HXTAL or CK_PLL by changing the System Clock Switch bits, SCS, in the Clock configuration
register 0, RCU_CFG0. When the SCS value is changed, the CK_SYS will continue to
operate using the original clock source until the target clock source is stable. When a clock
source is directly or indirectly (by PLL) used as the CK_SYS, it is not possible to stop it.
HXTAL clock monitor (CKM)
The HXTAL clock monitor function is enabled by the HXTAL Clock Monitor Enable bit,
CKMEN, in the Control Register (RCU_CTL). This function should be enabled after the
HXTAL start-up delay and disabled when the HXTAL is stopped. Once the HXTAL failure is
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Clock Source 0 Selection bits
Clock Source
00xx
NO CLK
0100
CK_SYS
0101
CK_IRC8M
0110
CK_HXTAL
0111
CK_PLL/2
1000
CK_PLL1
1001
CK_PLL2/2
1010
EXT1
1011
CK_PLL2
DSLPVS[1:0]
Deep-sleep mode voltage(V)
00
1.2
01
1.1
10
1.0
11
0.9
detected, the HXTAL will be automatically disabled. The HXTAL Clock Stuck interrupt Flag,
CKMIF, in the Clock Interrupt Register, RCU_INT, will be set and the HXTAL failure event will
be generated. This failure interrupt is connected to the Non-Maskable Interrupt, NMI, of the
RISC-V. If the HXTAL is selected as the clock source of CK_SYS, PLL and CK_RTC, the
HXTAL failure will force the CK_SYS source to IRC8M, the PLL will be disabled automatically.
If the HXTAL is selected as the clock source of PLL, the HXTAL failure will force the PLL
closed automatically. If the HXTAL is selected as the clock source of RTC, the HXTAL failure
will reset the RTC clock selection.
Clock output capability
The clock output capability is ranging from 0.09375 MHz to 108 MHz. There are several clock
signals can be selected via the CK_OUT0 Clock Source Selection bits, CKOUT0SEL, in the
Clock Configuration Register 0 (RCU_CFG0). The corresponding GPIO pin should be
configured in the properly Alternate Function I/O (AFIO) mode to output the selected clock
signal..
Table 5-1. Clock output 0 source select
Voltage control
The 1.2V domain voltage in Deep-sleep mode can be controlled by DSLPVS[1:0] bit in the
Deep-sleep mode voltage register (RCU_DSV).
Table 5-2. 1.2V domain voltage selected in deep-sleep mode
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31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
PLL2STB
PLL2EN
PLL1STB
PLL1EN
PLLSTB
PLL
EN
Reserved
CKMEN
HXTALB
PS
HXTALST
B
HXTALE
N
r rw r rw r rw rw
rw r rw
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
IRC8MCALIB[7:0]
IRC8MADJ[4:0]
Reserved
IRC8MST
B
IRC8MEN
r
rw
r rw
Bits
Fields
Descriptions
31:30
Reserved
Must be kept at reset value.
29
PLL2STB
PLL2 Clock Stabilization Flag
Set by hardware to indicate if the PLL2 output clock is stable and ready for use.
0: PLL2 is not stable
1: PLL2 is stable
28
PLL2EN
PLL2 enable
Set and reset by software. Reset by hardware when entering Deep-sleep or Standby
mode.
0: PLL2 is switched off
1: PLL2 is switched on
27
PLL1STB
PLL1 Clock Stabilization Flag
Set by hardware to indicate if the PLL1 output clock is stable and ready for use.
0: PLL1 is not stable
1: PLL1 is stable
26
PLL1EN
PLL1 enable
Set and reset by software. Reset by hardware when entering Deep-sleep or Standby
mode.
0: PLL1 is switched off
1: PLL1 is switched on
25
PLLSTB
PLL Clock Stabilization Flag
5.3. Register definition
RCU base address: 0x4002 1000
5.3.1. Control register (RCU_CTL)
Address offset: 0x00
Reset value: 0x0000 xx83 where x is undefined.
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
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Set by hardware to indicate if the PLL output clock is stable and ready for use.
0: PLL is not stable
1: PLL is stable
24
PLLEN
PLL enable
Set and reset by software. This bit cannot be reset if the PLL clock is used as the
system clock. Reset by hardware when entering Deep-sleep or Standby mode.
0: PLL is switched off
1: PLL is switched on
23:20
Reserved
Must be kept at reset value.
19
CKMEN
HXTAL Clock Monitor Enable
0: Disable the High speed 3 ~ 25 MHz crystal oscillator (HXTAL) clock monitor
1: Enable the High speed 3 ~ 25 MHz crystal oscillator (HXTAL) clock monitor
When the hardware detects that the HXTAL clock is stuck at a low or high state, the
internal hardware will switch the system clock to be the internal high speed IRC8M
RC clock. The way to recover the original system clock is by either an external reset,
power on reset or clearing CKMIF by software.
Note: When the HXTAL clock monitor is enabled, the hardware will automatically
enable the IRC8M internal RC oscillator regardless of the control bit, IRC8MEN,
state.
18
HXTALBPS
High speed crystal oscillator (HXTAL) clock bypass mode enable
The HXTALBPS bit can be written only if the HXTALEN is 0.
0: Disable the HXTAL Bypass mode
1: Enable the HXTAL Bypass mode in which the HXTAL output clock is equal to the
input clock.
17
HXTALSTB
High speed crystal oscillator (HXTAL) clock stabilization flag
Set by hardware to indicate if the HXTAL oscillator is stable and ready for use.
0: HXTAL oscillator is not stable
1: HXTAL oscillator is stable
16
HXTALEN
High Speed crystal oscillator (HXTAL) Enable
Set and reset by software. This bit cannot be reset if the HXTAL clock is used as
the system clock or the PLL input clock when PLL clock is selected to the system
clock. Reset by hardware when entering Deep-sleep or Standby mode.
0: High speed 3 ~ 25 MHz crystal oscillator disabled
1: High speed 3 ~ 25 MHz crystal oscillator enabled
15:8
IRC8MCALIB[7:0]
Internal 8MHz RC Oscillator calibration value register
These bits are load automatically at power on.
7:3
IRC8MADJ[4:0]
Internal 8MHz RC Oscillator clock trim adjust value
These bits are set by software. The trimming value is these bits (IRC8MADJ) added
to the IRC8MCALIB[7:0] bits. The trimming value should trim the IRC8M to 8 MHz
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± 1%.
2
Reserved
Must be kept at reset value.
1
IRC8MSTB
IRC8M Internal 8MHz RC Oscillator stabilization Flag
Set by hardware to indicate if the IRC8M oscillator is stable and ready for use.
0: IRC8M oscillator is not stable
1: IRC8M oscillator is stable
0
IRC8MEN
Internal 8MHz RC oscillator Enable
Set and reset by software. This bit cannot be reset if the IRC8M clock is used as the
system clock. Set by hardware when leaving Deep-sleep or Standby mode or the
HXTAL clock is stuck at a low or high state when CKMEN is set.
0: Internal 8 MHz RC oscillator disabled
1: Internal 8 MHz RC oscillator enabled
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
PLLMF[4]
ADCPSC[
2]
CKOUT0SEL[3:0]
USBFSPSC[1:0]
PLLMF[3:0]
PREDV0
_LSB
PLLSEL
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
ADCPSC[1:0]
APB2PSC[2:0]
APB1PSC[2:0]
AHBPSC[3:0]
SCSS[1:0]
SCS[1:0]
rw
rw
rw
rw
r
rw
Bits
Fields
Descriptions
31:30
Reserved
Must be kept at reset value.
29
PLLMF[4]
Bit 4 of PLLMF
see bits 21:18 of RCU_CFG0
28
ADCPSC[2]
Bit 2 of ADCPSC
see bits 15:14 of RCU_CFG0
27:24
CKOUT0SEL[3:0]
CKOUT0 Clock Source Selection
Set and reset by software.
00xx: No clock selected
0100: System clock selected
0101: High Speed 8M Internal Oscillator clock selected
0110: External High Speed oscillator clock selected
0111: (CK_PLL / 2) clock selected
5.3.2. Clock configuration register 0 (RCU_CFG0)
Address offset: 0x04
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
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1000: CK_PLL1 clock selected
1001: CK_PLL2 clock divided by 2 selected
1010: EXT1 selected
1011: CK_PLL2 clock selected
23:22
USBFSPSC[1:0]
USBFS clock prescaler selection
Set and reset by software to control the USBFS clock prescaler value. The USBFS
clock must be 48MHz. These bits can’t be reset if the USBFS clock is enabled.
00: CK_USBFS = CK_PLL / 1.5
01: CK_USBFS = CK_PLL
10: CK_USBFS = CK_PLL / 2.5
11: CK_USBFS = CK_PLL / 2
21:18
PLLMF[3:0]
The PLL clock multiplication factor
Bit 29 of RCU_CFG0 and these bits are written by software to define the PLL
multiplication factor
Caution: The PLL output frequency must not exceed 108 MHz
00000: (PLL source clock x 2)
00001: (PLL source clock x 3)
00010: (PLL source clock x 4)
00011: (PLL source clock x 5)
00100: (PLL source clock x 6)
00101: (PLL source clock x 7)
00110: (PLL source clock x 8)
00111: (PLL source clock x 9)
01000: (PLL source clock x 10)
01001: (PLL source clock x 11)
01010: (PLL source clock x 12)
01011: (PLL source clock x 13)
01100: (PLL source clock x 14)
01101: (PLL source clock x 6.5)
01110: (PLL source clock x 16)
01111: (PLL source clock x 16)
10000: (PLL source clock x 17)
10001: (PLL source clock x 18)
10010: (PLL source clock x 19)
10011: (PLL source clock x 20)
10100: (PLL source clock x 21)
10101: (PLL source clock x 22)
10110: (PLL source clock x 23)
10111: (PLL source clock x 24)
11000: (PLL source clock x 25)
11001: (PLL source clock x 26)
11010: (PLL source clock x 27)
11011: (PLL source clock x 28)
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11100: (PLL source clock x 29)
11101: (PLL source clock x 30)
11110: (PLL source clock x 31)
11111: (PLL source clock x 32)
17
PREDV0_LSB
The LSB of PREDV0 division factor
This bit is the same bit as PREDV0 division factor bit [0] from RCU_CFG1. Changing
the PREDV0 division factor bit [0] from RCU_CFG1, this bit is also changed. When
the PREDV0 division factor bits [3:1] are not set, this bit controls PREDV0 input
clock divided by 2 or not.
16
PLLSEL
PLL Clock Source Selection
Set and reset by software to control the PLL clock source.
0: (IRC8M / 2) clock selected as source clock of PLL
1: HXTAL selected as source clock of PLL
15:14
ADCPSC[1:0]
ADC clock prescaler selection
These bits and bit 28 of RCU_CFG0 are written by software to define the ADC
prescaler factor.Set and cleared by software.
000: (CK_APB2 / 2) selected
001: (CK_APB2 / 4) selected
010: (CK_APB2 / 6) selected
011: (CK_APB2 / 8) selected
100: (CK_APB2 / 2) selected
101: (CK_APB2 / 12) selected
110: (CK_APB2 / 8) selected
111: (CK_APB2 / 16) selected
13:11
APB2PSC[2:0]
APB2 prescaler selection
Set and reset by software to control the APB2 clock division ratio.
0xx: CK_AHB selected
100: (CK_AHB / 2) selected
101: (CK_AHB / 4) selected
110: (CK_AHB / 8) selected
111: (CK_AHB / 16) selected
10:8
APB1PSC[2:0]
APB1 prescaler selection
Set and reset by software to control the APB1 clock division ratio.
Caution: The CK_APB1 output frequency must not exceed 60 MHz.
0xx: CK_AHB selected
100: (CK_AHB / 2) selected
101: (CK_AHB / 4) selected
110: (CK_AHB / 8) selected
111: (CK_AHB / 16) selected
7:4
AHBPSC[3:0]
AHB prescaler selection
Set and reset by software to control the AHB clock division ratio
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0xxx: CK_SYS selected
1000: (CK_SYS / 2) selected
1001: (CK_SYS / 4) selected
1010: (CK_SYS / 8) selected
1011: (CK_SYS / 16) selected
1100: (CK_SYS / 64) selected
1101: (CK_SYS / 128) selected
1110: (CK_SYS / 256) selected
1111: (CK_SYS / 512) selected
3:2
SCSS[1:0]
System clock switch status
Set and reset by hardware to indicate the clock source of system clock.
00: select CK_IRC8M as the CK_SYS source
01: select CK_HXTAL as the CK_SYS source
10: select CK_PLL as the CK_SYS source
11: reserved
1:0
SCS[1:0]
System clock switch
Set by software to select the CK_SYS source. Because the change of CK_SYS has
inherent latency, software should read SCSS to confirm whether the switching is
complete or not. The switch will be forced to IRC8M when leaving Deep-sleep and
Standby mode or HXTAL failure is detected by HXTAL clock monitor when HXTAL
is selected directly or indirectly as the clock source of CK_SYS
00: select CK_IRC8M as the CK_SYS source
01: select CK_HXTAL as the CK_SYS source
10: select CK_PLL as the CK_SYS source
11: reserved
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CKMIC
PLL2
STBIC
PLL1
STBIC
PLL
STBIC
HXTAL
STBIC
IRC8M
STBIC
LXTAL
STBIC
IRC40K
STBIC w w w w w w w w 15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Reserved
PLL2
STBIE
PLL1
STBIE
PLL
STBIE
HXTAL
STBIE
IRC8M
STBIE
LXTAL
STBIE
IRC40K
STBIE
CKMIF
PLL2
STBIF
PLL1
STBIF
PLL
STBIF
HXTAL
STBIF
IRC8M
STBIF
LXTAL
STBIF
IRC40K
STBIF rw
rw
rw
rw
rw
rw
rw r r r r r r r r
5.3.3. Clock interrupt register (RCU_INT)
Address offset: 0x08
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
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Bits
Fields
Descriptions
31:24
Reserved
Must be kept at reset value
23
CKMIC
HXTAL Clock Stuck Interrupt Clear
Write 1 by software to reset the CKMIF flag.
0: Not reset CKMIF flag
1: Reset CKMIF flag
22
PLL2STBIC
PLL2 stabilization Interrupt Clear
Write 1 by software to reset the PLL2STBIF flag.
0: Not reset PLL2STBIF flag
1: Reset PLL2STBIF flag
21
PLL1STBIC
PLL1 stabilization Interrupt Clear
Write 1 by software to reset the PLL1STBIF flag.
0: Not reset PLL1STBIF flag
1: Reset PLL1STBIF flag
20
PLLSTBIC
PLL stabilization Interrupt Clear
Write 1 by software to reset the PLLSTBIF flag.
0: Not reset PLLSTBIF flag
1: Reset PLLSTBIF flag
19
HXTALSTBIC
HXTAL Stabilization Interrupt Clear
Write 1 by software to reset the HXTALSTBIF flag.
0: Not reset HXTALSTBIF flag
1: Reset HXTALSTBIF flag
18
IRC8MSTBIC
IRC8M Stabilization Interrupt Clear
Write 1 by software to reset the IRC8MSTBIF flag.
0: Not reset IRC8MSTBIF flag
1: Reset IRC8MSTBIF flag
17
LXTALSTBIC
LXTAL Stabilization Interrupt Clear
Write 1 by software to reset the LXTALSTBIF flag.
0: Not reset LXTALSTBIF flag
1: Reset LXTALSTBIF flag
16
IRC40KSTBIC
IRC40K Stabilization Interrupt Clear
Write 1 by software to reset the IRC40KSTBIF flag.
0: Not reset IRC40KSTBIF flag
1: Reset IRC40KSTBIF flag
15
Reserved
Must be kept at reset value
14
PLL2STBIE
PLL2 Stabilization Interrupt Enable
Set and reset by software to enable/disable the PLL2 stabilization interrupt.
0: Disable the PLL2 stabilization interrupt
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1: Enable the PLL2 stabilization interrupt
13
PLL1STBIE
PLL1 Stabilization Interrupt Enable
Set and reset by software to enable/disable the PLL1 stabilization interrupt.
0: Disable the PLL1 stabilization interrupt
1: Enable the PLL1 stabilization interrupt
12
PLLSTBIE
PLL Stabilization Interrupt Enable
Set and reset by software to enable/disable the PLL stabilization interrupt.
0: Disable the PLL stabilization interrupt
1: Enable the PLL stabilization interrupt
11
HXTALSTBIE
HXTAL Stabilization Interrupt Enable
Set and reset by software to enable/disable the HXTAL stabilization interrupt
0: Disable the HXTAL stabilization interrupt
1: Enable the HXTAL stabilization interrupt
10
IRC8MSTBIE
IRC8M Stabilization Interrupt Enable
Set and reset by software to enable/disable the IRC8M stabilization interrupt
0: Disable the IRC8M stabilization interrupt
1: Enable the IRC8M stabilization interrupt
9
LXTALSTBIE
LXTAL Stabilization Interrupt Enable
LXTAL stabilization interrupt enable/disable control
0: Disable the LXTAL stabilization interrupt
1: Enable the LXTAL stabilization interrupt
8
IRC40KSTBIE
IRC40K Stabilization interrupt enable
IRC40K stabilization interrupt enable/disable control
0: Disable the IRC40K stabilization interrupt
1: Enable the IRC40K stabilization interrupt
7
CKMIF
HXTAL Clock Stuck Interrupt Flag
Set by hardware when the HXTAL clock is stuck.
Reset when setting the CKMIC bit by software.
0: Clock operating normally
1: HXTAL clock stuck
6
PLL2STBIF
PLL2 stabilization interrupt flag
Set by hardware when the PLL2 is stable and the PLL2STBIE bit is set.
Reset when setting the PLL2STBIC bit by software.
0: No PLL2 stabilization interrupt generated
1: PLL2 stabilization interrupt generated
5
PLL1STBIF
PLL1 stabilization interrupt flag
Set by hardware when the PLL1 is stable and the PLL1STBIE bit is set.
Reset when setting the PLL1STBIC bit by software.
0: No PLL1 stabilization interrupt generated
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1: PLL1 stabilization interrupt generated
4
PLLSTBIF
PLL stabilization interrupt flag
Set by hardware when the PLL is stable and the PLLSTBIE bit is set.
Reset when setting the PLLSTBIC bit by software.
0: No PLL stabilization interrupt generated
1: PLL stabilization interrupt generated
3
HXTALSTBIF
HXTAL stabilization interrupt flag
Set by hardware when the High speed 3 ~ 25 MHz crystal oscillator clock is stable
and the HXTALSTBIE bit is set.
Reset when setting the HXTALSTBIC bit by software.
0: No HXTAL stabilization interrupt generated
1: HXTAL stabilization interrupt generated
2
IRC8MSTBIF
IRC8M stabilization interrupt flag
Set by hardware when the Internal 8 MHz RC oscillator clock is stable and the
IRC8MSTBIE bit is set.
Reset when setting the IRC8MSTBIC bit by software.
0: No IRC8M stabilization interrupt generated
1: IRC8M stabilization interrupt generated
1
LXTALSTBIF
LXTAL stabilization interrupt flag
Set by hardware when the Low speed 32,768 Hz crystal oscillator clock is stable
and the LXTALSTBIE bit is set.
Reset when setting the LXTALSTBIC bit by software.
0: No LXTAL stabilization interrupt generated
1: LXTAL stabilization interrupt generated
0
IRC40KSTBIF
IRC40K stabilization interrupt flag
Set by hardware when the Internal 40kHz RC oscillator clock is stable and the
IRC40KSTBIE bit is set.
Reset when setting the IRC40KSTBIC bit by software.
0: No IRC40K stabilization clock ready interrupt generated
1: IRC40K stabilization interrupt generated
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
5.3.4. APB2 reset register (RCU_APB2RST)
Address offset: 0x0C
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
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Reserved
USART0
RST
Reserved
SPI0RST
TIMER0R
ST
ADC1RS
T
ADC0RS
T
Reserved
PERST
PDRST
PCRST
PBRST
PARST
Reserved
AFRST
rw rw
rw
rw
rw rw
rw
rw
rw
rw rw
Bits
Fields
Descriptions
31:15
Reserved
Must be kept at reset value
14
USART0RST
USART0 Reset
This bit is set and reset by software.
0: No reset
1: Reset the USART0
13
Reserved
Must be kept at reset value
12
SPI0RST
SPI0 reset
This bit is set and reset by software.
0: No reset
1: Reset the SPI0
11
TIMER0RST
Timer 0 reset
This bit is set and reset by software.
0: No reset
1: Reset the TIMER0
10
ADC1RST
ADC1 reset
This bit is set and reset by software.
0: No reset
1: Reset the ADC1
9
ADC0RST
ADC0 reset
This bit is set and reset by software.
0: No reset
1: Reset the ADC0
8:7
Reserved
Must be kept at reset value
6
PERST
GPIO port E reset
This bit is set and reset by software.
0: No reset
1: Reset the GPIO port E
5
PDRST
GPIO port D reset
This bit is set and reset by software.
0: No reset
1: Reset the GPIO port D
4
PCRST
GPIO port C reset
This bit is set and reset by software.
0: No reset
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1: Reset the GPIO port C
3
PBRST
GPIO port B reset
This bit is set and reset by software.
0: No reset
1: Reset the GPIO port B
2
PARST
GPIO port A reset
This bit is set and reset by software.
0: No reset
1: Reset the GPIO port A
1
Reserved
Must be kept at reset value
0
AFRST
Alternate function I/O reset
This bit is set and reset by software.
0: No reset
1: Reset Alternate Function I/O
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
DACRST
PMURST
BKPIRST
CAN1RS
T
CAN0RS
T
Reserved
I2C1RST
I2C0RST
UART4R
ST
UART3R
ST
USART2
RST
USART1
RST
Reserved
rw
rw
rw
rw
rw rw
rw
rw
rw
rw
rw 15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
SPI2RST
SPI1RST
Reserved
WWDGT
RST
Reserved
TIMER6R
ST
TIMER5R
ST
TIMER4R
ST
TIMER3R
ST
TIMER2R
ST
TIMER1R
ST
rw
rw rw rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:30
Reserved
Must be kept at reset value
29
DACRST
DAC reset
This bit is set and reset by software.
0: No reset
1: Reset DAC unit
28
PMURST
Power control reset
This bit is set and reset by software.
0: No reset
5.3.5. APB1 reset register (RCU_APB1RST)
Address offset: 0x10
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
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1: Reset power control unit
27
BKPIRST
Backup interface reset
This bit is set and reset by software.
0: No reset
1: Reset backup interface
26
CAN1RST
CAN1 reset
This bit is set and reset by software.
0: No reset
1: Reset the CAN1
25
CAN0RST
CAN0 reset
This bit is set and reset by software.
0: No reset
1: Reset the CAN0
24:23
Reserved
Must be kept at reset value
22
I2C1RST
I2C1 reset
This bit is set and reset by software.
0: No reset
1: Reset the I2C1
21
I2C0RST
I2C0 reset
This bit is set and reset by software.
0: No reset
1: Reset the I2C0
20
UART4RST
UART4 reset
This bit is set and reset by software.
0: No reset
1: Reset the UART4
19
UART3RST
UART3 reset
This bit is set and reset by software.
0: No reset
1: Reset the UART3
18
USART2RST
USART2 reset
This bit is set and reset by software.
0: No reset
1: Reset the USART2
17
USART1RST
USART1 reset
This bit is set and reset by software.
0: No reset
1: Reset the USART1
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GD32VF103 User Manual
16
Reserved
Must be kept at reset value
15
SPI2RST
SPI2 reset
This bit is set and reset by software.
0: No reset
1: Reset the SPI2
14
SPI1RST
SPI1 reset
This bit is set and reset by software.
0: No reset
1: Reset the SPI1
13:12
Reserved
Must be kept at reset value
11
WWDGTRST
WWDGT reset
This bit is set and reset by software.
0: No reset
1: Reset the WWDGT
10:6
Reserved
Must be kept at reset value
5
TIMER6RST
TIMER6 reset
This bit is set and reset by software.
0: No reset
1: Reset the TIMER6
4
TIMER5RST
TIMER5 reset
This bit is set and reset by software.
0: No reset
1: Reset the TIMER5
3
TIMER4RST
TIMER4 reset
This bit is set and reset by software.
0: No reset
1: Reset the TIMER4
2
TIMER3RST
TIMER3 reset
This bit is set and reset by software.
0: No reset
1: Reset the TIMER3
1
TIMER2RST
TIMER2 reset
This bit is set and reset by software.
0: No reset
1: Reset the TIMER2
0
TIMER1RST
TIMER1 reset
This bit is set and reset by software.
0: No reset
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1: Reset the TIMER1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Reserved
USBFSE
N
Reserved
EXMCEN
Reserved
CRCEN
Reserved
FMCSPE
N
Reserved
SRAMSP
EN
DMA1EN
DMA0EN
rw rw rw rw rw
rw
rw
Bits
Fields
Descriptions
31:13
Reserved
Must be kept at reset value
12
USBFSEN
USBFS clock enable
This bit is set and reset by software.
0: Disabled USBFS clock
1: Enabled USBFS clock
11:9
Reserved
Must be kept at reset value
8
EXMCEN
EXMC clock enable
This bit is set and reset by software.
0: Disabled EXMC clock
1: Enabled EXMC clock
7
Reserved
Must be kept at reset value
6
CRCEN
CRC clock enable
This bit is set and reset by software.
0: Disabled CRC clock
1: Enabled CRC clock
5
Reserved
Must be kept at reset value
4
FMCSPEN
FMC clock enable when sleep mode
This bit is set and reset by software to enable/disable FMC clock during Sleep
mode.
0: Disabled FMC clock during Sleep mode
1: Enabled FMC clock during Sleep mode
5.3.6. AHB enable register (RCU_AHBEN)
Address offset: 0x14
Reset value: 0x0000 0014
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
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3
Reserved
Must be kept at reset value
2
SRAMSPEN
SRAM interface clock enable when sleep mode
This bit is set and reset by software to enable/disable SRAM interface clock during
Sleep mode.
0: Disabled SRAM interface clock during Sleep mode.
1: Enabled SRAM interface clock during Sleep mode
1
DMA1EN
DMA1 clock enable
This bit is set and reset by software.
0: Disabled DMA1 clock
1: Enabled DMA1 clock
0
DMA0EN
DMA0 clock enable
This bit is set and reset by software.
0: Disabled DMA0 clock
1: Enabled DMA0 clock
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Reserved
USART0
EN
Reserved
SPI0EN
TIMER0E
N
ADC1EN
ADC0EN
Reserved
PEEN
PDEN
PCEN
PBEN
PAEN
Reserved
AFEN
rw rw
rw
rw
rw rw
rw
rw
rw
rw rw
Bits
Fields
Descriptions
31:15
Reserved
Must be kept at reset value
14
USART0EN
USART0 clock enable
This bit is set and reset by software.
0: Disabled USART0 clock
1: Enabled USART0 clock
13
Reserved
Must be kept at reset value
12
SPI0EN
SPI0 clock enable
This bit is set and reset by software.
0: Disabled SPI0 clock
1: Enabled SPI0 clock
5.3.7. APB2 enable register (RCU_APB2EN)
Address offset: 0x18
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
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11
TIMER0EN
TIMER0 clock enable
This bit is set and reset by software.
0: Disabled TIMER0 clock
1: Enabled TIMER0 clock
10
ADC1EN
ADC1 clock enable
This bit is set and reset by software.
0: Disabled ADC1 clock
1: Enabled ADC1 clock
9
ADC0EN
ADC0 clock enable
This bit is set and reset by software.
0: Disabled ADC0 clock
1: Enabled ADC0 clock
8:7
Reserved
Must be kept at reset value
6
PEEN
GPIO port E clock enable
This bit is set and reset by software.
0: Disabled GPIO port E clock
1: Enabled GPIO port E clock
5
PDEN
GPIO port D clock enable
This bit is set and reset by software.
0: Disabled GPIO port D clock
1: Enabled GPIO port D clock
4
PCEN
GPIO port C clock enable
This bit is set and reset by software.
0: Disabled GPIO port C clock
1: Enabled GPIO port C clock
3
PBEN
GPIO port B clock enable
This bit is set and reset by software.
0: Disabled GPIO port B clock
1: Enabled GPIO port B clock
2
PAEN
GPIO port A clock enable
This bit is set and reset by software.
0: Disabled GPIO port A clock
1: Enabled GPIO port A clock
1
Reserved
Must be kept at reset value
0
AFEN
Alternate function IO clock enable
This bit is set and reset by software.
0: Disabled Alternate Function IO clock
1: Enabled Alternate Function IO clock
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31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
DACEN
PMUEN
BKPIEN
CAN1EN
CAN0EN
Reserved
I2C1EN
I2C0EN
UART4E
N
UART3E
N
USART2
EN
USART1
EN
Reserved
rw
rw
rw
rw
rw rw
rw
rw
rw
rw
rw 15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
SPI2EN
SPI1EN
Reserved
WWDGT
EN
Reserved
TIMER6E
N
TIMER5E
N
TIMER4E
N
TIMER3E
N
TIMER2E
N
TIMER1E
N
rw
rw rw rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:30
Reserved
Must be kept at reset value
29
DACEN
DAC clock enable
This bit is set and reset by software.
0: Disabled DAC clock
1: Enabled DAC clock
28
PMUEN
PMU clock enable
This bit is set and reset by software.
0: Disabled PMU clock
1: Enabled PMU clock
27
BKPIEN
Backup interface clock enable
This bit is set and reset by software.
0: Disabled Backup interface clock
1: Enabled Backup interface clock
26
CAN1EN
CAN1 clock enable
This bit is set and reset by software.
0: Disabled CAN1 clock
1: Enabled CAN1 clock
25
CAN0EN
CAN0 clock enable
This bit is set and reset by software.
0: Disabled CAN0 clock
1: Enabled CAN0 clock
24:23
Reserved
Must be kept at reset value
22
I2C1EN
I2C1 clock enable
This bit is set and reset by software.
5.3.8. APB1 enable register (RCU_APB1EN)
Address offset: 0x1C
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
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0: Disabled I2C1 clock
1: Enabled I2C1 clock
21
I2C0EN
I2C0 clock enable
This bit is set and reset by software.
0: Disabled I2C0 clock
1: Enabled I2C0 clock
20
UART4EN
UART4 clock enable
This bit is set and reset by software.
0: Disabled UART4 clock
1: Enabled UART4 clock
19
UART3EN
UART3 clock enable
This bit is set and reset by software.
0: Disabled UART3 clock
1: Enabled UART3 clock
18
USART2EN
USART2 clock enable
This bit is set and reset by software.
0: Disabled USART2 clock
1: Enabled USART2 clock
17
USART1EN
USART1 clock enable
This bit is set and reset by software.
0: Disabled USART1 clock
1: Enabled USART1 clock
16
Reserved
Must be kept at reset value
15
SPI2EN
SPI2 clock enable
This bit is set and reset by software.
0: Disabled SPI2 clock
1: Enabled SPI2 clock
14
SPI1EN
SPI1 clock enable
This bit is set and reset by software.
0: Disabled SPI1 clock
1: Enabled SPI1 clock
13:12
Reserved
Must be kept at reset value
11
WWDGTEN
WWDGT clock enable
This bit is set and reset by software.
0: Disabled WWDGT clock
1: Enabled WWDGT clock
10:6
Reserved
Must be kept at reset value
5
TIMER6EN
TIMER6 clock enable
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This bit is set and reset by software.
0: Disabled TIMER6 clock
1: Enabled TIMER6 clock
4
TIMER5EN
TIMER5 clock enable
This bit is set and reset by software.
0: Disabled TIMER5 clock
1: Enabled TIMER5 clock
3
TIMER4EN
TIMER4 clock enable
This bit is set and reset by software.
0: Disabled TIMER4 clock
1: Enabled TIMER4 clock
2
TIMER3EN
TIMER3 clock enable
This bit is set and reset by software.
0: Disabled TIMER3 clock
1: Enabled TIMER3 clock
1
TIMER2EN
TIMER2 clock enable
This bit is set and reset by software.
0: Disabled TIMER2 clock
1: Enabled TIMER2 clock
0
TIMER1EN
TIMER1 clock enable
This bit is set and reset by software.
0: Disabled TIMER1 clock
1: Enabled TIMER1 clock
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
BKPRST rw
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
RTCEN
Reserved
RTCSRC[1:0]
Reserved
LXTALBP
S
LXTALST
B
LXTALEN
rw rw
rw r rw
5.3.9. Backup domain control register (RCU_BDCTL)
Address offset: 0x20
Reset value: 0x0000 0018, reset by Backup domain Reset.
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
Note: The LXTALEN, LXTALBPS, RTCSRC and RTCEN bits of the Backup domain control
register (RCU_BDCTL) are only reset after a Backup domain Reset. These bits can be
modified only when the BKPWEN bit in the Power control register (PMU_CTL) is set.
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Bits
Fields
Descriptions
31:17
Reserved
Must be kept at reset value
16
BKPRST
Backup domain reset
This bit is set and reset by software.
0: No reset
1: Resets Backup domain
15
RTCEN
RTC clock enable
This bit is set and reset by software.
0: Disabled RTC clock
1: Enabled RTC clock
14:10
Reserved
Must be kept at reset value
9:8
RTCSRC[1:0]
RTC clock entry selection
Set and reset by software to control the RTC clock source. Once the RTC clock
source has been selected, it cannot be changed anymore unless the Backup
domain is reset.
00: No clock selected
01: CK_LXTAL selected as RTC source clock
10: CK_IRC40K selected as RTC source clock
11: (CK_HXTAL / 128) selected as RTC source clock
7:3
Reserved
Must be kept at reset value
2
LXTALBPS
LXTAL bypass mode enable
Set and reset by software.
0: Disable the LXTAL Bypass mode
1: Enable the LXTAL Bypass mode
1
LXTALSTB
Low speed crystal oscillator stabilization flag
Set by hardware to indicate if the LXTAL output clock is stable and ready for use.
0: LXTAL is not stable
1: LXTAL is stable
0
LXTALEN
LXTAL enable
Set and reset by software.
0: Disable LXTAL
1: Enable LXTAL
5.3.10. Reset source/clock register (RCU_RSTSCK)
Address offset: 0x24
Reset value: 0x0C00 0000, ALL reset flags reset by power Reset only, RSTFC/IRC40KEN
reset by system reset.
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31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LP
RSTF
WWDGT
RSTF
FWDGT
RSTF
SW
RSTF
POR
RSTF
EP
RSTF
Reserved
RSTFC
Reserved
r r r r r r
rw 15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Reserved
IRC40K
STB
IRC40KE
N r
rw
Bits
Fields
Descriptions
31
LPRSTF
Low-power reset flag
Set by hardware when Deep-sleep /standby reset generated.
Reset by writing 1 to the RSTFC bit.
0: No Low-power management reset generated
1: Low-power management reset generated
30
WWDGTRSTF
Window watchdog timer reset flag
Set by hardware when a window watchdog timer reset generated.
Reset by writing 1 to the RSTFC bit.
0: No window watchdog reset generated
1: Window watchdog reset generated
29
FWDGTRSTF
Free watchdog timer reset flag
Set by hardware when a free watchdog timer reset generated.
Reset by writing 1 to the RSTFC bit.
0: No free watchdog timer reset generated
1: free Watchdog timer reset generated
28
SWRSTF
Software reset flag
Set by hardware when a software reset generated.
Reset by writing 1 to the RSTFC bit.
0: No software reset generated
1: Software reset generated
27
PORRSTF
Power reset flag
Set by hardware when a Power reset generated.
Reset by writing 1 to the RSTFC bit.
0: No Power reset generated
1: Power reset generated
26
EPRSTF
External PIN reset flag
Set by hardware when an External PIN reset generated.
Reset by writing 1 to the RSTFC bit.
0: No External PIN reset generated
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
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1: External PIN reset generated
25
Reserved
Must be kept at reset value
24
RSTFC
Reset flag clear
This bit is set by software to clear all reset flags.
0: Not clear reset flags
1: Clear reset flags
23:2
Reserved
Must be kept at reset value
1
IRC40KSTB
IRC40K stabilization flag
Set by hardware to indicate if the IRC40K output clock is stable and ready for use.
0: IRC40K is not stable
1: IRC40K is stable
0
IRC40KEN
IRC40K enable
Set and reset by software.
0: Disable IRC40K
1: Enable IRC40K
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Reserved
USBFSR
ST
Reserved
rw
Bits
Fields
Descriptions
31:13
Reserved
Must be kept at reset value
12
USBFSRST
USBFS reset
This bit is set and reset by software.
0: No reset
1: Reset the USBFS
11:0
Reserved
Must be kept at reset value
5.3.11. AHB reset register (RCU_AHBRST)
Address offset: 0x28
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
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31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
I2S2SEL
I2S1SEL
PREDV0
SEL rw
rw
rw
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
PLL2MF[3:0]
PLL1MF[3:0]
PREDV1[3:0]
PREDV0[3:0]
rw
rw
rw
rw
Bits
Fields
Descriptions
31:19
Reserved
Must be kept at reset value
18
I2S2SEL
I2S2 Clock Source Selection
Set and reset by software to control the I2S2 clock source.
0: System clock selected as I2S2 source clock
1: (CK_PLL2 x 2) selected as I2S2 source clock
17
I2S1SEL
I2S1 Clock Source Selection
Set and reset by software to control the I2S1 clock source.
0: System clock selected as I2S1 source clock
1: (CK_PLL2 x 2) selected as I2S1 source clock
16
PREDV0SEL
PREDV0 input Clock Source Selection
Set and reset by software.
0: HXTAL selected as PREDV0 input source clock
1: CK_PLL1 selected as PREDV0 input source clock
15:12
PLL2MF[3:0]
The PLL2 clock multiplication factor
Set and reset by software.
00xx: reserve
010x: reserve
0110: (PLL2 source clock x 8)
0111: (PLL2 source clock x 9)
1000 :(PLL2 source clock x 10)
1001: (PLL2 source clock x 11)
1010: (PLL2 source clock x 12)
1011: (PLL2 source clock x 13)
1100: (PLL2 source clock x 14)
1101: (PLL2 source clock x 15)
1110: (PLL2 source clock x 16)
5.3.12. Clock configuration register 1 (RCU_CFG1)
Address offset: 0x2C
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
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1111: (PLL2 source clock x 20)
11:8
PLL1MF[3:0]
The PLL1 clock multiplication factor
Set and reset by software.
00xx: reserve
010x: reserve
0110: (PLL1 source clock x 8)
0111: (PLL1 source clock x 9)
1000 :(PLL1 source clock x 10)
1001: (PLL1 source clock x 11)
1010: (PLL1 source clock x 12)
1011: (PLL1 source clock x 13)
1100: (PLL1 source clock x 14)
1101: (PLL1 source clock x 15)
1110 :(PLL1 source clock x 16)
1111: (PLL1 source clock x 20)
7:4
PREDV1[3:0]
PREDV1 division factor
This bit is set and reset by software. These bits can be written when PLL1 and PLL2
are disable
0000: PREDV1 input source clock not divided
0001: PREDV1 input source clock divided by 2
0010: PREDV1 input source clock divided by 3
0011: PREDV1 input source clock divided by 4
0100: PREDV1 input source clock divided by 5
0101: PREDV1 input source clock divided by 6
0110: PREDV1 input source clock divided by 7
0111: PREDV1 input source clock divided by 8
1000: PREDV1 input source clock divided by 9
1001: PREDV1 input source clock divided by 10
1010: PREDV1 input source clock divided by 11
1011: PREDV1 input source clock divided by 12
1100: PREDV1 input source clock divided by 13
1101: PREDV2 input source clock divided by 14
1110: PREDV2 input source clock divided by 15
1111: PREDV2 input source clock divided by 16
3:0
PREDV0[3:0]
PREDV0 division factor
This bit is set and reset by software. These bits can be written when PLL is disable.
Note: The bit 0 of PREDV0 is same as bit 17 of RCU_CFG0, so modifying
Bit 17 of RCU_CFG0 also modifies bit 0 of RCU_CFG1.
0000: PREDV0 input source clock not divided
0001: PREDV0 input source clock divided by 2
0010: PREDV0 input source clock divided by 3
0011: PREDV0 input source clock divided by 4
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0100: PREDV0 input source clock divided by 5
0101: PREDV0 input source clock divided by 6
0110: PREDV0 input source clock divided by 7
0111: PREDV0 input source clock divided by 8
1000: PREDV0 input source clock divided by 9
1001: PREDV0 input source clock divided by 10
1010: PREDV0 input source clock divided by 11
1011: PREDV0 input source clock divided by 12
1100: PREDV0 input source clock divided by 13
1101: PREDV0 input source clock divided by 14
1110: PREDV0 input source clock divided by 15
1111: PREDV0 input source clock divided by 16
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
Reserved
DSLPVS[1:0]
rw
Bits
Fields
Descriptions
31:2
Reserved
Must be kept at reset value
1:0
DSLPVS[1:0]
Deep-sleep mode voltage select
These bits are set and reset by software
00 : The core voltage is 1.2V in Deep-sleep mode
01 : The core voltage is 1.1V in Deep-sleep mode
10 : The core voltage is 1.0V in Deep-sleep mode
11
: The core voltage is 0.9V in Deep-sleep mode
5.3.13. Deep-sleep mode voltage register (RCU_DSV)
Address offset: 0x34
Reset value: 0x0000 0000
This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit)
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6. Interrupt/event controller (EXTI)
6.1. Overview
RISC-V integrates the Enhancement Core-Local Interrupt Controller (ECLIC) for efficient
interrupts processing. ECLIC is designed to provide low-latency, vectored, pre-emptive
interrupts for RISC-V systems. When activated the ECLIC subsumes and replaces the
existing RISC-V local interrupt scheme (CLINT). The CLIC design has a base design that
requires minimal hardware, but supports additional extensions to provide hardware
acceleration. The goal of the ECLIC design is to provide support for a variety of software ABI
and interrupt models, without complex hardware that can impact high-performance processor
implementations. It’s tightly coupled to the processer core. You can read the Technical
Reference Manual of RISC-V for more details about ECLIC.
EXTI (interrupt/event controller) contains up to 19 independent edge detectors and generates
interrupt requests or events to the processer. The EXTI has three trigger types: rising edge,
falling edge and both edges. Each edge detector in the EXTI can be configured and masked
independently.
6.2. Characteristics
Up to 68 maskable peripheral interrupts.
4 bits interrupt priority configuration - 16 priority levels.
Support interrupt pre-emption and tail-chaining.
Wake up system from power saving mode.
Up to 19 independent edge detectors in EXTI.
Three trigger types: rising, falling and both edges.
Software interrupt or event trigger.
Trigger sources configurable.
6.3. Function overview
The RISC-V processor and the Enhancement Core-Local Interrupt Controller (ECLIC)
prioritize and handle all interrupts in machine mode.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed
without the overhead of state saving and restoration. The following tables list all interrupt
types.
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Vector
Number
Interrupt Description
Vector Address
3
CLIC_INT_SFT
0x0000_000C 7 CLIC_INT_TMR
0x0000_001C
17
CLIC_INT_BWEI
0x0000_0044
18
CLIC_INT_PMOVI
0x0000_0048
19
WWDGT interrupt
0x0000_004C
20
LVD from EXTI interrupt
0x0000_0050
21
Tamper interrupt
0x0000_0054
22
RTC global interrupt
0x0000_0058
23
FMC global interrupt
0x0000_005C
24
RCU global interrupt
0x0000_0060
25
EXTI Line0 interrupt
0x0000_0064
26
EXTI Line1 interrupt
0x0000_0068
27
EXTI Line2 interrupt
0x0000_006C
28
EXTI Line3 interrupt
0x0000_0070
29
EXTI Line4 interrupt
0x0000_0074
30
DMA0 channel0 global interrupt
0x0000_0078
31
DMA0 channel1 global interrupt
0x0000_007C
32
DMA0 channel2 global interrupt
0x0000_0080
33
DMA0 channel3 global interrupt
0x0000_0084
34
DMA0 channel4 global interrupt
0x0000_0088
35
DMA0 channel5 global interrupt
0x0000_008C
36
DMA0 channel6 global interrupt
0x0000_0090
37
ADC0 and ADC1 global interrupt
0x0000_0094
38
CAN0 TX interrupts
0x0000_0098
39
CAN0 RX0 interrupts
0x0000_009C
40
CAN0 RX1 interrupts
0x0000_00A0
41
CAN0 EWMC interrupts
0x0000_00A4
42
EXTI line[9:5] interrupts
0x0000_00A8
43
TIMER0 break interrupt
0x0000_00AC
44
TIMER0 update interrupt
0x0000_00B0
45
TIMER0 trigger and channel commutation interrupts
0x0000_00B4
46
TIMER0 channel capture compare interrupt
0x0000_00B8
47
TIMER1 global interrupt
0x0000_00BC
48
TIMER2 global interrupt
0x0000_00C0
49
TIMER3 global interrupt
0x0000_00C4
50
I2C0 event interrupt
0x0000_00C8
51
I2C0 error interrupt
0x0000_00CC
52
I2C1 event interrupt
0x0000_00D0
53
I2C1 error interrupt
0x0000_00D4
Table 6-1. Interrupt vector table
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Vector
Number
Interrupt Description
Vector Address
54
SPI0 global interrupt
0x0000_00D8
55
SPI1 global interrupt
0x0000_00DC
56
USART0 global interrupt
0x0000_00E0
57
USART1 global interrupt
0x0000_00E4
58
USART2 global interrupt
0x0000_00E8
59
EXTI line[15:10] interrupts
0x0000_00EC
60
RTC alarm from EXTI interrupt
0x0000_00F0
61
USBFS wakeup from EXTI interrupt
0x0000_00F4
62
Reserved
0x0000_00F8
63
Reserved
0x0000_00FC
64
Reserved
0x0000_0100
65
Reserved
0x0000_0104
66
Reserved
0x0000_0108
67
Reserved
0x0000_010C
68
Reserved
0x0000_0110
69
TIMER4 global interrupt
0x0000_0114
70
SPI2 global interrupt
0x0000_0118
71
UART3 global interrupt
0x0000_011C
72
UART4 global interrupt
0x0000_0120
73
TIMER5 global interrupt
0x0000_0124
74
TIMER6 global interrupt
0x0000_0128
75
DMA1 channel0 global interrupt
0x0000_012C
76
DMA1 channel1 global interrupt
0x0000_0130
77
DMA1 channel2 global interrupt
0x0000_0134
78
DMA1 channel3 global interrupt
0x0000_0138
79
DMA1 channel4 global interrupt
0x0000_013C
80
Reserved
0x0000_0140
81
Reserved
0x0000_0144
82
CAN1 TX interrupt
0x0000_0148
83
CAN1 RX0 interrupt
0x0000_014C
84
CAN1 RX1 interrupt
0x0000_0150
85
CAN1 EWMC interrupt
0x0000_0154
86
USBFS global interrupt
0x0000_0158
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EXTI Line0~18
Edge
detector
Polarity
Control
Software
Trigger
Interrupt Mask
Control
Event
Generate
Event Mask
Control
To ECLIC
To Wakeup Unit
6.4. External interrupt and event (EXTI) block diagram
Figure 6-1. Block diagram of EXTI
6.5. External Interrupt and Event function overview
The EXTI contains up to 19 independent edge detectors and generates interrupts request or
event to the processer. The EXTI has three trigger types: rising edge, falling edge and both
edges. Each edge detector in the EXTI can be configured and masked independently.
The EXTI trigger source includes 16 external lines from GPIO pins and 3 lines from internal
modules (including LVD, RTC Alarm, USB Wakeup). All GPIO pins can be selected as an
EXTI trigger source by configuring AFIO_EXTISSx registers in GPIO module (please refer to
GPIO and AFIO section for detail).
EXTI can provide not only interrupts but also event signals to the processor. The RISC-V
processor fully implements the Wait For Interrupt (WFI), Wait For Event (WFE) and the Send
Event (SEV) instructions. EXTI can be used to wake up processor and the whole system
when some expected event occurs, such as a special GPIO pin toggling or RTC alarm.
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GD32VF103 User Manual
EXTI Line
Number
Source
0
PA0/PB0/PC0/PD0/PE0
1
PA1/PB1/PC1/PD1/PE1
2
PA2/PB2/PC2/PD2/PE2
3
PA3/PB3/PC3/PD3/PE3
4
PA4/PB4/PC4/PD4/PE4
5
PA5/PB5/PC5/PD5/PE5
6
PA6/PB6/PC6/PD6/PE6
7
PA7/PB7/PC7/PD7/PE7
8
PA8/PB8/PC8/PD8/PE8
9
PA9/PB9/PC9/PD9/PE9
10
PA10/PB10/PC10/PD10/PE10
11
PA11/PB11/PC11/PD11/PE11
12
PA12/PB12/PC12/PD12/PE12
13
PA13/PB13/PC13/PD13/PE13
14
PA14/PB14/PC14/PD14/PE14
15
PA15/PB15/PC15/PD15/PE15
16
LVD
17
RTC Alarm
18
USB Wakeup
Table 6-2. EXTI source
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GD32VF103 User Manual
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
INTEN18
INTEN17
INTEN16
rw
rw
rw
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
INTEN15
INTEN14
INTEN13
INTEN12
INTEN11
INTEN10
INTEN9
INTEN8
INTEN7
INTEN6
INTEN5
INTEN4
INTEN3
INTEN2
INTEN1
INTEN0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:19
Reserved
Must be kept at reset value
18: 0
INTENx
Interrupt enable bit
0: Interrupt from Linex is disabled.
1: Interrupt from Linex is enabled.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
EVEN18
EVEN17
EVEN16
rw
rw
rw
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
EVEN15
EVEN14
EVEN13
EVEN12
EVEN11
EVEN10
EVEN9
EVEN8
EVEN7
EVEN6
EVEN5
EVEN4
EVEN3
EVEN2
EVEN1
EVEN0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:19
Reserved
Must be kept at reset value
18: 0
EVENx
Event enable bit
0: Event from Linex is disabled.
6.6. Register definition
EXTI base address: 0x4001 0400
6.6.1. Interrupt enable register (EXTI_INTEN)
Address offset: 0x00
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
6.6.2. Event enable register (EXTI_EVEN)
Address offset: 0x04
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
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GD32VF103 User Manual
1: Event from Linex is enabled.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
RTEN18
RTEN17
RTEN16
rw
rw
rw
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
RTEN15
RTEN14
RTEN13
RTEN12
RTEN11
RTEN10
RTEN9
RTEN8
RTEN7
RTEN6
RTEN5
RTEN4
RTEN3
RTEN2
RTEN1
RTEN0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31:19
Reserved
Must be kept at reset value
18:0
RTENx
Rising edge trigger enable
0: Rising edge of Linex is invalid
1: Rising edge of Linex is valid as an interrupt/event request
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
FTEN18
FTEN17
FTEN16
rw
rw
rw
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
FTEN15
FTEN14
FTEN13
FTEN12
FTEN11
FTEN10
FTEN9
FTEN8
FTEN7
FTEN6
FTEN5
FTEN4
FTEN3
FTEN2
FTEN1
FTEN0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits
Fields
Descriptions
31: 19
Reserved
Must be kept at reset value
18: 0
FTENx
Falling edge trigger enable
0: Falling edge of Linex is invalid
1: Falling edge of Linex is valid as an interrupt/event request
6.6.3. Rising edge trigger enable register (EXTI_RTEN)
Address offset: 0x08
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
6.6.4. Falling edge trigger enable register (EXTI_FTEN)
Address offset: 0x0C
Reset value: 0x0000 0000
This register has to be accessed by word(32-bit)
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