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Stiletto Rev.2.4
Schematics
33 pgs1.48 Mb0

Gigabyte Stiletto Rev.2.4 Schematics

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A
A
STILETTO SCHEMATICS
CONTENTS
B
PAGE 1 TITLE PAGE 2,3 P4 SOCKET 478 PIN
PAGE 4,5,6,7 INTEL SPRINGDALE
PAGE 8,9 ICH5
PAGE 10 CLOCK GENERATOR
PAGE 11 DDR CHANNEL A DIMM X 2
C
PAGE 12 DDR CHANNEL B DIMM X 2
PAGE 13 DDR CHANNEL A TERMINATION RESISTORS
PAGE 14 DDR CHANNEL B TERMINATION RESISTORS
PAGE 15 DDR DECOUPLING CAPACITORS
PAGE 16 PCI SLOTS X 2
PAGE 17 PCI SLOT X 1 AND AGP SLOT
D
PAGE 18 VGA CONNECTOR
PAGE 19 IDE,K/B,MOUSE CONNECTORS AND REAR USB PORTS X 4
PAGE 20 SIO(LPC47M233)
PAGE 21 PARALLEL & SERIAL PORTS
PAGE 22 AC97 CODEC(AD1981B),MONO AMP & AFP HEADER PAGE 23 AUDIO CONNECTOR,REAR USB PORTS X 2 & FRONT USB PORTS X 2
E
PAGE 24 FAN X 3,S-ATA & POV3
PAGE 25 ATX POWER CONNECTOR & RESET
PAGE 26 SYSTEM POWER
PAGE 27 CPU PWM PAGE 28 LAN(10/100/1000Mbps) PAGE 29 H/W MONITOR
F
PAGE 30 SYSTEM BLOCK DIAGRAM LAST PAGE HISTORY
PCB REV : 2.4
1
23
45
678
ENGINEER:
W.P. YU
DATE CHANGED: SIZE:
JUN,28,2003
CHANGED BY:
R&D CHK:
QA CHK:
Universal Scient ific Industrial
W.P. YU
TITLE:
REV:
2.2
Stiletto
TITLE
DRAWING NUMBER:
######
PAGE
B
C
D
E
F
A3
301
OF
12345D678
J3
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#
RS0# RS1# RS2#
DEP0# DEP1# DEP2# DEP3#
BPM5# BPM4# BPM3# BPM2# BPM1# BPM0#
TESTHI12 TESTHI11 TESTHI10 TESTHI9 TESTHI8 TESTHI7 TESTHI6 TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI1 TESTHI0
BSEL0 BSEL1
AP0# AP1#
COMP1 COMP0
VCC1.2V
1
4
5
3
2
2
3
2
2 2 A
2
E
D
7
D
F
F
F
A
A
A
A
A
A
A
2
3
0
1
4
5
6
7
D
D
D
D
D
D
D
D
E
E
E
E
E
E
E
E
V
V
V
V
V
V
V
V
R
R
R
R
R
R
R
R
E
E
E
E
E
E
E
E
S
S
S
S
S
S
S
S
E
E
E
E
E
E
E
E
R
R
R
R
R
R
R
R
)
)
)
t
t
t
t
t
t
o
o
o
c
c
c
s
s
s
e
e
e
r
r
r
P
P
P r
r
r
o
o
o
f
f
f
5
D
V
D
2
O
.
I
1
O
V (
C
G
C
_
V
D
(
I V
(
REQ4# REQ3# REQ2# REQ1# REQ0#
ITP_CLK0 ITP_CLK1
BCLK1 BCLK0
ADSTB1# ADSTB0#
DBRESET#
LINT1 LINT0
STBP3# STBP2# STBP1# STBP0# STBN3# STBN2# STBN1# STBN0#
IERR#
MCERR#
FERR#
STPCLK#
BINIT#
DBSY# DRDY# TRDY#
LOCK#
HITM#
BPRI#
DEFER#
TRST#
PROCHOT#
IGNNE#
A20M#
PWRGOOD
RESET#
CPUVID(5)
27,20
VID_GOOD
26
4
H_D(0:63)
A
B
D
4
H_RS-(0:2)
H_BPRM5_PREQ-
2
H_BPRM4_PRDY-
2
2
H_BPRM3
2
H_BPRM2 H_BPRM1
E
E R O C
V
FSA FSB Freq
F
1 0 533MHZ
0 1 800MHZ
2 2
H_BPRM0
RN17 8P4R 62R56
RN16 8P4R 62R56
RN17 8P4R 62R12
RN18 8P4R 62R87
10,4 10,4
R340 62R
H_FSA H_FSB
R257 61R9_1%
62RR339
61R9_1%R256
62R8P 4RRN16 7 8
TESTHI7
TESTHI1
62R8P4RRN17 3 4
TESTHI0
T65 T66
H_RS-(0) H_RS-(1) H_RS-(2)
TESTHI12 TESTHI11 TESTHI10 TESTHI9 TESTHI8
H_COMP1 H_COMP0
H_D(0) H_D(1) H_D(2) H_D(3) H_D(4) H_D(5) H_D(6) H_D(7) H_D(8) H_D(9) H_D(10) H_D(11) H_D(12) H_D(13) H_D(14) H_D(15) H_D(16) H_D(17) H_D(18) H_D(19) H_D(20) H_D(21) H_D(22) H_D(23) H_D(24) H_D(25) H_D(26) H_D(27) H_D(28) H_D(29) H_D(30) H_D(31) H_D(32) H_D(33) H_D(34) H_D(35) H_D(36) H_D(37) H_D(38) H_D(39) H_D(40) H_D(41) H_D(42) H_D(43) H_D(44) H_D(45) H_D(46) H_D(47) H_D(48) H_D(49) H_D(50) H_D(51) H_D(52) H_D(53) H_D(54) H_D(55) H_D(56) H_D(57) H_D(58) H_D(59) H_D(60) H_D(61) H_D(62) H_D(63)
B21 B22 A23 A25 C21 D22 B24 C23 C24 B25 G22 H21 C26 D23
J21 D25 H22 E24 G23 F23 F24 E25 F26 D26 L21 G26 H24
M21
L22
J24 K23 H25
M23
N22 P21
M24
N23
M26
N26 N25 R21 P24 R25 R24 T26 T25 T22 T23 U26 U24 U23 V25 U21 V22 V24
W26
Y26
W25
Y23 Y24 Y21
AA25 AA22 AA24
F1 G5 F4
J26 K25 K26 L25
AB4 AA5
Y6 AC4 AB5 AC6
AD25
A6
Y3
W4
U6
AB22 AA20 AC23 AC24 AC20 AC21
AA2
AD24
AD6 AD5
AC1
V5
P1
L24
P4-478_1
12345
DB#3 DB#2 DB#1 DB#0
INIT#
ADS#
BR0# BNR#
T72
T67
T73
H_A(31) H_A(30) H_A(29) H_A(28) H_A(27) H_A(26) H_A(25) H_A(24) H_A(23) H_A(22) H_A(21) H_A(20) H_A(19) H_A(18) H_A(17) H_A(16) H_A(15) H_A(14) H_A(13) H_A(12) H_A(11) H_A(10)
H_A(9) H_A(8) H_A(7) H_A(6) H_A(5) H_A(4) H_A(3)
CPUVID(0) CPUVID(1) CPUVID(2) CPUVID(3) CPUVID(4)
H_REQ(4) H_REQ(3) H_REQ(2) H_REQ(1) H_REQ(0)
H_DBI-(3) H_DBI-(2) H_DBI-(1) H_DBI-(0)
HD_STBP-(3) HD_STBP-(2) HD_STBP-(1) HD_STBP-(0) HD_STBN-(3) HD_STBN-(2) HD_STBN-(1) HD_STBN-(0)
T68 T69
T70
T71
T74
H_A(3:31)
CPUVID(0:4)
H_REQ(0:4)
CLK_HOST_CPU_ITP CLK_HOST_CPU_ITP-
CLK_HOST_CPU­CLK_HOST_CPU
H_DBI-(0:3)
HA_STB1­HA_STB0­DBRESET-
H_NMI H_INTR
HD_STBP-(0:3)
HD_STBN-(0:3)
H_FERR­H_STPCLK-
H_INIT-
H_DBSY­H_DRDY­H_TRDY­H_ADS­H_LOCK­H_BR0­H_BNR­H_HIT­H_HITM­H_BPRI­H_DEFER­H_TCK H_TDI H_TMS H_TRST­H_TDO H_PROCHOT­H_IGNNE­H_SMI­H_A20M­H_SLP­H_PWRGD CPU_RESET-
4
4
4 4 24,25,9,2
9 9
9 9
9
4 4 4 4 4 4,2 4 4 4 4 4 2 2 2 2 2 9,4,2 9 9,20 9 9 9,2 4,2
A
VCORE
9,4,2
2 2
2 2 2 2
4,2 9,2 4,2
2
H_BPRM5_PREQ­H_BPRM4_PRDY-
H_BPRM3 H_BPRM2 H_BPRM1 H_BPRM0
CPU_RESET-
H_PWRGD
H_BR0-
H_TDI
H_PROCHOT-
H_TRST-
2
RN18 5 6 RN18 62R34 RN16 62R43
R392 62R
R393 R263 R264 R265 150R
CLOSE TO CPU
R267 680R
62R
62RRN16 2 1 62RRN18 1 2
62R 300R 200R
120RR266
B
27,20
CC
10 10
10 10
4
4
10
4
10
4,2
H_BPRM5_PREQ-
2
H_BPRM4_PRDY-
2 2 2
2 2
H_TCK
2
CLK_HOST_ITP-
CLK_HOST_ITP
H_TCK
2
CPU_RESET-
H_BPRM3 H_BPRM2 H_BPRM1 H_BPRM0
150R
R262
XR261
X
U21
13
BPM5
15
BPM4
17
BPM3
19
BPM2
21
BPM1
23
BPM0
4
NC1
6
NC2
8
BCLKN
9
BCLKP
11
FBO
12
RST
X_ITP700FLEX
Molex 52435-2891
TRST
VTAP VTT1 VTT2
47R
7
R268 X
TDO
5
TCK
1
TDI
2
TMS
3
25
DBR
24
DBA
26 27 28
10
VSS1
14
VSS2
16
VSS3
18
VSS4
20
VSS5
22
VSS6
H_TDO
H_TDI H_TMS H_TRST-
DBRESET-
E R O C V
2 2
2 2 2
24,25,9,2
H_TCK
2
6
0
0
4
1
0
B C
E
VCORE
51R_1%
H_TDO
2
H_TMS
2
H_TCK
2
R258
R260 47R
CLOSE TO ITP700
6
47RR259
ENGINEER:
W.P. YU
DRAWN BY:
DATE CHANGED: SIZE:
JUN,28,2003
CHANGED BY:
R&D CHK:
QA CHK:
78
Universal Scientific Industri al
W.P. YU
TITLE:
REV:
2.2
Stiletto
P4 SOCKET-1
DRAWING NUMBER:
######
PAGE
F
A3
302
OF
AB1
A35#
Y1
A34#
W2
A33#
V3
A32#
U4
A31#
T5
A30#
W1
A29#
R6
A28#
V2
A27#
T4
A26#
U3
A25#
P6
A24#
U1
A23#
T2
A22#
R3
A21#
P4
A20#
P3
A19#
R2
A18#
T1
A17#
N5
A16#
N4
A15#
N2
A14#
M1
A13#
N1
A12#
M4
A11#
M3
A10#
L2
A9#
M6
A8#
L3
A7#
K1
A6#
L6
A5#
K4
A4#
K2
A3#
AE5
VID0
AE4
VID1
AE3
VID2
AE2
VID3
AE1
VID4
H3 J3 J4 K5 J1
AC26 AD26
AF23 AF22
V21 P26 G25 E21
R5 L5 AE25
E5 D1
W23 P23 J23 F21 W22 R22 K22 E22
AC3 V6 B6 Y4 AA3 W5 AB2
RSP#
H5 H2 J6 G1 G4 H6 G2 F3
HIT#
E3 D2 E2 D4
TCK
C1
TDI
F7
TMS
E6 D5
TDO
C3 B2 B5
SMI#
C6 AB26
SLP#
AB23 AB25
7
9
3
3
5
1
1
1
2
1
E
E
E
E
E
3
4
1
5
2
0
0
0
0
0
1
1
1
1
1
S
S
S
S
S
S
S
S
S
S
V
V
V
V
V
(OPTIMIZED/COMPAT- for Prescott)
9
8
5
1
0
4
4
7
5
5
1
1
1
1
1
S
S
S
S
S
S
S
S
S
S
V
V
V
V
V
2
6
5
5
2
2
2
T
U
U
U
U
5
T78
2
6
2
2
4
7
9
C
E
E
E
E
0
6
7
8
9
1
0
0
0
0
1
1
1
1
1
S
S
S
S
S
S
S
S
S
S
V
V
V
V
V
(BOOT SELECT for Prescott)
7
6
4
3
2
7
7
5
5
5
1
1
1
1
1
S
S
S
S
S
S
S
S
S
S
V
V
V
V
V
1
4
3
6
1
2
2
2
V
V
V
V
W
6
VCORE
2 T C
POS CAP
3
1
9
7
5
1
1
8
2
1
1
1
C
C
B
C
C
C
C
4
1
2
3
1
1
1
1
1
1
1
1
S
S
S
S
S
S
S
S
V
V
V
V
7
6
5
8
5
5
5
7
1
1
1
1
S
S
S
S
S
S
S
S
V
V
V
V
3
2
6
4
2
2
2
Y
W
W
Y
W
H1
5
6
7
VSS0
1
1
1
H4
1
1
1
VSS1
S
S
S
H23
S
S
S
VSS2
V
V
V
H26
VSS3
A11
VSS4
A13
VSS5
A15
VSS6
A17
VSS7
A19
VSS8
A21
VSS9
A24
VSS10
A26
VSS11
A3
VSS12
A9
VSS13
AA1
VSS14
AA11
VSS15
AA13
VSS16
AA15
VSS17
AA17
VSS18
AA19
VSS19
AA23
VSS20
AA26
VSS21
AA4
VSS22
AA7
VSS23
AA9
VSS24
AB10
VSS25
AB12
VSS26
AB14
VSS27
AB16
VSS28
AB18
VSS29
AB20
VSS30
AB21
VSS31
AB24
VSS32
AB3
VSS33
AB6
VSS34
AB8
VSS35
AC11
VSS36
AC13
VSS37
AC15
VSS38
AC17
VSS39
AC19
VSS40
AC2
VSS41
AC22
VSS42
AC25
VSS43
AC5
VSS44
AC7
VSS45
AC9
VSS46
AD1
VSS47
AD10
VSS48
AD12
VSS49
AD14
VSS50
AD16
VSS51
AD18
VSS52
AD21
VSS53
AD23
VSS54
AD4
VSS55
AD8
VSS56
AE11
VSS57
AE13
VSS58
AE15
VSS59
AE17
VSS60
AE19
VSS61
AE22
VSS62
AE24
VSS63
AE26
VSS64
AE7
VSS65
AE9
VSS66
AF1
VSS67
AF10
VSS68
AF12
VSS69
AF14
VSS70
AF16
VSS71
AF18
VSS72
AF20
VSS73
AF6
VSS74
AF8
VSS75
B10
VSS76
B12
VSS77
B14
VSS78
B16
VSS79
B18
VSS80
B20
VSS81
B23
8
9
9
VSS82
5
7
5
B26
1
1
1
VSS83
S
S
S
B4
S
S
S
VSS84
V
V
V
5
5 2
Y
Y
9 6 2 R
0 7 2 R
VCC3
X
X
VCORE
% 1 _ R 5 6 1
% 1 _ 3 R 5 9
T81
F
F
U
U
0
0
1
1
9
2
6
7
C
C
BOOTSELECT
F U 0 1
5 7 C
67
21
4 F
VCORE
AA10 AA12 AA14 AA16 AA18
AB11 AB13 AB15 AB17 AB19
AC10 AC12 AC14 AC16 AC18
AD11 AD13 AD15 AD17 AD19
AE10 AE12 AE14 AE16 AE18 AE20
AF11 AF13 AF15 AF17 AF19
AF21
A10 A12 A14 A16 A18 A20
A8
AA8
AB7 AB9
AC8
AD7 AD9
AE6 AE8
AF2
AF5 AF7 AF9 B11 B13 B15 B17 B19
B7
B9 C10 C12 C14 C16 C18 C20
C8 D11 D13 D15 D17 D19
D7
D9 E10 E12 E14 E16 E18 E20
E8 F11 F13 F15 F17 F19
F9
33UF
100UF_16V
VCCIOPLL_1
J3
VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84
X
NOPOP
CT3
CE47
2
0
3
2
2
2
D
E
D
A
A
A
L
A
A
L
S
C
P
S
C
O
V
V
I C C V
9
8
1
0
0
1
1
2
6
2
1
1
1
1
1
S
S
S
S
S
S
S
S
S
S
V
V
V
V
V
0
2
4
8
6
1
1
1
1
1
F
F
F
F
F
L15
10UH_100MA
A A
L16
10UH_100MA
VCORE
B
D
E
F
E R V _ D H _ L T
2
G
0
F
4 0
P
0
_
0
6
P
2
C
2
A C
2 _ L
T76
L
T77
T75
P O
I C
1
C
6
2
0
V
A
A
6
2
F
F
A
A
2
3
1
0
F
F
F
F
E
E
E
E
R
R
R
R
L
L
L
L
T
T
T
T
G
G
G
G
8
7
6
5
3
4
2
2
3
1
2
2
6
1
1
1
S
S
S
S
S
S
V
V
V
2
2
5
2
2
F
F
F
2
2
2
2
2
6
6
1
1
1
1
1
1
1
S
S
S
S
S
S
S
S
S
S
S
S
S
S
V
V
V
V
V
V
V
2
4
6
8
1
3
5
J
2
2
F
F
G
G
G
G
9
0
0
-
2
2
H
+
-
C I
D
D
_
E
M
M
P
E
I
S
R
R
S
R
N
E
E
N
T
E
H
H
E
S
M
S
T
T
_
_
_
_
R
C
S
U
U
E
VCC1.2V
C
S
P
P
H
V
V
C
C
T
6
4
2
0
4
5
2
3
4
A
A
B
C
A
E
E
C
A
S
S
D
D
N
N
M
M
E
E
R
R
S
S
_
_
E
E
S
C
H
H
S
C
T
T
V
V
5
F A
#
D
P
I
I
V
R
C
T
C
M
V R E
H T
1
F
5
7
9
2
C
C
C
D
C
A
5
6
7
0
#
8
8
8
8
C
1
S
S
S
C
S
S
S
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ENGINEER:
W.P. YU
DRAWN BY:
DATE CHANGED: SIZE:
JUN,28,2003
CHANGED BY:
R&D CHK:
QA CHK:
Universal Scientific Industri al
W.P. YU
TITLE:
REV:
2.2
Stiletto
P4 SOCKET-2
DRAWING NUMBER:
######
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5
A
A
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S
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DDR Channel A
SPRINGDALE_1
Host Interface
DDR Channel A
H
-
-
-
­0 A _
2
3
4
5
-
-
-
A
A
A
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A
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A
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B
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3
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1 3 K A
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4
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5
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A
A
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K
K
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C
C
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P
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R
R
R
R D D
R
D
D
D
D
D
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D
D
1
1
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1
1
1
1
1
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L
O
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V
V
P
P
P
A
M
M
M
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O
O
O
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C
C
C
R
R
R
R
V
X
X
X
M
M
M
M
S
S
S
S
4
9
9
9
3
L
K
N
E
A
A
A
SMXRCOMPVOL
SMXRCOMPVOH
SMXRCOMP
2
5
0
0
4 0
8
F
9
4
0
5
U
P
_
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C
P
.
C
2
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3
7
8
9
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1
2
6
5
5
5
6
6
6
(
(
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(
(
(
(
A
A
A
A
A
A
A
_
_
_
_
_
_
_
D
D
D
D
D
D
D
_
_
_
_
_
_
_
M
M
M
M
M
M
M
4
4
1
3
4
3
4
3
3
3
3
3
3
3
H
G
F
J
F
K
E
8
7
6
2
3
1
9
0
5
5
5
6
6
6
5
6
A
A
A
A
A
A
A
A
_
_
_
_
_
_
_
_
B23
Q
Q
Q
Q
Q
Q
Q
Q
HD0-
D
D
D
D
D
D
D
D
S
S
S
S
S
S
S
S
HD1­HD2­HD3­HD4­HD5­HD6­HD7­HD8-
HD9­HD10­HD11­HD12­HD13­HD14­HD15­HD16­HD17­HD18­HD19­HD20­HD21­HD22­HD23­HD24­HD25­HD26­HD27­HD28­HD29­HD30­HD31­HD32­HD33­HD34­HD35­HD36­HD37­HD38­HD39­HD40­HD41­HD42­HD43­HD44­HD45­HD46­HD47­HD48­HD49­HD50­HD51­HD52­HD53­HD54­HD55­HD56­HD57­HD58­HD59­HD60­HD61­HD62­HD63-
PROCHOT-
BSEL0 BSEL1
ENGINEER:
DRAWN BY:
DATE CHANGED: SIZE:
JUN,28,2003
CHANGED BY:
R&D CHK:
QA CHK:
78
H_D(0)H_A(3)
E22
H_D(1)H_A(4)
B21
H_D(2)H_A(5)
D20
H_D(3)H_A(6)
B22
H_D(4)H_A(7)
D22
H_D(5)H_A(8)
B20
H_D(6)H_A(9)
C21
H_D(7)H_A(10)
E18
H_D(8)H_A(11)
E20
H_D(9)H_A(12)
B16
H_D(10)H_A(13)
D16
H_D(11)H_A(14)
B18
H_D(12)H_A(15)
B17
H_D(13)H_A(16)
E16
H_D(14)H_A(17)
D18
H_D(15)H_A(18)
G20
H_D(16)H_A(19)
F17
H_D(17)H_A(20)
E19
H_D(18)H_A(21)
F19
H_D(19)H_A(22)
J17
H_D(20)H_A(23)
L18
H_D(21)H_A(24)
G16
H_D(22)H_A(25)
G18
H_D(23)H_A(26)
F21
H_D(24)H_A(27)
F15
H_D(25)H_A(28)
E15
H_D(26)H_A(29)
E21
H_D(27)H_A(30)
J19
H_D(28)H_A(31)
G14
H_D(29)
E17
H_D(30)
K17
H_D(31)H_REQ(1)
J15
H_D(32)H_REQ(2)
L16
H_D(33)H_REQ(3)
J13
H_D(34)
F13
H_D(35)
F11
H_D(36)
E13
H_D(37)
K15
H_D(38)
G12
H_D(39)
G10
H_D(40)
L15
H_D(41)
E11
H_D(42)
K13
H_D(43)
J11
H_D(44)
H10
H_D(45)
G8
H_D(46)
E9
H_D(47)
B13
H_D(48)
E14
H_D(49)
B14
H_D(50)
B12
H_D(51)
B15
H_D(52)
D14
H_D(53)
C13
H_D(54)
B11
H_D(55)
D10
H_D(56)
C11
H_D(57)
E10
H_D(58)
B10
H_D(59)
C9
H_D(60)
B9
H_D(61)
D8
H_D(62)
B8
H_D(63)
L20
L13 L12
%
%
1
1
_
_
9
9
4
4
K
K
2
2
0
9
7
6
1
1
R
R
W.P. YU
Universal Scientific Industri al
W.P. YU
TITLE:
REV:
2.2
R172 2K_1%
DDR Channel A,Host bus
VCC2.5_DDR
% 1
_ 9
3 7
K
1
0 3
R
% 1 _
4 7
K
1
0 1
R
VCC2.5_DDR
% 1 _
5 7
K
1
0
R
1
% 1 _ 9
6 7
K
1
0
R
3
H_PROCHOT-
2K_1%R171
Stiletto
GMCH
DRAWING NUMBER:
######
8
H_D(0:63)
2 0 4 0
5 P C
2 0 4
3
0
2 P C
2 0 4
0
0
7 B C
2
SMXRCOMPVOL
SMXRCOMPVOH
9,2
H_FSA H_FSB
10,2 10,2
A3
PAGE
430
OF
A
B
C
D
E
F
12345678
M_DQS_B(0:7)
SMVREF_GMCH
5 0 8 0 _ P A C
M_DQM_B(0:7)
M_D_B(0:63)
VCC1.5V
% 1 _
3
R
3
6
2
2
R
2
% 1 _
4
R
3
7
2
4
R
1
% 1 _
5
R
3
3
2
1
R
1
VCC1.5V
% 1 _
6
R
3
6
2
2
R
2
% 1 _
7
R
3
7
2
4
R
1
% 1 _
8
R
3
3
2
1
R
1
3 7 B C
4 7 B C
VCC3
) 4 ( B _ D _
M
8 L A
3
4
B
B
_
_
Q
Q D
D
S
S
3 B
_ K L C D M C S
0 3 J A
B _ 3 P _
K L C _
2 1
)
)
)
7
6
5
(
(
(
B
B
B
_
_
_
D
D
D
_
_
_
M
M
M
1
2
2
1
1
1
K
G
F
A
A
A
6
5
B
B
_
_
Q
Q
D
D
S
S
DDR Channel B
­3 B _ K L C D
M C S
9
5
2
1
H
K
A
A
B _
3 N
_ K L C
_
R
R
D
D
D
D
2 1
)
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1 (
1 (
B
)
B
_
8
_
(
M
S
B
Q
Q
_
D
D
D
_
_
_
M
M
M
3
5
7
1
1
1 E
G
G
A
A
A
7
1
1
B
B
B
_
_
_
S
Q
M
Q
D
D
S
D
S
S
-
-
4
4
5
5
B
B
B
B
_
_
_
_
K
K
K
K
L
L
L
L
C
C
C
C
D
D
D
D
M
M
M
M
C
C
C
C
S
S
S
S
5
0
1
1
3
3
L
N
N
A
B
B
B
B
_
_
_
_
4
5
4
5
P
P
N
N
_
_
_
_
K
K
K
K
L
L
L
L
C
C
C
C
_
_
_
_
R
R
R
R
D
D
D
D
D
D
D
D
2
2
2
1
121
1
)
)
)
)
)
)
)
5
4
3
2
1
0
9
1
1
1
1
1
1
(
(
(
(
(
(
(
B
B
B
B
B
B
B
_
_
_
_
_
_
_
D
D
D
D
D
D
D
_
_
_
_
_
_
_
M
M
M
M
M
M
M 7
3
3
7
8
4
6
1
1
1
1
1
1
1
L
K
L
J
K
J
J
A
A
A
A
A
A
A
8
9
5
0
4
1
2
3
1
1
1
1
1
1
B
B
_
_
B
B
B
B
B
B
_
_
_
_
_
_
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
D
D
D
D
S
S
S
S
S
S
S
S
SDQS_B2
SDM_B2
SDQ_B16 SDQ_B17 SDQ_B18 SDQ_B19 SDQ_B20 SDQ_B21 SDQ_B22 SDQ_B23
SDQS_B3
SDM_B3
SDQ_B24 SDQ_B25 SDQ_B26 SDQ_B27 SDQ_B28 SDQ_B29 SDQ_B30 SDQ_B31
SDQS_B4
SDM_B4
SDQ_B32 SDQ_B33 SDQ_B34 SDQ_B35 SDQ_B36 SDQ_B37 SDQ_B38 SDQ_B39
SDQS_B5
SDM_B5
SDQ_B40 SDQ_B41 SDQ_B42 SDQ_B43 SDQ_B44 SDQ_B45 SDQ_B46 SDQ_B47
SDQS_B6
SDM_B6
SDQ_B48 SDQ_B49 SDQ_B50 SDQ_B51 SDQ_B52 SDQ_B53 SDQ_B54 SDQ_B55
SDQS_B7
SDM_B7
SDQ_B56 SDQ_B57 SDQ_B58 SDQ_B59 SDQ_B60
H
L
O
O
SDQ_B61
V
V
P
P
P
SDQ_B62
B
M
M
M
_
SDQ_B63
O
O
O
F E
C
C
C
R
R
R
R
V
Y
Y
Y
M
M
M
M
S
S
S
S
9
3
4
3
3
3
3
P
R
R
A
A
A
2 0 4 0
9 P C
AG21 AE21
AE19 AE20 AG23 AK23 AL19 AK21 AJ24 AE22
AH27 AJ28
AK25 AH26 AG27 AF27 AJ26 AJ27 AD25 AF28
AD29 AC31
AE30 AC27 AC30 Y29 AE31 AB29 AA26 AA27
U30 U31
AA30 W30 U27 T25 AA31 V29 U25 R27
L27 M29
P29 R30 K28 L30 R31 R26 P25 L32
J30 J31
K30 H29 F32 G33 N25 M25 J29 G32
SMYRCOMPVOL
SMYRCOMPVOH
SMYRCOMP
SMVREF_GMCH
M_DQS_B(2) M_DQM_B(2)
M_D_B(16) M_D_B(17) M_D_B(18) M_D_B(19) M_D_B(20) M_D_B(21) M_D_B(22) M_D_B(23)
M_DQS_B(3) M_DQM_B(3)
M_D_B(24) M_D_B(25) M_D_B(26) M_D_B(27) M_D_B(28) M_D_B(29) M_D_B(30) M_D_B(31)
M_DQS_B(4) M_DQM_B(4)
M_D_B(32) M_D_B(33) M_D_B(34) M_D_B(35) M_D_B(36) M_D_B(37) M_D_B(38) M_D_B(39)
M_DQS_B(5) M_DQM_B(5)
M_D_B(40) M_D_B(41) M_D_B(42) M_D_B(43) M_D_B(44) M_D_B(45) M_D_B(46) M_D_B(47)
M_DQS_B(6) M_DQM_B(6)
M_D_B(48) M_D_B(49) M_D_B(50) M_D_B(51) M_D_B(52) M_D_B(53) M_D_B(54) M_D_B(55)
M_DQS_B(7) M_DQM_B(7)
M_D_B(56) M_D_B(57) M_D_B(58) M_D_B(59) M_D_B(60) M_D_B(61) M_D_B(62) M_D_B(63)
VCC2.5_DDR
% 1 _
2
R
3
0
4
5
R
1
% 1 _
3
R
3
0
4
5 1
R
F
9 2
U 2
C
. 2
)
)
0 (
0 (
B
)
)
)
)
B
A
3
3 1
3
5
F
3
3
0
1
2
9
1
1
1
B
B
B
B
_
_
_
_
A
A
A
A
A
A
A
A
M
M
M
M
S
S
S
S
9
1
0
2
2
2 J
F
L
A
A
A
)
)
)
2
0
1
1
1
1
(
(
(
B
B
B
_
_
_
A
A
A
A
A
A
M
M
M
_
_
_ M
M
M
M_BS_B(0:1)
M_SCS_B-(0:3)
M_SCKE_B(0:3)
3
A
A
A
A
1
2
0
C
C
C
N
N
N
1
3
2
4
5
B
B
B
B
B
_
_
_
_
_
B
B
B
B
B
A
A
A
A
A
M
M
M
M
M
S
S
S
S
S
7
6
9
7
3
2
2
2
2
2
E
L
L
E
D
A
A
A
A
A
)
)
)
)
)
5
1
4
2
3
(
(
(
(
(
B
B
B
B
B
_
_
_
_
_
B
B
B
B
B
A
A
A
A
A
M
M
M
M
M
_
_
_
_
_
M
M
M
M
M
7 K 4
127R_1%
52R3_1%R228
U1
2 3 2 R
H3
DDCA_DATA
F2
DDCA_CLK
F4
RED
E4
RED-
H6
GREEN
G5
GREEN-
H7 G6
G3 E2
D2
R231
AF5 AG3 AK2 AG5 AK5 AL3 AL2 AL4
AJ2 AH2
AJ3 AH5 AH4 AD4 AE3 AE2
AK7 AH7
AD11
AF7 AD7
AC10
AF8 AG7 AE9 AH9 AG6
AJ6
AJ5
AG2
AF2
AF4
G4 AP8 AJ8
AK4
AG10
AG9 AN35 AP34
AR1
BLUE BLUE-
HSYNC VSYNC
REFSET
HI0 HI1 HI2 HI3 HI4 HI5 HI6 HI7 HI8 HI9 HI10 HISTRF HISTRS HI_RCOMP HI_SWING HI_VREF
CI0 CI1 CI2 CI3 CI4 CI5 CI6 CI7 CI8 CI9 CI10 CISTRF CISTRS
CI_RCOMP CI_SWING CI_VREF
DREFCLK EXTTS­ICH_SYNC­RSTIN-
RESERVED0 RESERVED1 RESERVED2 RESERVED3 RESERVED4
12,14
12,14 12,14 12,14
0 B _ A A M S
1
1
3
3 J
G
A
A
)
)
1
0
(
(
B
B
_
_
A
A
A
A
M
M
_
_ M
M
VGA PORT
Hub Interface
CSA Interface
1
2
3
4
B
B
B
B
_
_
_
_
A
A
A
A
A
A
A
A
M
M
M
M
S
S
S
S
5
7
4
7
2
2
2
2
E
G
D
K
A
A
A
A
)
)
)
)
3
4
5
2
(
(
(
(
B
B
B
B
_
_
_
_
A
A
A
A
A
A
A
A
M
M
M
M
_
_
_
_
M
M
M
M
M_MAB_B(1:5)
M_WE_B­M_CAS_B­M_RAS_B-
12,14
12,14
12,14
5
6
7
8
B
B
B
B
_
_
_
_
A
A
A
A
A
A
A
A
M
M
M
M
S
S
S
S
5
1
3
2
2
2
2
2 J
F
L
L
A
A
A
A
)
)
)
)
7
8
9
6
(
(
(
(
B
B
B
B
_
_
_
_
A
A
A
A
A
A
A
A
M
M
M
M
_
_
_
_
M
M
M
M
0 3
7
2
K
R
4
18
VGA_DDCSDA_3V
18
VGA_DDCSCL_3V
VGA_RED
18
18
VGA_GREEN
VGA_BLUE
18
B
C
VCC1.5V
18 18
VGA_HSYNC VGA_VSYNC
9
9 9
9,5 9,5
HI(0:10)
HI_STBF HI_STBS
HI_SWING HI_VEREF
HI(0) HI(1) HI(2) HI(3) HI(4) HI(5) HI(6) HI(7) HI(8) HI(9) HI(10)
D
VCC1.5V
R229 52R3_1%
T34
10
CI_SWING
5
CI_VREF
5
CLK_48M_DOTCLK
9
ICH_SYNC-
PCIRST-
25,8
E
M_MAA_B(0:12)
12,14
F
5
3
2
1
3
3
3
2
2
1
R
R
P
N
F
J
R
2
A
A
A
A
A
A
B
A
8
6
7
9
5
3
4
0 1
C
C
C
C
C
C
C
C
N
N
N
N
N
N
N
N
SPRINGDALE_2
-
-
-
0
1
B
B
B
_
_
B
B
_
S
_
S
_
E
A
A
A
A
W
R
B
C
B
S
S
S
S
S
7
6
6
5
1
5
2
2
2
2
3
2 A
U
Y
W
W
W
A
)
)
)
0
1
0
(
(
(
-
B
B
_
_
B
S
S
_ S
B
B
_
_
C S
M
M
_ M
5
3
4
5
6
3
2
1
3
2
2 E
C
C
C
B
B
6
5
4
3
2
1
1
1
1
1
1
1
C
C
C
C
C
C
N
N
N
N
N
N
0
-
-
-
­B
0
1
2
3
_
B
B
B
B
E
_
_
_
_
S
S
S
S
K
C
C
C
C
C
S
S
S
S
S
9
5
5
9
9
2
2
2
1
1 F
T
K
V
W
A
A
)
)
)
3
2
1
)
)
(
(
(
-
-
-
0
1
(
(
B
B
B
B
B
_
_
_
_
_
S
S
S
E
E
C
C
C
S
S
S
K
K
_
_
_
C
C
S
S
M
M
M
_
_
M
M
123
_
2
3
1
0
_
(
(
(
(
M
S
B
B
B
B
_
Q
Q
_
_
_
D
D
D
D
D
D
_
_
_
_
_
_
M
M
M
M
M
M
1
6
1
5
5
0
1
1
5
3
2
M
R
9
7
8
1
1
1
C
C
C
N
N
N
0 B _ K
1
2
3
L
B
B
B
C
_
_
_
D
E
E
E
M
K
K
K
C
C
C
C
S
S
S
S
9
0
9
8
2
3
1
1 E
G
G
G
A
A
A
A
B _ 0 P _
)
)
K
3
2
(
(
L
B
B
_
_
C
E
E
_
K
K
R
C
C
S
S
D
_
_
D
M
M
2 1
1
1
1
1
1
F
E
L
J
G
E
A
A
A
A
A
A
0
2
0
1
0
B
B
B
B
B
_
_
_
_
_
S
Q
Q
Q
M
Q
D
D
D
D
D
S
S
S
S
S
-
-
­2
2
1
0
1
B
B
B
B
B
_
_
_
_
_
K
K
K
K
K
L
L
L
L
L
C
C
C
C
C
D
D
D
D
D
M
M
M
M
M
C
C
C
C
C
S
S
S
S
S
6
7
7
7
2
2
1
1
F
G
N
N
A
A
B
B
B
B
B
_
_
_
_
_
0
2
2
1
1
P
P
N
N
N
_
_
_
_
_
K
K
K
K
K
L
L
L
L
L
C
C
C
C
C
_
_
_
_
_
R
R
R
R
R
D
D
D
D
D
D
D
D
D
D
2
2
2
2
2
1
1
1
1
1
45678
12,14
12,14
12,14
6,5
V_SMYRCOMPVO
% 1
9
_
3
9
2
K
R
0 3
%
0
1
4
_
2
K
R
0 1
6,5
V_SMYRCOMPVO
9,5
HI_SWING
HI_VEREF
6
V_SMYRCOMP
CI_SWING
CI_VREF
W.P. YU
W.P. YU
9,5
5
5
Universal Scientific Industri al
TITLE:
DDR Channel B,Hub-Link,VGA signals
REV:
2.2
2
2
0
0
5
4
4
0
0
7 B C
2
2
0
0
6
4
4
7
0
0
B C
ENGINEER:
DRAWN BY:
DATE CHANGED: SIZE:
JUN,28,2003
CHANGED BY:
R&D CHK:
QA CHK:
%
1
1
4
_
2
K
R
0 1
% 1
2
_
4
9
2
K
R
0 3
% 1
_ 2
3 4
R
2
2 4
R
% 1
_
4
2
4
R
2
2
R
4
Stiletto
GMCH
DRAWING NUMBER:
######
0 1 P C
4 2 P C
1 7 B C
2 1 P C
2 0 4 0
2 0 4 0
2 0 4 0
2 0 4 0
SMYRCOMPVOL
SMYRCOMPVOH
SMYRCOMP
PAGE
A
B
C
D
E
F
A3
305
OF
2 0
6
4 0
6 B C
V 6 1
3
_
1
F
E
U
C
0 0 1
9 3 E C
5 0 8
6
F
0
0
_
U
1
0
P
C
1
A C
Stiletto
GMCH
AGP signals
DRAWING NUMBER:
######
8
0 4 E C
8 6 B C
V 6 1 _ F U 0 0 1
2 0 4 0
5 3 2
VCCA_DAC_1.6V
VCCA_FSB_1.5V
V 6 1 _ F U 0 0 1
VCCA_SM_1.5V
2 0 4 0
VCCA_DPLL_1.5V
2 0 4 0
B C
7 6 B C
(1.7V)
A3
PAGE
630
OF
AA
B
C
D
E
F
6712345
V
1 1
0 D A G
3 R D D _ C C V
5
. 1 C C
V
Q48
2
)
)
1
2
(
(
D
D
A
A
_
_
G
G
5
C
D
A
A
1 D A G
4 R D D _ C C V
2
1
M
M
A
A
1
2N7002
3
Place close to
resistor circuit
G_ADSTB1-
G_ADSTB1
)
)
)
3
4
5
(
(
(
D
D
D
A
A
A
_
_
_
G
G
G
0 1
9
5
A
C
E
A
A
A
2
4
3
D
D
D
A
A
A
G
G
G
7
6
5
R
R
R
D
D
D
D
D
D
_
_
_
C
C
C
C
C
C
V
V
V
6
5
3
M
M
M
A
A
A
VCC2.5_DDR
R219 60R4_1%
% 1 _
1
2
2
R
2
9
R
3
R220 39R2_1%
2 0
2
4 0
6 B C
)
)
)
)
)
)
)
6
7
8
9
0
1
2
(
(
(
(
1
1
1
(
(
(
D
D
D
D
D
D
D
A
A
A
A
_
_
_
_
A
A
A
_
_
_
G
G
G
G
G
G
G 1
1
5
0
1
6
9
1
7
1
A
A
B
B
A
A
A
W
A
A
A
A
A
0
1
5
6
9
8
7
1
1
D
D
D
D
D
D
D
A
A
A
A
A
A
A
G
G
G
G
G
G
G
4
3
2
1
0
1
1
1
1
1
9
8
R
R
R
R
R
R
R
D
D
D
D
D
D
D
D
D
D
D
D
D
D
_
_
_
_
_
_
_
C
C
C
C
C
C
C
C
C
C
C
C
C
C
V
V
V
V
V
V
V
7
6
5
4
2
8
7
N
N
N
N
N
M
M
A
A
A
A
A
A
A
2
2
0
0
4
3
4
0
0
6
8
B
P
C
C
2 0 4 0
7 P C
)
)
)
3
4
5
1
1
1
(
(
(
D
D
D
A
A
A
_
_
_
G
G
G
6
9
7
5
4
W
V
W
V
V
2
5
4
3
1
1
1
1
1
1
S
F
D
D
D
D
B
B
T
T
A
A
A
A
S
S
G
G
G
G
D
D
A
A
G
G
5
0
1
8
9
6
7
1
2
2
1
1
1
1
R
R
R
R
R
R
R
D
D
D
D
D
D
D
D
D
D
D
D
D
D
_
_
_
_
_
_
_
C
C
C
C
C
C
C
C
C
C
C
C
C
C
V
V
V
V
V
V
V
5
6
7
8
5
3
4
1
P
P
P
P
P
N
R
A
A
A
A
A
A
A
F U
2 0
2
4
4
2
0
6
. 0
B C
4 5 C
34 8
G_SWING
Place within 0.25 in. of GMCH
% 1 _
2
R
2
0
2
0 1
R
G_SBA(0:7)
17
G_SBSTB-
17
G_SBSTB
17
)
)
)
)
)
)
6
7
1
1
(
(
D
D
A
A
_
_
G
G
2
4
A
Y
A
6 1 D A G
)
)
)
0
1
2
3
4
8
9
2
2
2
2
2
1
1
(
(
(
(
(
(
(
D
D
D
D
D
D
D
A
A
A
A
A
A
A
_
_
_
_
_
_
_
G
G
G
G
G
G
G
2
3
5
2
3
2
2
Y
W
Y
T
U
W
V
9
8
7
3
2
1
0
1
1
1
2
2
2
2
D
D
D
D
D
D
D
A
A
A
A
A
A
A
G
G
G
G
G
G
G
AGP Interface
SPRINGDALE_3
9
8
7
4
6
5
3
2
2
2
2
2
2
2
2
2
R
R
R
R
R
R
R
R
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
_
_
_
_
_
_
_
_
C
C
C
C
C
C
C
C C V
C
C
C
C
C
C
C
V
V
V
V
V
V
V
5
5
1
5
4
7
1
3
3
3
2
R
R
R
E
R
R
R
A
A
A
A
A
F U
F
7
U
4 .
2
0
2 . 0
5
6
5
5
C
C
VCC1.5V
3 2
AGPREF
)
)
)
5
6
7
2
2
2
(
(
(
D
D
D
A
A
A
_
_
_
G
G
G
2
5
4
R
T
T
7
6
5
4
2
2
2
2
D
D
D
D
A
A
A
A
G
G
G
G
0
1
C
C
A
A
D
D
_
_
C
C
C
C
V
V
2
1
G
G
VCC3
O V P M O C
R Y M S
_ V
5
17
G_C_BE(0:3)
17
)
)
)
)
0
1
3
2
(
(
(
(
E
E
E
E
B
B
B
B
_
_
_
_
C
C
C
C
_
_
_
_
G
G
G
0 1 C C V
7 L
2
1
1
1
C
C
C
C
V
V
0
9
1
L
M
VCC1.5V
G
3
4
5
2
6
4
B
A
7
U
U
H
A
A
W
Y
3
2
1
0
E
N I
E
E
E
E
M
B
B
B
B
K
A
L
C
C
C
C
R
C
G
G
G
G
F
G
G
8
7
6
5
4
3
1
1
C
C
C
C
V
V
1 1
M
1
0
9
1
1
1
1
2
2
1
C
C
C
C
C
C
C
C
C
C
C
C
C
C
V
V
V
V
V
V
V
1
0
9
8 M
1
1
0
9
1
1
1
1
1
N
M
P
P
R
N
N
)
)
)
)
)
)
)
)
3
1
0
4
2
5
6
7
(
(
(
(
(
(
(
(
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
S
S
S
S
S
S
S
S
_
_
_
_
_
_
_
_
G
G
G
G
G
G
G
)
)
)
)
8
9
0
1
2
2
3
3
(
(
(
(
D
D
D
D
A
A
A
A
_
_
_
_
G
G
G
G
1
1
2
1
6
1
2
5
4
P
M
P
P
T
U
R
0
1
8
9
S
F
3
3
2
2
B
B
D
D
D
D
T
T
S
S
A
A
A
A
D
D
G
G
G
G
A
A
G
G
0
1
2
L
R
C
R
R
P
L
B
D
A
P
D
D
G
S
D
D
D
D
A
F
D
_
_
_
_
_
_
_
A
A
A
A
A
A
A
C
C
C
C
C
C
C
C
C
C
C
C
C
C
V
V
V
V
V
V
V
1
3
5
5
6
4
2
1
2
2
2
B
B
C
C
B
C
Y
A
A
A
) V 7
. 1 (
V
V
5
V
.
6
V
.
5
1
.
5
1
_
.
1
_
1
L
_
_
C
L
B
A
P
S
M
F
S
D
D
_
_
_
_
A
A
A
A
C
C
C
C
C
C
C
C
V
V
V
V
G
0
5
1
9
3
5
7
7 P
R
T
U
U
U
R
-
-
-
-
-
-
-
-
2
0
1
7
6
5
4
3
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
S
S
S
S
S
S
S
S
G
G
G
G
G
G
G
G
0
1
2
3
4
9
8
6
7
5
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
V
V
V
V
V
V
V
V
V
V
6
7
8
9
J
J
J
J
6
6
1
0
8
9
7
1
1
L
K
K
K
K
L
L
2 R
% 1
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V
V
V
1
9
7
5
3
2
2
2
D
D
D
D
6
0
7
8
9
6
6
6
6
1
1
1
1
S
S
S
S
S
S
S
S
V
V
V
V
9
1
3
5
3
3
E
D
D
D
0
6
6
6
6
6
6
7
1
1
1
1
1
1
1
S
S
S
S
S
S
S
S
S
S
S
S
S
S
V
V
V
V
V
V
V
3
0
1
2
4
6
8
1
1
1
1
1
F
E
F
F
F
F
F
7
1
2
3
4
5
6
7
7
7
7
7
7
1
1
1
1
1
1
S
S
S
S
S
S
S
S
S
S
S
S
V
V
V
V
V
V
8
5
0
2
6
4
3
2
2
2
2
F
F
F
F
F
F
F
4
2
3
0
1
8
9
7
8
8
8
8
8
7
7 1 S S V
1
1
1
1
1
1
1
S
S
S
S
S
S
S
S
S
S
S
S
S
S
V
V
V
V
V
V
V
8
6
2
4
1
5
8
1
1
1
1
3
3
2
H
H
H
H
G
G
G
U1
3
1
2
9
0
7
8
5
6
3
D
C
D
VCC2.5_DDR
2
E
F
123 8
6
V
0
3
4
6
5
0
2
1
2
_
B
E
F
C
C
U 0 2 2
ENGINEER:
W.P. YU
DRAWN BY:
DATE CHANGED: SIZE:
JUN,28,2003
CHANGED BY:
R&D CHK:
QA CHK:
7456
Universal Scientific Industri al
W.P. YU
TITLE:
REV:
2.2
Stiletto
GMCH
power,ground
DRAWING NUMBER:
######
A3
PAGE
730
OF
E
F
AD(0:31)
C_BE-(0:3)
IDE_SDD(0:15)
IDE_SDIOW­IDE_SDDACK­IDE_SDDREQ­IDE_SDIOR­IDE_SIORDY
IDE_SDA2 IDE_SDA1 IDE_SDA0
IDE_SDCS3­IDE_SDCS1-
IRQ15
28,17,8 17,8 8 8
16,17,8 16,17,8 16,17,8 16,17,8
Stiletto
ICH5
IDE bus,PCI bus
DRAWING NUMBER:
######
8
28,16,17
28,16,17
19 19 19 19 19
19 19 19
19 19
19
19
A3
PAGE
830
OF
A
B
C
D
E
F
12
SB3V
8
1
1
B
E
2
_ 3 _ 3 S U S C C V
1 2 _ 5 _ 1 C C V
0
1 1
1
W
W
For EMI only.
VCC3
2 0
6
4 0
3 B C
0
3
2
1
7
4
1
9
1
2
2
1
D
D
G
G
A
A
W
W
1
8
4
7
6
5
_
1
1
1
1
1
_
_
_
_
_
3
3
3
3
3
3
_ 3
_
_
_
_
_
3
3
3
3
3
S
C
C
C
C
C
U S
C
C
C
C
C
C
V
V
V
V
V C V
3 _ 5
H
C I
0
9
8
5
4
7
6
2
1
1
1
1
1
1
_
_
_
_
_
_
_
5
5
5
5
5
5
5
_
_
_
_
_
_
_
1
1
1
1
1
1
1
C
C
C
C
C
C
C
C
C
C
C
C
C
C
V
V
V
V
V
V
V
9
2
5
4
5
3
9
1
1
2
1
1
1
W
F
F
E
R
N
W
C105 X
CAP_0402
VCC5
SB5V
A
2 0
0
4
3
0
B C
VBAT
SB5V
2 0
2
4 0
3 B C
1
4
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59
1
6
1
D
1
W
A
E
2
S
C
F
T
U
E
S
R
_
R
C
5
F
C
E
V
V
R 5 V
6 _
3
2
1
5
_
_
_
_
D
O
O
O
1
I
I
I
V
S
_
_
_
S
U
U
U
U
R
S
P
P
P
_
C
S
C
C
C
_
_
C
S
_
V
V
V
V
V
9
9
5
1
8
1
1
1
F
A
T
R
R
B
A10 A15 A17 A19 A21 A23
A7 AA11 AA13 AA21 AA24
AA5 AA7 AA9
C
D
E
AB11 AB15 AB18
AB5 AB7
AB9 AC10 AC13
AC2 AC23
AC4
AC6
AC8 AD17 AD21 AD12
AD4
AD6
AD8
B13 B17 B19 B21 B23 C16 C18 C20 C22
C3 C8
D1 D11 D16 D18 D20 D22 D24
D6
F9
F3 E23 E21 E20 E19 E17
VCORE
3
VCORE
3 B
F
2 0
1
4
3
0
B
C
C
SB1.5V
VCC3
7 5 1
K
2
R
1
D8 BAT54C
4
F
1
3
U
M
1
F
C
E R V 5 _ H C
I
5
6
8
7
8
6
1
1
1
1
A
F
V
K
F
F
1
0
3
2
1
1
1
1
1
F
_
_
_
_
E
3
3
3
3
R
_
_
_
_
5
3
3
3
3
S
S
S
S
V
U
U
U
U
S
S
S
S
C
C
C
C
C
C
C
C
V
V
V
V
1
2
3
4
5
_
_
_
_
_
5
5
5
5
5
_
_
_
_
_
1
1
1
1
1
S
S
S
S
S
U
U
U
U
U
S
S
S
S
S
C
C
C
C
C
C
C
C
C
C
V
V
V
V
V
5
9
4
4
7
2
1
F
B
A
Y
F
A
A
2
2
2
0
0
0
4
4
4
0
0
0
4
5
3
3
B
B
C
C
5
4
3
1
0
1
6
1
1
1
1
1
U
E
F
E
F
E
9
8
7
6
5
4
3
_
_
_
_
_
_
_
3
3
3
3
3
3
3
_
_
_
_
_
_
_
3
3
3
3
3
3
3
S
S
S
S
S
S
S
U
U
U
U
U
U
U
S
S
S
S
S
S
S
C
C
C
C
C
C
C
C
C
C
C
C
C
C
V
V
V
V
V
V
V
2
1
L
L
L
L
L
P
P
L
5
4
3
2
2
2
2
2
P
A
A
_
_
_
_
B
T
T
5
5
5
5
S
A
A
_
_
_
_
U
S
S
1
1
1
1
C
C
C
C
C
C
C
C
C
C
C
C
C
C
V
V
V
V
V
V
V
4
6
6
8
7
6
2
2
B
A
W
W
W
E
C
A
A
VCC1.5V
1
2
34
567
SB3V
U16
28,16,17
P_FRAME-
28,16,17
P_IRDY-
28,16,17
2
2
0
0
0
1
4
4
4
4
0
2
2
2
0
0
0
9
7
8
4
4
4
0
0
0
3
3
3
B
B
B
C
C
C
0
B
B
C
C
VCC3
5
0
0
9
3
1
1
1
6
1
6
1
1
6 P
N
W
V
R
9
3
2
1
0
_
1
1
1
1
3
_
_
_
_
_
3
3
3
3
3
_
_
_
_
3
3
3
3
C
C
C
C
C
C
C
C
C
C
V
V
V
V
V
1
0
3
2
1
1
9
1
1
_
_
_
_
_
5
5
5
5
5
_
_
_
_
_
1
1
1
1
1
C
C
C
C
C
C
C
C
C
C
V
V
V
V
V
9
9
4
5
5
1
1
1
1
2
J
K
N
H
M
0.1UF
5
6
6 F
H
G
L
K
M
8
3
4
5
6
7
_
_
_
_
_
_
3
3
3
3
3
3
_
_
_
_
_
_
3
3
3
3
3
3
C
C
C
C
C
C
C
C
C
C
C
C
V
V
V
V
V
V
8
3
2
6
7
5
4
_
_
_
_
_
_
5
5
5
5
5
5
_
_
_
_
_
_
1
1
1
1
1
1
C
C
C
C
C
C
C
C
C
C
C
C
V
V
V
V
V
V
9
3
6
2
0
9
1
1
1
1
1
R
P
L
R
K
K
VCC1.5V
6
B
1
2
1
U
_
_
3
3
_
_
3
3
G20
C
C
VSS60
C
C
G24
VSS61
V
V
G6
VSS62
H1
VSS63
H19
VSS64
H22
VSS65
J21
VSS66
J23
VSS67
J6
VSS68
K11
VSS69
K14
VSS70
K20
VSS71
K22
VSS72
K24
VSS73
K3
VSS74
L10
VSS75
L11
VSS76
L12
VSS77
L13
VSS78
L14
VSS79
L15
VSS80
L21
VSS81
L23
VSS82
M1
VSS83
M11
VSS84
M12
VSS85
M13
VSS86
M14
VSS87
M22
VSS88
M24
VSS89
M5
VSS90
N11
VSS91
N12
VSS92
N13
VSS93
N14
VSS94
N20
VSS95
P1
VSS96
P10
VSS97
P11
VSS98
P12
VSS99
P13
VSS100
P14
VSS101
P15
VSS102
P21
VSS103
R11
VSS104
R14
VSS105
T23
VSS106
T3
VSS107
T6
VSS108
U19
VSS109
V1
VSS110
V21
VSS111
W16
VSS112
W18
VSS113
Y10
VSS114
Y3
VSS115
Y6
VSS116
Y7
1
VSS117
_
_
Y8
5
5
VSS118
_
_
1
1
C
C
C
C
V
V
0 1 K
VCC1.5V
2 0
2
4 0
4 B C
2
2
0
0
3
4
4
4
0
0
4
4
B
B
C
C
19,8 19,8
28,16,17 28,16,17 28,16,17 28,16,17
16,17 28,16,17 28,16,17
25,5
CLK_33M_ICH
10
28,17,8
17,8
8
8 16,17,8 16,17,8 16,17,8 16,17,8
16,8
8 17,8 28,8 16,8
PRI_FASTCABLE-
SEC_FASTCABLE-
16
17 28 16
IDE_PDD(0:15)
19
19
IDE_PDIOW-
19
IDE_PDDACK-
19
IDE_PDDREQ-
19
IDE_PDIOR-
19
IDE_PIORDY
19 19 19
19
IDE_PDCS3-
19
IDE_PDCS1-
19
P_TRDY-
P_DEVSEL-
P_STOP-
P_PAR P_PERR­P_LOCK­P_SERR-
P_PME-
PCIRST-
PCI_INTA­PCI_INTB­PCI_INTC­PCI_INTD­PCI_INTE-
PCI_INTF­PCI_INTG­PCI_INTH-
P_REQ0­P_REQ1­P_REQ2­P_REQ3­P_REQ4-
P_GNT0-
P_GNT2­P_GNT3­P_GNT4-
IDE_PDA2 IDE_PDA1 IDE_PDA0
IRQ14
VCC5
T20
T18 T19
IDE_PDD(15) IDE_PDD(14) IDE_PDD(13) IDE_PDD(12) IDE_PDD(11) IDE_PDD(10) IDE_PDD(9) IDE_PDD(8) IDE_PDD(7) IDE_PDD(6) IDE_PDD(5) IDE_PDD(4) IDE_PDD(3) IDE_PDD(2) IDE_PDD(1) IDE_PDD(0)
56
2K7 8P4R RN878
4
2K7 8P4R RN83
12
R158
R160
D2
FRAME-
M3
IRDY-
E4
TRDY-
L3
DEVSEL-
E5
STOP-
F1
PAR
K2
PERR-
L2
PLOCK-
L4
SERR-
V2
PME-
V4
PCIRST-
N1
PCICLK
B3
PIRQA-
E1
PIRQB-
A2
PIRQC-
C2
PIRQD-
D7
PIRQE-_GPI2
A6 E2 B1
D5 C1 C5 B6 C6 A5 E7
D4 A3 B7 C7 A4 E8 B4
AB17 AA16
Y16 AC16 AA15 AD16
Y15 AD15 AB14 AD14 AC15 AA14 AC14
Y14
Y13 AB16
AA17 AC18 AC17 AD18 AA18
AC19 AD19 AA19
Y18 AB19
Y17
PCI Interface
PIRQF-_GPI3 PIRQG-_GPI4 PIRQH-_GPI5
REQ0­REQ1­REQ2­REQ3­REQ4-_GPO40 REQA-_GPI0 REQB-_REQ5-_GPI1
GNT0­GNT1­GNT2­GNT3­GNT4-_GPO48 GNTA-_GPO16 GNTB-_GNT5-_GPO17
PDD15 PDD14 PDD13 PDD12 PDD11 PDD10 PDD9 PDD8 PDD7 PDD6 PDD5 PDD4 PDD3 PDD2
I D
E
PDD1
I n
PDD0
t e r f a c
PDIOW-
e ( P
PDDACK-
r i m
PDDREQ
a r
PDIOR-
y )
PIORDY
PDA2 PDA1 PDA0
PDCS3­PDCS1-
IRQ14 IRQ15
) y r a d n o c e S ( e c a f r e t n I
E D
I
ICH5_1
VCC3
8K2 8P4R RN1056
34
8K2 8P4R RN9
8K2 8P4R RN1012 8K2 8P4R RN956
RN88P4R2K7
RN88P4R2K7
2K7 10KR159 10K
P_REQ0-
16,8 8
P_REQ1­P_REQ2-
17,8
P_REQ3-
28,8
P_REQ4-
16,8 PRI_FASTCABLE­SEC_FASTCABLE-
19,8
19,8
VCC3
345678
AD(31)
P2
AD31
AD(30)
F4
AD30
AD(29)
P4
AD29
AD(28)
F5
AD28
AD(27)
N2
AD27
AD(26)
D3
AD26
AD(25)
P3
AD25
AD(24)
E6
AD24
AD(23)
N4
AD23
AD(22)
C4
AD22
AD(21)
N5
AD21
AD(20)
H3
AD20
AD(19)
P5
AD19
AD(18)
B2
AD18
AD(17)
L1
AD17
AD(16)
G4
AD16
AD(15)
G5
AD15
K1
AD(14)
AD14
G2
AD(13)
AD13
L5
AD(12)
AD12
H4
AD(11)
AD11
M4
AD(10)
AD10
AD(9)
F2
AD9
AD(8)
K5
AD8
AD(7)
J2
AD7
AD(6)
J3
AD6
AD(5)
H2
AD5
AD(4)
H5
AD4
AD(3)
K4
AD3
AD(2)
G3
AD2
J5
AD(1)
AD1
J4
AD(0)
AD0
C_BE-(3)
M2
C_BE3-
C_BE-(2)
N3
C_BE2-
C_BE-(1)
J1
C_BE1-
C_BE-(0)
E3
C_BE0-
AA23 AB24 AC24 AB22 AA20 AC22 AD22 Y19 AC20 AB20 AC21 AB21 AD24 AD23 AB23 AA22
Y22 W20 Y20 Y23 Y21
W21 W23 W22
V20 V22
Y24
RN98P4R8K2 7 8 RN108P4R8K2 7 8
RN108P4R8K2 3 4
RN98P4R8K2 1 2
JUN,28,2003
IDE_SDD(15) IDE_SDD(14) IDE_SDD(13) IDE_SDD(12) IDE_SDD(11) IDE_SDD(10)
IDE_SDD(9) IDE_SDD(8) IDE_SDD(7) IDE_SDD(6) IDE_SDD(5) IDE_SDD(4) IDE_SDD(3) IDE_SDD(2) IDE_SDD(1) IDE_SDD(0)
PCI_INTA­PCI_INTB­PCI_INTC­PCI_INTD-
PCI_INTE­PCI_INTF­PCI_INTG­PCI_INTH-
W.P. YU
Universal Scientific Industri al
W.P. YU
TITLE:
REV:
2.2
SDD15­SDD14­SDD13­SDD12­SDD11­SDD10-
SDD9­SDD8­SDD7­SDD6­SDD5­SDD4­SDD3­SDD2­SDD1­SDD0-
SDIOW-
SDDACK-
SDDREQ
SDIOR-
SIORDY
SDA2 SDA1 SDA0
SDCS3­SDCS1-
ENGINEER:
DRAWN BY:
DATE CHANGED: SIZE:
CHANGED BY:
R&D CHK:
QA CHK:
12 6
3 7
4
5
8
U16
A20GATE
20
2
24,17,20
2,20,9
2,9
2,9
20
2
2
2 2
2
H_A20M-
H_SLP-
H_FERR-
H_IGNNE-
H_INIT­H_INTR
H_NMI
KBREST
SERIRQ
H_SMI-
H_STPCLK-
A
B
10 10
VBAT
6 1 1
K 0
R
8
C
1
2 0
4
4 0
2 B C
VCC1.5V
D
5
HI_SWING HI_VEREF
5
28
LAN_PWRGD-
2 0
5
6
4 0
2
2
B
B
C
C
E
NOPOP
D19 X_4148
5
ICH_SYNC-
F
PWR_GD
25,4,9
21
21
X_4148 D20
R215 0R
RN4
78
RN3
RN3 X56
RN4 X5
RN4 X12
24
SATA0TXP
24
SATA0TXN
24
SATA0RXN
24
SATA0RXP
24
SATA1TXP
24
SATA1TXN
24
SATA1RXN
24
SATA1RXP
CLK_100M_ICH
CLK_100M_ICH-
L_AD(0:3)
24,20,9
24,20,9
L_FRAME-
24,20
L_DRQ0-
RTX1
9
RTX2
9
RSMRST-
28,25,9
9
ICH_PWR_GD
HI(0:10)
5
R122 62R
5
HI_STBF
5
HI_STBS
52R3_1%
R120
10
CLK_66M_ICH
2 0 4 0
28
LAN_RXD0
28
LAN_RXD1 LAN_RXD2
28 28
LAN_TXD0
28
LAN_TXD1 LAN_TXD2
28
LAN_RSTSYNC
28
LAN_CLK
28
0R
R118
9 1
K
1
X
0
R
K 1
X
22
22 22,9 22,9
9 9
22,9
1
AC_SYNC
AC_RST-
AC_SDOUT
AC_SDIN0 AC_SDIN1 AC_SDIN2
AC_BITCLK
ICH_PWR_GD
CLEAR_CMOS-
9
LAN of ICH5 Disable
VCC3
6 3 3 R
4 6 2
R121 24R9_1%
X34 X
XRN3 3
XRN3 1
T11
EE_SHCLK
EE_DOUT
1 45
T22
A20GATE
V23
A20M-
P22
CPUSLP-
U24
FERR-
R21
IGNNE-
R23
INIT-
U23
CPU Interface
INTR
R22
NMI
P23
RCIN-
F23
SERIRQ
V24
AA10 AB10
AC11 AB12 AA12 AB13 AC12
T24
P20 R24
AA8 AB8 AD7 AC7
AD9 AC9
Y11
Y9
AC5 AD5
T5 R4 R3 U4
T4 U5 R2
H20 H21
J20
H23 M23 M21 N21 M20
L22
J22
K21 G22
K23
J24
N24
L20 L24
N22
C10
C9
C11
D9
E9
B12
D10
E10
AA1
B11 B10
A12
B9
B8
C12
A9
E12 D12 A13
D8
SMI­STPCLK-
DPRSLPVR DPSLP-
SATA0T_P SATA0T_N SATA0R_N SATA0R_P
SATA1T_P SATA1T_N SATA1R_N SATA1R_P
SATARBIASP SATARBIASN
CLK100P CLK100N
LAD0 LAD1 LAD2 LAD3 LFRAME­LDRQ0­LDRQ1-_GPI41
RTC_1 RTC_2 RTCRST­RSMRST­PWROK
HI0 HI1 HI2 HI3 HI4 HI5 HI6 HI7 HI8 HI9 HI10 HI11
HI_STBF HI_STBS HIRCOMP HI_VSWING HIREF CLK66
LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 LAN_RSTSYNC LAN_CLK LAN_RST-
EE_DIN EE_CS EE_SHCLK EE_DOUT
AC_SYNC AC_RST­AC_SDOUT AC_SDIN0 AC_SDIN1 AC_SDIN2 AC_BIT_CLK
S-ATA
LPC
Hub Link
LAN
AC97
XRN4 7 8
T9
T10
L_AD(0) L_AD(1) L_AD(2) L_AD(3)
HI(0) HI(1) HI(2) HI(3) HI(4) HI(5) HI(6) HI(7) HI(8) HI(9) HI(10)
EE_DIN
EE_CS
GPIO
SMBus
USB
AGPBUSY-_GPI6
SMBALERT-_GPI11
STP_CPU-_GPO20 C3_STAT-_GPO21
CPUPERF-_GPO22
SSMUXSEL_GPO23
CLKRUN-_GPIO24
VGATE_VRMPWRGD
CPUPWRGD_GPO49
ICH5_2
VCC3
9
2
R117
10K
2-3 :CLEAR CMOS
JP7
1
NC
2
CLEAR
3
GND
CLEAR-CMOS_3X1
RN5 X 8K234
RN5 X 8K278
3 8
GPI7 GPI8
GPI12 GPI13
STP_PCI_GPO18
SLP_S1-_GPO19
GPIO25 GPIO27 GPIO28 GPIO32 GPIO33 GPIO34
SMBCLK
SMBDATA
SMLINK0 SMLINK1
LINKALERT-
SPKR
RI-
PWRBTN-
SUSCLK
BATLOW-
SUS_STAT-
SLP_S3­SLP_S4­SLP_S5-
SYS_RESET-
THRMTRIP-
THRM-
INTVRMEN
CLK14
INTRUDER-
NC
USBP0P USBP0N USBP1P USBP1N USBP2P USBP2N USBP3P USBP3N USBP4P USBP4N USBP5P USBP5N USBP6P USBP6N USBP7P USBP7N
OC0­OC1­OC2­OC3-
OC4-_GPIO9 OC5-_GPIO10 OC6-_GPIO14 OC7-_GPIO15
USBRBIAS
USBRBIAS-
CLK48
R123 10K R124
22K 10KR125
R5 U3 Y2 AC3 W4 W5 U21 T20 U22 R1 U20 F22 AC1 W3 V3 W2 T1 G23 F21
AD2 AD1 AD3 AA2 V5
E24 AB3 Y4 Y1 AB2 AB1 W1 U2 AA3 U1 R20 P24 T21 T2 AD10 F20 Y12
A11
C23 D23 A22 B22 C21 D21 A20 B20 C19 D19 A18 B18 C17 D17 A16 B16
C15 D15 D14 C14 B14 A14 D13 C13
A24 B24
F24
XRN5 8K256
XRN5 8K212
RN6 8K27
RN6
T17
R126
X
330K R127
1M
T13 T14
T15 T16
R128
22R6_1%
PWR_GD
RSMRST­AC_BITCLK AC_SDIN0 AC_SDIN1 AC_SDIN2 AC_SDOUT
POV_ID0­POV_ID1­SIO_WAKE-
INTRUDER­USB_P0 USB_P0­USB_P1 USB_P1­USB_P2 USB_P2­USB_P3 USB_P3­USB_P4 USB_P4­USB_P5 USB_P5­USB_P6 USB_P6­USB_P7 USB_P7-
USB_ICH_OC1-
USB_ICH_OC2-
USB_ICH_OC3-
BRD_ID2
2ND_SERIAL-
R129
CLK_48M_USB
24,9 24,9 20,9
TEMP_THERM-
BRD_ID0 BRD_ID1
C2_BLOCK_RESET­C2_BLOCK_SET-
AFP_PRES­POWER_LED­POV_BLOCK_RST­ENET_DISABLE­CLEAR_CMOS-
SATA_LED-
FRONT_USB­SMB_CLK_STBY SMB_DATA_STBY
4
8K2RN6 3
8
8K2RN6 1 2
SPKR
WOR­SW_ON­SUSCLK
8K256
LPCPD-
SLP_S3-
SLP_S4-
DBRESET-
VRMPWRGD
H_PWRGD THERMTRIP_ICH­THRM-
CLK_14M_ICH
R357X
330K
24 19 19 19 19 19 19 19 19 23 23 23 23 23 23 23 23
9
25,4,9 28,25,9 22,9 22,9 9 9 22,9
19
23
23
21,9
10
V 3 B S
9 9
22 25 24 28 9 19
23,9 28,24,16,17,23 28,24,16,17,23
V 3 B
22
S
21,9 25 20
24 25,4 26,25
24,25,2,9 28,26,27 2
3,9
9
20,9 9 9
VBAT
6 2 C
3,9
10
F P 8 1
4,2
THERMTRIP_ICH-
C2_BLOCK_RESET-
9
9
EE_DOUT
EE_DIN
EE_SHCLK
EE_CS
1
D N G
2
R130 10M
2 0 4
F
0
7
_
P
2
8
P
C
1
A C
E R O C V
H_PROCHOT-
H_SMI-
2,20,9
C2_BLOCK_SET-
Flash Write-Protect Latch
U17
93C46
RTX1
X1
32.768KHZ
RTX2
2 0 4 0 _ P A C
VCC3
SB3V
POV_ID0-
24,9
POV_ID1-
21,9
23,9
24,25,2,9
20,9
3,9
GPIO4 : Pullup for 10/100 Etherent. GPIO4 : Pulldown for gigabit Etherent.
2 4 1
K
R
1
R137
1K
R138
1K
1KR139
VCC3
1 4 1 R
7 K 4
1
3
24,9
SIO_WAKE-
20,9 21,9
2ND_SERIAL­FRONT_USB-
DBRESET-
TEMP_THERM-
9
2,9
THERMTRIP_ICH-
X
U19
3 4
1
1 R
12 11 10
9
6 5 4 3
30
8 7
2 24 31 29
4 4 1
FWH_32
R 7
K 4
H_INIT-
THRM-
H_FERR-
VPP
ID0 ID1 ID2 ID3
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4
TBL# WP#
RST# INIT# CLK IC
9
Q41
3904 R131 4K7
Q40
1
2
3
C28 X
1500PF
CAP_0402
2 3
K
1
0
R
1
1
2
2N7002
3
THRM-
VCC3
Q43
3904
R135 4K7
2
4 3
K
1
0
R
1
1
Q42
2
2N7002
3
25
10
R140 X
PRST_FWH-
CLK_33M_FWH
SB3V
VCORE
8
VCC
3
EEDI
7
4
NC2
EEDO
2
6
EESK
NC1
1
EECS
GND
2 0
7
4
2
0
B
5
C
ONLY FOR Kinnereth-R
6 3 1 R
Q44
7
3904
K 4
2
9
9
VBAT
9
9
3
F
9
U18 BATTERY
R133 3K
1
U
M
1
C
ENGINEER:
SB3V
1
3
2
BAT54C D7
W.P. YU
DRAWN BY:
W.P. YU
DATE CHANGED: SIZE:
JUN,28,2003
CHANGED BY:
R&D CHK:
QA CHK:
67
RN7 8K256
RN7 8K278
WOR-
R145 4K7
R148
R149
R150
32
VCC1
25
VCC2
27
VCCA
13
FWH0
14
FWH1
15
FWH2
17
FWH3
23
FWH4
18
RFU0
19
RFU1
20
RFU2
21
RFU3
22
RFU4
28
GNDA
26
GND1
16
GND2
2,9
Stiletto ID : 000 Shadow ID : 001
BRD_ID0
BRD_ID1
BRD_ID2
Universal Scientific Industri al
TITLE:
AC97,LAN,Hub interface,USB,FWH
REV:
2.2
2
4K7R305
10KR146 10K
4K7R147
VCC3
L_AD(0) L_AD(1) L_AD(2) L_AD(3)
Stiletto
ICH5
DRAWING NUMBER:
######
8K2RN7 3 4
8K2RN7 1
62R
62R
2 0
8
9
4 0
2
2
B
B
C
C
R152
R153 X
R156
2 0 4 0
L_AD(0:3)
L_FRAME-
XR151
4K7
4K7R154
XR155
4K7
VCORE
24,20,9
24,20,9
SB3V
930
PAGE
A
B
C
D
E
F
A3
OF
123456
78
VCC3
VCC3
Z
VCC3_CLK
H_FSB
H_FSA
CLK_100M_ICH
R183 X
R186 0R
F
0 3
U
7
C
. 4
15PF
CAP_0402
15PF
H M
0 0 1 _ R
9
1 3
L _ B F
VCC3_CLK
2
2
2
0
0
0
8
0
9
4
4
4
4
5
4
0
0
0
B
B
B
C
C
C
3
FB_31R_100MHZ
C C V
2 8 1
K 1
R
X2
C31
14.318MHZ
GND
3
C32
CAP_0402
0RR 184 XR185
L10 1
7 8 1
K 1
R
12,11,23 12,11,23
1
2
%
%
%
%
1
1
1
1
_
_
_
_
9
9
9
9
R
R
R
R
9
9
9
9
4
4
4
4
1
9
0
8
9
8
9
8
1
1
1
1
R
R
R
R
2 0
1
4
5
0
B C
3 3 C
SMB_DATA
VCC3_CLK
CLK_XTAL_IN CLK_XTAL_OUT
%
%
%
1
1
1
_
_
_
9
9
9
R
R
R
9
9
9
4
4
4
3
2
4
9
9
9
1
1
1
R
R
R
FB_31R_100MHZ
2
2
0
0
3
2
4
4
5
5
0
0
B
B
C
C
2 0
4
4
F
5
0
U
B 7 .
C 4
SMB_CLK
R196
R197
R199 33R R200 R201 R202 33R
R204 R205
% 1 _ 9 R 9 4
5 9 1 R
1K
L11
5 5 B C
475R_1%
1
2 0
6
4
F
0
4
5
3
U
B
7
C
.
C
2 0 4 0
A D D V _ K L C
33RR198
33R 33R
33RR203 33R 33R
4
8 4 D D V _ K
U20
L C
3 10 16 48 42 36 24 55 34
56 51
30 28
35
52 53
50 49
21
4
5
38 37 46 47 43 44 40 41
54
6 11 17 45 39 25 33
VDD1 VDD2 VDD3 VDD4 VDD5 VDD_SRC VDD_66 VDD_A VDD48
FSB FSA
SDATA SCLK
VTT_PWRGD-
IREF VSS_IREF
CPU_STOP­PCI_STOP-
PWRDWN-
XTAL_IN XTAL_OUT
SRC SRC­CPU2­CPU2 CPU1­CPU1 CPU0­CPU0
VSS_A VSS1 VSS2 VSS3 VSS4 VSS_SRC VSS_66 VSS48
PCIF_1
PCIF_0
PCIF_2
3V66_0
3V66_1
3V66_2
3V66_3
3V66_4_VCH
DOT_48MHZ
USB_48MHZ
PCI_6
PCI_5
PCI_4
PCI_3
PCI_2
PCI_1
PCI_0
2
REF0
1
REF1
20
19
18
15
14
13
12
8
7
9
22
23
26
27
29
32
31
R207 22R
R208
33R 8P4R RN1112
33R 8P4R RN1156
33R 8P4R RN1212
33R 8P4R RN1278
R209
R210
R211
R213 33R
33RR206
22R
RN118P4R33R 3 4
RN118P4R33R 7 8
RN128P4R33R 5
6
RN128P4R33R 3 4
33R
33R
33R
33RR212
CLK_14M_ICH
CLK_14M_SIO
CLK_14M_CODEC
CLK_33M_LAN
CLK_33M_FWH
CLK_33M_SIO
CLK_33M_ICH
CLK_33M_POV3
PCICLK1
PCICLK0
PCICLK2
CLK_66M_GMCH
CLK_66M_AGP
CLK_66M_ICH
CLK_48M_DOTCLK
CLK_48M_USB
9,10
20,10
22,10
28,10
9,10
20,10
8,10
24,10
16,10
17,10
16,10
6,10
17,10
9,10
5,10
9,10
A
B
C
D
ICS952601
XC36
24,10
22,10
20,10
20,10
16,10
17,10
16,10
17,10
28,10
9,10
9,10
8,10
6,10
9,10
5,10
9,10
CLK_33M_POV3
CLK_14M_CODEC
CLK_14M_ICH
CLK_14M_SIO
CLK_33M_SIO
CLK_33M_FWH
CLK_33M_ICH
PCICLK1
PCICLK0
PCICLK2
CLK_66M_GMCH
CLK_66M_ICH
CLK_66M_AGP
CLK_33M_LAN
CLK_48M_DOTCLK
CLK_48M_USB
C37 X
C39
C42
C44 X
C46 X
C47 X
C49 X
C51 X
XC38
X
XC40
XC41
X
XC43
XC45
XC48
XC50
CAP_0402
10PF
10PF
10PF
10PF
10PF
10PF
10PF
10PF
10PF
10PF
10PF
10PF
10PF
10PF
10PF
10PF
ENGINEER:
W.P. YU
DRAWN BY:
DATE CHANGED: SIZE:
JUN,28,2003
CHANGED BY:
R&D CHK:
QA CHK:
Universal Scientific Industri al
W.P. YU
TITLE:
REV:
2.2
Stiletto
CLOCK
DRAWING NUMBER:
######
PAGE
E
F
A3
3010
OF
A
B
VCC3_CLK
VCORE
0 8
K
1
0
R
9
R
7
0
1
2
R
2
1
Q45 3904
2
4,2 4,2
1
1 8 1 R
X
3
C
9 9
CLK_100M_ICH-
4
CLK_HOST_GMCH-
4
CLK_HOST_GMCH
2
CLK_HOST_CPU-
2
CLK_HOST_CPU
2
CLK_HOST_CPU_ITP-
2
D
E
2
CLK_HOST_CPU_ITP
2
CLK_HOST_ITP-
CLK_HOST_ITP
CLOCK SELSETION :
FSA FSB Frequenc y
0 0 100MHZ
1 0 133MHZ
1 1 166MHZ
0 1 200MHZ
F
12345678
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