Gigabyte Jamaica Schematic REV.3.1

1

2

34

5

6

7

8

A

Jamaica Schematics

CONTENTS

B

PAGE 1 TITLE PAGE 2 SYSTEM BLOCK DIAGRAM PAGE 3,4,5 LGA775 SOCKET

PAGE 6,7,8,9 INTEL LAKEPORT PAGE 10 DDR2 CHANNEL A DIMM X 2

PAGE 11 DDR2 CHANNEL B DIMM X 2 PAGE 12 DDR2 TERMINATION RESISTORS

C

PAGE 13 DDR2 DECOUPLING CAPACITORS PAGE 14 VGA CONNECTOR

PAGE 15,16,17 ICH7 PAGE 18 CLOCK GENERATOR

PAGE 19 SIO(PC8375T/PC8375S) PAGE 20 PARALLEL & SERIAL PORTS PAGE 21 FAN X 3,S-ATA2 PAGE 22 IDE,K/B,MOUSE CONNECTORS AND REAR USB PORTS X 4

D

PAGE 23 AC97/AZALIA CODEC(AD1981B/AD1981HD) & MONO AMP PAGE 24 AUDIO CONNECTOR,REAR USB PORTS X 2 & AFPIO PAGE 25 LAN TEKOA (10/100/1000Mbps)

PAGE 26 SYSTEM POWER PAGE 27 CPU PWM

PAGE 28 PCI-EXP X 1 SLOT & PCI-EXP X 16 SLOT PAGE 29 PCI SLOTS X 2

E

PAGE 30 CHANGED HISTORY

B

C

D

E

R

USI

F

1

2

REV : 3.1

3

45

6

Universal Scientific Industrial Co.,Ltd.

TITLE:

Document Number:

Prepared by:

A3

XXXXXXXX

I.J. Shen

7

Jamaica

TITLE

Date:

2005/4/12

REV:

3.1

PAGE:SIZE:

OF

301

8

F

1

2 8

3

4

5

6

7

A

LGA775

Processor

(Smithfield)

(Prescott)

CPU CORE

B

C

D

PWM

P27

SYSTEM

POWER

P26

ATX Connector

P19,21

PCI Express X 16 SLOT

SDVO

P28

VGA CONNECTOR

P14

1 IDE Connector

ATA66/ATA100

P22

4 Serial ATA2

3Gb/s

P25

PCI-EXP Bus

R,G,B

LPC Bus(33MHZ)

Super I/O

Fan x 3

P21

NS PC8375T NS PC8375S

P19

(Cedar Mill)

P3,4,5

Intel Lakeport

P6,7,8,9

P15,16,17

FWH 8M

FSB (533/800/1066MHz)

GMCH

DMI(100MHZ)

Intel ICH7

DDR2 533/667 MHz

PCI -EXP X 1(100MHZ)

33MHZ

PCI -EXP X 1(100MHZ)

AC97/Azalia Link

USB 2.0

CLOCK

Generator

CK-410

P18

Support Dual Channel mode.

DDR2 DIMM X 4

P10,11,12,13

P25

P29

PCI-EXP X 1 Slot

P28

P23,24

PCI-EXP X 1 LAN

INTEL 82573E

10/100/1000Mbps

PCI Slots X 2

Audio Codec

SPI FOR ICH7

Shared for ICH7 and LAN

SPI FOR LAN

Line In Line Out

A

B

C

D

EE

Jamaica Block Diagram

USB Port X 2 Mic In Line Out

Jamaica

System Block

Date:

2005/4/12

PAGE:SIZE:

230

REV:

3.1

OF

84

F

P19

Floppy

Connector

2

6M bit Flash

P19

F

1

Keyboard/Mouse

Connector

P22

Parallel Front Connector

P20

3

Serial

Connector x 2

P20

Rear

USB Ports X 6

P22,24

Front

USB Ports X 2

P24

5

6

Board

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

Document Number:

Prepared by:

XXXXXXXX

I.J. Shen

A3

7

6

FSB_VTT

6

H_REQ-(0:4)

H_ADSTB0-

6

H_ADSTB1-

6

15

H_A20M-

15 15

H_FERR15 15

H_IGNNE-

15 15

H_STPCLK-

27

CPUVID(0:5)

18

CLK_HOST_CPU

18

CLK_HOST_CPU19 19

CPU_THERMDA CPU_THERMDC

19

VCC_SENSE

27

VSS_SENSE

27

LB2012T100MR

L46

10UH_100MA

R404

L47

10UH_100MA

H_A-(3:31)

H_SMI-

H_INTR

H_NMI

SKTOCC-

JMK325BJ476MM-T

0R

H_REQ-(0) H_REQ-(1) H_REQ-(2) H_REQ-(3) H_REQ-(4)

H_VCCA_VCCIOPLL

H_VSSA

H_VCCA_VCCIOPLL

V

0

3

X

.

1

6

2

_

1

F

_

P

U

7

1

A

4

1

C

T156 T157

T158

T43 T48 T50

T67 T154 T155

CPUVID(0) CPUVID(1) CPUVID(2) CPUVID(3) CPUVID(4) CPUVID(5)

T136

T159

V

0

1

_

F U

3

H_VSSA

T30 T31

J14

L5

H_A-(3) H_A-(4) H_A-(5) H_A-(6) H_A-(7) H_A-(8) H_A-(9) H_A-(10) H_A-(11) H_A-(12) H_A-(13) H_A-(14) H_A-(15) H_A-(16)

H_A-(17) H_A-(18) H_A-(19) H_A-(20) H_A-(21) H_A-(22) H_A-(23) H_A-(24) H_A-(25) H_A-(26) H_A-(27) H_A-(28) H_A-(29) H_A-(30) H_A-(31)

1 L C

A3-

P6

A4-

M5

A5-

L4

A6-

M4

A7-

R4

A8-

T5

A9-

U6

A10-

T4

A11-

U5

A12-

U4

A13-

V5

A14-

V4

A15-

W5

A16-

N4

RSVED1

P5

RSVED2

K4

REQ0-

J5

REQ1-

M6

REQ2-

K6

REQ3-

J6

REQ4-

R6

ADSTB0-

G5

PCREQ

AB6

A17-

W6

A18-

Y6

A19-

Y4

A20-

AA4

A21-

AD6

A22-

AA5

A23-

AB5

A24-

AC5

A25-

AB4

A26-

AF5

A27-

AF4

A28-

AG6

A29-

AG4

A30-

AG5

A31-

AH4

A32-

AH5

A33-

AJ5

A34-

AJ6

A35-

AC4

RSVD3

AE4

RSVD4

AD5

ADSTB1-

P2

SMI-

K3

A20M-

R3

FERR-_PBE-

K1

LINT0

L1

LINT1

N2

IGNNE-

M3

STPCLK-

A23

VCCA

B23

VSSA

D23

RSVD5

C23

VCCIOPLL

AM2

VID0

AL5

VID1

AM3

VID2

AL6

VID3

AK4

VID4

AL4

VID5

AM5

RSVD6_FC11

F28

BCLK0

G28

BCLK1

AE8

SKTOCC-

AL1

THERMDA

AK1

THERMDC

AN3

RSVD7

AN4

RSVD8

AN5

VCC_SENSE

AN6

VSS_SENSE

F29

RSVD118

LGA775_BW_CDM_1

FORCEPH_RSVD9

TESTHI_13_SLP-

CS_GTLREF_RSVD120

GTLREF1_RSVD122

COMP4_RSVD123

ADSBNR-

BPRIDBSYDRDYHITM-

IERR-

INITLOCKTRDYBINIT-

DEFEREDRDYMCERR-

TESTHI_8 TESTHI_9

TESTHI_10

GTLREF

RESET-

TESTHI_00

TESTHI_01 TESTHI_011 TESTHI_012

TESTHI_02

TESTHI_03

TESTHI_04

TESTHI_05

TESTHI_06

TESTHI_07

RSVD10

RSVD11 PWRGOOD PROCHOT-

THERMTRIP-

COMP0 COMP1 COMP2 COMP3

RSVD12

RSVD13

RSVD14

RSVD15

RSVD16

RSVD17

RSVD119

RSVD121

RSVD124

BOOTSELECT

LL_ID0 LL_ID1

HITRSP-

AP0AP1-

BR0-

DP0DP1DP2DP3-

RS0RS1RS2-

D2 C2 D4 H4

T32

G8 B2 C1 E4 AB2 P3 C3 E3 AD3

T33

G7 F2

T160

AB3

T34

U2

T35

U3

T36

F3 G3

TESTHI_8

G4

TESTHI_9

H5

TESTHI_10

J16

T107

H15

T108

H16

T109

J17

T110

H1

G23

B3 F5 A3

F26 W3 P1 W2 F25 G25 G27 G26 G24 F24 AK6 G6

T42

L2 AH2 N1 AL2 M2

H_COMP0

A13

H_COMP1

T1

H_COMP2

G2 R1

H_COMP3

N5 AE6 C9 G10 D16 A20

E23

T111

E24 F23

T112

H2 J2 J3

Y1

T68

V2 AA2

CPU_GTLREF0

2

0

4

0

2

_

X

8

P

1

A

C

TESTHI_0 TESTHI_1 TESTHI_11 TESTHI_12 TESTHI_2-7

H_ADSH_BNRH_HIT-

H_BPRIH_DBSYH_DRDYH_HITMH_IERRH_INITH_LOCKH_TRDY-

H_DEFER-

H_BR0-

H_CPURSTH_RS0-

H_RS1H_RS2-

H_FORCEPH_IO-

TESTHI_13 H_PWRGD-

H_PROCHOTTHERMTRIP_ICH-

CPU_GMCH_GTLREF CPU_GTLREF1

H_COMP4

LL_ID0 LL_ID1

3,4,5,27

3,4

3,4,5,27

27 3

6 6 6

6 6 6 6 3 15 6 6

6

3,6

3,5,6 6

6 6

VTT_OUT_L

VTT_OUT_R

3,19

VTT_OUT_R 3 3,15

3,15

15,19

VTT_OUT_R

3 3

H_BPM-(0) H_BPM-(1) H_BPM-(2) H_BPM-(3) H_BPM-(4) H_BPM-(5)

H_D-(0) H_D-(1) H_D-(2) H_D-(3) H_D-(4) H_D-(5) H_D-(6) H_D-(7) H_D-(8) H_D-(9) H_D-(10) H_D-(11) H_D-(12) H_D-(13) H_D-(14) H_D-(15)

H_D-(16) H_D-(17) H_D-(18) H_D-(19) H_D-(20) H_D-(21) H_D-(22) H_D-(23) H_D-(24) H_D-(25) H_D-(26) H_D-(27) H_D-(28) H_D-(29) H_D-(30) H_D-(31)

6

H_D-(0:63)

60R4_1%R340

R341 60R4_1%

H_COMP0 H_COMP1

FSB_VTT

H_DBI0-

6

H_DSTBN0- H_DSTBN2-

6

H_DSTBP0- H_DSTBP2-

3

3,6 3 4 3,15

3 3

3,15

3,6,18 3,6,18 3,6,18 3,5,6

3,19

3,6,18 3,6,18 3,6,18

6

H_DBI1-

6 6

H_DSTBN1-

H_DSTBP1-

6

5 5 5 5 5

H_TRST-

5

H_BPM-(0:5)

5,15

DBRESET-

5

ITP_CLKOUT

ITP_CLKOUT-

5

FSB_SEL0 FSB_SEL1 FSB_SEL2

CPU_GTLREF1

H_TCK

H_TDI H_TDO H_TMS

3

62R

R403 R335 62R

R337 R338 R353 62R

R348 R349

R613 62R

R365 R343 62R R344 62R R345 62R

R350 62R

R615 60R4_1% R378

R80 X R334 130R

%

1

_

1

R

9

4

3

2

1

R

%

1

_

9

R

1

0

4

1

2

R

%

1

_

7

R

1

4

6

2

1

6

R

%

1

_

8

R

1

0

6

1

2

R

470RR336 470R 470R

60R4_1% 60R4_1%

62R

62RR346 62RR347

60R4_1%R614

X

62RR342 XR396

3

0

6

4

0

1 M C

3

0

3

6

0

6 M C

TESTHI_0 TESTHI_2-7

H_COMP2 H_COMP3

TESTHI_1 TESTHI_8 TESTHI_9 TESTHI_10 TESTHI_11 TESTHI_12

R620 10R

R621 10R

FSB_SEL0 FSB_SEL1 FSB_SEL2 H_CPURST-

TESTHI_13

H_BR0H_COMP4 H_COMP5 H_PWRGD-

H_IERRLL_ID1 H_FORCEPH_IOH_PROCHOT-

CPU_GTLREF0

2

0

2

4

7

0

X

_

C

P A C

CLOSE TO CPU_GTLREF PIN

2

4

0

8

4

1

0

X

_

C

P A C

CLOSE TO CPU_GTLREF PIN

J14

B4

D0-

C5

D1-

A4

D2-

C6

D3-

A5

D4-

B6

D5-

B7

D6-

A7

D7-

A10

D8-

A11

D9-

B10

D10-

C11

D11-

D8

D12-

B12

D13-

C12

D14-

D11

D15-

A8

DBI0-

C8

DSTBN0-

B9

DSTBP0

G9

D16-

F8

D17-

F9

D18-

E9

D19-

D7

D20-

E10

D21-

D10

D22-

F11

D23-

F12

D24-

D13

D25-

E13

D26-

G13

D27-

F14

D28-

G14

D29-

F15

D30-

G15

D31-

G11

DBI1-

G12

DSTBN1-

E12

DSTBP1

AE1

TCK

AD1

TDI

AF1

TDO

AC1

TMS

AG1

TRST-

AJ2

BPM0-

AJ1

BPM1-

AD2

BPM2-

AG2

BPM3-

AF2

BPM4-

AG3

BPM5-

AC2

DBR-

AK3

ITPCLK0

AJ3

ITPCLK1

G29

BSEL0

H30

BSEL1

G30

BSEL2

LGA775_BW_CDM_2

7

5

3

K

R

1

USI

TITLE:

Document Number:

Prepared by:

H_D-(32)

G16

D32-

H_D-(33)

E15

D33-

H_D-(34)

E16

D34-

H_D-(35)

G18

D35-

H_D-(36)

G17

D36-

H_D-(37)

F17

D37-

H_D-(38)

F18

D38-

H_D-(39)

E18

D39-

H_D-(40)

E19

D40-

H_D-(41)

F20

D41-

H_D-(42)

E21

D42-

H_D-(43)

F21

D43-

H_D-(44)

G21

D44-

H_D-(45)

E22

D45-

H_D-(46)

D22

D46-

H_D-(47)

G22

D47-

D19

DBI2-

G20

DSTBN2-

G19

DSTBP2

DBI3-

DSTBN3-

DSTBP3

VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8

VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24

VTT_PWRGD

VTT_OUT_R VTT_OUT_L

VTT_SEL

VTT_OUT_L

VTT_PWRGD

R

Universal Scientific Industrial Co.,Ltd.

H_D-(48)

D20

D48-

H_D-(49)

D17

D49-

H_D-(50)

A14

D50-

H_D-(51)

C15

D51-

H_D-(52)

C14

D52-

H_D-(53)

B15

D53-

H_D-(54)

C18

D54-

H_D-(55)

B16

D55-

H_D-(56)

A17

D56-

H_D-(57)

B18

D57-

H_D-(58)

C21

D58-

H_D-(59)

B21

D59-

H_D-(60)

B19

D60-

H_D-(61)

A19

D61-

H_D-(62)

A22

D62-

H_D-(63)

B22

D63-

C20 A16 C17

A29 B25 B29 B30 C29 A26 B27 C28 A25

FSB_VTT

A28 A27 C30 A30 C25 C26 C27 B26 D27 D28 D25 D26 B28 D29 D30 AM6

AA1 J1 F27

3,4

3,26,27

H_DBI2-

H_DBI3H_DSTBN3H_DSTBP3-

VTT_PWRGD

2

0

4

8

0

3 B C

2

0

4

0

Jamaica

CPU SOCKET(Host Bus)

XXXXXXXX

I.J. Shen

A3

Date:

2005/4/12

PAGE:SIZE:

6 6 6

3,26,27

VTT_OUT_R VTT_OUT_L

9

3 B C

REV:

3.1

330

OF

3,4,5,27 3,4

4 4 4 3 4

MS_ID0

COMP7 COMP6

H_COMP5

MS_ID1

AG22

K29

AM26

AL8 AE12 AE11

W23

W24

W25

Y28 AL18 AC25

W30

Y30

AN14 AD28

Y26 AC29

M29

U24

AC27

AM18 AM19

AB8 AC26

AM9

AF15

AC8 AE14

N23

W29

U29 AC24 AC23

Y23

AN26 AN25 AN11 AN18

Y27

Y25

AD24

AE23 AE22 AN19

AE21

AM30

AE19 AC30 AE15

M30

K27

M24 AN21

VCORE

3

VTT_OUT_L

VTT_OUT_R

VCORE

7

F

9

U

C

2

3

0

F

1

U

C

2

TITLE:

Document Number:

Prepared by:

0

F

1

U

C

2

USI

V

5

.

4

3

2

T

_

C

F U

0

1

R394 62R R377

X

NOPOP_RES_0603

62RR610

60R4_1%R105

R269 60R4_1%

R

Universal Scientific Industrial Co.,Ltd.

Jamaica

CPU SOCKET(Vcore)

XXXXXXXX

I.J. Shen

A3

Date:

V

5

.

5

.

2

_

5

_

F

T

F

U

C

U

0

1

MS_ID0

MS_ID1

COMP7 COMP6

2005/4/12

4

4 4

REV:

3.1

PAGE:SIZE:

OF

304

6

5

0

1

T

2

9

2

9

2

J14

VCCP1 VCCP2 VCCP3 VCCP4 VCCP5 VCCP6 VCCP7 VCCP8 VCCP9

T25

VCCP10 VCCP11 VCCP12 VCCP13 VCCP14 VCCP15 VCCP16 VCCP17 VCCP18 VCCP19 VCCP20 VCCP21

J23

VCCP22 VCCP23 VCCP24 VCCP25 VCCP26 VCCP27

J8

VCCP28

J28

VCCP29

T30

VCCP30 VCCP31 VCCP32 VCCP33 VCCP34 VCCP35 VCCP36 VCCP37 VCCP38 VCCP39 VCCP40 VCCP41 VCCP42 VCCP43 VCCP44 VCCP45 VCCP46 VCCP47 VCCP48 VCCP49 VCCP50

V8

VCCP51

K8

VCCP52 VCCP53 VCCP54 VCCP55 VCCP56 VCCP57 VCCP58 VCCP59 VCCP60 VCCP61

3

4

3

1

E

3

1 V

1

0

3 D V S R

_

1 D

I

S M

2

6 P C C V

8 T

1

5

6

7

2

6

A

Y

F

T

5

4

2

3

0

3

3 D

D

V

S

R

_

5 P

M O C

6

5

4

3

6

P

C

V

6

8

5

8

2

1

2

E

C

N

W

A

E

D

E

D

B

E

W

1

0

9

8

7

6

2

1

0

1

3

D

V

S

R

_

0 D

I

S M

6

7

8

7

6

P

C

V

5

8

0

2

3

M

D

N

A

5

4

2

3

1

0

9

6 P C C V

6

2 D A

7

P

C

V

5

8

6

9

5

6

2

L

Y

J

U

M

A

9

8

1

6

2

4

K

F

2

8

1

A

M

A

K

N

J

6

5

4

2

3

1

2

P

C

V

LGA775_BW_CDM_3

5

4

8

9

3

0

1

2

8

7

8

P

C

V

8

2

1

J A

8

7

3

9

2

D

G

U

N

U

M

A

9

2

8

2

8

2

4

8

N

2

H

D

G

L

A

N

A

W

A

9

8

7

6

5

4

0

2

2 P C C V

6

7

8

P

C

V

8

2

U

K

3

1

2

P

C

V

9

8

3

0

1

2

8

9

P

C

V

8

4

8

1

2

1

2

1

D

K

H

K

A

4

8

1

0

A

G

3

A

J

2

1

0

1

2

P

C

V

6

5

4

9

P

C

V

4

9

2

1

2

T

H

M

A

0

4

7

1

2

F A

M

9

8

0

2

P

C

V

8

7

9

P

C

V

5

9

2

E A

M A

9

1

3

1

9

2

4

7

K

2

F

D

L

G

9

J

7

0

2 P C C V

9

9 P C C V

9

2 Y

2

A

Y

A

J

6

5

4

3

2

1

0

2

P

C

V

5

4

2

3

1

0

1

P

C

V

1

4

1

5

2

5

9

2

1

2

1

J

T

G

K

M

A

1

8

2

3

4

M

2

1

2

J

W

T

J

A

9

8

7

6

5

0

6

0

1 P C C V

4

9

0

1

2

P

C

V

7

1

9

2

8

0

1

0

1

0

1

P

C

V

5

8

1

9

5

0

2

1

2

1

2

3

J

L

G

U

A

1

8

7

9

6

2 L A

3

9

1 P C C V

3

1

1 P C C V

0

3 H A

2

4

1

2

9

6

1

H

J

H

F

G

H

F

H

2

A

N

9

8

7

6

2

9

1 P C C V

4

1

1 P C C V

5

2

1

J

G A

5

1

0

4

8

9

8

1

P

C

V

AG9

VCCP183

AN12

VCCP182

AK8

VCCP181

T27

VCCP180

AJ19

VCCP179

U26

VCCP178

AJ8

VCCP177

AN15

VCCP176

AL22

VCCP175

AH12

VCCP174

N28

VCCP173

T26

VCCP172

AM8

VCCP171

AL19

VCCP170

K23

VCCP169

P8

VCCP168

K25

VCCP167

J11

VCCP166

J29

VCCP165

AH9

VCCP164

AJ25

VCCP163

AL30

VCCP162

N29

VCCP161

AG14

VCCP160

AK11

VCCP159

AJ9

VCCP158

AL12

VCCP157

AH25

VCCP156

AN30

VCCP155

AL14

VCCP154

K30

VCCP153

AJ11

VCCP152

AL11

VCCP151

AM11

VCCP150

AJ21

VCCP149

AG30

VCCP148

AK21

VCCP147

AF8

VCCP146

AM15

VCCP145

AD23

VCCP144

AF11

VCCP143

AK15

VCCP142

AG27

VCCP141

J21

VCCP140

J18

VCCP139

J26

VCCP138

AL15

VCCP137

AF18

VCCP136

AH15

VCCP135

AN9

VCCP134

AG26

VCCP133

AJ15

VCCP132

J10

VCCP131

AK26

VCCP130

AG11

VCCP129

AN29

VCCP128

AK22

VCCP127

R8

VCCP126

T23

VCCP125

U27

VCCP124

AH14

VCCP123

6

5

9

8

1

2

7

0

1

2

1

2

1

P

C

V

2

0

8

5

6

8

7

2

1

2

N

J

L

H

A

W

A

3,5,27

5

FC16

T135

AE16

AL10 AK23

AL16 AL24 AK13

AL20

AK16 AK20

AM27

AL13 AL17

AK30

AL23

AE28 AE29

AE30 AN20 AF10 AE24

AM24

AN23

AM16

AE25 AE27

AH13

7

8

3

J14

C10

VSS1

D12

VSS2

AM7

VSS3_FC12

C24

VSS4

K2

VSS5

C22

VSS6

AN1

VSS7

B14

VSS8

K7

VSS9 VSS10

B11

VSS11 VSS12 VSS13

H12

VSS14

AF7

VSS15

AK7

VSS16

H7

VSS17

E14

VSS18

L28

Y5

VSS20

E11

VSS21 VSS22 VSS23 VSS24

AL3

VSS25

D21

VSS26 VSS27

D18

VSS28

AN2

VSS29 VSS30 VSS31 VSS32

AM1

VSS33 VSS34 VSS35

C19

VSS36

E28

VSS37

AH7

VSS38 VSS39

D24

VSS40 VSS41

A12

VSS42

L25

VSS43

J7

VSS44 VSS45 VSS46

K5

VSS47

J4

VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54

H9

VSS55

H8

VSS56

H13

VSS57

AC6

VSS58

AC7

VSS59

AH6

VSS60

C16

VSS61 VSS62 VSS63 VSS64

AJ28

VSS65

AJ7

VSS66

F19

VSS67 VSS68

AD7

VSS69

2

6

F

2

L

A

G

A

V

A

6

2

4

3

5

7

2

S

V

2

0

1

4

3

7

S

V

6

7

0

7

1

2

1

E

H

K

H

A

8

0

7

4

7

1

0

2

7

M

E

B

J

3

2

7

E

A

T

R

1

5

0

9

8

6

7

6

7

6

2

S

V

8

9

7

6

1

5

0

7

8

7

8

S

V

3

4

7

3

5

0

1

2

3

1

E

J

H

A

M

A

4

0

2

4

E

2 P

A

4

3

6

2

S

V

4

3

7

2

1

F

N

3

N

A

H

A

6

9

1

0

1

5

6

2

C

S

F

S

_

2

V

6

2 S

S V

6

7

5

2

F

N

G

F

1

F

A

G

A

5

4

3

6

8

7

5

2

S

V

0

2

1

5

2

S

V

LGA775_BW_CDM_4

9

8

7

6

5

4

3

2

8 S

S V

3

5

F

K

A

8

S

V

2

3

7

9

6

0

2

1

2

1

F

H

J

F

K

A

6

4

5

3

2

1

0

9

S

V

0

3

7

3

6

0

1

2

1

G

J

F

M

A

0

3

9

0

8

1

2

3

2

8

F

E

F

2

G

7

4

A

F

H

A

F

7

4

8

6

5

9

4

2 S

S V

7

9 S

S V

6

2 L

3

2

4

2

S

V

4

2

3

1

0

8

9

0

9

1

S

V

4

1

0

3

5

3

4

1

2

1

2

D

L

H

A

M

A

6

0

3

2 B

A

3

A

N

9

1

0

3

4

2

S

V

L E

S

_ F

E R L T G

_

7

6

5

0

1

S

V

3

4

9

2

L

B

H

7

4

5

2

B

A

8

3

2 S

S V

8

0

1 S

S V

7

1

2

H

A

0

6

7

1

2

7

N

B

N

G

8

M

A

E

A

5

4

7

6

3

2

1

0

3

2

S

V

6

4

5

2

3

1

9

0

1

S

V

2 E A

1

S

V

0

8

0

4

7

9

2

J

B

K

A

M

A

4

8

9

0

6

1

2

3

2

3

4

1

B

7

A

M

A

L

9

8

7

2

S

V

9

8

7

1

S

V

7

5

6

4

1

2

B

H

9

H

E

J

B

K

7

1

6

2

L

A

C

V

E

4

6

5

3

2

1

0

2

S

V

6

4

5

2

3

0

1

2

1

S

V

2

6

0

7

3

2

1

2

A

H

A

3

9

5

6

1

8

5

A

B

9

8

7

6

5

1

2

S

V

8

7

1

9

0

2

3

2

3

1

S

V

0

1

7

8

9

2

1

B

H

A

4

B

D

A

D

A

C

D

4

3

2

1

0

9

1

2 S

S V

2

3

1 S

S V

7

1 H

8

1

0

2

S

V

D9

VSS207

E2

VSS206

A2

VSS205

A18

VSS204

H6

VSS203

AF13

VSS202

AE10

VSS201

AF16

VSS200

P29

VSS199

V3

VSS198

P30

VSS197

R23

VSS196

R24

VSS195

U7

VSS194

R25

VSS193

R26

VSS192

R27

VSS191

R28

VSS190

R29

VSS189VSS19

U1

VSS188

E25

VSS187

AL7

VSS186

T6

VSS185

V23

VSS184

V24

VSS183

T3

VSS182

V25

VSS181

AN10

VSS180

E20

VSS179

R7

VSS178

V27

VSS177

R5

VSS176

V28

VSS175

V29

VSS174

R2

VSS173

V30

VSS172

E26

VSS171

P7

VSS170

AA24

VSS169

AA25

VSS168

P4

VSS167

AA26

VSS166

AA27

VSS165

AN13

VSS164

AA28

VSS163

N7

VSS162

N6

VSS161

AA29

VSS160

L27

VSS159

Y7

VSS158

AL27

VSS157

D15

VSS156

L29

VSS155

L30

VSS154

Y2

VSS153

C7

VSS152

AG17

VSS151

AG16

VSS150

AG13

VSS149

P23

VSS148

W7

VSS147

AJ20

VSS146

P25

VSS145

W4

VSS144

AJ13

VSS143

AM28

VSS142

P26

VSS141

P27

VSS140

AK2

VSS139

8

7

6

5

4

3

1

S

V

4

8

3

7

4

6

1

2

1

2

C

V

J

P

H

M

A

18 18

3 3

3,4,5,27

10,11,18,19 10,11,18,19

3,15

3,6

3,5 3,5 3,5 3,5 3,5

3,5

DBRESET-

CLK_HOST_ITP-

CLK_HOST_ITP

ITP_CLKOUT-

ITP_CLKOUT

VTT_OUT_R

H_CPURST-

SMB_CLK

SMB_DATA

TESTIN-

5

H_TDO

H_TDI H_TMS H_TCK

H_TRST-

H_BPM-(0:5)

5 3,5 3,5 3,5 3,5 3,5

5

TESTIN-

H_TDO

H_TDI H_TMS H_TCK

H_TRST-

FC16

R3180R

0R

R319 R320

X

R321X

49R9_1% R608

1K

H_BPM-(0) H_BPM-(1) H_BPM-(2) H_BPM-(3) H_BPM-(4) H_BPM-(5)

R330 49R9_1% R331 R332 49R9_1%

R609

48 42 40 39

R322

46 53 51 41

52 56 58 57 54

1 2 7

8 13 14 19 20 25 26 31 32 37 38 49 50 59 60

SAMTEC BSH-03-01-H-D

R323 R324 R325 R326 R327

X

J12

DBR ITP_CLKN ITP_CLKP PWRGOOD RESETSCL SDA TESTIN-

TDO TDI TMS TCK TRST-

VSS1 VSS2 VSS3 VSS4 VSS5

NOA_PILOTCLK

VSS6

NOA_PILOTCLKVSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18

X_XDP_CONN

62R 62R 62R 62R 62R 62RR328

49R9_1%R173 49R9_1%R329

49R9_1%

49R9_1%R333

62R

BPM5BPM4BPM3BPM2BPM1-

BPM0

NC10 NC11

NOA_PILOT0 NOA_PILOT1 NOA_PILOT2 NOA_PILOT3 NOA_PILOT4 NOA_PILOT5 NOA_PILOT6 NOA_PILOT7

VTT1 VTT2

H_BPM-(5)

3

H_BPM-(4)

5

H_BPM-(3)

9

H_BPM-(2)

11

H_BPM-(1)

15

H_BPM-(0)

17

21

NC1

22

NC2

23

NC3

24

NC4

27

NC5

29

NC6

33

NC7

35

NC8

45

NC9

47 55

4 6 10 12 16 18 28 30 34 36

43 44

2

0

4

0

7

3 B C

VTT_OUT_R

H_BPM-(0:5)

VTT_OUT_R

3,4,5,27

3,5

3,4,5,27

T153

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

Document Number:

Prepared by:

A3

Jamaica

CPU SOCKET(Ground) & XDP

XXXXXXXX

I.J. Shen

Date:

2005/4/12

REV:

3.1

PAGE:SIZE:

OF

305

1 43 65 87

H_A-(3:31)

A

3

B

3

H_REQ-(0:4)

3

H_ADSTB0H_ADSTB1-

C

D

3

3 3 3 3 3 3 3 3 3 3 3 3

3,5

3 3 3 3

3 3 3

3 3 3 3

H_DSTBP0-

H_DSTBN0-

H_DBI0-

H_DSTBP1-

H_DSTBN1-

H_DBI1-

H_DSTBP2-

H_DSTBN2-

H_DBI2-

H_DSTBP3-

H_DSTBN3-

H_DBI3-

H_ADSH_BNR-

H_BPRI-

H_BR0-

H_CPURST-

H_DBSY-

H_DEFER-

H_DRDY-

H_HIT-

H_HITM-

H_LOCK-

H_RS0H_RS1H_RS2-

H_A-(3) H_A-(4) H_A-(5) H_A-(6) H_A-(7) H_A-(8) H_A-(9) H_A-(10) H_A-(11) H_A-(12) H_A-(13) H_A-(14) H_A-(15) H_A-(16) H_A-(17) H_A-(18) H_A-(19) H_A-(20) H_A-(21) H_A-(22) H_A-(23) H_A-(24) H_A-(25) H_A-(26) H_A-(27) H_A-(28) H_A-(29) H_A-(30) H_A-(31)

H_REQ-(0) H_REQ-(1) H_REQ-(2) H_REQ-(3) H_REQ-(4)

E

FSB_VTT

2

U42

J39

HA3-

K38

HA4-

J42

HA5-

K35

HA6-

J37

HA7-

M34

HA8-

N35

HA9-

R33

HA10-

N32

HA11-

N34

HA12-

M38

HA13-

N42

HA14-

N37

HA15-

N38

HA16-

R32

HA17-

R36

HA18-

U37

HA19-

R35

HA20-

R38

HA21-

V33

HA22-

U34

HA23-

U32

HA24-

V42

HA25-

U35

HA26-

Y36

HA27-

Y38

HA28-

AA37

HA29-

V32

HA30-

Y34

HA31-

E41

HREQ0-

D41

HREQ1-

K36

HREQ2-

G37

HREQ3-

E42

HREQ4-

M36

HADSTB0-

V35

HADSTB1-

K41

HDSTBP0-

L43

HDSTBN0-

K40

HDINV0-

F35

HDSTBP1-

G34

HDSTBN1-

A38

HDINV1-

J27

HDSTBP2-

M26

HDSTBN2-

E29

HDINV2-

E34

HDSTBP3-

B37

HDSTBN3-

B32

HDINV3-

W42

HADS-

U39

HBNR-

D42

HBPRI-

AA41

HBREQ0-

C30

HCPURST-

U42

HDBSY-

P40

HDEFER-

V41

HDRDY-

Y40

HEDRDY-

U41

HHIT-

W41

HHITM-

U40

HLOCK-

F38

HPCREQ-

T40

HRS0-

Y43

HRS1-

T43

HRS2-

W40

HTRDY-

LAKEPORT_1

Host Interface

FSB_VTT

HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63

HDSWING

HSCOMP HRCOMP

HDVREF

HACCVREF

HCLKP

HCLKN

P41

HD0

M39

HD1

P42

HD2

M42

HD3

N41

HD4

M40

HD5

L40

HD6

M41

HD7

K42

HD8

G39

HD9

J41 G42 G40 G41 F40 F43 F37 E37 J35 D39 C41 B39 B40 H34 C37 J32 B35 J34 B34 F32 L32 J31 H31 M33 K31 M27 K29 F31 H29 F29 L27 M24 J26 K26 G26 H24 K24 F24 E31 A33 E40 D37 C39 D38 D33 C35 D34 C34 B31 C31 C32 D32 B30 D30

B27

R371 60R4_1%

C27 A28 D27 D28

M31 M29

%

1

_

9

0

7

R

3

6

1

R

H_D-(0) H_D-(1) H_D-(2) H_D-(3) H_D-(4) H_D-(5) H_D-(6) H_D-(7) H_D-(8)

H_D-(9) H_D-(10) H_D-(11) H_D-(12) H_D-(13) H_D-(14) H_D-(15) H_D-(16) H_D-(17) H_D-(18) H_D-(19) H_D-(20) H_D-(21) H_D-(22) H_D-(23) H_D-(24) H_D-(25) H_D-(26) H_D-(27) H_D-(28) H_D-(29) H_D-(30) H_D-(31) H_D-(32) H_D-(33) H_D-(34) H_D-(35) H_D-(36) H_D-(37) H_D-(38) H_D-(39) H_D-(40) H_D-(41) H_D-(42) H_D-(43) H_D-(44) H_D-(45) H_D-(46) H_D-(47) H_D-(48) H_D-(49) H_D-(50) H_D-(51) H_D-(52) H_D-(53) H_D-(54) H_D-(55) H_D-(56) H_D-(57) H_D-(58) H_D-(59) H_D-(60) H_D-(61) H_D-(62) H_D-(63)

F

P

2

.

2

3

2 C

HXSWING

X

H_D-(0:63)

FSB_VTT

0 : GMCH's PCI Express lane numbers are reversed. 1 : Normal operation. (for ATX)

CPU_GMCH_GTLREF

CLK_HOST_GMCH CLK_HOST_GMCH-

3,6

18 18

3

28

SDVO_CTRL_DATA

28

SDVO_CTRL_CLK

3,18 3,18 3,18

EXP_RXP_0

28

EXP_RXN_0

28

EXP_RXP_1

28

EXP_RXN_1

28

EXP_RXP_2

28

EXP_RXN_2

28 28

EXP_RXP_3

EXP_RXN_3

28

EXP_RXP_4

28

EXP_RXN_4

28 28

EXP_RXP_5

EXP_RXN_5

28 28

EXP_RXP_6

EXP_RXN_6

28

EXP_RXP_7

28

EXP_RXN_7

28

EXP_RXP_8

28

EXP_RXN_8

28

EXP_RXP_9

28

EXP_RXN_9

28 28

EXP_RXP_10

EXP_RXN_10

28

EXP_RXP_11

28

EXP_RXN_11

28

EXP_RXP_12

28

EXP_RXN_12

28

EXP_RXP_13

28

EXP_RXN_13

28

EXP_RXP_14

28 28

EXP_RXN_14

EXP_RXP_15

28

EXP_RXN_15

28

DMI_RXP_0

16 16

DMI_RXN_0

DMI_RXP_1

16

DMI_RXN_1

16 16

DMI_RXP_2

16

DMI_RXN_2

16

DMI_RXP_3

16

DMI_RXN_3

18

CLK_PE_100M_GMCH

CLK_PE_100M_GMCH-

18

FSB_SEL0 FSB_SEL1 FSB_SEL2

R373

3K

EXP_EN

28

VCC3

R79 X

R446 100R

R447

T144 T145 T146

T9

T10

100R

AA10

G12 F12 D11 D12

J13 H13 E10 F10

J9

H10

F7 F9

C4 D3 G6

J6 K9 K8

F4 G4 M6 M7 K2

L1

U11 U10

R8

R7

P4 N3

Y10 Y11

Y7 Y8

AA9

AA6 AA7 AC9 AC8

B14 B16

F15 E15

F21 H21 L20 K18 H20 L18 K21 L21 F20 N21

U42

EXP_RXP0 EXP_RXN0 EXP_RXP1 EXP_RXN1 EXP_RXP2 EXP_RXN2 EXP_RXP3 EXP_RXN3 EXP_RXP4 EXP_RXN4 EXP_RXP5 EXP_RXN5 EXP_RXP6 EXP_RXN6 EXP_RXP7 EXP_RXN7 EXP_RXP8 EXP_RXN8 EXP_RXP9 EXP_RXN9 EXP_RXP10 EXP_RXN10 EXP_RXP11 EXP_RXN11 EXP_RXP12 EXP_RXN12 EXP_RXP13 EXP_RXN13 EXP_RXP14 EXP_RXN14 EXP_RXP15 EXP_RXN15

DMI_RXP0 DMI_RXN0 DMI_RXP1 DMI_RXN1 DMI_RXP2 DMI_RXN2 DMI_RXP3 DMI_RXN3

GCLKP GCLKN

SDVO_CTRLDATA SDVO_CTRLCLK

BSEL0 BSEL1 BSEL2 ALLZTEST XORTEST RSV_TP5 EXP_SLR RSV_TP4 EXP_EN RSV_TP6

6

7

6

2

2 B B

0

2

_

2 C N

2

5

V

W

V

W

4

A

3

A

E

C

A

B

A

5

2

9

6

0

_

1

_

1

_

1

2

_

2

_

2

_

2

C

N

3

2

4

2

1

4

1

2

B

C

4

C

4 B

5

1

_

2 C N

B

4

8

7

3

4

_

1

_

1

2

_

2

_

2

C

N

PCI Express Interface

3

2

3

2

4

C

B

3

7

2

1

_

1

_

2

_

2

C

N

EXP_TXP0

EXP_TXN0

EXP_TXP1

EXP_TXN1

EXP_TXP2

EXP_TXN2

EXP_TXP3

EXP_TXN3

EXP_TXP4

EXP_TXN4

EXP_TXP5

EXP_TXN5

EXP_TXP6

EXP_TXN6

EXP_TXP7

EXP_TXN7

EXP_TXP8

EXP_TXN8

EXP_TXP9

EXP_TXN9

EXP_TXP10

EXP_TXN10

EXP_TXP11

EXP_TXN11

EXP_TXP12

EXP_TXN12

EXP_TXP13

EXP_TXN13

EXP_TXP14

EXP_TXN14

EXP_TXP15

EXP_TXN15

D14 C13 A13 B12 A11 B10 C10 C9 A9 B7 D7 D6 A6 B5 E2 F1 G2 J1 J3 K4 L4 M4 M2 N1 P2 T1 T4 U4 U2 V1 V3 W4

EXP_TXP_0 EXP_TXN_0 EXP_TXP_1 EXP_TXN_1 EXP_TXP_2 EXP_TXN_2 EXP_TXP_3 EXP_TXN_3 EXP_TXP_4 EXP_TXN_4 EXP_TXP_5 EXP_TXN_5 EXP_TXP_6 EXP_TXN_6 EXP_TXP_7 EXP_TXN_7 EXP_TXP_8 EXP_TXN_8 EXP_TXP_9 EXP_TXN_9 EXP_TXP_10 EXP_TXN_10 EXP_TXP_11 EXP_TXN_11 EXP_TXP_12 EXP_TXN_12 EXP_TXP_13 EXP_TXN_13 EXP_TXP_14 EXP_TXN_14 EXP_TXP_15 EXP_TXN_15

28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28

A

B

LAKEPORT_2

DMI Interface

Analog Display Port

DMI_TXP0

DMI_TXN0

DMI_TXP1

DMI_TXN1

DMI_TXP2

DMI_TXN2

DMI_TXP3

DMI_TXN3

EXP_COMPO

EXP_COMPI

CRTHSYNC CRTVSYNC

CRTRED

CRTGREEN

CRTBLUE

CRTRED-

CRTGREEN-

CRTBLUE-

CRTDDC_DATA

CRTDDC_CLK

DREFCLKP

DREFCLKN

CRTREFSET

EXTTSRSVRD55 RSVRD56

RSTIN-

PWROK

ICH_SYNC-

NC30

W2 Y1 AA2 AB1 Y4 AA4 AB3 AC4

AC12 AC11

39R R383

D17 C17

F17 K17 H18

G17 J17 J18

N18 N20

J15 H15

A20

J20 M11 V30 AJ12 AJ9 M18 A42

R421 255R_1%

T49 T45

R385 24R9_1%

R386 10K

DMI_TXP_0 DMI_TXN_0 DMI_TXP_1 DMI_TXN_1 DMI_TXP_2 DMI_TXN_2 DMI_TXP_3 DMI_TXN_3

R38439R

VGA_RED VGA_GREEN VGA_BLUE

VGA_DDC_DA_3V VGA_DDC_CLK_3V

CLK_96M_DOT CLK_96M_DOT-

PRST_GMCH-H_TRDYPWR_GD ICH_SYNC-

PCI_EXP_1.5V

VGA_HSYNC VGA_VSYNC

V

5

.

2 C C V

16 16 16 16 16 16 16 16

14 14 14

19 15,19 15

14 14

6,19 6,19

18 18

C

7

D

E

VCC3

%

1

_

7

R

6

1

3

0

3

R

R64 62R

F

2

0

%

4

1

0

_

7

5

8

P

6

R

C

3

4

8

R

HXSWING

2345

%

1

_

9

R

6

4

3

2

R

1

R626 10R

3

%

0

4

6

1

0

6

_

0

R

M

2

0

4

C

1

2

R

5

8

1

X

C

CPU_GMCH_GTLREF

)

2

0

T

4

P

0

O

_

P

F

A

P

C

0

2

(

3,6

VGA_DDC_CLK_3V

6,19

VGA_DDC_DA_3V

6,19

1

2

8

3

K

3

R

9

8

2

K

6

0

1

R

61

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

GMCH(Host Bus,DMI,PCI_EXP Bus,VGA signals)

Document Number:

Prepared by:

A3

Jamaica

XXXXXXXX

I.J. Shen

Date:

2005/4/12

7

REV:

3.1

PAGE:SIZE:

OF

306

F

8

VCC1.5V

6

L45

0R

PCI_EXP_1.5V

5

X

7 E C

L44

1UH_300MA

LB2012T1R0M

L40

600R_200MA

L41

10UH_100MA LB2012T100MR

L42

10UH_100MA LB2012T100MR

L43

600R_200MA

REV:

730

OF

VCC1.5V

3.1

VCC1.5V

R423

3

0

6

0

2005/4/12

9

1 M C

2

0

4

0

2

0

4

0

2

0

4

0

3

0

6

0

L5 FB_180R

0R51_1%

6

F

8

U

C

0

1

4

8

1 B C

V

5

6

8

1

7

1

_

E

F

B

C

U

0

2

V

6

7

8

1

7

1

_

E

F

B

C

U

0

2

1

2 M C

PAGE:SIZE:

VCCA_GPLL

5

8

6

5

7

1

0

4

7

2

5

U42

W21

VSSNCTF1

V29

VSSNCTF2

V26

VSSNCTF3

V24

VSSNCTF4

U29

VSSNCTF5

R29

VSSNCTF6

R26

VSSNCTF7

D43

VSSNCTF8

D1

VSSNCTF9

A40

VSSNCTF10

A4

VSSNCTF11

AE21

VSSNCTF12

AE23

VSSNCTF13

AE25

VSSNCTF14

AF18

VSSNCTF15

AF20

VSSNCTF16

AF22

VSSNCTF17

AF24

VSSNCTF18

W23

VSSNCTF19

W25

VSSNCTF20

Y20

VSSNCTF21

Y22

VSSNCTF22

Y24

VSSNCTF23

Y26

VSSNCTF24

Y29

VSSNCTF25

AA25

VSSNCTF26

AA27

VSSNCTF27

AA29

VSSNCTF28

AY1

VSSNCTF29

AC19

VSSNCTF30

AC25

VSSNCTF31

AC29

VSSNCTF32

AD18

VSSNCTF33

AD20

VSSNCTF34

AD22

VSSNCTF35

AD24

VSSNCTF36

AD27

VSSNCTF37

AD29

VSSNCTF38

AE19

VSSNCTF39

BC4

VSSNCTF40

AD4

VCC_EXP1

AD5

VCC_EXP2

AD6

VCC_EXP3

AD8

VCC_EXP4

AD10

VCC_EXP5

AD12

VCC_EXP6

N5

VCC_EXP7

N7

VCC_EXP8

N9

VCC_EXP9

N10

VCC_EXP10

N12

VCC_EXP11

R5

VCC_EXP12

R10

VCC_EXP13

AE2

VCC_EXP14

R11

VCC_EXP15

R13

VCC_EXP16

U6

VCC_EXP17

U7

VCC_EXP18

U8

VCC_EXP19

U13

VCC_EXP20

V5

VCC_EXP21

V6

VCC_EXP22

V7

VCC_EXP23

V9

VCC_EXP24

AE3

VCC_EXP25

V10

VCC_EXP26

V13

VCC_EXP27

Y13

VCC_EXP28

AA5

VCC_EXP29

AA13

VCC_EXP30

AC5

VCC_EXP31

AC6

VCC_EXP32

AC13

VCC_EXP33

AD1

VCC_EXP34

AD2

VCC_EXP35

AE4

VCC_EXP36

N11

VCC_EXP37

4

5

F

8

U

C

0

1

M

L

5

6

2

D

R

V

S

R

3

2

1

0

5

4

6

C

V

1

3

4

5

7

0

2

1

2

R

U

1

9

8

2

G

J

G

A

9

0

7

8

2

3

2

D

R

V

S

R

9

8

7

6

C

V

5

7

9

8

1

2

1

F

R

A

7

F

J

F

A

2

1

3

4

5

3

C

D

C

R

V

V S R

6

5

1

F

T

C

4

3

2

1

0

N

7

N

C

V

2

6

4

3

1

0

5

1

2

F

U

A

2

4

3

2

1

2

5

2

1

2

6

B

C

F

D

A

9

8

6

7

C

V

0

9

8

7

2

1

F

T

C

N

C

V

5

7

8

5

2

1

F

V

A

1

8

1

0

J

A

B

1

2

P

A

P

A

5

3

4

2

1

0

6

1

C

V

6

5

4

3

2

1

7

2

F

T

C

N

C

V

4

9

7

6

2

0

1

2

1

2

F

G

V

U

V

A

VCC1.5V

7

0

9

3

2

1

8

1

2

1

2

1

G

B

G

A

7

8

1

C

V

5

4

2

3

0

1

9

2

1

C

V

0

7

6

4

8

7

9

8

9

7

5

2

1

2

W

Y

0

1

9

8

7

6

3

2

C

V

5

7

2

1

J

H

1

U

N

W

U

A

P

A

4

3

2

8

6

7

5

3

C

V

LAKEPORT_3

6

5

4

3

2

1

0

9

8

3

2

F

T

C

N

C

V

9

7

8

5

7

2

3

1

2

V

W

0

9

8

7

3

4

3

F

T

T C N C C V

T

C

N

C

V

4

5

2

3

5

7

1

2

1

2

1

2

A

Y

W

A

7

6

5

4

3

2

1

4

F

T

C

N

C

V

7

8

1

A

9

8

4

F

T

C

N

C

V

4

6

9

0

9

7

2

1

2

1

B

A

4

0

5

0

4

3

1

3

2

4 K A

9

3 C C V

0

5 F T C N C C V

0

2 B A

1

3

1

K

J

K

F

K

J

A

4

2

3

1

0

4 C C V

1

5 F T C N C C V

5

4

2

B

A

7

6

5

4

C

V

8

7

6

5

4

3

2

5

F

T

C

N

C

V

8

7

5

7

6

0

1

2

C

B

C

A

0

2

1

4

3

1

2

1

G

H

A

2

0

1

8

9

5

4

C

V

3

2

1

0

9

6

5

F

T

C

N

C

V

5

7

6

4

1

2

C

D

A

3

4

1

3

2

9

1

G

F

G

A

4

3

9

8

6

7

5

C

V

8

7

6

5

4

6 F T C N C C V

7

9

1

J

D

A

1

0

9

6

7

6

F

T

C

N

C

C V

C

V

5

6

1

3

0

8

7

2

1

E

D

A

8

7

6

5

4

3

2

7

F

T

C

N

C

V

7

5

7

6

8

4

2

1

2

1

2

J

F

E

A

9

7 F T C N C C V

0

8 F T C N C C V

9

1

F A

1

8 F T C

N C C V

3

1

2

F

A

VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8

VCCSM9 VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15 VCCSM16 VCCSM17 VCCSM18 VCCSM19 VCCSM20 VCCSM21 VCCSM22 VCCSM23 VCCSM24 VCCSM25 VCCSM26 VCCSM27 VCCSM28 VCCSM29 VCCSM30

VCCA_HPLL VCCA_SMPLL VCCA_DPLLA VCCA_DPLLB

VCCA_EXPPLL

VCC_DAC VCCCRT_DAC1 VCCCRT_DAC2 VSSACRT_DAC

5

4

3

2

8

F

T

C

N

C

V

8

7

0

2

G

J

A

6 G A

VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8

VTT9 VTT10 VTT11 VTT12 VTT13 VTT14 VTT15 VTT16 VTT17 VTT18 VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25

6

8 F T C N C C V

5 G A

VCC1.8_DDR2

BC18 BC22 BC26 BC31 BC35 BC13 BB42 BB38 BB33 BB28 BB24 BB20 BB16 AY41 AW21 AW13 AV31 AV21 AW35 AW34 AW31 AW29 AW24 AW20 AW15 AV42 AV23

FSB_VTT

AV18 BC40 AY43 F27 G23 H23 J23 K23 L23 M23 A24 N23 C26 D23 D24 D25 P23 F23 E27 E26 E24 E23 C25 C23 B26 B25 B24 B23

VCCA_HPLL

C21 B20

VCCA_MPLL VCCA_DPLLA

C19

VCCA_DPLLB

B19

VCCA_GPLL

B17

D19 C18 B18 A18

8

7

8

F

T

C

N

C

V

4 G A

2

0

4

8

0

1 B C

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

Document Number:

Prepared by:

A3

VCCA_HPLL

VCCA_DPLLA

VCCA_DPLLB

VCCA_MPLL

VCC2.5V VCC2.5V

2

V

0

5

4

0

1

4

2

3

_

P

E

F

C

U

0

1

Jamaica

GMCH(Power & Ground)

XXXXXXXX

I.J. Shen

Date:

A

B

C

D

E

F

1

2345678

U42

BA32

10,12

M_MAA_A(0:13)

M_WE_A-

10,12

M_CAS_A-

10,12

M_RAS_A-

10,12

M_SBS_A(0:2)

10,12

M_SCS_A-(0:3)

10,12

M_SCKE_A(0:3)

10,12

M_ODT_A(0:3)

10,12

DDR_CLK_P0_A

10

DDR_CLK_N0_A

10

DDR_CLK_P1_A

10

DDR_CLK_N1_A

10

DDR_CLK_P2_A

10

DDR_CLK_N2_A

10

DDR_CLK_P3_A

10

DDR_CLK_N3_A

10 11

DDR_CLK_P4_A

10

DDR_CLK_N4_A

10

DDR_CLK_P5_A

10

DDR_CLK_N5_A

10

VCC1.5V

GMCH_VREF

8

VCC1.8_DDR2

R622 1K_1%

2

0

4

2

%

0

1

3

B

_

2

C

6

K

R

1

M_MAA_A(0) M_MAA_A(1) M_MAA_A(2) M_MAA_A(3) M_MAA_A(4) M_MAA_A(5) M_MAA_A(6) M_MAA_A(7) M_MAA_A(8) M_MAA_A(9) M_MAA_A(10) M_MAA_A(11) M_MAA_A(12) M_MAA_A(13)

M_SBS_A(0) M_SBS_A(1) M_SBS_A(2)

M_SCS_A-(0) M_SCS_A-(1) M_SCS_A-(2) M_SCS_A-(3)

M_SCKE_A(0) M_SCKE_A(1) M_SCKE_A(2) M_SCKE_A(3)

M_ODT_A(0) M_ODT_A(1) M_ODT_A(2) M_ODT_A(3)

T137 T138

CLOSE TO GMCH

SMA_A0

AW32

SMA_A1

BB30

SMA_A2

BA30

SMA_A3

AY30

SMA_A4

BA27

SMA_A5

BC28

SMA_A6

AY27

SMA_A7

AY28

SMA_A8

BB27

SMA_A9

AY33

SMA_A10

AW27

SMA_A11

BB26

SMA_A12

BC38

SMA_A13

BB35

SWE_A-

BA37

SCAS_A-

BA34

SRAS_A-

BC33

SBS_A0

AY34

SBS_A1

BA26

SBS_A2

BB37

SCS_A0-

BA39

SCS_A1-

BA35

SCS_A2-

AY38

SCS_A3-

BB25

SCKE_A0

AY25

SCKE_A1

BC24

SCKE_A2

BA25

SCKE_A3

AW37

SODT_A0

AY39

SODT_A1

AY37

SODT_A2

BB40

SODT_A3

BB32

SCLK_A0

AY32

SCLK_A0-

AY5

SCLK_A1

BB5

SCLK_A1-

AK42

SCLK_A2

AK41

SCLK_A2-

BA31

SCLK_A3

BB31

SCLK_A3-

AY6

SCLK_A4

BA5

SCLK_A4-

AH40

SCLK_A5

AH43

SCLK_A5-

AK40

RSVRD32

AL17

RSV_TP1

AK17

RSV_TP0

M17

RSV4_1

L17

RSV4_2

AM4

SVREF0

2

8

0

4

7

0

1

B C

SDQS_A0

SDQS_A0-

SDM_A0 SDQ_A0 SDQ_A1 SDQ_A2 SDQ_A3 SDQ_A4 SDQ_A5 SDQ_A6 SDQ_A7

SDQS_A1

SDQS_A1-

SDM_A1 SDQ_A8

SDQ_A9 SDQ_A10 SDQ_A11 SDQ_A12 SDQ_A13 SDQ_A14 SDQ_A15

SDQS_A2

SDQS_A2-

SDM_A2 SDQ_A16 SDQ_A17 SDQ_A18 SDQ_A19 SDQ_A20 SDQ_A21 SDQ_A22 SDQ_A23

SDQS_A3

A

SDQS_A3-

SDM_A3

L

SDQ_A24

E

SDQ_A25 SDQ_A26

N

SDQ_A27

N

SDQ_A28 SDQ_A29

A

SDQ_A30

H

SDQ_A31

C

SDQS_A4

2

SDQS_A4-

R

SDM_A4 SDQ_A32

D

SDQ_A33

D

SDQ_A34 SDQ_A35 SDQ_A36 SDQ_A37 SDQ_A38 SDQ_A39

SDQS_A5

SDQS_A5-

SDM_A5 SDQ_A40 SDQ_A41 SDQ_A42 SDQ_A43 SDQ_A44 SDQ_A45 SDQ_A46 SDQ_A47

SDQS_A6

SDQS_A6-

SDM_A6 SDQ_A48 SDQ_A49 SDQ_A50 SDQ_A51 SDQ_A52 SDQ_A53 SDQ_A54 SDQ_A55

SDQS_A7

SDQS_A7-

SDM_A7 SDQ_A56 SDQ_A57 SDQ_A58 SDQ_A59 SDQ_A60 SDQ_A61 SDQ_A62 SDQ_A63

AU4 AR2 AR3 AP3 AP2 AU3 AV4 AN1 AP4 AU5 AU2

BA3 BB4 AY2 AW3 AY3 BA7 BB7 AV1 AW4 BC6 AY7

AY11 BA10 BB10 AW12 AY10 BA12 BB12 BA9 BB9 BC11 AY12

AU18 AR18 AP18 AM20 AM18 AV20 AM21 AP17 AR17 AP20 AT20

AU35 AV35 AT34 AP32 AV34 AV38 AU39 AV32 AT32 AR34 AU37

AP42 AP40 AP39 AR41 AR42 AN43 AM40 AU41 AU42 AP41 AN40

AG42 AG41 AG40 AL41 AL42 AF39 AE40 AM41 AM42 AF41 AF42

AC42 AC41 AC40 AD40 AD43 AA39 AA40 AE42 AE41 AB41 AB42

M_DQS_A(0) M_DQS_A-(0) M_DQM_A(0)

M_DQS_A(1) M_DQS_A-(1) M_DQM_A(1)

M_DQS_A(2) M_DQS_A-(2) M_DQM_A(2)

M_DQS_A(3) M_DQS_A-(3) M_DQM_A(3)

M_DQS_A(4) M_DQS_A-(4) M_DQM_A(4)

M_DQS_A(5) M_DQS_A-(5) M_DQM_A(5)

M_DQS_A(6) M_DQS_A-(6) M_DQM_A(6)

M_DQS_A(7) M_DQS_A-(7) M_DQM_A(7)

M_D_A(0) M_D_A(1) M_D_A(2) M_D_A(3) M_D_A(4) M_D_A(5) M_D_A(6) M_D_A(7)

M_D_A(8)

M_D_A(9) M_D_A(10) M_D_A(11) M_D_A(12) M_D_A(13) M_D_A(14) M_D_A(15)

M_D_A(16) M_D_A(17) M_D_A(18) M_D_A(19) M_D_A(20) M_D_A(21) M_D_A(22) M_D_A(23)

M_D_A(24) M_D_A(25) M_D_A(26) M_D_A(27) M_D_A(28) M_D_A(29) M_D_A(30) M_D_A(31)

M_D_A(32) M_D_A(33) M_D_A(34) M_D_A(35) M_D_A(36) M_D_A(37) M_D_A(38) M_D_A(39)

M_D_A(40) M_D_A(41) M_D_A(42) M_D_A(43) M_D_A(44) M_D_A(45) M_D_A(46) M_D_A(47)

M_D_A(48) M_D_A(49) M_D_A(50) M_D_A(51) M_D_A(52) M_D_A(53) M_D_A(54) M_D_A(55)

M_D_A(56) M_D_A(57) M_D_A(58) M_D_A(59) M_D_A(60) M_D_A(61) M_D_A(62) M_D_A(63)

M_DQS_A-(0:7) M_DQM_A(0:7) M_D_A(0:63)

LAKEPORT_4

1

23

U42

BB22

T140 T141

T142 T143

M_MAA_B(0) M_MAA_B(1) M_MAA_B(2) M_MAA_B(3) M_MAA_B(4) M_MAA_B(5) M_MAA_B(6) M_MAA_B(7) M_MAA_B(8) M_MAA_B(9) M_MAA_B(10) M_MAA_B(11) M_MAA_B(12) M_MAA_B(13)

M_SBS_B(0) M_SBS_B(1) M_SBS_B(2)

M_SCS_B-(0) M_SCS_B-(1) M_SCS_B-(2) M_SCS_B-(3)

M_SCKE_B(0) M_SCKE_B(1) M_SCKE_B(2) M_SCKE_B(3)

M_ODT_B(0) M_ODT_B(1) M_ODT_B(2) M_ODT_B(3)

1

8

1 B C

SMA_B0

BB21

SMA_B1

BA21

SMA_B2

AY21

SMA_B3

BC20

SMA_B4

AY19

SMA_B5

AY20

SMA_B6

BA18

SMA_B7

BA19

SMA_B8

BB18

SMA_B9

BA22

SMA_B10

BB17

SMA_B11

BA17

SMA_B12

AW42

SMA_B13

BB23

SWE_B-

AY24

SCAS_B-

BA23

SRAS_B-

AW23

SBS_B0

AY23

SBS_B1

AY17

SBS_B2

BA40

SCS_B0-

AW41

SCS_B1-

BA41

SCS_B2-

AW40

SCS_B3-

BA14

SCKE_B0

AY16

SCKE_B1

BA13

SCKE_B2

BB13

SCKE_B3

AY42

SODT_B0

AV40

SODT_B1

AV43

SODT_B2

AU40

SODT_B3

AM29

SCLK_B0

AM27

SCLK_B0-

AV9

SCLK_B1

AW9

SCLK_B1-

AL38

SCLK_B2

AL36

SCLK_B2-

AP26

SCLK_B3

AR26

SCLK_B3-

AU10

SCLK_B4

AT10

SCLK_B4-

AJ38

SCLK_B5

AJ36

SCLK_B5-

AL39

RSVRD46

AK18

RSV_TP3

AK23

RSV_TP2

R27

RSV5_1

U27

RSV5_2

AM2

SVREF1

AJ6

SRCOMP1

AL5

SRCOMP0

AM3

SOCOMP1

AJ8

SOCOMP0

2

0

4

0

LAKEPORT_5

CLOSE TO GMCH

SDQS_B0

SDQS_B0-

SDM_B0 SDQ_B0 SDQ_B1 SDQ_B2 SDQ_B3 SDQ_B4 SDQ_B5 SDQ_B6 SDQ_B7

SDQS_B1

SDQS_B1-

SDM_B1 SDQ_B8

SDQ_B9 SDQ_B10 SDQ_B11 SDQ_B12 SDQ_B13 SDQ_B14 SDQ_B15

SDQS_B2

SDQS_B2-

SDM_B2 SDQ_B16 SDQ_B17 SDQ_B18 SDQ_B19 SDQ_B20 SDQ_B21 SDQ_B22 SDQ_B23

SDQS_B3

SDQS_B3-

B

SDM_B3 SDQ_B24

L

SDQ_B25

E

SDQ_B26 SDQ_B27

N

SDQ_B28

N

SDQ_B29 SDQ_B30

A

SDQ_B31

H C

SDQS_B4

SDQS_B4-

2

SDM_B4

R

SDQ_B32 SDQ_B33

D

SDQ_B34

D

SDQ_B35 SDQ_B36 SDQ_B37 SDQ_B38 SDQ_B39

SDQS_B5

SDQS_B5-

SDM_B5 SDQ_B40 SDQ_B41 SDQ_B42 SDQ_B43 SDQ_B44 SDQ_B45 SDQ_B46 SDQ_B47

SDQS_B6

SDQS_B6-

SDM_B6 SDQ_B48 SDQ_B49 SDQ_B50 SDQ_B51 SDQ_B52 SDQ_B53 SDQ_B54 SDQ_B55

SDQS_B7

SDQS_B7-

SDM_B7 SDQ_B56 SDQ_B57 SDQ_B58 SDQ_B59 SDQ_B60 SDQ_B61 SDQ_B62 SDQ_B63

10 10 10 10

VCC1.8_DDR2

11,12

11,12 11,12 11,12

11,12

11 11 11 11 11 11

11 11

11 11 11

GMCH_VREF

8

2

9

0

4

7

0

1

B C

M_MAA_B(0:13)

M_WE_BM_CAS_BM_RAS_B-

M_SBS_B(0:2)

M_SCS_B-(0:3)

M_SCKE_B(0:3)

M_ODT_B(0:3)

DDR_CLK_P0_B

DDR_CLK_N0_B

DDR_CLK_P1_B

DDR_CLK_N1_B

DDR_CLK_P2_B

DDR_CLK_N2_B

DDR_CLK_P3_B

DDR_CLK_N3_B

DDR_CLK_P4_B

DDR_CLK_N4_B

DDR_CLK_P5_B

DDR_CLK_N5_B

80R6_1%

R363

%

1

_

6

4

6

R

3

0

8

R

45678

M_DQS_B(0)

AM8

M_DQS_B-(0)

AM6

M_DQM_B(0)

AL11 AL6 AL8 AP8 AP9 AJ11 AL9 AM10 AP6

M_DQS_B(1)

AV7

M_DQS_B-(1)

AR9

M_DQM_B(1)

AW7 AU7 AV6 AV12 AM11 AR5 AR7 AR12 AR10

M_DQS_B(2)

AV13

M_DQS_B-(2)

AT13

M_DQM_B(2)

AP13 AM15 AM13 AV15 AM17 AN12 AR13 AP15 AT15

M_DQS_B(3)

AU23

M_DQS_B-(3)

AR23

M_DQM_B(3)

AP23 AM24 AM23 AV24 AM26 AP21 AR21 AP24 AT24

M_DQS_B(4)

AT29

M_DQS_B-(4)

AV29

M_DQM_B(4)

AR29 AU27 AN29 AR31 AM31 AP27 AR27 AP31 AU31

M_DQS_B(5)

AP36

M_DQS_B-(5)

AM35

M_DQM_B(5)

AR38 AP35 AP37 AN32 AL35 AR35 AU38 AM38 AM34

M_DQS_B(6)

AG34

M_DQS_B-(6)

AG32

M_DQM_B(6)

AJ39 AL34 AJ34 AF32 AF34 AL31 AJ32 AG35 AD32

M_DQS_B(7)

AD36

M_DQS_B-(7)

AD38

M_DQM_B(7)

AD39 AC32 AD34 Y32 AA32 AF35 AF37 AC33 AC35

USI

TITLE:

GMCH(DDR2 Channel A and Channel B)

Document Number:

Prepared by:

M_D_B(0) M_D_B(1) M_D_B(2) M_D_B(3) M_D_B(4) M_D_B(5) M_D_B(6) M_D_B(7)

M_D_B(8)

M_D_B(9) M_D_B(10) M_D_B(11) M_D_B(12) M_D_B(13) M_D_B(14) M_D_B(15)

M_D_B(16) M_D_B(17) M_D_B(18) M_D_B(19) M_D_B(20) M_D_B(21) M_D_B(22) M_D_B(23)

M_D_B(24) M_D_B(25) M_D_B(26) M_D_B(27) M_D_B(28) M_D_B(29) M_D_B(30) M_D_B(31)

M_D_B(32) M_D_B(33) M_D_B(34) M_D_B(35) M_D_B(36) M_D_B(37) M_D_B(38) M_D_B(39)

M_D_B(40) M_D_B(41) M_D_B(42) M_D_B(43) M_D_B(44) M_D_B(45) M_D_B(46) M_D_B(47)

M_D_B(48) M_D_B(49) M_D_B(50) M_D_B(51) M_D_B(52) M_D_B(53) M_D_B(54) M_D_B(55)

M_D_B(56) M_D_B(57) M_D_B(58) M_D_B(59) M_D_B(60) M_D_B(61) M_D_B(62) M_D_B(63)

R

Universal Scientific Industrial Co.,Ltd.

Jamaica

XXXXXXXX

I.J. Shen

A3

Date:

M_DQS_B(0:7)M_DQS_A(0:7) M_DQS_B-(0:7) M_DQM_B(0:7) M_D_B(0:63)

2005/4/12

11 11 11 11

PAGE:SIZE:

830

REV:

A

B

C

D

E

3.1

OF

F

AA11 AA12 AA14 AA21 AA23

AA31 AA33 AA36

AB43 AC10 AC14

AC21 AC23

AC31 AC36 AC37 AC38 AC39

AD11 AD13

AF38 AF43

AN31

AN42 AP10 AP12 AP29 AP34 AP38

AR15 AR20 AR24 AR32 AR37 AR39 AR43

AT12 AT17 AT18 AT21 AT23 AT26 AT27 AT31 AU12 AU13 AU15 AU17 AU20 AU21 AU24 AU26 AU29 AU32 AU34

AV10 AV17

AV37

0

9

2

7

8

3

6

0

1

3

G

A

U42

A16

VSS6_2

A22

VSS6_3

A26

VSS6_4

A31

VSS6_5

A35

VSS6_6

Y31

VSS6_7

Y35

VSS6_8 VSS6_9 VSS6_10 VSS6_11 VSS6_12 VSS6_13

Y37

VSS6_14

Y39

VSS6_15

Y42

VSS6_16

AA3

VSS6_17 VSS6_18 VSS6_19 VSS6_20

AA8

VSS6_21

AB2

VSS6_22 VSS6_23 VSS6_24 VSS6_25

Y5

VSS6_26

AC2

VSS6_27 VSS6_28 VSS6_29

Y6

VSS6_30

Y9

VSS6_31

AC3

VSS6_32 VSS6_33 VSS6_34 VSS6_35 VSS6_36 VSS6_37

AC7

VSS6_38 VSS6_39 VSS6_40

M37

VSS6_41 VSS6_42 VSS6_43

AF5

VSS6_44 VSS6_45

AN4

VSS6_46 VSS6_47 VSS6_48 VSS6_49 VSS6_50 VSS6_51 VSS6_52

AP5

VSS6_53

AP7

VSS6_54

AR1

VSS6_55 VSS6_56 VSS6_57 VSS6_58 VSS6_59 VSS6_60 VSS6_61 VSS6_62

AR6

VSS6_63 VSS6_64 VSS6_65 VSS6_66 VSS6_67 VSS6_68 VSS6_69 VSS6_70 VSS6_71 VSS6_72 VSS6_73 VSS6_74 VSS6_75 VSS6_76 VSS6_77 VSS6_78 VSS6_79 VSS6_80 VSS6_81 VSS6_82

AU6

VSS6_83

AU9

VSS6_84 VSS6_85 VSS6_86

AV2

VSS6_87 VSS6_88

H32

VSS6_89

J10

VSS6_90

J12

VSS6_91

J2

VSS6_92

J21

VSS6_93

J24

VSS6_94

J29

VSS6_95

J38

VSS6_96

J43

VSS6_97

J5

VSS6_98

J7

VSS6_99

K10

VSS6_100

A

2

1

0

1

_

6

S

V

3

2

1

0

3

_

6

S

V

5

2

3

1

K

0

5

3

1

0

3

4

3

1

3

J

G

H

G

A

5

4

3

0

1

_

6

S

V

6

5

4

0

3

_

6

S

V

7

3

0

2

K

J

A

9

8

7

6

2

1

0

1

_

6

S

V

9

7

8

3

2

1

0

1

3

_

6

S

V

7

2

4

7

6

5

9

3

K

0

6

9

4

6

7

3

J

A

3

4

1

_

6

S

V

5

4

1

3

_

6

S

V

3

2

1

L

1

3

2

1

3

8

1

2

1

3

K

F

K

W

L

A

9

8

7

6

5

0

1

2

1

_

6

S

V

9

8

7

1

6

0

1

2

1

2

3

_

6

S

V

9

6

2

4

1

2

4

2

3

L

2

1

B

A

B

A

B

3

7

2

6

5

1

4

2

1

_

6

S

V

5

4

3

2

6

2

3

_

6

S

V

0

3

0

1

3

2

1

2

M

2

4

9

4

1

4

8

3

3 B

8

2

1

_

6 S

S V

1

3

6

9

B

4

A

B

9

3

2

1

0

4

2

3

1

_

6

S

V

1

9

3

1

6

1

4

3

B

9

8

7

2

6

1

5

0

3

4

3

4

3

4

1

_

6

S

V

4

2

3

7

1

5

1

C

A

B

9

8

7

1

6

0

5

4

3

4

5

4

5

4

1

_

6

S

S V

V

9

3

0

2

4

2

F

B

2

3

1

0

6

0

1

F

1

D

A

D

4

3

2

5

1

_

6

S

V

3

7

2

5

2

F

2

1

D

A

D

E

9

7

8

6

5

1

0

2

5

6

1

_

6

S

V

7

3

1

4

6

9

5

8

0

1

2

E

N

E

3

5

4

6

1

_

6

S

V

3

2

3

2

3

N

9

8

1

7

0

6

1

_

6 S

S

2

6

7

6

7

1

_

6

S

V

5

4

6

4

7

8

4

6

3

1

2

P

N

4

3

7

1

_

6

S

V

P

9

8

7

6

5

1

0

2

7

8

1

_

6

6 S

S V

6

S

V

LAKEPORT_6

9

7

8

5

6

3

4

1

2

0

5

6

7

8

2

3

1

_

6

V

S

R

4

0

3

C

D

Y

A

9

1

4

_

6

V

S

R

1

3

F

D

Y

A

1

_

6

V

S

R

0

1

0

6

3

0

1

3

2

3

2

J

C

A

K

U

V

A

1

_

6

V

S

R

9

6

7

0

1

9

2

J

L

K

A

9

1

4

2

1

0

9

3

2

3

P

5

4

3

8

1

_

6

S

V

1

2

0

2

_

6

V

S

R

5

2

9

3

4

2

A

G

A

4

D

F

1

3

A

R

A

R

9

8

7

6

1

0

2

8

9

1

_

6

S

V

5

6

7

8

9

3

4

2

_

6

V

S

R

6

4

7

8

3

4

8

1

4

3

C

Y

A

W

B

A

2

7

3 R

3

9

1

_

6 S

S V

4

9

2

1

6

9

3

2

4

U

T

R

U

9

7

8

6

5

4

0

9

0

1

2

_

6

S

V

VSS6_201 VSS6_202 VSS6_203 VSS6_204 VSS6_205 VSS6_206 VSS6_207 VSS6_208 VSS6_209 VSS6_210 VSS6_211 VSS6_212 VSS6_213 VSS6_214 VSS6_215 VSS6_216 VSS6_217 VSS6_218 VSS6_219 VSS6_220 VSS6_221 VSS6_222 VSS6_223 VSS6_224 VSS6_225 VSS6_226 VSS6_227 VSS6_228 VSS6_229 VSS6_230 VSS6_231 VSS6_232 VSS6_233 VSS6_234 VSS6_235 VSS6_236 VSS6_237 VSS6_238 VSS6_239 VSS6_240 VSS6_241 VSS6_242 VSS6_243 VSS6_244 VSS6_245 VSS6_246 VSS6_247 VSS6_248 VSS6_249 VSS6_250 VSS6_251 VSS6_252 VSS6_253 VSS6_254 VSS6_255 VSS6_256 VSS6_257 VSS6_258 VSS6_259 VSS6_260 VSS6_261 VSS6_262 VSS6_263 VSS6_264 VSS6_265 VSS6_266 VSS6_267 VSS6_268 VSS6_269 VSS6_270 VSS6_271 VSS6_272 VSS6_273 VSS6_274 VSS6_275 VSS6_276 VSS6_277 VSS6_278 VSS6_279 VSS6_280 VSS6_281 VSS6_282 VSS6_283 VSS6_284 VSS6_285 VSS6_286 VSS6_287 VSS6_288 VSS6_289 VSS6_290 VSS6_291 VSS6_292 VSS6_293 VSS6_294 VSS6_295 VSS6_296 VSS6_297 VSS6_298 VSS6_299 VSS6_300

AD7 U3 U31 U33 U36 U38 U5 U9 AL10 AL12 AL13 AL15 AL18 AL2 AL21 AL23 AL24 AL27 AL3 AL32 AL33 AL37 AL43 AL7 AM33 AM36 AM37 AM39 AM5 AM7 AM9 AN13 AN15 AN17 AN18 AN2 AN20 AN21 AN23 AN24 AN26 AN27 E21 E3 E32 E4 E7 E9 F13 F18 F2 F26 F34 F42 F6 G10 G13 G15 G18 G20 G21 G24 G27 G29 G3 G31 G32 G35 G38 G5 G7 G9 H12 H17 H26 H27 V11 V12 V14 V2 AD42 AD37 AD35 V34 V36 V37 V38 V39 V43 V8 AD33 N13 M35 W3 Y12 Y14 Y2 M9 M8 M5

FSB_VTT

3

F

7

U

C

0

1

F

7

B

U

C

0

C

1

2

4

0

4

7

0

9

6

VCC1.8_DDR2

L

L L A M

S

4

5

F

_

3

U

0

C

2

6

.

0

_

2

P A C

L

A

A M

M

S

0

F

_

7

3

U

0

C

2

6

.

0

_

2

P

A

C

VCC1.5V

5

.

2

5

8

5

F

7

U

C

0

1

P

5

_

E

V

C

0

1

_

F U

0

7

4

VCC1.5V

R68 0R47_1%

5

0

8

0

C109

_

P

10UF

A C

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

Document Number:

Prepared by:

A3

Jamaica

GMCH(Ground)

XXXXXXXX

I.J. Shen

Date:

2005/4/12

2

6

5

0

4

7

0

1

B

C

L

L L A M

S

4

7

F

_

7

3

U

0

C

2

6

.

0

_

2

P A C

L

A

M

S

0

F

_

8

3

U

0

C

2

6

.

0

_

2

P

A

C

U16

1

H1

2

H2

3

H3

4

H4

LAKEPORT_KEEPOUT

R390R260 0R47_1%

0R47_1%

5

0

8

0

C110

C111

_

P

10UF

A

C

REV:

3.1

PAGE:SIZE:

930

OF

M_ODT_A(0:3)

8,10,12

M_ODT_A(0:3)

8,10,12

J9

J10

M_DQS_A-(0:7)

8,10

M_DQS_A(0:7)

8,10

8

6

1 C N

1 S

S V

2

M_ODT_A(0) M_ODT_A(1)

2

9

0

1

T

S E T

_

2 C N

2 S

S V

5

8

5

9

7

1

7

3

0

1

T

C

D

N

O

3

4

5

6

S

V

1

4

7

1

2

1

7

6

9

6

3

8

2

6

1

4

1

4

1

5

4

3

2

1

0 B C

7

8

S

V

0

3

2

6

B

C

3

4

1

2

0

1

9

S

V

8

1

2

5

9

6

3

4

3

2

)

1

0

1

0

(

-

A

_

S

Q

D

_

M

8

6

5

6

1

7

1

6

1

0

1

0

7

-

S

B

S

Q

C

Q

D

7

5

6

1

9

0

8

1

2

1

2

1

S

V

4

7

2

5

6

9

0

5

4

8

6

7

5

6

SMBUS address : A0h

DDR2 CHANNEL A DIMM 0

M_DQS_A-(0:7)

8,10

M_DQS_A(0:7)

8,10

8

6

1 C N

M_ODT_A(2) M_ODT_A(3)

2

0

9

1

T

S E T

_

2 C N

5

7

9

7

1

0

1

3

T

C

D

N

O

7

1

2

6

8

9

2

3

1

4

6

4

5

2

3

0

1

B

C

)

1

0

1

0

(

-

A

_

S

Q

D

_

M

8

6

5

6

7

1

6

1

0

7

-

S

B

S

Q

C

Q

D

M_DQM_A(0:7)

8,10

M_D_A(0:63)

8,10

)

2

(

-

A

_

S

Q

D

_

M

8

7

2

-

S

Q

D

)

4

3

5

4

3

(

-

A

_

S

Q

D

_

M

3

6

3

4

7

8

3

9

8

3

4

3

4

3

-

S

Q

D

)

7

6

5

7

6

(

-

A

_

S

Q

D

_

M

4

3

5

0

2

1

0

1

9

1

5

6

7

6

5

-

S

Q

D

1

0

(

A

_

M

Q

D

_

M

6

5

4

5

2

5

6

4

8 S Q D

3

2

1

4

1

8

9

0

9

-

1

S

-

S

Q

S

Q

D

Q

D

_

D

_

0

_

C

1

M

C

N

M

D

N

D

4

3

2

(

A

_

M

Q

D

_

M

7

6

4

1

S Q D

_

2 M D

3

6

2

5

0

5

0

5

2

1

2

1

3

2

1

2

3

1

-

S

Q

D

_

3

4

C

M

N

D

7

6

5

(

A

_

M

Q

D

_

M

2

3

1

2

1

2

4

5

4

1

-

S

Q

D

_

6

5

C

M

N

D

5

3

4

2

3

2

6

3

2

1

2

6

5

7

6

1

-

S

Q

D

_

8

7

C

M

N

D

)

3

2

1

0

(

A

_

D

_

M

6

0

1

9

3

4

7

3

2

0

1

Q

S

D

D Q D

_ C N

)

7

6

5

4

(

A

_

D

_

M

9

8

3

2

1

6

5

4

Q

D

3

2

4

5

1

9

8

1

(

A

_

D

_

M

1

2

0

2

1

7

8

Q

D

1

3

4

1

2

1

2

9

1

2

3

4

5

0

1

Q

D

)

0

)

1

)

7

6

1

(

A

_

D

_

M

4

5

2

6

7

1

Q

D

)

8

9

1

(

A

_

D

_

M

0

1

3

9

8

1

Q

D

)

0

2

( A

_ D

_ M

3

4

1

0

2 Q D

)

2

1

2

( A

_ D

_ M

4

1

2 Q D

)

3

4

6

5

7

8

0

9

1

2

3

5

4

6

7

9

8

0

2

3

2

3

(

A

_

D

_

M

9

0

9

0

4

5

3

4

3

4

1

3

7

2

3

4

5

6

2

Q

D

3

(

A

_

D

_

M

2

3

8

9

6

5

0

1

8

1

8

3

4

8

9

0

1

2

3

2

3

Q

D

1

3

4

(

A

_

D

_

M

9

0

5

6

0

7

9

0

9

8

1

2

8

1

0

5

6

7

8

9

4

3

Q

D

)

3

2

4

5

7

6

8

4

(

A

_

D

_

M

8

9

4

5

6

0

1

9

2

3

4

5

6

7

4

Q

D

)

4

6

9

4

_ M

8

9

8

4 Q D

5

0

2

1

3

5

(

A

_

D

_

M

0

7

8

7

8

6

7

9

4 Q D

1

0

1

2

1

2

5

6

0

1

2

3

4

5

Q

D

)

7

8

0

9

1

2

3

5

6

5

6

(

A

_

D

_

M

6

1

6

7

9

0

5

3

1

2

3

2

1

2

7

5 Q D

3

8

9

0

1

2

6

5

6

Q

D

DDR2_240P_1

U

1

5

3

4

2

7

8

6

2

S

V

4

7

8

1

6

0

3

9

8

9

0

1

5

3

4

1

2

0

9

3

2

S

V

2

9

1

0

1

7

8

6

3

S

V

4

8

1

5

1

6

0

3

7

2

3

2

1

5

3

4

1

2

0

9

4

3

S

V

2

9

4

3

1

7

8

6

4

S

V

8

1

5

4

1

6

0

3

4

7

5

6

5

1

5

3

4

1

2

9

0

5

4

5

S

V

4

8

1

9

0

9

0

6

2

1

2

1

9

7

8

6

5

S

V

7

5

2

6

9

0

3

0

2

1

2

3

4

1

2

0

6

S

V

1

4

7

8

1

5

3

2

3

2

Q

D

V

6

5

1

4

5

8

2

8

9

7

6

7

1

4

5

6

Q

D

V

5

3

0

7

5

7

1

7

8

1

2

D

V

9

4

5

6

9

3

D

V

9

7

9

2

7

4

8

9

6

7

8

7

1

0

1

9

1

7

8

5

6

1

3

4

D

P

0

1

S D D V

7

6

F

D

E

1

0

2

A

D V

L

D

R

C

A

C

D

S

R

V

1

0

9

8

5

1

8

0

4

2

1

5

3

1

2

1

2

3 C C V

1

0

E

0

1

A

K

A

S

B

C

9

0

1

2

3

9

7

5

2

1

)

0

1

0

1

(

A

_

E

S

K

B

C

S

_

S

_

M

VCC1.8_DDR2

DIMM_VREF_A

10

SMB_CLK

SMB_DATA

2

0

4

7

0

1 B C

8,10

M_DQM_A(0:7)

5,10,11,18,19 5,10,11,18,19

U

F

R

_

0 E K C

-

_

-

_

1

0

2

-

K

0

1

S

C

3

6

8

7

6

1

0

9

7

3

8

2

1

2

)

0

1

(

-

A

_

S

C

S

_

M

3

4

5

6

7

8

2

0

1

K

A

C

A

3

2

5

8

3

6

8

1

)

1

0

3

2

(

A

_

A

M

_

M

9

A

1

0

8

9

7

0

6

8

5

7

1

)

0

)

4

( A

_

1

9

8

7

6

5

(

A

_

A

M

_

M

8,10

)

3

2

4

3

2

(

-

A

_

S

Q

D

_

M

7

6

7

8

3

2

3

2

3

2

-

S

Q

D

)

6

5

4

6

(

5

(

-

(

-

A

_

S

Q

D

_

_ M

4

8

4 S Q D

_

M

5

4

0

3

2

3

0

1

9

8

1

5

6

4

5

6

-

S

Q

D

)

7

0

7

(

-

A

_

S

M

Q

D

_

M

4

3

1

7 S Q D

6

5

2

6

5

2

1

4

1

9

8

7

8

9

-

S

Q

D

_

0

C

M

N

D

)

3

1

2

(

A

_

_ M

M

Q

D

_

M

4

3

1

0

1

S Q D

_

1 M D

6

7

5

6

5

4

3

5

4

1

2

1

0

2

1

-

S

Q

D

_

3

2

C

M

N

D

)

6

7

5

4

(

A

_

_ M Q D

_ M

3

2

0

2

3

1

-

S

Q

D

_

4

C

M

N

D

M

Q

D

_

M

4

2

3

1

2

1

3

2

1

2

4

5

6

5

4

1

-

S

Q

D

_

7

6

5

C

M

N

D

)

0

1

2

3

(

A

_

D

_

M

5

3

4

3

6

2

1

6

7

1

-

S

Q

D

_

8

C

M

N

D

M

6

0

1

9

3

4

7

3

2

0

1

Q

S

D

D Q D

_ C N

)

0

)

9

1

4

5

6

7

8

(

A

_

D

_

M

8

9

3

2

3

2

1

2

6

7

8

9

5

4

0

1

Q

D

)

1

2

1

(

A

_

D

_

M

1

2

3

2

1

2

1

Q

D

)

7

8

9

3

4

5

6

1

(

A

_

D

_

M

2

0

1

3

4

5

0

1

2

3

4

5

6

7

8

9

1

Q

D

)

6

5

0

2

1

3

4

2

(

A

_

D

_

M

3

4

9

0

4

5

3

4

9

1

3

0

1

2

3

4

5

6

2

Q

D

)

7

2

( A

_ D

_ M

0

4

7

2 Q

D

)

3

4

8

0

9

1

2

3

2

3

2

3

(

A

_

D

_

M

3

8

9

2

5

0

1

6

5

1

8

1

0

1

2

3

4

8

9

3

2

Q

D

)

5

3

( A

_ D

_ M

7

8

5

3 Q D

)

1

2

6

7

9

8

0

4

3

4

(

A

_

D

_

M

6

9

0

5

0

9

0

5

9

0

2

8

9

1

2

0

1

6

3 Q D

2

7

8

9

4

3

Q

D

)

3

4

5

7

6

4

(

A

_

D

_

M

8

9

4

6

0

1

9

2

3

4

5

6

4

Q

D

)

9

0

2

1

3

8

4

5

4

(

A

_

D

_

M

7

8

7

8

5

9

0

1

8

9

1

2

9

0

1

2

7

8

4

5

4

Q

D

P

A

_

2

3

0

1

A

7

6

5

7

9

1

)

3

2

1

(

A

_

A

M

_

M

M_D_A(0:63)

)

4

6

5

(

A

_

D

_

M

6

7

0

2

1

2

1

3

4

5

Q

D

2 A B

-

_

-

S

4

5

6

E

1

A

R

A

C

W

2

4

3

4

3

9

7

5

7

1

)

2

( A

_

S B

S

_ M

M_MAA_A(0:13) DDR_CLK_P0_A DDR_CLK_N0_A DDR_CLK_P1_A DDR_CLK_N1_A DDR_CLK_P2_A DDR_CLK_N2_A M_SCS_A-(0:3) M_SCKE_A(0:3)

M_SBS_A(0:2)

)

7

8

0

9

1

2

3

5

6

5

6

(

A

_

D

_

M

6

7

9

0

5

6

1

2

3

1

2

1

9

0

1

2

6

7

5

Q

D

3

8

5

6

5

Q

D

M_WE_AM_RAS_AM_CAS_A-

8,10,12 8,10,12 8,10,12

8,10,12 8 8 8 8 8 8 8,10,12 8,10,12

8,10,12

0

2

1

2

3

S

V

2

5

8

1

4 S

S V

4

1

5

8

7

6

9

S

V

9

5

8

2

0

7

3

6

2

3

2

1

2

9

8

7

6

5

4

3

1

S

V

7

1

4

2

1

0

1

2

S

V

5

6

0

5

8

9

2

6

5

8

7

8

SMBUS address : A2h

DDR2 CHANNEL A DIMM 1

DDR2_240P_2

U

1

3

2

8

7

6

5

4

3

2

S

V

7

1

4

9

2

1

0

9

2

3

2

S

V

3

0

5

9

2

6

0

1

0

1

0

1

8

7

6

5

4

3

3 S

8

1

9

3

S

V

7

0

1

4

9

3

6

2

3

2

3

1

6

5

4

3

2

1

0

4

S

V

5

8

2

4

1

9

8

7

4

S

V

7

0

1

4

9

3

6

5

6

5

6

1

6

5

4

3

2

1

0

5

S

V

1

8

0

9

2

1

8

7

5

S

V

7

0

4

9

2

3

6

0

1

0

1

2

1

2

1

4

3

2

1

0

9

6

5

S

V

1

5

8

3

2

Q

6

D

S

D

S

V

6

2

1

2

5

7

4

5

6

5

7

3

2

VCC1.8_DDR2

5,10,11,18,19

VCC1.8_DDR2

%

1

_

0

4

K

1

R

%

1

_

1

4

K

1

R

2

0

4

0

7 B C

DIMM_VREF_A

10

5,10,11,18,19

1

9

8

7

6

5

Q

D

V

5

0

4

1

8

1

7

9

8

7

9

1

10

5

1

4

2

3

Q

D

V

9

2

3

4

7

9

6

7

5

6

9

5

1

DIMM_VREF_A

SMB_CLK

SMB_DATA

6

7

9

8

D

V

9

8

7

4

8

7

8

1

0

4

D

P

0

1

S D D V

7

6

F

D

E

1

0

2

A

D V

L

R

D

C

A

D

C

S

R

S

V

8

1

3 C C V

0

5

9

1

0

8

1

4

5

1

0

2

3

2

1

2

1

0

4

7

0

1 B C

1

0

1

0

E

1 A S

9

3

2

E

0

A

K

A S

B

C

6

0

1

2

1

7

9

7

5

7

1

)

2

3

0

1

(

3

(

A

-

A

_

A

_

E

S

_

K

S

B

C

S

_

S

_

M

U

F

R

_

-

_

-

0

2

1

0

-

K

0

1

S

C

3

0

1

7

8

9

2

3

1

2

1

)

2

(

A

_

S C

S

_ M

2

1

0

K

A

C

A

2

3

5

6

3

8

6

8

1

)

3

2

1

0

(

A

_

A

M

_

M

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

Document Number:

DDR2 Channel A DIMM X 2

Prepared by:

A3

4

3

A

0

1

6

)

5

4

(

A

_

A

M

_

M

XXXXXXXX

I.J. Shen

5

6

A

0

8

1

)

6

( A

_

A A M

_ M

8

7

A

7

8

9

7

5

7

1

)

9

8

7

(

A

_

A

M

_

M

Jamaica

Date:

9 A

0

7

)

0

1

( A

_ A A M

_ M

2

P

A B

A

_

2

3

0

1

A

6

7

9

5

1

)

1

3

2

1

(

A

_

A

M

_

M

2005/4/12

-

_

-

S

6

4

5

E

1

A

R

C

W

A

2

4

3

4

3

9

7

5

7

1

)

2

( A

_

S B

S

_ M

M_MAA_A(0:13) DDR_CLK_P3_A DDR_CLK_N3_A DDR_CLK_P4_A DDR_CLK_N4_A DDR_CLK_P5_A DDR_CLK_N5_A M_SCS_A-(0:3) M_SCKE_A(0:3)

M_SBS_A(0:2)

PAGE:SIZE:

10 30

M_WE_AM_RAS_AM_CAS_A-

REV:

3.1

OF

8,10,12 8,10,12 8,10,12

8,10,12 8 8 8 8 8 8 8,10,12 8,10,12

8,10,12

M_ODT_B(0:3)

8,11,12

M_ODT_B(0:3)

8,11,12

J3

J4

M_DQS_B-(0:7)

8,11

M_DQS_B(0:7)

8,11

8

6

1 C N

1 S

S V

2

M_ODT_B(0) M_ODT_B(1)

2

0

1

T

S E T

_

2 C N

2 S

S V

5

9

7

1

7

3

1 T

C

D

N

O

3

4

5

S

V

8

1

4

1

9

6

3

8

2

1

4

1

4

0

3

1

2

0

T

B

D

C

O

1

0

1

6

9

8

7

S

V

2

5

9

7

6

0

3

2

1

2

)

0

1

(

0

1

-

(

B

_

S

Q

D

_

M

2

6

1

5

4

B

C

3

2

1

S

V

8

3

M

7

8

6

1

6 B C

4

1 S

S V

1

4

5

6

1

7

1

6

1

0

1

0

7

-

S

B

S

Q

C

Q

D

2

1

0

9

8

7

6

5

1 S

S V

4

7

4

2

1

S

V

2

5

9

6

0

5

8

7

6

5

6

SMBUS address : A4h

DDR2 CHANNEL B DIMM 0

M_DQS_B-(0:7)

8,11

M_DQS_B(0:7)

8,11

8

6

1 C N

M_ODT_B(2) M_ODT_B(3)

2

0

1

T

S E T

_

2 C N

5

9

7

9

1

7

1

3

0

1

T

C

D

N

O

7

1

2

8

9

2

3

6

4

1

2

0

1

6

4

5

3

B

C

)

1

0

1

(

-

B

_

S

Q

D

_

M

8

6

5

6

7

1

6

1

0

1

7

-

S

B

S

Q

C

Q

D

M_DQM_B(0:7)

8,11

M_D_B(0:63)

8,11

)

4

3

2

(

2

3

4

5

-

(

B

_

S

Q

D

_

M

3

7

4

8

7

3

6

9

3

8

2

8

3

5

4

2

3

2

3

4

-

S

Q

D

)

6

7

5

(

6

7

-

(

B

_

S

Q

D

_

M

4

5

3

4

1

0

1

0

2

1

9

7

6

7

6

5

-

S

Q

D

)

0

1

(

B

_

M

Q

D

_

M

5

6

4

5

3

2

6

5

3

2

1

4

1

0

9

8

0

9

-

1

S

S Q D

-

S

Q

S

Q

D

Q

D

_

D

_

0

_

C

1

M

C

N

M

D

N

D

4

3

2

(

B

_

M

Q

D

_

M

6

7

5

6

5

4

5

4

1

2

1

-

S

Q

D

_

3

2

C

M

N

D

)

5

7

6

(

B

_

M

Q

D

_

M

3

2

4

3

2

0

2

3

1

-

S

Q

D

_

4

C

M

N

D

2

3

1

2

4

1

S Q D

_

5 M D

3

1

2

3

2

6

5

4

6

5

1

-

S

Q

D

_

7

6

C

M

N

D

)

1

2

3

0

(

B

_

D

_

M

5

4

6

1

7

1

S Q D

_

8 M D

0

1

9

3

4

7

3

0

1

2

1

Q

S

D

D Q D

_ C N

)

0

)

5

4

6

(

B

_

D

_

M

3

8

2

1

5

4

Q

D

2

1

3

)

7

( B

_ D

_

M

9

2

1

6

7

Q

D

4

)

8

( B

_ D

_ M

2

1

8 Q D

5

8

7

6

9

0

5

1

4

3

6

2

1

9

1

2

(

B

_

D

_

M

1

2

0

3

4

1

2

1

2

9

3

4

0

1

2

1

Q

D

2

(

B

_

D

_

M

3

1

4

5

0

1

2

3

0

5

6

7

8

9

2

1

Q

D

7

2

(

B

_

D

_

M

4

9

0

4

5

3

4

9

0

1

3

4

7

1

2

3

4

5

6

2

Q

D

)

8

1

0

9

2

3

4

2

3

2

3

(

B

_

D

_

M

2

3

8

9

6

5

0

1

8

1

8

4

8

0

9

1

2

3

2

3

2

3

Q

D

)

1

4

3

2

5

6

1

7

0

9

2

8

3

4

6

5

8

7

9

0

4

3

4

(

B

_

D

_

M

9

0

5

6

0

9

7

9

0

9

8

1

2

1

0

5

6

7

8

9

4

3

Q

D

4

(

B

_

D

_

M

4

5

8

9

1

6

0

5

8

2

9

2

9

6

3

5

7

2

8

4

Q

D

5

4

5

(

B

_

D

_

M

8

7

8

6

7

0

7

9

0

1

2

1

0

9

1

2

1

9

1

3

4

6

0

2

5

4

5

Q

D

)

7

8

9

0

2

1

3

5

6

(

B

_

D

_

M

6

7

5

6

9

0

1

3

1

3

1

2

3

1

2

1

2

1

2

1

3

9

2

8

1

7

0

6

5

6

5

6

5

6

Q

D

DDR2_240P_3

U

1

3

2

3

5

4

2

S

V

4

7

8

1

9

8

9

2

1

0

9

8

7

6

2

S

V

0

3

0

1

4

3

2

3

S

V

2

5

9

6

0

1

4

8

1

0

2

1

2

1

0

9

8

7

6

5

3

S

V

0

3

7

3

2

1

4

3

2

4

3

4

S

V

2

5

9

6

3

1

4

8

1

4

3

5

4

5

1

0

9

8

7

6

5

4

S

V

8

1

9

6

0

3

7

9

0

6

5

1

2

1

8

7

6

5

4

3

2

5

S

V

2

6

9

0

3

4

7

2

1

0

2

1

0

9

4

3

2

Q

6

5

6

D

S

D

S

V

8

5

1

2

3

2

5

2

6

1

4

7

6

7

5

3

2

1

9

8

7

6

1

2

Q

D

V

8

1

4

7

9

1

3

Q

D

V

3

9

4

0

5

1

5

6

7

8

1

9

8

5

6

7

4

D

V

9

4

8

7

9

2

7

8

7

9

6

7

8

1

0

5

4

D

P

0

1

S D D V

7

6

F

D

E

1

0

2

A

D V

3 C C V

L

R

D

C

A

C

D

S

R

V

1

0

9

8

5

1

8

0

4

2

1

5

3

1

2

1

2

1

0

1

E

0

1

A

S

9

3

2

E

A

K

B

C

6

0

1

2

7

9

7

5

1

)

0

1

0

1

(

1

(

B

-

B

_

B

E

S

_

K

S

B

C

S

_

S

_

M

VCC1.8_DDR2

DIMM_VREF_B

11

SMB_CLK

SMB_DATA

2

0

4

3

0

1 B C

8,11

M_DQM_B(0:7)

5,10,11,18,19 5,10,11,18,19

U

F

R

_

-

_

-

2

1

0

-

1

0

S

3

9

1

)

0

(

B

_

S C

S

_ M

0

1

2

0

K

A

C

1

0

7

8

2

3

2

1

A

C

A

3

2

6

5

8

6

8

1

)

1

0

3

2

(

B

_

A

M

_

M

9

8

7

6

4

5

3

A

)

4

( B

_ A A M

0

9

7

8

0

1

7

5

6

8

6

1

)

0

)

1

9

8

7

6

5

(

B

_

A

M

_

M

8,11

)

4

3

2

3

4

(

-

B

_

S

Q

D

_

M

4

8

7

6

7

3

8

2

3

2

8

4

3

2

3

4

-

S

Q

D

)

7

6

5

7

5

( B

_

S Q D

_ M

3

9

5 S Q D

(

6

(

-

(

-

B

_

S

Q

D

_

M

4

3

4

5

1

0

2

1

9

5

6

7

6

-

S

Q

D

)

1

0

(

B

_

M

Q

D

_

M

5

6

4

5

3

2

6

5

3

2

1

4

1

0

9

8

0

9

-

1

S

S Q D

-

S

Q

S

Q

D

Q

D

_

D

_

0

_

C

1

M

C

N

M

D

N

D

4

3

2

(

B

_

_ M Q D

_ M

6

4

1

M

Q

D

_

M

3

7

6

5

2

0

4

5

0

2

1

2

3

1

2

1

3

1

-

S

Q

D

_

3

2 M D

4

C

M

N

D

7

6

5

(

B

_

M

Q

D

_

M

2

3

1

2

1

2

4

5

4

1

-

S

Q

D

_

6

5

C

M

N

D

5

3

4

2

6

3

2

6

3

1

2

1

2

6

5

1

S Q D

7

6

1

-

S

Q

D

_

8

7

C

M

N

D

)

4

3

2

1

0

6

5

(

B

_

D

_

M

8

3

2

0

1

3

4

9

6

5

4

3

0

1

2

Q

D

)

3

2

1

0

)

1

9

8

7

(

B

_

D

_

M

9

2

1

2

3

1

2

3

1

2

1

7

8

9

0

1

2

1

Q

D

)

9

8

7

6

5

4

1

(

B

_

D

_

M

0

1

4

5

0

1

2

3

4

5

6

7

8

3

1 Q D

9

1

Q

D

)

6

5

4

3

2

1

0

2

(

B

_

D

_

M

0

3

4

9

5

3

4

9

4

1

3

1

4

5

6

0

1

2

3

2

Q

D

)

3

2

1

0

9

8

7

3

2

(

B

_

D

_

M

2

3

8

9

1

0

5

0

8

4

1

8

3

7

8

9

0

1

2

3

2

3

Q

D

)

0

9

8

7

6

5

4

3

(

B

_

D

_

M

9

0

5

6

7

9

0

9

8

1

2

8

4

3 Q D

0

5

6

7

8

9

4

3

Q

D

)

7

6

5

4

3

2

1

4

(

B

_

D

_

M

8

9

4

5

6

0

1

0

9

2

9

3

4

5

6

1

2

4

Q

D

)

3

2

1

0

9

8

5

4

(

B

_

D

_

M

7

8

7

8

1

8

9

0

2

9

1

2

7

8

9

0

1

5

4

5

Q

D

P A

_

0

1

2

1

A

7

6

5

7

9

1

)

3

2

1

(

B

_

A

M

_

M

M_D_B(0:63)

)

6

5

4

5

(

B

_

D

_

M

6

7

0

2

1

2

1

3

4

5

Q

D

2 A B

-

_

-

S

6

4

5

3

1 A

4

7

1

)

7

5

( B

_ D

_ M

1

6

5 Q D

E

1

A

R

A

C

W

3

2

4

3

7

9

5

7

1

)

2

( B

_

S B

S

_ M

M_MAA_B(0:13) DDR_CLK_P0_B DDR_CLK_N0_B DDR_CLK_P1_B DDR_CLK_N1_B DDR_CLK_P2_B DDR_CLK_N2_B M_SCS_B-(0:3) M_SCKE_B(0:3)

M_SBS_B(0:2)

)

3

2

1

0

9

8

6

5

(

B

_

D

_

M

5

6

7

9

0

3

1

2

3

2

1

2

3

7

8

9

0

1

6

5

6

Q

D

M_WE_BM_RAS_BM_CAS_B-

8,11,12 8,11,12 8,11,12

8,11,12 8 8 8 8 8 8 8,11,12 8,11,12

8,11,12

4

3

2

1

0

5

9

8

7

1

2

3

4

5

6

S

V

3

0

2

5

8

1

4

7

2

1

S

V

6

2

V

1

4

5

8

9

2

7

4

3

2

3

4

2

1

0

9

8

7

6

2

1

S

V

5

9

2

5

6

0

8

7

8

6

5

SMBUS address : A6h

DDR2 CHANNEL B DIMM 1

DDR2_240P_4

U

0

3

2

4

3

7

6

5

2

S

V

1

4

8

3

7

0

9

8

0

9

0

1

4

3

2

1

0

9

8

3

2

S

V

9

2

6

0

1

0

1

7

6

5

3

S

V

1

5

8

3

7

0

4

2

1

3

2

3

2

1

4

3

2

1

0

9

8

4

3

S

V

9

2

6

3

4

3

1

7

6

5

4

S

V

5

8

3

7

0

1

4

6

5

6

5

1

4

3

2

1

0

9

8

5

4

S

V

9

8

6

9

6

1

7

6

5

S

V

1

4

9

3

6

7

0

1

0

1

2

4

3

2

1

0

9

8

5 S

S V

2

Q

6

5

D

S

D

S

V

7

1

2

5

6

2

1

4

5

8

3

5

7

5

6

3

2

1

9

Q

D

V

8

1

3

5

0

4

1

7

9

5

7

9

8

1

7

8

3

2

1

D

V

4

9

6

5

9

4

5

6

D

V

7

4

8

7

9

2

9

8

7

9

6

7

8

1

8

7

1

6

5

4

D

P

0

1

S D D V

7

6

F

D

E

1

0

2

A

D V

3 C C V

L

D

R

C

A

C

D

S

R

V

0

1

0

9

8

5

8

1

4

0

2

1

5

3

2

1

2

1

0

1

0

E

1

0

A

S

9

3

2

E

A

K

B

C

6

0

1

2

7

9

7

5

1

)

2

3

0

1

(

3

(

B

-

B

_

B

_

E

S

_

S

K

S

K

B

C

S

_

S

_

M

VCC1.8_DDR2

DIMM_VREF_B

11

VCC1.8_DDR2

%

1

_

8

3

K

1

R

%

1

_

9

3

K

1

R

5,10,11,18,19 5,10,11,18,19

2

0

4

0

3 B C

DIMM_VREF_B

11

SMB_CLK

SMB_DATA

2

1

0

4

3

0

1 B C

-

1 S

-

0 S

3

9

1

)

2

(

B

_

S C

S

_ M

U

F

R

_

-

_

1

0

2

K

C

8

0

1

3

2

1

2

TITLE:

Document Number:

Prepared by:

1

K

C

7

6

5

3

8

1

R

USI

A3

4

3

2

8

9

7

6

5

1

0

K

A

C

A

0

2

1

3

8

6

8

1

)

4

3

2

1

0

(

B

_

A

M

_

M

0

7

8

9

0

6

7

5

7

8

1

)

0

)

8

7

6

5

1

9

(

B

_

A

M

_

M

Universal Scientific Industrial Co.,Ltd.

Jamaica

DDR2 Channel B DIMM X 2

XXXXXXXX

I.J. Shen

Date:

P A

_

0

1 A

7

5

)

1

( B

_ A A M

_ M

2

1

A

6

7

1

)

2

1

( B

_ A A M

_ M

2005/4/12

2 A B

-

_

-

S

6

3

4

5

E

1

A

W

R

A

C

3

2

4

6

4

3

7

9

5

7

9

7

1

)

2

)

(

3

B

1

(

_

S

B

_

B

A

S

_

A

M

_ M

M_MAA_B(0:13) DDR_CLK_P3_B DDR_CLK_N3_B DDR_CLK_P4_B DDR_CLK_N4_B DDR_CLK_P5_B DDR_CLK_N5_B M_SCS_B-(0:3) M_SCKE_B(0:3)

M_SBS_B(0:2)

REV:

PAGE:SIZE:

M_WE_BM_RAS_BM_CAS_B-

3.1

OF

3011

8,11,12 8,11,12 8,11,12

8,11,12 8 8 8 8 8 8 8,11,12 8,11,12

8,11,12

8,10 8,10 8,10 8,10 8,10

M_MAA_A(0:13)

M_RAS_AM_CAS_A-

M_WE_A-

M_SBS_A(0:2)

M_SBS_A(0)

M_SBS_A(1)

M_SBS_A(2)

VTT_MEM

33R

M_MAA_A(0)

M_MAA_A(1)

M_MAA_A(2)

M_MAA_A(3)

M_MAA_A(4)

M_MAA_A(5)

M_MAA_A(6)

M_MAA_A(7)

M_MAA_A(8)

M_MAA_A(9)

M_MAA_A(10)

M_MAA_A(11)

M_MAA_A(12)

M_MAA_A(13)

R188

R189

33R

R190

33R 33R

33R

R191

R19233R

33R R193

33R R194

33R

R195

R19633R

R197

33R

R198

R19933R

R20033R

33R R201

33R R202

33R R203

33R

R204

33R

R205

R20633R

8,11 8,11 8,11 8,11 8,11

M_MAA_B(0:13)

M_RAS_BM_CAS_B-

M_WE_B-

M_SBS_B(0:2)

33R R207

M_SBS_B(0)

M_SBS_B(1)

M_SBS_B(2)

M_MAA_B(0)

M_MAA_B(1)

M_MAA_B(2)

M_MAA_B(3)

M_MAA_B(4)

M_MAA_B(5)

M_MAA_B(6)

M_MAA_B(7)

M_MAA_B(8)

M_MAA_B(9)

M_MAA_B(10)

M_MAA_B(11)

M_MAA_B(12)

M_MAA_B(13)

33R

R220

R22133R

R222

33R R223

33R R224

R22533R

R22633R

33R R227

33R R228

R22933R

R23033R

33R

R231

33R R232

R233

33R

R23433R

R23533R

33R R236

33R R237

33R R238

33R

R239

VTT_MEM

8,10

M_SCS_A-(0:3)

M_SCKE_A(0:3)

M_ODT_A(0:3)

M_SCS_A-(0)

M_SCS_A-(1)

M_SCS_A-(2)

M_SCS_A-(3)

M_SCKE_A(0)

M_SCKE_A(1)

M_SCKE_A(2)

M_SCKE_A(3)

M_ODT_A(0)

M_ODT_A(1)

M_ODT_A(2)

M_ODT_A(3)

Channel A Termination resistors

R208

43R

43R R209

43R R210

R21143R

43R

R212

R21343R

R214

43R

43R R215

R21643R

43R R217

43R R218

43R

R219

8,11

M_SCS_B-(0:3)

M_SCKE_B(0:3)

M_ODT_B(0:3)

M_SCS_B-(0)

M_SCS_B-(1)

M_SCS_B-(2)

M_SCS_B-(3)

M_SCKE_B(0)

M_SCKE_B(1)

M_SCKE_B(2)

M_SCKE_B(3)

M_ODT_B(0)

M_ODT_B(1)

M_ODT_B(2)

M_ODT_B(3)

43R R240

43R

43R R245

43R R246

43R

43R R248

43R R251

Channel B Termination resistors

R24143R

R242

R243

R244

R247

R24943R

R25043R

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

Document Number:

Prepared by:

A3

Jamaica

DDR2 VTT TERMINATION

XXXXXXXX

I.J. Shen

Date:

2005/4/12

REV:

3.1

PAGE:SIZE:

3012

OF

VTT_MEM

VCC1.8_DDR2

2

0

4

7

5

0

9

B

C

Channel A VTT Decoupling Caps

VTT_MEM

2

0

4

6

8

0

9

B

C

Channel B VTT Decoupling Caps

3

2

0

4

9

0

9

B C

2

1

5

0

4

0

1

B

C

2

3

9

0

4

1

0

1

B

C

2

1

7

0

4

1

0

1 B C

5

0

4

2

0

1

B

C

1

0

2

F

1

U

C

7

.

4

0

6

0

3 M C

3

0

2

4

6

0

3 M C

6

0

3

M

C

3

0

8

6

0

3 M C

3

0

6

0

4 M C

3

0

2

4

6

0

4

4 M

M

C

Channel A(Each DIMM must have 4 X 1.0UF capacitors.)

VCC1.8_DDR2

2

0

4

0

1

B C

6

0

4

0

1

B

C

2

0

4

0

4

1

0

1

B

C

2

8

0

4

1

0

1 B C

2

6

0

4

2

0

4

6

F

1

B

C

F

4

U

C

7

.

4

3

0

1

6

0

3 M C

3

0

3

6

0

3 M C

7

5

6

0

3

M

C

3

0

6

0

3

0

1

9

6

0

4

3

M

C

3

0

5

3

6

0

4

M

C

Channel B(Each DIMM must have 4 X 1.0UF capacitors.)

VTT_MEM

2

3

0

4

0

1 B C

2

7

0

4

0

1 B C

2

1

0

4

1

0

1 B C

9

5

0

4

1

0

1

B

C

VCC1.8_DDR2

2

3

7

0

4

2

0

1

B

C

Channel A

VTT_MEM

VCC1.8_DDR2

4

0

1 B C

2

0

4

0

Channel B

2

8

0

4

1

0

1

B

C

2

0

6

0

4

2

1

0

1

B

C

2

4

8

0

4

2

0

1

B

C

R

USI

Universal Scientific Industrial Co.,Ltd.

PAGE:SIZE:

REV:

13 30

OF

3.1

TITLE:

Document Number:

Prepared by:

A3

Jamaica

DDR2 VTT DECOUPLING

XXXXXXXX

I.J. Shen

Date:

2005/4/12

6

14 14

VGA_RED

VGA_GREEN

VGA_BLUE

VGA_VSYNC_5V VGA_HSYNC_5V

CB40

0402

3

1 C

2

5

2 R

X

VCC2.5V

%

1

_ R

0

5

1

VCC3

CB72

2

0

4

U7

VCC

6

1OE-1Y

1A

3

2OE-72Y

2A

4

GND

0

8

1 2

5

VGA_VSYNC VGA_HSYNC

6 6

74LVC2G125

VCC5

BAV99

D7

23

5

4

%

1

C

_

3

R

5

0

2

5

R

1

X

%

1

C

_

4

R

5

0

2

5

1

R

X

BAV99

1

D9

23

BAV99

23

%

1

_

6

R

5

0

2

5

1

R

1

L36

0.18UH

L33

0.18UH

L35

0.18UH

F

P

8

.

6

%

1

_

7

R

5

0

2

5

1

R

6

1

2

8

5

6

C

F

P

8

.

6

8

9 C

1

D10

%

1

_

5

R

5

0

2

5

1

R

VCC5

9

8

0

3

1

TH3

SMD1210P110TS

2

1346

GND1GND2

2

5

100R

100R R259

Z H M

0

7

1

2

_

L

R

1

3

_ B F

2

9

0

4

2

0

1

F

B

P

8

C

.

6

1

9

0

9

1

C

P5

VGA_PORT

6 1 7 2 8 3 9 4

10

5

11

12

13

14

15

2

1

H

7

6

1

3

5

C

2

0

4

0

_

P

A C

2

0

4

0

_

P

F

A

P

0

C

7

4

D11

BZA462A

3

R

%

1

_

2

K

2

R258

2

VGA_DDCSDA_5V VGA_DDCSCL_5V

19 19

CLOSE TO GMCH

WITHIN 750MILS OF PIN

CLOSE TO VGA CONN.

R399 18R

R402 18R

2

0

6

F

4

5

P

2

C

2

4

5

0

P

C

_

2

P

A

C

VGA_HSYNC_5V

VGA_VSYNC_5V

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

Document Number:

Prepared by:

XXXXXXXX

I.J. Shen

A3

Jamaica

VGA PORT

Date:

14

2005/4/12

REV:

3.1

PAGE:SIZE:

OF

3014

21

4

53

6

78

SB3V

15

U38

AC22

DPRSLPVR-GPIO16

AE22

A20GATE

AH28

A20M-

AG27

CPUSLP-

AG26

FERR-

AG22

IGNNE-

AF22

INIT-

AF25

INTR

AH24

NMI

AG23

RCIN-

AH21

SERIRQ

AF23

SMI-

AH22 AF21

STPCLK-

AG21

INIT3_3-

AF24

DPRSTP-_TP_2

AH25

DPSLP-

AH2

SATA0T_P

AG2

SATA0T_N

AF3

SATA0R_N

AE3

SATA0R_P

AH4

SATA1T_P

AG4

SATA1T_N

AE5

SATA1R_N

AD5

SATA1R_P

AH6

SATA2T_P

AG6

SATA2T_N

AF7

SATA2R_N

AE7

SATA2R_P

AH8

SATA3T_P

AG8

SATA3T_N

AD9

SATA3R_N

AE9

SATA3R_P

AG10

SATARBIASP

AH10

SATARBIASN

AE1

SATA_CLKP

AF1

SATA_CLKN

AF18

SATALED-

AF19

SATA_0GP_GPIO21

AH18

SATA_1GP_GPIO19

AH19

SATA_2GP_GPIO36

AE19

SATA_3GP_GPIO37

AA6

LAD0_FB0

AB5

LAD1_FB1

AC4

LAD2_FB2

Y6

LAD3_FB3

AB3

LFRAME-

AC3

LDRQ0-

AA5

LDRQ1-_GPIO23

AB1

RTCX_1

AB2

RTCX_2

AA3

RTCRST-

Y4

RSMRST-

AA4

PWROK

U5

LAN_RXD0

V4

LAN_RXD1

T5

LAN_RXD2

U7

LAN_TXD0

V6

LAN_TXD1

V7

LAN_TXD2

U3

LAN_RSTSYNC

V3

LAN_CLK

C19

LAN_RST-

W3

EE_DIN

W1

EE_CS

Y1

EE_SHCLK

Y2

EE_DOUT

R6

ACZ_SYNC

R5

ACZ_RST-

T4

ACZ_SDOUT

T2

ACZ_SDIN0

T3

ACZ_SDIN1

T1

ACZ_SDIN2

U1

ACZ_BIT_CLK

P5

SPI_MOSI

P2

SPI_MISO

P6

SPI_CS-

R2

SPI_CLK

P1

SPI_ARB

PLACE CLOSE TO ICH7 SPI USED FOR ICH7 SHOULD BE STUFF 8.2K~10K

ICH7_2

R4 24R9_1%

T113

CLOSE ICH7

8K2RN6 8P4R12

8K2RN6 8P4R78

L_AD(0) L_AD(1) L_AD(2) L_AD(3)

T7

T1 T2

8P4RRN6 8K234

8P4RRN6 8K256

19

A20GATE

3

3,15

19 19

15

H_A20M-

H_FERR-

3

H_IGNNE-

H_INIT-

3

H_INTR

3 3

H_NMI

KBREST

SERIRQ

H_SMI-

3

H_STPCLK-

3

ICH_INIT_3V-

VCC3

R522 X

21

SATA0TXP

21

SATA0TXN

21

SATA0RXN

21

SATA0RXP

21

SATA1TXP

21

SATA1TXN

21

SATA1RXN

21

SATA1RXP

21

SATA2TXP

21

SATA2TXN

21

SATA2RXN

21

SATA2RXP

21

SATA3TXP

21

SATA3TXN

21

SATA3RXN

21

SATA3RXP

R131

18 18

19

CLK_100M_SATA

CLK_100M_SATA-

SATALED-

10K

A

B

C C

VCC3

L_AD(0:3)

VBAT

R518 20K_1%

D

CM2

15,19

15,19,25

6,15,19

19 15

ICH_GPIO23

15 15

L_FRAME-

L_DRQ0-

RTX1 RTX2

RSMRST-

PWR_GD

T8

15,19,25

RSMRST-

23

E

25

ICH_SPI_MOSI

25

ICH_SPI_MISO 25 25 25

RESISTOR SHOULD BE PLACED LESS THAN 100MILS FROM ICH7 EMRTY:NO USED SPI FOR ICH7 47R:USED SPI FOR ICH7

F

ICH_SPI_CSICH_SPI_CLK ICH_SPI_ARB

JP4

1 2

23 23 23

ACZ_BITCLK

23

ACZ_SYNC

ACZ_RST-

ACZ_SDOUT

ACZ_SDIN0

SB3V

DBRESET-

R123 X

XR300

X

R130 R81X

XR85

3,5,15

T114 T115

BMBUSY-_GPIO0

SMBALERT-_GPIO11

STP_PCI-_GPIO18

STP_CPU-_GPIO20

EL_RSVD_GPIO26 EL_STATE0_GPIO27 EL_SATAE1_GPIO28

CLKRUN-_GPIO32

AZ_DOCK_EN-_GPIO33

AZ_DOCK_RST-_GPIO34

SUS_STAT-_LPCPD-

VRMPWRGD1

CPUPWRGD_GPIO49

OC5-_GPIO29 OC6-_GPIO30 OC7-_GPIO31

15

X_HEADER_2X1

RESET SW

1

23

GPIO6 GPIO7 GPIO8 GPIO9

GPIO10

GPIO12 GPIO13 GPIO14 GPIO15

GPIO24 GPIO25

GPIO35 GPIO38 GPIO39

SMBCLK

SMBDATA

SMLINK0 SMLINK1

LINKALERT-

SPKR

RI-

PWRBTN-

SUSCLK

BATLOW-

SLP_S3SLP_S4SLP_S5-

SYS_RESET-

THRMTRIP-

THRM-

INTVRMEN

CLK14

INTRUDER-

MCH_SYNC-

WAKE-

USBP0P

USBP0N

USBP1P

USBP1N

USBP2P

USBP2N

USBP3P

USBP3N

USBP4P

USBP4N

USBP5P

USBP5N

USBP6P

USBP6N

USBP7P

USBP7N

OC0OC1OC2OC3OC4-

USBRBIAS

USBRBIAS-

CLK48

TP_3

CLEAR_CMOS-

2-3 :CLEAR CMOS

AB18 AC21 AC18 E21 E20 A20 B23 F19 E19 R4 E22 AC20

T118 T11

R3 D20 A21

T119

B21

T14

E23 AG18 AC19

T121

U2

T122

AD21 AD20 AE20

C22 B22 B25

RN1 8P4R8K256 A25 A26

RN1 8P4R8K278

A19 A28 C23 C20

RN1 C21 A27

T28

B24 D23 F22

T126

A22 AD22 AG24 AF26 AF20 W4

R523 AC1 Y5

R524 1M AH20 F20

F2 F1 G3 G4 H2 H1 J3 J4 K2 K1 L5 L4 M2 M1 N3 N4

D3 C4 D5 D4 E5 C3 A2 B3

R525

D1

22R6_1%

D2

B2

F21

T95

VCC3

R5 10K

R526 X

8P4RRN1 8K234

8K212

8P4R

330K

0RR352

USB_P0 USB_P0USB_P1 USB_P1USB_P2 USB_P2USB_P3 USB_P3USB_P4 USB_P4USB_P5 USB_P5USB_P6 USB_P6USB_P7 USB_P7-

USB_ICH_OC0USB_ICH_OC1USB_ICH_OC2USB_ICH_OC3-

CLOSE ICH7

CLK_48M_USB

1 2 3

CLEAR-CMOS_3X1

AFP_PRES-

CLEAR_CMOS-

PRI_FASTCABLE-

2ND_SERIAL-

ICH_GPIO39

SMB_CLK_STBY SMB_DATA_STBY

SPKR

WORSW_ONSIO_CLK32

SLP_S3SLP_S4-

DBRESETVRMPWRGD H_PWRGDTHERMTRIP_ICHTHRM-

CLK_14M_ICH

ICH_SYNCWAKE-

24 24 24 24 22 22 22 22 22 22 22 22 24 24 24 24

24 22 22 24

18

JP7

NC CLEAR GND

ICH_GPIO0 POV_ID0POV_ID1-

SIO_WAKEICH_GPIO9 ICH_GPIO10

TEMP_THERM-

ICH_GPIO12

BRD_ID0

BRD_ID1

BRD_ID2

LAN_DISABLE-

15,24

15

16,22 15,20 15

V

3 B

S

23 15,20 24 19

V

3 B

S

19,26 19,26

3,5,15 27 3

3,15,19

15

18 6

15,25,28

JP18

1 2

BOX_2X1

Tamper Switch connector

15 15 15 15,19 15 15 15,19 15

15

25

3,15,19

19,25,28,29 19,25,28,29

VBAT

5

H_PROCHOT-

3

THERMTRIP_ICH-

6,15,19

D N G

R11

F P

8

2

1

0

4

0

_

P A

1

C

R12 4K7

PWR_GD

1

32.768KHZ

2

10M

F P

8

2

1

0

4

0

_

P A

2

C

3K

R13

U3 BATTERY

15

Q1 3904

1

2

3

CAP_0402

THRM-

15,25,28

C3

X

3,15

3,15,19

R14 1K

R17 X

FLOCK-

PRST_FWH-

CLK_33M_FWH

ICH_INIT_3V-

8

1 R

XR15

XR16

RTX1

10KR110

19 19 18 15

15

X1

15

RTX2

VBAT

1 M C

D1 BAT54C

SB3V

R

USI

TITLE:

ICH7(AC97,LAN,DMI,USB,FWH)

Document Number:

Prepared by:

A3

64

ICH_GPIO9

15

ICH_GPIO10

15

ICH_GPIO12

15,24

AFP_PRES-

15,19

SIO_WAKE-

15,20

3,5,15

15,19

15,20

15 15 15 15

15 15

WOR-

DBRESET-

WAKE-

TEMP_THERM-

ICH_GPIO23 ICH_GPIO39

POV_ID0POV_ID1-

2ND_SERIAL-

THRM-

ICH_GPIO0

H_FERR-

R20 62R

THERMTRIP_ICH-

X

U4

1

VPP

ID0 ID1 ID2 ID3

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4

TBL# WP#

RST# INIT# CLK IC

15

FWH_8M

VCC1 VCC2

VCCA

FWH0 FWH1 FWH2 FWH3 FWH4

RFU0 RFU1 RFU2 RFU3 RFU4

GNDA

GND1 GND2

BRD_ID0

BRD_ID1

BRD_ID2

9

1 R

12 11 10

9

6 5 4 3

30

8 7

2 24 31 29

7 K

4

X_FWH_32

5

8

1 R

Universal Scientific Industrial Co.,Ltd.

Jamaica

XXXXXXXX

I.J. Shen

Date:

2005/4/12

7

R143

R366 4K7 R1 8K2

R22 10K R23 1K

R148 R149

R375

R158 10K

62RR21

VCC3

32 25 27

L_AD(0)

13

L_AD(1)

14

L_AD(2)

15

L_AD(3)

17 23

18

T96

19

T97

20

T98

21

T99

22

T100

28 26 16

Jamaica ID : 110

10KR112 10K 10KR144

8K2R65

10KR24

10K 10K 8K2R374 8K2 4K7R25 10KR26

2

0

4

0

4

B C

R28

R30 4K7

R31

PAGE:SIZE:

15 30

REV:

OF

8

VCC3

FSB_VTT

2

0

4

0

5 B C

15,19

L_AD(0:3)

L_FRAME-

15,19

SB3V

XR27

4K7

XR29

4K7R32 X

3.1

A

B

D

E

F

123

45678

A

VCC5

U38

IDE_PDD(15) IDE_PDD(14) IDE_PDD(13) IDE_PDD(12) IDE_PDD(11) IDE_PDD(10) IDE_PDD(9) IDE_PDD(8) IDE_PDD(7) IDE_PDD(6) IDE_PDD(5) IDE_PDD(4) IDE_PDD(3) IDE_PDD(2) IDE_PDD(1) IDE_PDD(0)

AH14 AH13

AD12

AD14

AG13

AH15

AG16

AH17

AD16

AH16

AC15

AF14 AC14 AB13 AF12 AE12 AC12

AC13

AF13

AE14 AB15

AF16 AE15 AF15

AF17 AE17

AE16

F16

A7

F14

A12

F15 E10

C9 E11 B10 B19 B18

A9 C26

A3

B4

C5

B5

G8

F7 F8

G7

D7 C16 C17 E13

A13

C8

E7 D16 D17

F13

A14

D8

FRAMEIRDYTRDYDEVSELSTOPPAR PERRPLOCKSERRPMEPCIRSTPCICLK PLTRST-

PIRQAPIRQBPIRQCPIRQDPIRQE-_GPI2 PIRQF-_GPI3 PIRQG-_GPI4 PIRQH-_GPI5

REQ0REQ1REQ2REQ3REQ4-_GPO22 REQ5-_GPIO1

GNT0GNT1GNT2GNT3GNT4-_GPIO48 GNT5-_GPIO17

DD_15 DD_14 DD_13 DD_12 DD_11 DD_10 DD_9 DD_8 DD_7 DD_6 DD_5 DD_4 DD_3 DD_2 DD_1 DD_0

DIOWDDACKDDREQ DIORIORDY

DA_2 DA_1 DA_0

DCS3DCS1-

IDEIRQ

E C A

F R E T

N

I I C

P

ICH7_1

E C A

F R E T N

I Y

R

A M

I R

P E D

I

E C A

F R E T N

I S

S E

R

P X E I C

P

P_FRAME-

29 29

P_IRDY-

P_TRDY-

29

P_DEVSEL-

29

P_STOP-

29

P_PAR

29

P_PERR-

29

P_LOCK-

29

P_SERR-

29

P_PME-

29

PCIRST-

B

C

29 29

22

29

CLK_33M_ICH

18 19

PLTRST-

16

PCI_INTA-

16

PCI_INTB-

16

PCI_INTC-

16

PCI_INTD-

16,29

PCI_INTE-

16,29

PCI_INTF-

16,29

PCI_INTG-

16,29

PCI_INTH-

16,29

P_REQ0-

16

P_REQ1-

16,29

P_REQ2-

16

P_REQ3-

16 16

P_REQ4-

16

P_REQ5-

P_GNT0P_GNT2-

X R634

Install 0R for SPI boot support.

IDE_PDD(0:15)

D

22

IDE_PDIOW-

22

IDE_PDDACK-

22

IDE_PDDREQ-

22

IDE_PDIOR-

22

IDE_PIORDY

22

IDE_PDA2

22

IDE_PDA1

22

IDE_PDA0

22

IDE_PDCS3-

22

E

IDE_PDCS1-

22

IRQ14

F

12

3 5678

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10

C_BE3C_BE2C_BE1C_BE0-

DMI_0RXN DMI_0RXP DMI_0TXN

DMI_0TXP DMI_1RXN DMI_1RXP DMI_1TXN

DMI_1TXP DMI_2RXN DMI_2RXP DMI_2TXN

DMI_2TXP DMI_3RXN DMI_3RXP DMI_3TXN

DMI_3TXP

PERN1

PERP1 PETN1 PETP1

PERN2

PERP2 PETN2 PETP2

PERN3

PERP3 PETN3 PETP3

PERN4

PERP4 PETN4 PETP4

PERN5

PERP5 PETN5 PETP5

PERN6

PERP6 PETN6 PETP6

DMI_ZCOMP

DMI_IRCOMP

DMI_CLKN DMI_CLKP

D6

AD(31)

E6

AD(30)

B6

AD(29)

C7

AD(28)

A6

AD(27)

A8

AD(26)

B9

AD(25)

D9

AD(24)

E9

AD(23)

F10

AD(22)

F11

AD(21)

A10

AD(20)

A11

AD(19)

D11

AD(18)

C11

AD(17)

E12

AD(16)

G13

AD(15)

G15

AD(14)

C13

AD(13)

B12

AD(12)

D14

AD(11)

E14

AD(10)

C14

AD(9)

AD9

A15

AD(8)

AD8

A17

AD(7)

AD7

E17

AD(6)

AD6

A18

AD(5)

AD5

E16

AD(4)

AD4

F18

AD(3)

AD3

A16

AD(2)

AD2

C18

AD(1)

AD1

E18

AD(0)

AD0

C15

C_BE-(3)

D12

C_BE-(2)

C12

C_BE-(1)

B15

C_BE-(0)

V26 V25 U28 U27 Y26 Y25 W28 W27 AB26 AB25 AA28 AA27 AD25 AD24 AC28 AC27

F26 F25 E28

0402

CB35 E27 H26 H25

0402

CB195

G28 G27 K26

T18

K25

T19

J28

T20

J27

T21

M26

T22

M25

T23

L28

T24

L27

T25

P26

T127

P25

T128

N28

T129

N27

T130

T25

T131

T24

T132

R28

T133

R27

T134

C25 D25

AE28 AE27

24R9_1%

CLOSE ICH7

CB196

R527

CB36

AD(0:31)

C_BE-(0:3)

DMI_TXN_0 DMI_TXP_0 DMI_RXN_0 DMI_RXP_0 DMI_TXN_1 DMI_TXP_1 DMI_RXN_1 DMI_RXP_1 DMI_TXN_2 DMI_TXP_2 DMI_RXN_2 DMI_RXP_2 DMI_TXN_3 DMI_TXP_3 DMI_RXN_3 DMI_RXP_3

0402

CLK_100M_ICHCLK_100M_ICH

29

6,16 6,16 6,16 6,16 6,16 6,16 6,16 6,16 6,16 6,16 6,16 6,16 6,16 6,16 6,16 6,16

PCIE_LAN_RXDN PCIE_LAN_RXDP PCIE_LAN_TXDN PCIE_LAN_TXDP

HSI_N0 HSI_P0 HSO_N0 HSO_P0

V_PCIE_PWR

12

2K7 8P4R RN25

78

2K7 8P4R RN25

2K7 2K7 R45

RN258P4R2K7 3 4

RN258P4R2K7 5

6

R42

R3410K

16

P_REQ4-

16

P_REQ1-

16

P_REQ5P_REQ3-

16

P_REQ0-

16,29 16,29

P_REQ2PRI_FASTCABLE-

15,22

B

VCC3

78

8K2 8P4R RN7

8K2 8P4R RN712

12 8K2 8P4R RN856 8K2 8P4R RN834

RN78P4R8K2 5 6 RN78P4R8K2 3 4

RN88P4R8K2

RN88P4R8K2 7 8

PCI_INTAPCI_INTBPCI_INTCPCI_INTD-

PCI_INTEPCI_INTFPCI_INTGPCI_INTH-

16 16 16

16,29 16,29 16,29 16,29

C

D

J11

A1

6,16

DMI_RXP_3

6,16 25 25 25 25 28 28 28 28

6,16

DMI_RXN_3

DMI_RXP_2

DMI_RXN_2

DMI_RXP_1

DMI_RXN_1

DMI_RXP_0

DMI_RXN_0

D_ITMR_3P

A2

D_ITMR_3N

A3

GND3

A4

D_ITMR_2P

A5

D_ITMR_2N

A6

GND2

A7

D_ITMR_1P

A8

D_ITMR_1N

A9

GND1

A10

D_ITMR_0P

A11

D_ITMR_0N

A12

GND0

X_DMI_DEBUG_PORT

GND7

D_MTIR_3N

D_MTIR_3P

GND6

D_MTIR_2N

D_MTIR_2P

GND5

D_MTIR_1N

D_MTIR_1P

GND4

D_MTIR_0N

D_MTIR_0P

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12

DMI_TXN_3 DMI_TXP_3

DMI_TXN_2 DMI_TXP_2

DMI_TXN_1 DMI_TXP_1

DMI_TXN_0 DMI_TXP_0

6,16 6,16

E

17 18

18

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

Document Number:

Prepared by:

A3

Jamaica

ICH7(IDE Bus,PCI Bus)

XXXXXXXX

I.J. Shen

Date:

2005/4/12

REV:

3.1

PAGE:SIZE:

OF

3016

F

4

A

B

C

D

E

F

VCC3

PATA Filter

4

5

1

B

2

0

C

4

0

8

1 B

2

0

C

4

0

16,17

VCC1.5V

1

FB_100R_4A

SB3V

2

0

4

0

USB Classic filter

12 45

7

0

5

3

7

3

7

2

1

2

3

7

1

H

G

H

A

0

7

8

9

1

2

9

8

9

S

V

2

3

4

5

6

7

S

V

1

7

4

5

6

7

1

2

1

C

R

G A

4

2

H

4

1

8

1

B

A

B

5

6

3

4

7

8

9

S

V

1

2

3

4

0

1

8

9

1

S

V

3

4

5

6

8

1 R

7

6

2

1

T

6

1 B

2

0

C

4

0

V_PCIE_PWR

PCI Express PWR

2

L1

8

3

5

1

B

2

0

C

4

0

1 G A

U38

SB3V

VCC3

7

1 B

2

0

C

4

0

6

7

6

7

B

2

0

4

0

2

0

C

4

0

9

5

SB3V

V

6

1

4

7

_

E

F

C

U

2

0

4

2

0

2

3

6 B

2

0

C

4

0

7

8

B

2

0

C

4

0

5

8

7

B

2

0

C

4

0

AD13 AD18 AG12 AG15 AG19 AH11

AA22 AA23

AB12 AB20 AC16

AB22

V1 V5 W2 W7 A5

AA7

B13 B16 B27

B7

C10

D15

F9

G11

A24

C24 D19 D22

E3

G19

K3 K4 K5 K6

L1 L2 L3 L6

L7 M6 M7 N7

P7

D26 D27 D28

E24 E25 E26 F23

F24 G22 G23 H22 H23

J22

J23 K22 K23

L22

L23 M22 M23 N22 N23

P22

P23

R22

R23

R24

R25

R26

T22

T23

T26

T27

T28 U22 U23 V22 V23 W22 W23 Y22 Y23

6

8 S

S V

VCCSUS3_3_21 VCCSUS3_3_22 VCCSUS3_3_23 VCCSUS3_3_24 VCC3_3_5 VCC3_3_6 VCC3_3_7 VCC3_3_8 VCC3_3_9 VCC3_3_10 VCC3_3_11 VCC3_3_12 VCC3_3_13 VCC3_3_14 VCC3_3_15 VCC3_3_16 VCC3_3_17 VCC3_3_18 VCC3_3_19 VCC3_3_20 VCC3_3_21 VCC3_3_22 VCC3_3_23

VCCSUS3_3_1 VCCSUS3_3_2 VCCSUS3_3_3 VCCSUS3_3_4 VCCSUS3_3_5 VCCSUS3_3_6 VCCSUS3_3_7 VCCSUS3_3_8 VCCSUS3_3_9 VCCSUS3_3_10 VCCSUS3_3_11 VCCSUS3_3_12 VCCSUS3_3_13 VCCSUS3_3_14 VCCSUS3_3_15 VCCSUS3_3_16 VCCSUS3_3_17 VCCSUS3_3_18 VCCSUS3_3_19

VCC1_5_0 VCC1_5_1 VCC1_5_2 VCC1_5_3 VCC1_5_4 VCC1_5_5 VCC1_5_6 VCC1_5_7 VCC1_5_8 VCC1_5_9 VCC1_5_10 VCC1_5_11 VCC1_5_12 VCC1_5_13 VCC1_5_14 VCC1_5_15 VCC1_5_16 VCC1_5_17 VCC1_5_18 VCC1_5_19 VCC1_5_20 VCC1_5_21 VCC1_5_22 VCC1_5_23 VCC1_5_24 VCC1_5_25 VCC1_5_26 VCC1_5_27 VCC1_5_28 VCC1_5_29 VCC1_5_30 VCC1_5_31 VCC1_5_32 VCC1_5_33 VCC1_5_34 VCC1_5_35 VCC1_5_36 VCC1_5_37 VCC1_5_38 VCC1_5_39 VCC1_5_40 VCC1_5_41 VCC1_5_42 VCC1_5_43 VCC1_5_44

1 S

S V

4 E

2

3

5

4

2

4

8

1

0

2 B

1

0

1

S

V

1

6

2

D

C

B

7

6

5

3

4

2

0

1

S

V

5

8

2

1

E

D

E

D

1

2

0

9

8

1

0

1

S

V

7

1

8

E

4

3

1

S

V

1

3

2

1

2

4

5

F

G

F

5

1

0

9

7

8

6

1

2

1

S

V

3

6

8

1

4

8

6

9

2

5

2

1

G

4

3

2

7

8

5

6

2

1

S

V

4

5

6

4

2 G

9

2

1 S

S V

7

8

5

2

3

4

2

H

G

H

3

4

2

1

0

3

1

S

V

7

5

6

3

1

S

V

4

8

7

4

5

3

5

6

4

2

1

2

5

2

1

2

J

K

J

2

0

1

8

9

4

3

1

S

V

L

K

L

K

3

4

9

8

7

6

5

4

1

S

V

3

6

5

4

5

3

1

2

M

L

1

0

5

1

S

V

M

3

2

8

7

6

5

4

5

1

S

V

ICH7_3

7

1

9

0

5

6

8

1

2

1

2

1

S

V

2

6

5

4

3

1

U

31

7

8

6

5

3

4

2

S

V

6

4

5

7

2

1

U

1

0

9

2

3

2

S

V

5

3

2

6

8

7

4

1

2

V

W

V

8

6

7

5

4

2

3

S

V

5

4

2

W

0

1

9

3

4

3

S

V

7

3

4

6

2 W

5

1

4

8

2

A

Y

A

Y

A

4

8

7

6

5

4

3

2

4

S

V

4

6

2

B

A

0

9

4

5

4

S

V

4

1

6

4

1

9

6

1

2

1

B

A

7

6

5

4

3

2

1

5

S

V

8

7

2

B

A

9

8

5

S

V

1

9

5

2

3

1

C

D

C

A

5

6

3

4

1

2

0

6

5

S

V

4 D A

2

9

3

1

5

7

8

1

2

1

E

D

A

3

2

1

0

9

8

7

6

S

V

1

8

3

1

8

4

2

1

E

A

5

678

8

7

4

7

6

2

1

M

1

0

9

6

5

1

S

V

6

5

4

7

S

V

2

5

4

2

F

E

A

1

2

1

5

6

1

2

N

M

2

6

1 S

S V

7

8

7 S

S V

8

4

F

A

3

6

1 S

S V

7 S

S V

4

6

1 S

S V

9

7 S

S V

1

F A

6

5

6

1

S

V

1

0

8

S

V

8

7

2

F

A

9

8

7

6

1

S

V

VCC1_05_1 VCC1_05_2 VCC1_05_3 VCC1_05_4 VCC1_05_5 VCC1_05_6 VCC1_05_7 VCC1_05_8

VCC1_05_9 VCC1_05_10 VCC1_05_11 VCC1_05_12 VCC1_05_13 VCC1_05_14 VCC1_05_15 VCC1_05_16 VCC1_05_17 VCC1_05_18 VCC1_05_19 VCC1_05_20

VCC1_5_67

VCC1_5_68

VCC1_5_69

VCC1_5_70

VCC1_5_71

VCC1_5_72

VCC1_5_73

VCC1_5_74

VCC1_5_75

VCC1_5_76

VCC1_5_77

VCC1_5_78

VCC1_5_79

VCC1_5_80

VCC1_5_81

VCC1_5_82

VCC1_5_83

VCC1_5_84

VCC1_5_85

VCC1_5_86

VCC1_5_87

VCC1_5_88

VCC1_5_89

VCC1_5_90

VCC1_5_91

VCC1_5_92

VCC1_5_93

VCC1_5_94

VCC1_5_95

VCC1_5_96

VCC_CPU_IO_1 VCC_CPU_IO_2 VCC_CPU_IO_3

VCC3_3_26

VCCDMIPLL

VCCSATAPLL

VCCUSBPLL

VCCSUS1_5_A VCCSUS1_5_B VCCSUS1_5_C VCCSUS1_5_D VCCSUS1_5_E

VCC3_3_24

VSS171

VCC3_3_25

VSS172

VCCSUS3_3_20

VSS173

V5REF1 V5REF2

V_REF5V_SUS

VCCRTC

3

4

2

8

S

V

4

7

3

1

G

A

6

VCC_1.05V

P15 P16 P17 P24 P27 P28 R1 R11 R12 R13 AH12 AC26 AD26 AD27 AD28

F U

9

7

5

.

1

4

C

R36

R415

TDK GLF2012T100K

K

1

7

3 R

2

0

4

0

PAGE:SIZE:

VCC_1.05V

2

0

4

0

1 B

2

0

C

4

0

L2

1UH_300MA

RES_0805

REF5V_STBY REF5V

2

9 B C

REV:

17 30

OF

8

1

5 B C

2

0

4

0

VCC1.5V

XR414

10UH

3.1

A

2

5 B

2

0

C

4

0

B

C

1

1 B C

D

E

19

F

L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17

VCC1.5V

V18

A1 AB10 AB17 AB7 AB8 AB9 AC10 AC17 AC6 AC7 AC8 AD10 AD6 AE10 AE6 AF10 AF5 AF6 AF9 AG5 AG9 AH5 AH9 F17 G17

VCC3

H6 H7 J6 J7 T7

AE23 AE26 AH26

U6

VCC1.5V

AG28 AD2 C1

AA2

T15

C28

T16

G20

T17

K7

T26

Y7

T27

G12 N13

G16 N14

R7 N15

AD17 G10

F6

W5

2

3 B

5

8 S

S V

2

0

C

4

0

TITLE:

Document Number:

Prepared by:

VCC1.5V

1

16,17

3

4 B C

2

0

4

0

V_PCIE_PWR

N16 N17 N18 N24 N25 N26

P3

P4 P12 P13 P14

AB23 AC23 AC24 AC25

4

4 B C

2

0

4

0

U38

VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VCC1_5_97 VCC1_5_98 VCC1_5_99 VCC1_5_100

7

8

4

B

C

2

0

4

0

VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194

VSS195 VCC1_5_101 VCC1_5_102 VCC1_5_103 VCC1_5_104

ICH7_4

FSB_VTT

3

2

B

0

4

C

0

1R

T

5

7

H

3

P

5

1

G

I

F

C

SB3V

P

2

R

_

2

0

4

2

0

4

_

0

F U

1

.

0

5

C

D

0

A

8

e

0

s

o

l C

_

2

F

P

0

4

U

0

A

0

C

1

SB5V

R

0

1

5

3 R

R138

X

2

8 B

2

0

C

4

0

5

3

0

U

4

8

0

1

0

1

C

_

P A C

VCC3

0402

CB8

Close R7

T A

B V

R

USI

Universal Scientific Industrial Co.,Ltd.

Jamaica

ICH7(Power & Ground)

XXXXXXXX

I.J. Shen

A3

Date:

2005/4/12

5

0

8

0

_

P A C

VCC5

0R

7

VCC3

FB_31R_100MHZ

12

L23

VCORE

3

1

F

1

U

C

7

.

4

2

0

4

0

1 P C

FB_31R_100MHZ

L28

12

VCC3_CLK

61K9R512

1

5 C

F U

1

C57

22PF

X3

CAP_0402

GND

3

C58

22PF

CAP_0402

2

0

4

0

3

2

P

C

5 5

3 3

CLK_HOST_GMCH-

6 6

2

0

4

0

5

9

F

2

5

U

P

C

7

C

.

4

K

0

1

Q32 3904

1

2

3

5

0

8

0

_

P A C

14.318MHZ

1

2

3,6 3,6 3,6

2

0

4

0

CLK_HOST_CPU-

VCC3

0

4

P C

CLK_HOST_ITP-

CLK_HOST_ITP

CLK_HOST_CPU

CLK_HOST_GMCH

2

0

4

0

6

2 P C

VCC3

1

6

2 R

FB_31R_100MHZ

2

0

4

0

7

2 P C

R424 2R4_1%

5,10,11,19 5,10,11,19

FSB_SEL2 FSB_SEL1 FSB_SEL0

L2912

0

6 C

1

6 C

F U

7

.

4

3

2

6

2

R

%

1

_

9

R

9

4

VDD48_CLK

1

F

3

U

P

7

C

.

4

SMB_DATA

SMB_CLK

CLK_XTAL_OUT CLK_XTAL_IN

R393 X

NOPOP_RES_0603

2

0

4

0

3

P C

0

6

5

4

7

6

2

R

%

1

_

9

R

9

4

VCC3_CLK

2

0

4

0

R271

475R_1%

R52 0R R53 R57 0R

VDDA_CLK

33R

33R R274 33R

33R 33R

VCC3_CLK

8

7

K

2

0

R

REF0

PCIF_2

PCIF_1

PCI_5

PCI_4

PCI_3

PCI_2

PCI_1

PCI_0

USB_48

VSS1 VSS2 VSS3

VSS_48

SRC5-

SRC5

SRC4-

SRC4

SRC3-

SRC3

SRC2-

SRC2

SRC1-

SRC1

SRC0-

SRC0

DOT_96-

DOT_96

1

33R R307

52

15R R294

10

33R R295

9

33R

39R R297

33R

33R R299

C102

47PF

33R

33R R280

33R R282

33R R285

33R 33R R287

33R 33R R291

33R 33R R605

33R R292

R296

R298

R448

R28133R

R28333R

R28433R

R286

R290

R604

R29333R

8

5

4

3

56

55

54

12

2 6 51 13

32 33

30 31

27 26

25 24

23 22

20 19

15 14

3

2

0

3

R

%

1

_

9

R

9

4

CLK_14M_SIO CLK_14M_ICH

PCICLK1 PCICLK0 CLK_33M_FWH CLK_33M_SIO CLK_33M_ICH

CLK_48M_USB

5

0

2

3

4

1

0

1

0

1

3

R

%

1

_

9

R

9

4

18,19

15,18

18,29 18,29 15,18 18,19 16,18

18,19 15,18 18,29 18,29 15,18 18,19 16,18

CLK_14M_SIO

CLK_14M_ICH

PCICLK1 PCICLK0

CLK_33M_FWH

CLK_33M_SIO

CLK_33M_ICH

C65 10PF

C67 10PF

C69 10PF

10PFC63 X

10PF

XC64

10PFC66

10PFC68

15

CLK_PE_100M_GMCHCLK_PE_100M_GMCH

CLK_PE_100M_16PORTCLK_PE_100M_16PORT

CLK_100M_SATACLK_100M_SATA

CLK_PE_100M_1PORTCLK_PE_100M_1PORT

CLK_100M_ICHCLK_100M_ICH

CLK_100M_LAN_DN CLK_100M_LAN_DP

CLK_96M_DOT-

7

0

6 R

%

1

_

9 R

9

4

CLK_96M_DOT

6

7

5

4

6

0

1

6

3

R

%

1

_

9

R

9

4

6 6

28 28

15 15

28 28

16 16

25 25

6 6

U23

1

VDD1

7

VDD2

48

VDD3

11

VDD_48

17

VTT_PWRGD-

47

SDA

46

SCL

49

XTAL_OUT

50

XTAL_IN

39

IREF

53

FSB_C-TEST_SEL

16

0R

FSB_B-TEST_MODE

18

FSB_A

21

VDD_SRC1

34

VDD_SRC2

28

VDD_SRC3

42

VDD_CPU

37

VDD_A

35

R27233R

ITP_SRC6-

36

R273

ITP_SRC6

40

CPU_1-

41

R275

CPU_1

R276

43

CPU_0-

44

R277

CPU_0

38

VSS_A

45

VSS_CPU

29

VSS_SRC

ICS-CK410

(ICS954101)

PCIF_0-TP_EN

SEL0 SEL1 SEL2 Frequency

1 1 1 166MHZ 1 0 0 200MHZ 0 0 0 266MHZ

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

Document Number:

Prepared by:

A3

Jamaica

XXXXXXXX

I.J. Shen

CK410

Date:

2005/4/12

REV:

3.1

PAGE:SIZE:

OF

30

18

1

VCC3

V

15,19

SKTOCC-

25

5

2

1

_

F

E C

U

0

1

19 19 19 19

19 19

19 19 19 19 19 19 19 19

18 15

15 16 15 18

15 15

24 24

3

NVM_PROT

A

B

C

3

D

15,26

E

2

0

4

8

6

0

8

B

C

FDD_DRVDEN0

FDD_DRATE0

FDD_INDEX-

FDD_MTR0-

FDD_DR0FDD_DIR-

FDD_STEP-

FDD_WDATA-

FDD_WGATE-

FDD_TRK0-

FDD_WP-

FDD_RDATA-

FDD_HDSEL-

FDD_DISKCHG-

CLK_14M_SIO

L_AD(0:3)

L_FRAME-

L_DRQ0-

PLTRST-

TEMP_THERM-

CLK_33M_SIO

SERIRQ

SIO_WAKE-

SIO_CLK32

3 C C V

IDE_LED-

PW_LED-

H_FORCEPH_IO-

19

PS_ON-

SLP_S4-

2

0

4

3

4

0

8

B

C

2

0

4

9

0

8 B C

R9

10KR563

R429 0R

SB3V

2

0

2

4

5

0

3

8

E

B

C

0

9 B C

L_AD(0) L_AD(1) L_AD(2) L_AD(3)

2

0

4

0

22 21 20 19

18

17 16 15 14 13 12 11 10

65 62 61 59 57 56 54 63 52 55 53 99

91 75

X

77 66 94 79 80 83

100 101 102

81 86

3

0

1

6

0

1 M C

V

5

2

_

F U

0

1

SB5V

1

9 B C

U12

DENSEL DRATE0 INDEXMTR0-

DR0-

DIRSTEPWDATAWGATETRK0WPRDATAHDSEL-

9

DSKCHG-

CLOCKI14 LAD0 LAD1 LAD2 LAD3 LFRAMELDRQPCI_RESETSMIPCI_CLK SER_IRQ SIO_PME-

GPIO15 GPIOE13-FPRST-

BKFD_CUTHD_LEDGRN_LED LATCHED_BF_CUT GPIOE17

CPU_PRESENT-

GPIOE16 GPIOE14 NC1 PS_ON-

SLP_S5-

2

8

XR362

2

7

4

1

6

1

6

9

V

1

V

3

V

,

5

_

3

5

SB3V

2

0

4

0

-

2

K

E

C

O

I

O

P

L

F

G

X

0

2

0

R

)

E

K

O

I

0

1

P

:

G

T

P O

(

3

0

8

7

2

1

2

1

X

P

C

T

R

A

N

R

I

R

-

T

#

2

S

2

T

I

B

U

R

S

-

O

0

V

S

-

0

-

#

E

2

K

0

O

I

E

C

P

O

I

G

L

P

F

-

G

1

1 E O

I

P G

5

9

1

5

_

F

K

A

L

E

L

D

C

D

R

C

X

_

S

_

C

D

_

4

7

A

R

G

V

SB5V

1

9

1 B C

2

0

4

0

5

3

6

4

1

0

1

7

1

7

1

2

5

3

#

1

V

1

B

5

D

E

S

F

E

O

E

L

_ A T A

S

-

0

1 E

O

I P G

_ A D S C D D

_ V

5

V

I

R

P

-

0

G

1

_

E

L

A

C

O

D

I

S

P

C

G

D

_

C

V

C

5

C

FLOPPY

LPC

PC8375T PC8375S

FAN CONTROL

D E

A

L

D

C

S

_

2

B

M

S

V

S

A

L

S

3

P

-

D

C

_

A

L

T

-

S

D

S

3

D

C

_

S

G

S

1

S

1

R

_

R

B

M

P

M

S

M

L

W

H

S

H

S

R

S

P

9

0

8

5

7

2

8

4

8

9

6

8

9

8

-

K

Y

N

D

A

Y

3

T

L

T

B

O

_ W

P

9

1

S

G

S

_

C

T

A

R

P

_

S

R

D

_

L

M

B

_

W

S

K

A

B

M

P

R

T

L

S

M

C

A

S

_

D

B

_ B

M

S

M

5

6

S

2

1

,

5

6

1

9

2

1

,

8

2

1

,

5

1

2

1

,

9

0

1

,

5

1

3

1

2

-

H

D

_

E

D

L

H

_

D

Y

H

R

-

_

A

D

Y

E

D

R

L

N

A

_

O

M

W

I

C

L

E

R

S

Y

P

7

5

9

6

9

6

-

D

D E

E

L

D

A

P

T

_

A

E

S

D

I

2

5

2

1

3

C

M

A

W

T

_

N

A

-

F

-

D

1

6

7

E

0

L

E

_

I

O

I

S

P

C S

G

1

2

9

4

1

0

1

-

3

2

1

_

D E

H

L

C

_

A

I S

T

_

C

S

N

A

F

9

1

2

F

SCSI_LED

2

7

1

CM7

0603

Y B

VBAT

T

S

_ V

5

F E

R

8

M C

3

0

6

0

7

2

8

9

7

9

F

Y

R

B

O

T S

C

_

V

5 F E R

-

1

1 E O

I

P G

COM2

COM1

KB/MS

2

1

M

W

P

N

A

F

-

4

5

3

0

K

E

L

O

C

I

B

P

K

G

8

6

4

3

0

1

2

3

K

_

L

M

C B

W

P

K

_

N

A

F

2

1

2

,

9

1

JP17

HEADER_4X1

3

VCC3

2

0

4

0

3

9 B C

6

1

T

_

A

3

B

C

V

C V

PCIRST_OUT3#-GPIOE02-FANTACH4

GPO13-DTR_BOUT2#-RTS2#-VDDSTRAP2

SB3V

6

0

9

1

7

6

4

3

1

4

3

2

_

3

B

C

S

C

V

PCIRST_OUT1-

GPIOE12-PCIRST_OUT2-

IDERSTDRV_OD-

GPIOE07-IRTXDCD2#

GPIOE04-CTS2#-DSR2#

GPIOE03-DSR2#-SIN2

GPO12-RTS2#-SOUT2-VDDSTRAP1

GPIOE05-DCD2#-CTS2#

GPIOE06-IRRX-DTR2_BOUT2#

GPIOE01-SIN2-RI2#

DTR-_BOUT1-XOR_OUT-BADDR-

LPT

-

T

K

A

S

0

A

L

2

R

D

C

B

A

M

K

M

G

1

2

7

5

T

E

K

A

S

T

L

T

E

A

C

A

R

S

G

D

B

0

S

M

B

2

K

M

A

2

9

1

2

,

5

1

5

2

4

1

3

S

V

6

8

9

8

4

5

2

7

VCC3

R

8

0

5

3

R

1 2 3 4

3

2

0

4

0

1

4 P C

31

7

0

3

1

9

3

2

_

3

B

S

V

DCD1-

DSR1-

SIN1

RTS1-_TRIS-

SOUT1_TEST-

CTS1-

SLCT

BUSY_WAIT-

ACK-

SLIN-_ASTRB-

INIT-

ERRORAFD-_DSTRBSTB-_WRITE-

GPIOE00-SWD

7

6

S

V

0

6

1

9

1

SCSI_LED-

RI1-

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

4 8

5

JP20

19,20 19,20 19,20 19,20

DCD1-

SIN1

SOUT1

DTR1-

1102 34 56 78 9

DSR1RTS1CTS1RI1-

19,20 19,20 19,20 19,20

X_SMDHD_MM813_5X2_P2.54

For Debug only.

22R

R122

22R R132

R15122R

73 74 105 64

128 124 121 125 122 126 127 119

23 24 25 26 27 28 30 32

33 34

PE

35 36 37 38 39 40 41 42 43 44 47 48 45 50 51

103

R119

LPT_PD(7) LPT_PD(6) LPT_PD(5) LPT_PD(4) LPT_PD(3) LPT_PD(2) LPT_PD(1) LPT_PD(0)

22R

22R R153

LPT_SLCT LPT_PE LPT_BUSY LPT_ACKLPT_PD(0:7)

LPT_SLINLPT_INITLPT_ERRLPT_AFDLPT_STB-

SWD

R15222R

DCD2DSR2SIN2 RTS2SOUT2 CTS2DTR2RI2-

DCD1DSR1SIN1 RTS1SOUT1 CTS1DTR1RI1-

20 20 20 20 20 20 20 20

470R

19,20 19,20 19,20 19,20 19,20 19,20 19,20 19,20

PRST_GMCH-

PRST_LAN-

PRST_FWHPRST_PCIEX16PRST_PCIEX1-

PRST_IDE-

R83

R84

20 20 20 20 20

19

470R

GPIOE00

XR117

6 25 15 28 28

22

FLOCK-

1

JP13

2

HEADER_2X1

1

JP9

2

HEADER_2X1

19

3,15

THERMTRIP_ICH-

19

PS_ON-

VCC5

0

2

N

R

4

8

2

6

P

8

7

8

1

K

R

1

3

7

1

5

K

1

FDD_DRVDEN0

19

FDD_DRATE0

19 19

FDD_INDEX-

FDD_MTR0-

19

FDD_DR0-

19

FDD_DIR-

19

FDD_STEP-

19

FDD_WDATA-

19

FDD_WGATE-

19 19

FDD_TRK019 19 19 19

19

FDD_WP-

FDD_RDATA-

FDD_HDSEL-

FDD_DISKCHG-

1

JP3

2

DEVDEN0

43

NC

6

DRVDEN1

8

INDEX-

10

MTR0-

12

DR1-

14

DR0-

16

MTR1-

18

DIR-

20

STEP-

22

WDATA-

24

WGATE-

26

TRK0-

28

WP-

30

RDATA-

32

HDSEL-

34

DISKCHG-

FLOPPY_17X2 FLOPPY CONNECTOR

FDD CONNECTOR

4

5

6

SB3V

19

15,19

SWD

SB5V

0

2

1 R

K

1

4

7

9

2

B

0

C

4

0

C

0

4

0

_

P

F

A

P

C

0

1

VCC5

-12V

4

5

1

7

R

K

4

V

5

9

2

3

9

1

B C

GPIOE2

2

0

4

0

GND10 GND11 GND12 GND13 GND14 GND15

GND0 GND1

GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9

7

_

E

F

C

U

0

1

R376 4K7

1

7 9 11 13 15 17 19 21 23 25 27 29 31 33

ATX_PWR_CONN

13 14 15 16 17 18 19 20 21 22 23 24

3

3906

2

Q2

1

USI

TITLE:

Document Number:

Prepared by:

67

7

U15

1

NC1

2

GND

3

V+_3V3STB

4

SWD

5

ADD

6

NC2

7

NC3

LM32

Close PWM MOSFET

14

NC6

13

NC5

12

NC4

11

D2+

10

D2-

9

D1+

8

D1-

8

2 C

F P

0

1

9

2 C

F P

0

1

THERM_PCI+

2

0

4

0

_

P

A C

2

0

4

0

_

P

A C

THERM_PCI-

CPU_THERMDA

CPU_THERMDC

Hardware monitor

VCC5

SB5V

VCC3

5 E

GPIOE2

2005/4/12

C

33R

3

7 B C

J1

+3_3V11+3_3V2

-12V GND13GND2 PS_ON GND3 GND5 GND67GND7

-5VAUX +5V1 +5V2 RSVD1 GND8

+3_3V3

+5V3

GND4

+5V4

PWROK

+5VSB +12V1 +12V2

RSVD2

2

4 5 6

R359

8 9 10 11 12

ATX_POWER_P24

15,19

KBREST

15,19

A20GATE

15,19

SERIRQ

15,19

L_FRAME-

19,21

FAN_PWM_3

19,21

FAN_PWM_2

19,21 5,10,11,18,19 5,10,11,18,19

15,19,25,28,29 15,19,25,28,29

FAN_PWM_1

SMB_CLK

SMB_DATA

SMB_CLK_STBY

SMB_DATA_STBY

19

R

Universal Scientific Industrial Co.,Ltd.

Jamaica

SIO

XXXXXXXX

I.J. Shen

A3

Date:

2

+12V

V

5

2

6

_

E

F

C

U

0

1

2

0

4

F

0

U

2

.

0

R161 X

R162

R163 X

R164

R165 10K

R168 8K2

R170

R379 X

NOPOP_RES_0603

REV:

PAGE:SIZE:

OF

8

Q5

3904

A

3

B

V

5

2

_

F U

0

1

C

19

PW_ON

VCC3

XR160

10K

10KR166

8K2R167

SB3V

2K7R169

2K7

3.1

3019

D

E

F

123

L8

12 FB_31R_100MHZ

A

VCC5

D2

21

4148

B

19

LPT_PD(0:7)

LPT_STB-

LPT_PD(0) LPT_PD(1) LPT_PD(2) LPT_PD(3) LPT_PD(4) LPT_PD(5) LPT_PD(6) LPT_PD(7)

C

LPT_ACK-

19 19

LPT_BUSY

19

LPT_PE

19

LPT_SLCT

19

LPT_AFD-

19

LPT_ERR-

19

LPT_INIT-

19

LPT_SLIN-

D

7

K

4

R

4

P

8

3

2

3

5

3

5

1

N

R

7

K

4

1

4

1

9

0

6

5

6

R

RN17 8P4R33R56

RN19 8P4R33R34 RN19 8P4R33R56

RN19 8P4R33R12

7

K

4

4 R

R

4

P

8

K

8

1

2

1

3

2

N

6

N

6

R

7 K

4

R

4

P

8

2

1 N R

R18333R

33R 8P4RRN17 1 2 33R 8P4RRN17 3 4

33R 8P4RRN17 7 8

8

33R 8P4RRN19 7

100R

R175

100R R176

S

_

C

4

P

5

2

1 C

P

8

F P

0

3

F

3

P

0

3

1

A

C

R18433R

33R R288

2

0

4

0

_

P A C

F P

0

8

0

1

6

4

C

FB_31R_100MHZ 12 FB_31R_100MHZ

S

_

C

4

P

8

F

P

0

3

1

A

C

2

0

4

0

_

9

P

2

1

A

C

F

P

0

8

3

6

3

L912

L21

S

_

C

4

P

8

F

P

0

3

A

C

S

0

_

3

C

4

1

P

C

8

F

P

0

3

2

A

C

S

_

C

4

P

8

F

P

0

3

A

C

10 11 12 13 14 15 16 17 18 19 20 21 22 23

S

_

C

4

P

8

F

P

0

3

2

A

C

24 25

26 27 28

CC

456

33R 8P4RRN22 1 2

78

33R 8P4RRN21

56

33R 8P4RRN22 3 4

2

8P4R33R56

33R 8P4RRN24 5 6

P6

1 2 3 4 5 6 7 8 9

H1 H2 H3

LPT_PORT

LPT

P3

COM1

H1 H2

COM1_PORT

220PF

8P4C_S

7

CA8

220PF

8P4C_S

3

CA8

220PF

8P4C_S

1

CA6

1 2 3 4 5 6 7 8 9

10 11

Z H

2 M

0

2

1

_

L

R

1

3

_ B

1

F

C

F

P

0

2

S

_

C

4

P

8

6

A

C

F

P

0

2

S

_ C

4

P

8

6 A

C

RN22

RN21 8P4R33R12

RN21 8P4R33R34

RN22 8P4R33R78

F

P

0

2

S

_

C

4

P

8

A

C

20

C

12

220PF

5

220PF

78

220PF

EXT_RI1

8P4C_S

6

8P4C_S

RN24 8P4R33R1

RN23 8P4R33R78

CA7

CA5

C

HEADER_6X2

11 12 9

10

E

R171

D3

560K

20

EXT_RI1

EXT_RI2

4148

2

D4

2

SB3V

4

7

1 R

K

0

1

Q6 3904

1

2

3

2

7

1

K

R

0

7

4

WOR-

15

2ND_SERIAL-

15

78 56 34 1

JP14

2

S

_

C

4

P

8

F

P

0

2

5

A

C

F

RN23 8P4R33R

RN24 8P4R

S

_

C

4

P

8

F

P

0

2

7

A

C

20

12

33R 8P4RRN23

56

33R 8P4RRN23 3 4

33R34 33R 8P4RRN24 7 8

EXT_RI2

USI

TITLE:

Document Number:

Prepared by:

78

GD75232PWR

GD75232DBR

19

RY1

18

RY2

17

RY3

16

DA1

15

DA2

14

RY4

13

DA3

12

2

0

4

U21

0

_

P A C

GD75232PWR

GD75232DBR

2

0

4

0

_

U20

P A C

+12V

RY5

1

10

-12V

2

1

0

4

0

2 B C

19

RY1

18

RY2

17

RY3

16

DA1

15

DA2

14

RY4

13

DA3

12

RY5

1

10

-12V

2

0

4

0

2 B C

5 C C

V

F

9

3

P

0

C

3

5 C C V

F

8

3

P

0

C

3

R

Universal Scientific Industrial Co.,Ltd.

Jamaica

COM1,COM2,LPT1

XXXXXXXX

I.J. Shen

A3

Date:

2005/4/12

PAGE:SIZE:

V

2

1

-

V

2

1

-

20 30

REV:

OF

DCD1DSR1SIN1 RTS1SOUT1 CTS1DTR1RI1-

2

0

4

0

7

3 P C

DCD2DSR2SIN2 RTS2SOUT2 CTS2DTR2RI2-

2

0

4

0

6

3 P C

3.1

19 19 19 19 19 19 19 19

V

2

1 +

19 19 19 19 19 19 19 19

V

2

1 +

A

B

C

D

E

F

12345678

1

A

JP15

1

GND1

4

B

7

1

4

7

GND2

GND3

S-ATA-1 JP16

GND1

GND2

GND3

S-ATA-2

234 78

TXP

CP22

3

TXN

CP23

5

RXN

CP42

6

RXP

CP43

2

TXP

CP44

3

TXN

5

CP45

RXN

CP46

6

RXP

SATA0TXP

0402

SATA0TXN

0402

SATA0RXN

0402

SATA0RXP

0402

SATA1TXP

0402

SATA1TXN

0402 0402

SATA1RXN

0402

SATA1RXP

15 15 15 15

0402

CP21

2

1

4

7

1

4

7

JP2

GND1

GND2

GND3

S-ATA-1 JP12

GND1

GND2

GND3

TXP

TXN

RXN

RXP

TXP

TXN

RXN

RXP

0402

CP47

2

3

CP48

5

CP49

CP50

6

CP51

2

3

CP52

CP53

5

6

CP54

SATA2TXP

0402

SATA2TXN

0402

SATA2RXN

0402

SATA2RXP

0402

SATA3TXP

0402

SATA3TXN SATA3RXN

0402

SATA3RXP

15 15 15 15

S-ATA-2

56

VCC5

+12V

7 K

4

JP10

1

GND

2

12V

3

TACH

4

5

2

_

SYSTEM FAN CONNECTOR

F U

0

1

1 2 3 4

SYSTEM FAN CONNECTOR

CONTROL

SYS-FAN_4X1

(FAN 3)

Extra FAN

JP11

GND 12V TACH CONTROL

X_SYS-FAN_4X1

V 4

3 E C

X

5

3 E C

19

FAN_TACH_3

FAN_TACH_2

2

9 R

VCC5

X

3

9 R

+12V

FAN_PWM_3

(FAN 2)

Chassis FAN for SYSTEM

FAN_PWM_2

19

A

B

S-ATA CONN

C

VCC5

+12V

7 K

4

JP5

V

5

2

_

F U

0

1

GND

2

12V

3 4

SYS-FAN_4X1

SYSTEM FAN CONNECTOR

(FAN 1)

TACH

Chassis FAN for CPU

CONTROL

FAN_PWM_1

19

7

8

19

FAN_TACH_1

R

3

3 E C

D

C

D

H1

1 2 3 4 5 6 7 8

C_PAD_156 H2

1

E

2 3 4 5 6 7 8

C_PAD_156

H3

1 2 3 4

C

5 6 7 8

C_PAD_156

F F

H4

1 2 3 4 5 6 7 8

C_PAD_156 H6

1 2 3 4 5 6 7 8

C_PAD_156

F

4

0

P

4

1

0

C

0

1

2

0

4

0

_

P A C

CA

Screw Holes

2

0

4

0

_

P A C

1

H7

1 2 3 4 5 6 7 8

C_PAD_156

H5

1 2 3 4 5 6 7 8

2

C_PAD_156

0

X

6

5

L

0

8

0

_

1

S E

3

R

A

U

T3

PHOTO_PAD

T4

PHOTO_PAD

T5

PHOTO_PAD

T6

PHOTO_PAD

T37

IMP_END

IMP_VIA

T38

IMP_END

T39

IMP_VIA

T40

IMP_END

IMP_VIA

7.5/7.5/7.5 mils/90 Ohm

VCC5

T89

IMP_END

T90

IMP_END

5 mils/60 Ohm

T85

IMP_VIA

T86

IMP_VIA

T87

IMP_VIA

T88

IMP_VIA

VCC5

T73

T69

IMP_VIA

VCC5

T74

T70

IMP_VIA

T75

T71

IMP_VIA

T76

T72

IMP_VIA

T77

IMP_END

T78

IMP_END

T79

IMP_ENDIMP_END

T80

IMP_END

T81

IMP_VIA

T82

IMP_VIA

T83

IMP_VIA

T84

IMP_VIA

5/7/5 mils/100 Ohm

56234

T91

T93

IMP_VIA

T94

T92

IMP_VIA

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

Document Number:

Prepared by:

A3

Jamaica

FAN X 3 , S-ATA2 X 3

XXXXXXXX

I.J. Shen

Date:

2005/4/12

7

REV:

3.1

PAGE:SIZE:

OF

3021

8

E

12345678

A

15

TH6

1.60A

5V_DUAL

1

TH2

2

USB_ICH_OC1-

F P

2

0

3

0

C

0

1

1.60A

201209-0030P-N1

FB L56

12

V K

1

7

9 R

2

F

0

P

4

5

0

2

0

_

2

8

C

0

P

9

K

1

R

A C

15

USB_P5-

15

USB_P5

USB_P4-

15

USB_P4

15

NOPOP

15

USB_P2-

15

USB_P2

15

USB_P3-

USB_P3

15

0

1

6

_

3

F

E

U

C

0

3

0R8P4R RN2978

12

0R8P4R RN2934

T5W6560E-900T05

3

45

1

27

1

27

3

45

0R8P4R RN3034

0R8P4R RN3056

78

L19

L20

0

2 M C

C

RN298P4R 0R 5 6

RN298P4R 0R

6

8

6

2

RN308P4R 0R 1

RN308P4R 0R

REAR USB CONNECTOR

P13 USB_4STACK

1 2 3 4

5 6 7 8

9 10 11 12

13 14 15 16

5

2

3

6

4

1

H

2

3

6

4

1

5

H

C

F

1

P

N

0

-

201209-0030P-N1

FB L37

12

V K

1

6

2

4 R

2

0

4

0

7

_

2

P

4

K

A

1

R

C

0

1

8

_

3

F

E

U

C

0

3

6 M C

C

5V_DUAL

D13

1

6

CH4

CH1

5

VN2VP

3

CH24CH3

X_CM1213-04SO

CB192

2

0

4

0

_ X

2

0

4

0

2

2 L

D14

1

CH1

CH4

2

VN

VP

CH23CH3

X_CM1213-04SO

C

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

IDE Header,USB port X 4,K/B-Mouse port

Document Number:

Prepared by:

A3

Jamaica

XXXXXXXX

I.J. Shen

Date:

7

P

2

4

0

3

4

0

_

-

P

9

A

0

2

6

C

1

2

0

C

2

5V_DUAL

6 5 4

CB194

2

0

4

0

4

0

_ X

C

REV:

3.1

2005/4/12

PAGE:SIZE:

OF

3022

5

N

R

K

0

1

FB_1000R_100mA

L13

19

MSDATA

19

19 19

MSCLK

KBDATA

KBCLK

B

C

12

L14

12

FB_1000R_100mA

L15

12

L16

1

2

FB_1000R_100mA

2

0

F

9

7

4

8

P

0

_

C

3

P

3

A C

2

0

4

0

_

P A C

F

8

P

0

C

3

Z H M

0

7

1

_

L

R

1

3

_ B F

MOUSE

P1

13

7 8

14

2

0

4

0

_

P

2

A

0

4

6

F

0

C

4

P

B

0

C

3

2

0

4

0

_

P

A C

F

0

9

P

0

C

3

9 10 11

15

12

16

1

2

17

3

4

5

6

PS2_KB_MOUSE KEYBORARD

Z

H M

0

8

1

_

L

R

1

3

_ B F

C

VCC5

IRQ14

VCC3

2 K

8

4

9 R

K

0

1

6

9 R

JP1

1

REST-

IDE_PDD(7)

7

IDE_PDD(6)

K

4

IDE_PDD(5) IDE_PDD(4) IDE_PDD(3) IDE_PDD(2)

5

9

IDE_PDD(1)

R

IDE_PDD(0)

3

PDD(7)

5

PDD(6)

7

PDD(5)

9

PDD(4)

11

PDD(3)

13

PDD(2)

15

PDD(1)

17

PDD(0)

19

GND1

21

PDDREQ-

23

PDIOW-

25

PDIOR-

27

PIORDY

29

PDDACK-

31

IRQ

33

PDA1 PDA0 PDCS0PDLED-

PRI_FASTCABLE-

35 37 39

GND2 PDD(8) PDD(9)

PDD(10) PDD(11) PDD(12) PDD(13) PDD(14) PDD(15)

GND3

GND4

GND5

GND6

PDA2

PDCS1-

GND7

2 4

IDE_PDD(8)

6

IDE_PDD(9)

8

IDE_PDD(10)

10

IDE_PDD(11)

12

IDE_PDD(12) IDE_PDD(13)

14

IDE_PDD(14)

16 18

IDE_PDD(15)

22 24 26 28

28

30 32

NC

34 36 38 40

PRI_FASTCABLE-

IDE_PDA2 IDE_PDCS3-

IDE_PDD(0:15)

15,16 16 16

D

PRST_IDE-

19

E

16

IDE_PDDREQ-

16

IDE_PDIOW-

16

IDE_PDIOR-

16

IDE_PIORDY

16

IDE_PDDACK-

16

IDE_PDA1

16 16

IDE_PDA0

IDE_PDCS1-

16

IDE_PDLED-

19

15

5V_DUAL

1

2

16

USB_ICH_OC2-

IDE_PRIMARY

F U

4

7

2

X

4

C

0

.

0

F

12

345678

A

B

C

D

E

F

1 4

2

3

5

6

7

8

A

CM27

CB64

CM4

R631 2K2

R632

0RR633

0402

2K2R356

2K2

U11

2

1KR630

GPIO_2

3

GPIO_3

5

SDATA_OUT

6

33RR127

BIT_CLK

8

SDATA_IN

10

33RR129

SYNC

11

RESET-

45

NC4

X

46

NC5

47

EAPD

48

SPDIF-OUT

12

PCBEEP

13

SENSE_A-SRC_B

14

PORT-E_L

15

PORT-E_R

16

PORT-F_L

17

PORT-F_R

18

CD_L

19

CD_GND

20

CD_R

21

PORT-B_L

22

PORT-B_R

23

PORT-C_L

24

PORT-C_R

42

AVSS2

SENSE_B-SRC_A

AD1981HD

A

VCCA

CM17

0R

CM23

0R

C6 2.2UF

C7

2.2UF

R126 33R

R128 33R

C146 X

CAP_0402

R133

2K2R66

15

ACZ_SDOUT

15

ACZ_BITCLK

15

ACZ_SDIN0

15

ACZ_SYNC

15

ACZ_RST-

B B

24

MIC1

24

C

MIC2

24

LINE_L

24

LINE_R

VREF_FILT

MIC_BIAS-B

MIC_BIAS-C MIC_BIAS-F

MIC_BIAS-D

MONO_OUT

PORT-A_R PORT-A_L

PORT-D_R PORT-D_L

DVDD1 DVDD2

DVSS1 DVSS2

AVDD1 AVDD2

GPIO_0-JS_1

AVSS1

GPIO_1-JS_0

27 28

29 30

31

NC1

32

33

NC2

34

37

41 39

36 35

1 9 4 7

25 38 43

26 40

NC3

44

RES_0805

D

A

VCCA

A

24

MB_B

VCCA

Close SSM2211

20KR70

Close SSM2211

MONO_OUT

VCC3

2

0

4

9

0

6 B C

JS0

V

0

4

5

0

1

2

7

4

_

B

E

F

C

U

0

1

24

220UF_10V

CE42

220UF_10V

CE43

L_LOUT_R

L_LOUT_L

24

+12V

MC78M05CDT

1

V

5

4

2

4 E C

U9

3

D N

+5V

VIN

G

2

_

F U

0

1

5

4 E

C

A

VCCA

V

5

2

_

F

U

0

1

2

0

4

1

0

7 B C

A

VCCA

2

0

4

7

6

0

6

B

C

V

0

5

4

9

0

2

3

_

E

F

C

U

0

1

A

15,23

SPKR

VCC3

Disable Timeout Feature (No Reboot)

1

4

1

X

R

2

4

1 R

K

0

1

VCC5

Q30

R146

1K

3904

1

2

F

0

6

P

4

3

0

_

C

0

P

1

A

0

5

C

BUZZER LOGIC

3

1 R

R

7

4

SP1

1

POS

2

NEG

SPKR_NEG

A

C

D

MONO_OUT

E

15,23

SPKR

R124

47K

2

F

5

2

1

7

R

K

4

0

P

4

3

0

_

C

0

P

1

A C

A

CB61

R135

20K

0402

U8

1

SHUTDOWN

BYPASS +IN3+V

4

-IN

VOUT_B

VOUT_A

8 72

-V 6

5

SSM2211

2

0

4

2

0

6 B C

R136

30K

F

A

1

2

0

4

8

0

6 B C

A

BOX_2X1

2 1

E

JP6

Mono Output

R

USI

Universal Scientific Industrial Co.,Ltd.

F

PAGE:SIZE:

REV:

23 30

OF

83

3.1

TITLE:

A

Document Number:

Prepared by:

A3

45

Jamaica

AC97/Azalia CODEC

XXXXXXXX

I.J. Shen

Date:

2005/4/12

762

678

SB3V

3

0

6

0

3 M C

AFPIO Connector

JP19

AGND11AGND2

3

LMAIN

5

RSW

7

RMAIN

9

LSW

11

MICR

13

MICL

15

NC

17

IDE_LED_R

19

PWR_LED_R USB5V121USB5V2

23 24

AFP_PRESDGND325DGND4

27

USBP6+28USBP6DGND529DGND6

31

USBP7+32USBP7DGND733DGND8

AGND3 AGND4 AGND5 AGND6 AGND7

AGND8 PWRBTN IDE_LED

PWR_LED

DGND2

2 4 6 8 10 12 14 16 18 20 22

26

30

34

Place close to ICH7

VCC3

68RR180

VCC5

2

R

8

0

1

3

R

USB_P6USB_P7-

9

7

1

K

R

4

2

0

4

0

2

B C

5V_DUAL

1

8

1 R

X

SW_ON-

8

R

7

0

1

3

R

3

15 15

AFPIO_2X17_P2.0MM

A

R387

CM10

100R

2

0

4

5

0

K

5

2

3

1

P

R

C

A

VCCA

4

3

1 R

7

3

X

E C

23

X

R354 0R

MB_B

23

A

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

AFPIO,Rear USB X 2,Line in,Line out

Document Number:

Prepared by:

A3

Jamaica

XXXXXXXX

I.J. Shen

Date:

2005/4/12

REV:

3.1

PAGE:SIZE:

OF

3024

867

A

15

B

C

D

E

F

5V_DUAL

L_LOUT_L

23 24

L_LOUT_R

23 24

19 19

15

15 15

5

1

1.60A TH5

F

2

P

1

0

C

0

1

LOUT_R LOUT_L

IDE_LEDPW_LED-

AFP_PRES-

USB_P6 USB_P7

201209-0030P-N1

FB

12

2

K

1

4

5 R

2

0

4

2

5

0

5

_

K

P

1

R A C

7

5

1

K

1

R

L6

V

0

1

9

_

2

F

E

U

C

0

3

6

5

1

K

1

R

AA

R82 4K7

7

K

4

1

4

3

4

R

2

L58

4K7R67

L51

12

FB_1000R_100mA

L52

12

FB_1000R_100mA

2

0

4

F

0

P

_

0

P

7

A

4

C

1

4

1 C

12

2

0

F

4

P

0

_

7

P

4

A C

0

4

1 C

L59

CA

A

L39

FB_1000R_100mA

12

LIGHT BLUE

JACK_LINE_IN_FOX

1 2 3 4 5

3

2

F

1

P

C

0

7

4

L

R

FB_1000R_100mA

2

0

4

0

_

P A C

CA

P11

L53

12

A

15

USB_ICH_OC3-

1 34

A

LINE_L

23

LINE_R

23

9

8

1

x

C

B

U

L50

FB_1000R_100mA

12

7

2

F

1

P

C

0

7

4

LIGHT GREEN

U

5

0

8

0

_ R

0

JACK_LINE_OUT_FOX

1

L

2 3 4

R

5

FB_1000R_100mA

L48

LOUT_L

24

C

23 24

JS0

LOUT_R

12

L49

FB_1000R_100mA

F

P

0

7

4

2

0

4

0

_

P A

6

2

C

2

1

C

2

0

4

0

_

P A C

FB_1000R_100mA

L24

12

FB_1000R_100mA

L57

12

CA

Z

2

H M

0

5

6

0

5

2

1

L

_

X

R

1

3

_ B

1

F

A

FB_1000R_100mA

2

0

4

0

_

P A C

CA

P10

L54

12

A

D

5V_DUAL

2

1

1.60A TH4

USB_ICH_OC0-

15

E

USB_P0- USB_P1-

15

USB_P0

15

K

1

2

4

4 R

8

F

3

2

P

4

1

0

4

0

C

2

R

0

K

1

2

1

0

4

0

_

P

A C

T5W6560E-900T05

1

8

27

NOPOP

L62

6

0R8P4R RN285

8

F

REAR USB CONNECTOR

RN288P4R 0R 7

201209-0030P-N1

V

0

1

8

_

7

F

E

U

C

0

3

1 2

X_CM1213-04SO

FB

12

L25

5 M C

P8

RJ45-USB-F-1G_USB

U1 U5 U2 U3 U7 U4 U8

D12

6

CH1

CH4

VN5VP

4

CH23CH3

R186

CM9

100R

MIC2 MIC1

3

0

6

0

23

0603 0603

2

0

4

7

0

9

1 P C

K

7

3

1 R

C

RN28 8P4R0R12

U6

H3

H4H5

H6

3

4

5

6

H

5V_DUAL

C

CB190

2

0

2

0

4

0

_ X

NOPOP

1

N

-

7

P

L

0

3

0

-

9

0

2

1

0

2

T5W6560E-900T05

L62

6

F P

0

7

2

4

0

4

0

_

P

2

A

3

C

1 C

0R 8P4RRN28 34

3

45

USB_P1

15 15

A

C

1 3

2 54

SB2.5V

2

0

4

0

SB3V_LAN

X

4

1

5

C

0

8

0

_

P

F

A C

U

2

5

1

3

2

0

C

4

0

7

2

5

F

5

7

0

U

1

8

B

7

0

B

.

C

_

4

C

P A C

LAN_NVM_CSLAN_NVM_SK LAN_NVM_SI LAN_NVM_SO LAN_SPI_ARB

NVM_PROT NVMT_TYPE NVM_SHRD

100_LEDACTIVITY1000_LED-

19,25

25

SB3V_LAN

5

1

2

1

0

5

4

C

0

8

0

_

P

7

F

8

A

1

U

C

7

B

.

4

C

BCP69T1

R1151R

RES_1206

4

1

5

0

C

8

0

_

F

P

U

A

0

C

1

5

2

0

4

0

3

7

1

B C

25 25 25 25 25

19,25 25 25

25 25 25

NVM_PROT

NVM_SHRD

NVMT_TYPE

3

Q3

2

3

1

5

C

0

8

0

_

P

F

A

U

C

7

.

4

MDI_0+ MDI_0MDI_1+ MDI_1MDI_2+ MDI_2MDI_3+ MDI_3-

6

4

2 B C

STUFF TO DISABLE SPI NVM PROTECTION

SB3V_LAN

R

1

6

1

1 R

3

1

BCP69T1 Q7

2

7

3

1 C

F U

7

.

4

SB2.5V

%

1

_

9

R

9

4

7

8

4

5

R

2

9

0

4

0

2 B C

R140

R137 3K3

8

3

1

6

C

0

2

1

_ S

F

E

U

R

7

.

4

1R R428

RES_1206

5

0

8

0

_

P

A C

63

L72

BLM18BD601SN1D

12

%

1

_

9

R

9

4

2

0

1

9

5

4

5

R

2

0

4

5

0

2 B C

Place these components

Place these components close to the Chip.

close to the Chip.

15

ICH_SPI_MISO

15

ICH_SPI_MOSI

ICH_SPI_CLK

15 15

ICH_SPI_CS-

X

STUFF FOR SHARED SPI

STUFF FOR SPI FLASH

EMPTY FOR SPI EEPROM

25

LAN_NVM_SO

25

LAN_NVM_SI

25

LAN_NVM_SK

LAN_NVM_CS-

25

LAN_SPI_ARB

15

ICH_SPI_ARB

5

4

1

2

0

5

C

4

0

8

0

_

P

0

8

F

A

1

C

U

B

2

C

9

3

1

5

0

C

8

0

_

P

F

A

U

0

C

1

6

2

4

1 C

F U

0

1

SB1.2V

2

0

4

0

7

1 B C

2

0

4

3

0

3 B C

%

1

_

9

R

9

4

5

6

5

R

2

1

0

4

5

0

2 B C

5

0

8

0

_

P A C

2

0

4

0

3

8

1 B C

L10

STUFF FOR NON-SHARED SPI

STUFF FOR NON-SHARED SPI PLACE CLOSE TO LAN

PLACE CLOSE TO LAN

PLACE CLOSE TO LAN EMPTY FOR SHARED SPI

EMPTY FOR SHARED SPI

R301 8K2

GbE CONN : 0892-1XX1-62

P8 RJ45-USB-F-1G_RJ45

L1

VCC25_1

L2

YELLOW-

D0+

L3

D0-

L4

YELLOW

D1+

L5

D1-

L6

GREEN-

D2+

L7

D2-

L8

D3+

ORANGE-

L9

D3VCC25_2

1

2

7

H

JP8

1 2

HEADER_3X1

3

PLACED CLOSE TO LAN FLASH

PLACED CLOSE TO LAN FLASH EMPTY:NON-SHARED SPI

EMPTY:NON-SHARED SPI

EMPTY:NON-SHARED SPI 0R:SHARED SPI FOR IC H7 A ND 82573

0R:SHARED SPI FOR IC H7 A ND 82573

PLACE CLOSE TO FLASH WITHIN 100MIL

EMPTY FOR NON-SHARED SPI

0R FOR NON-SHARED SPI

USI

TITLE:

Document Number:

Prepared by:

1

SB3V

L3

V

A

5

0

2

3

_

F

E C

U

0

1

SB1.2V

2

0

4

0

8

4

3

B

15,28

15,19

16 16 16 16 18 18 19

15 25

25

B

C

PCIE_LAN_TXDP PCIE_LAN_TXDN PCIE_LAN_RXDP PCIE_LAN_RXDN

CLK_100M_LAN_DP

CLK_100M_LAN_DN

LAN_DISABLE-

LAN_DISABLE_A13LAN_DISABLE_D12-

B

C

VCC3

201209-0030P-N1

SB3V_LAN

8

9

C

5

F

0

U

8

7

0

.

_

4

P A C

PRST_LAN-

WAKE-

RSMRST-

SB3V_LAN

2

0

5

4

0

8

0

_

P

9

4

A

B

C

2

0

4

0

3

4

5

B

C

D

15,19,28,29 15,19,28,29

E

SMB_CLK_STBY

SMB_DATA_STBY

25

LAN_DISABLE_A13-

25

LAN_DISABLE_D12-

4K99_1%

1

D N

G

2

0

1

0

F

1

P

C

2

4

F

1

0

P

_

C

2

P

2

A

C

F

1

2 C

5

F

0

U

8

7

0

.

_

4

P A C

0402

R102 R106

R107 X

R108 3K3

R99 R1003K3

X2

25MHZ

2

0402

CB55

R118 0R

T12 T13

T29

3K3 X

T41

T44

T46 T47

T51 T52 T53 T54

T55 T56 T57 T58 T59 T60 T61 T62 T63 T64 T65

T66 T101 T102 T103 T104 T116

2 41

4

VCC25_8 VCC25_9

MDI0_P MDI0_N

MDI1_P MDI1_N

MDI2_P MDI2_N

MDI3_P MDI3_N

NVM_CS-

NVM_SK

NVM_SI

NVM_SO

JTMS

JTCK JTDO

CTRL_12 CTRL_25

VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46

3

4

3

_

S

V

1

0

1

G

SB2.5V

J5 K13 L12 M4 N7 B1 B2

MDI_0+

C13

MDI_0-

C14

MDI_1+

E13

MDI_1-

E14

MDI_2+

F13

MDI_2-

F14

MDI_3+

H13

MDI_3-

H14

B10

47RR114

C9

R139 47R

A9 B9 B4

A5 A6 D3

B11 C11 A12

N4 P4

JTDI

N5 P6

M12 N13 P13 L14 L13 M14 M13 N14

P3 A4

B5

D11

NC1

J13

NC2

L8

NC3

M5

NC4

M7

NC5

M9

NC6

N9

NC7

P14

NC8

H9 H10 K2 K12 L6 L11 M6 N1 N12 P8

5

6

3

_

S

V

4

1 G

T117 T120 T123 T124

T125 T139 T147 T148 T149 T150 T151 T152

R113 R109 3K3

3

3 C

F U

0

1

SB2.5V

2

0

4

0

6

9

B

C

U5

VCC12_1 VCC12_2 VCC12_3 VCC12_4 VCC12_5 VCC12_6 VCC12_7 VCC12_8 VCC12_9 VCC12_10 VCC12_11 VCC12_12 VCC12_13 VCC12_14

J6

VCC12_15

J7

VCC12_16

J8

VCC12_17

J9

VCC12_18 VCC12_19 VCC12_20 VCC12_21 VCC12_22 VCC12_23 VCC12_24 VCC12_25 VCC12_26 VCC12_27 VCC12_28 VCC12_29 VCC12_30

PERXP PERXN PETXP PETXN PE_CLK_P PE_CLK_N PERSTPEWAKE-

LAN_PWR_GOOD DEV_OFFTEST ISOL_TEX-REVS8 PHY_REF ISOL_TCK-REVS9 DOCK_IND AUX_PRESENT

PHY_TSTPT HS_DACN HS_DACP ALT_CLK125

SMB_ALRTSMB_CLK SMB_DATA

THRMDP THRMDN

SDP0 SDP1 SDP2 SDP3

XTAL1 XTAL2

TEST0 TEST1 TEST2

J1

TEST3

J2

TEST4

J3

TEST5 TEST6 TEST7 TEST8 TEST9 TEST10 TEST11 TEST12 TEST13 TEST14 TEST15 TEST16

1

_ S

S V

1 A

2

_ S

S V

3 B

SB3V_LAN

4

3

_

S

V

2

0

7

C

B

(1.2V)

5

_ S

S V

1 C

0

2

1

9

7

3

2

A

3

2

1

_

3

C

V

8

6

1

3

D

F

4

5

_

3

C

V

2

4

P

N

M

J

1

2

0

9

7

8

6

1

_

3

C

V

(3.3V)

1

2

1

4

E

L

6

5

4

3

1

_

3

C

V

2

5

4

5

3

1

6

1

J

H

G

A

B

7

6

5

4

3

2

1

_

5

2

C

C V

V

(2.5V)

V

VCC25_10 VCC25_11 VCC25_12 VCC25_13 VCC25_14

82573E

15mm X 15mm

3

1

2

0

1

7

8

9

6

_

S

V

7

6

2

4

5

2

1

D

C

7

6

5

4

1

_

S

V

2

3

8

7

6

5

4

1

E

D

4

2

3

1

9

0

8

1

2

1

_

S

V

8

9

E

6

5

2

_

S

V

4

5

0

8

6

7

1

F

E

NVMT_TYPE

LED0_SPD100LED-

LED1_TRAFFICLED-

LED2_SPD1000LED-

LAN_RXD2-RSVD5 LAN_RXD1-RSVD4 LAN_RXD0-RSVD3

LAN_TXD2-CLK_VIEW

LAN_TXD1-RSVD2 LAN_TXD0-RSVD1

LAN_RSTSYNC-RSVD6

LAN_CLK-RSVD7

0

1

9

7

8

3

2

_

S

V

4

7

8

1

9

0

1

F

G

F

NVM_REQ

NVM_PROT

NVM_SHRD

EN25_REG

2

3

_ S

S V

9 G

SB1.2V

A10

C4 C5

F12 G12 G13

G6 H11 H12

H6

H7

H8

J10

J11

K3

K4

K5

K6

K7

K8

K9 K10 K11

L5

L9

L10

F2 F1

D1

CB56

C1

G1

G2

P7

P10

R361

X

P5

L7 A13 D10 D12 D14

C3

C6

B14 B13 B12

N10

N11

P11

M11

L3

L2

A8

B8

C8

C7

K14

J14

H1

H2

H3

K1

L1

M1

M3

N2

P1 N3 M8

P9 E3

A14

3

7

Y

P35-152-19W9

P35-152-19W9 JW0C5K01U-X02

JW0C5K01U-X02

D2D2D2

D2

D4D4D4

D4

D1D1D1

D1

GGG

G

D3D3D3

D3

OOO

O

SB3V_LAN

D1

150R

D2

R121

D3

D4

8 H

C

R289 X

R425

X

R306 X

X

PLACED CLOSE TO ICH7 FLASH

PLACED CLOSE TO ICH7 FLASH EMPTY:NON-SHARED SPI

EMPTY:NON-SHARED SPI

EMPTY:NON-SHARED SPI 0R:SHARED SPI FOR ICH7 AND 82573

0R:SHARED SPI FOR IC H7 AN D 82573

0R:SHARED SPI FOR ICH7 AND 82573

5

6

2

9

5

0

7

3

4

3

R

X

1

5

8

7

5

0

5

0

3

4

3

4

R

0RR413 R412 0R R159 0R R267 0R

0R FOR NON-SHARED SPI

R268

X

R

Universal Scientific Industrial Co.,Ltd.

ACTIVITY-

100_LED1000_LED-

U10

15

D

16

C

7

S-

9

W-

1

X

9

8

0

4

R

HOLD-

13

NC7

14

NC8

X_M25P16

U14

5

SI

6

SCK

1

CE-

3

WP-

7

HOLD-

X_SST25LF040A

SB3V_LAN

3

K

3

1

0

1

4

R

U17

5

SI

6

SCK

1

CE-

3

WP-

7

HOLD-

SST25LF040A

Jamaica

LAN(Intel 82573 Lan)

XXXXXXXX

I.J. Shen

A3

Date:

2005/4/12

7

PAGE:SIZE:

8

25

SB3V_LAN

25

2

8

VCC

Q

3

NC1

4

NC2

5

NC3

6

NC4

11

NC5

12

NC6

VSS

10

8

VCC

2

SO

VSS

4

CB188

R279

8

PLACE CLOSE TO LAN FLASH

VCC

2

SO

VSS

4

REV:

3.1

25 30

OF

8

47R

0402

2

0

4

2

0

4

0

_

9

8

X

1

B C

0.1UF_0402

A

B

C

D

E

F

6

0

1

2

V

5

3

0

C

.

8

6

0

_

F

P

U

A

0

C

1

+1.5V/10A

VCC1.5V

V

3

7

.

E

6

_

C

F U

0

5

1

VCC1.5V

R101 X

10K

3

BAT54C

2

VCC3

0.1UF

CAP_0402

0.1UF

CAP_0402

V

3

.

6

_

F U

0

1

8 E C

D5

1

C45

C91

7

4

5

0

C

8

0

_

P

A C

2

X

V

5

3

0

.

8

6

0

_

F

P

U

A

0

C

1

L11

2.67UH

V

3

.

6

_

F U

0

5

1

VCC3

1

Q10 X_3904

3

VCC2.5V

VCC1.5V

8

4 C

R

0

3

1

VCC5

FOR EMI.

V

5

3

0

.

8

6

0

_

F

P

U

A

0

C

1

3

0

X

X_MMBT4403

6

8 R

7

3 C

1 R

0

V

2

0

1

E

_

C

F U

0

5

1

2 R

2

F P

0

1

R104

2

Q9

VCC3

2

1 M C

2

0

4

0

_

P A C

X

316R_1%

CAP_0402

INDUCTOR_DIP

3

0

6

0

2

3

(252)

2

3

+12V

0.1UF

X

C93

0.1UF

X

C116

(252)

1.2UH

Q8 IRFR3707Z

Q11 IRFR3707Z

SLP_S3-

VCC3

5V_DUAL

L10

1.2UH

V

0

9

4 C

V

5

3

0

.

8

6

0

_

F

P

U

A

0

1

C

C43

X

CAP_0402

0.1UF

0

5

V

5

3

0

C

.

8

6

0

CM18

_

F

P

U

A

0

1

C

3 C C V

FOR EMI.

0

1

_

CE26

F U

0

5

1

CE28

F U

0

5

1

+1.8V/14A

VCC1.8_DDR2

2.67UHL4

5

.

2

2 R

8

2

1

4 R

2

F

0

6

P

4

9

0

_

C

0

P

1

A C

2

P

_

0

1 E C

2

1

V

E

0

E

1

C

_

F

U

0

7

4

VTT_MEM

2K_1%R76

C42 X

+0.9V/2A

VTT_MEM

2

0

4

1

0

4

B C

5

.

2

8

P

1

_

E

V

C

0

1

_

F U

0

7

4

6

4 E C

5

.

2

P

_

4

3

1

V

E

0

E

1

C

_

F

U

0

7

4

5

.

2

P

_

0

4

V

E

0

1

C

_

F

U

0

7

4

VCC1.8_DDR2

5

.

2 P

_

7

4

V

0

E

1

C

_

F U

0

7

4

5

.

2

P

_

8

4

V

0

1

_

F U

0

7

4

5

V

C112

0

E

8

1

C

4.7UF

0

_

F

P

U

A

0

7

C

4

CAP_0402

R75

39K2_1%

2

0

4

0

2

4 B C

R422 24K

R417 0R

C94X

0R

C95

X

CAP_0402

7

7 R

SB5V

5V_DUAL

3

%

1

_

6 K

1

100UF_25V

0

6

K

3

0

R

0

1

D8 BAT54A

1

2

0

4

0

CP9

X

5

4 B C

Q24

IRLR3715Z

Q25

IRLR3715Z

0402

CE73

R

0

3

4

2

1

3

(252)

2

1

3

(252)

R56 X

1

0

6

X

R

FSB_VTT

L7

0

0R R73

XC18

R599

R71

1K_1%

CP18

0

6 R

2K_1%

K

1

5

2 B C

R10 2K_1%

2

0

4

0

12

2

23

19

0402

17

18

21

20

10

11

R72

13

14

2

6

F

0

8

4

U

1

0

2

_

C

2

.

P

0

A C

+12V

7

8

R

4

R

1

8 7 6

R111

1

0R

3

0

3

6

0

1 M C

CB2

0402

2R2

PHASE

UGATE PVCC VCC LGATE

ISL6612ACB

R90 4R7

R89

U43

1 2

BOOT

3

PWM

45

GND

1.05V/2A

+1.2V/6.2A

3,27 15,19,26 15,19,26

FSB_VTT

5

P

0

9

1

1 E

D

_

C

V

0

1

_

F

U

0

1

VTT_PWRGD

SLP_S3SLP_S4-

VCC_1.05V

9 E C

5

0

8

0

C92

_

P

4.7UF

A C

2KR392

%

1

_

2

9

6

K

2

R

39K2_1%

R91

VCC1.5V

CM15

0603

2

Q64

VCC1.5V

3

1

3

IRLR3715Z

1

619R_1%

Q202

IRLR3715Z

1

Q65 X_NDS351AN

2

(252)

V

C17

0

1

4.7UF

_

F U

0

3

(252)

CB197

2

0

4

0

C19

4.7UF

U2

VIDPGD

S3S5-

PWM4

COMP4

FB4

DRIVE3

FB3

DRIVE2_U

FB2

DRIVE2_L

VREF_IN

SB5V

ISL6548ACR

+12V

R389 4R7

3

0

9

6

0

4

M C

0805

1

3

V

Y

2

B

1

S

P

V

5

DDR_VTTSNS

3

1

2

D

N

G

9

4

7

2

BOTTOM PAD USE 6 VIAS CONNECT TO GND

BOOT

OCSET

UGATE

PHASE

LGATE

COMP

VDDQ1 VDDQ2

DDR_VTT1 DDR_VTT2

25 22

R416

26

24

28

16

15

FB

8 7

5 6 9

15,19,26

+2.5V/100mA

+3V

15,19,26 15,19,26

CE23

SB3V

CE22

1000UF_10V_D10P5

SLP_S3SLP_S4-

10UF_25V

Q22

IPD09N03LA

VCC3

3

1

2

U44

2

3V3AUX

ISL6506BCB

5VDUAL_NC

G-PAD

5VDLSB

9

3

S3-

4

S5-

SB5V

+12V

R78 1K

1

VCC

6

DLA

8

7

5

GND

C22

4.7UF

1

2

3

VCC5

3

2

U6

D2

D4

G

IRLMS6802

CE25

10UF_25V

Q23

NTD110N02RT4

(252)

6

D1

5

D3

S

4

10UF_25V

S0:+5V/10A S3:+5V/2A S5:Disable

5V_DUAL

SB5V

CE24

CE27 1000UF_10V_D10P5

+12V_PWM

R380

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

Document Number:

Prepared by:

A3

VCC3

CM22

0603

1K

3

0

6

0

_ P

C108

A C

X

_

P

(1UF_OPT)

O P O N

Jamaica

SYSTEM POWER

XXXXXXXX

I.J. Shen

Date:

Q4 2N2222A

1

2005/4/12

3

2

D6

3

SC431

1

VCC2.5V

V

REV:

5

2

1

_

8

F

E

U

C

0

1

3.1

OF

R602 20R_1%

2

R603 1K_1%

PAGE:SIZE:

26 30

12

3

4

5

6

7

8

J2

+12V_PWM

A

1

GND1

2

GND2

+12V1

+12V2

3

4

ATX+12V_4_1H

B

VRMPWRGD

15

VCC3

R565

4K7

1

Q59

3

3904

C

C170 X

VCC_SENSE

3

VSS_SENSE

3

D

C171 X

E R O C V

0.8UH

L30

CE58

CE21 1800UF_16V

3,4,5

VTT_OUT_R

SB5V

VCORE

R568

4K7

R572

4K7

1

2

3

Q60

3904

C172

X

CAP_0805

R566

100R

R567

100R

3

CPUVID(4)

3

CPUVID(3)

3

CPUVID(2)

3

CPUVID(1)

3

CPUVID(0)

3

3,26

C173

CAP_0402

5 C C V

CPUVID(5)

VTT_PWRGD

X

CP72

X

R576

75K_1%

2

3

0

9

6

0

5 M C

R570 0R

R571 0R

1800UF_16V

0402

2

0

4

3

0

5

2

B C

2

0

4

0

_ X

CB254

R575 X

CE59 1800UF_16V

0402

R579

1K_1%

R578 75K_1%

F P

0

7

4

CE60 1800UF_16V

R

0

8

6

7

6

8

5

R

R580

1000PF

24K3_1%

C176

10PF

R581 X

2

0

4

0

3

7 P C

R583

14K_1%

4

8

5

X

R

2

8

5

0R

R

8

5 R

X

C174

0.027UF

3

0

6

4

0

1

2

1

M

C

0805

CE61 X

R

4

P

8

R

0

8

6

2

6

4

8

1

5

3

7

1

3

N

R

C175

C177

X

R588

1K5_1%

CP6

2

0.01UF

0

4

0

CB1

2

0

4

0

R6

28K_1%

R7

28K_1%

R8

28K_1%

VIN

6

3

F

1

U

C

0

1

1206

U1

38

VID4

39

VID3

40

VID2

1

VID1

2

3 35 29 37

8

9

10

12

11

6

36

5

4

13

14

15

16

41

VID0 DACSEL-VID5 PGOOD ENLL

COMP FB

VDIFF

VSEN

RGND OFST

FS REF

VRM10

OCSET

ICOMP

ISUM

IREF

GND

UGATE1

PHASE1

LGATE1

UGATE2

PHASE2

LGATE2

UGATE3

PHASE3

LGATE3

ISL6566CR

PVCC1

BOOT1

ISEN1

PVCC2

BOOT2

ISEN2

PVCC3

BOOT3

ISEN3

VCC5

9

7

8

5

R

4

R

8

7

F

1

U

C

7

.

4

7

VCC

33 30

31

32

34

24 26

27

28

25

23

18 21

20

22

19

17

R590

4R7

R596

1K69_1%

R591

1K69_1%

4R7

+12V_PWM

5

9

7

5

R

4

3

0

6

0

6 M C

R592

R593

R594

1K69_1%

C179

C180

C181

7

9

5 R

3

1

6

0.22UF

8

9

7

5

R

4

3

0

6

0

2

6

M

C

R33 1R

R388 0R

R397 0R

R51 1R

R395 0R

RES_0805

1RR50

RES_0805

2

Q35

X_IRFR3707Z

1

3

2

IRFR3709Z

1

3

2

Q41

IRFR3707Z

1

3

2

Q42

IRFR3709Z

1

3

2

Q39

IRFR3707Z

1

3

2

Q40

IRFR3709Z

1

3

2

Q43

IRFR3707Z

1

3

2

Q36

1

2

3

2

3

2

X_IRFR3707Z

3

2

IRFR3709Z

3

Q44

IRFR3709Z

3

Q49

X_IRFR3707Z

Q50

IRFR3709Z

Q47

Q48

1

3

0

6

0

1

3

0

6

0

CM56

1

CM57

3

0

6

0

2

3

CM54

2

3

2

3

Q57

X_IRFR3709Z

C131

Q55

X_IRFR3709Z

VIN

C135

10UF 1206

Q56

X_IRFR3709Z

VIN

C134

10UF 1206

VIN

10UF 1206

L67 X

L_PA0513_SMD

L32

R398

2R2

C189

1000PF

R401

2R2

C188

1000PF

0.43UH

L68 X

L_PA0513_SMD

L31

0.43UH

VCORE

A

V

5

.

V

2

5

8

4

6 E C

1

.

_

6

2

T

F

_

E

C

U

F

C

0

U

2

0

8

2

8

VCORE

V

5

.

2

5

9

6

_

6

1

F

E

U

C

0

2

8

V

5

.

2

_

T

F

C

U

0

1

B

7

1 E

X

C

L69 X

L_PA0513_SMD

L34

R400

2R2

C187

1000PF

0.43UH

VCORE

V

5

1

3

6 E C

.

7

2

E

_

F

C

X

U

0

2

8

D

VCORE

E

+12V_PWM

SB5V

R573

X

X_4K7

R569

LL_ID0

3

X

X_4K7

2

1

Q61 X_3904

2

3

1

R577

X

R574

X_20K_1%

X

X_4K7

1

Q63

2

X_2N7002

3

1

Q62 X_3904

3

2

3

5

0

8

0

_

P

C82

A

C

X

_

P

O

O P O N

5

0

8

0

_ P

C105

C83

A C

X

_

P O P

P

O

N

4

VCORE

5

0

8

0

_

P

C106

A C

_

P O P O N

C107

A C

X

_

P O

P O N

V

3

.

6

_

F U

0

CL2

CL3

0

1

5

V

3

.

6

_

F

U

0

CL5

CL4

0

8

0

1

V

3

.

6

_

F

U

0

CL6

0

8

1

V

3

.

6

_

F

U

0

CL7

0

8

1

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

Document Number:

Prepared by:

A3

6

XXXXXXXX

I.J. Shen

7

Jamaica

CPU PWM

Date:

2005/4/12

2

6 E C

V

5

.

2

6

0

_

6

7

F

E

X

U

REV:

X

C

0

2

8

3.1

OF

3027

C

PAGE:SIZE:

8

E

FF

15,19,25,28,29 15,19,25,28,29

6

EXP_TXP_15

6

EXP_TXN_15

6

EXP_TXP_14

6

EXP_TXN_14

6

EXP_TXP_13

EXP_TXN_13

6

EXP_TXP_12

EXP_TXN_12

6

EXP_TXP_11

6

EXP_TXN_11

6

EXP_TXP_10

6

EXP_TXN_10

6

EXP_TXP_9

6

EXP_TXN_9

6

EXP_TXP_8

6

EXP_TXN_8

6

EXP_EN

EXP_TXP_7

6 6

EXP_TXN_7

EXP_TXP_6

6

EXP_TXN_6

6

EXP_TXP_5

6

EXP_TXN_5

6

EXP_TXP_4

EXP_TXN_4

6

EXP_TXP_3

6 6

EXP_TXN_3

EXP_TXP_2

6

EXP_TXN_2

6

EXP_TXP_1

6

EXP_TXN_1

6

EXP_TXP_0

6

EXP_TXN_0

6

SMB_CLK_STBY

SMB_DATA_STBY

WAKE-

15,25,28

SDVO_CTRL_CLK

6

SDVO_CTRL_DATA

6

CB132

CB133

CB134

CB135

CB136

CB137

CB138

CB139

CB140

CB141

CB142

CB143

CB144

CB145

CB146

CB147

SB3V

0402

CB148

CB149

CB150

CB151

CB152

CB153

CB154

CB155

CB156

CB157

CB158

CB159

CB160

CB161

CB162

CB163

VCC3

+12V

J5

B1

12V1

B2

12V2

B3

12V3

B4

GND1

B5

SMCLK

B6

SMDAT

B7

GND2

B8

3.3V1

B9

JTAG1

B10

3.4VAUX

B11

WAKE#

B12

RSVD1

B13

GND3

B14

0402

HSOP0

B15

HSON0

B16

GND4

B17

PRSNT2-1

B18

GND5

B19

HSOP1

B20

HSON1

B21

GND6

B22

GND7

B23

HSOP2

B24

HSON2

B25

GND8

B26

GND9

B27

HSOP3

B28

HSON3

B29

GND10

B30

RSVD2

B31

PRSNT2-2

B32

GND11

B33

HSOP4

B34

HSON4

B35

GND12

B36

GND13

B37

HSOP5

B38

HSON5

B39

GND14

B40

GND15

B41

HSOP6

B42

HSON6

B43

GND16

B44

GND17

B45

HSOP7

B46

HSON7

B47

GND18

B48

PRSNT2-3

B49

GND19

B50

HSOP8

B51

HSON8

B52

GND20

B53

GND21

B54

HSOP9

B55

HSON9

B56

GND22

B57

GND23

B58

HSOP10

B59

HSON10

B60

GND24

B61

GND25

B62

HSOP11

B63

HSON11

B64

GND26

B65

GND27

B66

HSOP12

B67

HSON12

B68

GND28

B69

GND29

B70

HSOP13

B71

HSON13

B72

GND30

B73

GND31

B74

HSOP14

B75

HSON14

B76

GND32

B77

GND33

B78

HSOP15

B79

HSON15

B80

GND34

B81

PRSNT2-4

B82

RSVD3

PCIE_X16

PRSNT1-1

12V4 12V5

GND35

JTAG2 JTAG3 JTAG4 JTAG5

3.3V2

3.3V3

PWRGD

GND36

REFCLK+

REFCLK-

GND68

HSIP0

HSIN0

GND37

RSVD4 GND38

HSIP1

HSIN1 GND39 GND40

HSIP2

HSIN2 GND41 GND42

HSIP3

HSIN3 GND43 RSVD5

RSVD6 GND44

HSIP4

HSIN4 GND45 GND46

HSIP5

HSIN5 GND47 GND48

HSIP6

HSIN6 GND49 GND50

HSIP7

HSIN7 GND51

RSVD7 GND52

HSIP8

HSIN8 GND53 GND54

HSIP9

HSIN9 GND55 GND56 HSIP10

HSIN10

GND57 GND58 HSIP11

HSIN11

GND59 GND60 HSIP12

HSIN12

GND61 GND62 HSIP13

HSIN13

GND63 GND64 HSIP14

HSIN14

GND65 GND66 HSIP15

HSIN15

GND67

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32

A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49

A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82

PRST_PCIEX16-

CLK_PE_100M_16PORT CLK_PE_100M_16PORT-

EXP_RXP_15 EXP_RXN_15

EXP_RXP_14 EXP_RXN_14

EXP_RXP_13 EXP_RXN_13

EXP_RXP_12 EXP_RXN_12

EXP_RXP_11 EXP_RXN_11

EXP_RXP_10 EXP_RXN_10

EXP_RXP_9 EXP_RXN_9

EXP_RXP_8 EXP_RXN_8

EXP_RXP_7 EXP_RXN_7

EXP_RXP_6 EXP_RXN_6

EXP_RXP_5 EXP_RXN_5

EXP_RXP_4 EXP_RXN_4

EXP_RXP_3 EXP_RXN_3

EXP_RXP_2 EXP_RXN_2

EXP_RXP_1 EXP_RXN_1

EXP_RXP_0 EXP_RXN_0

6 6

19

15,19,25,28,29 15,19,25,28,29

18 18

SMB_DATA_STBY

15,25,28

2

4

0

4

6

0

1

B C

SMB_CLK_STBY

WAKE-

16

HSO_P0

16

HSO_N0

VCC3

V

5

3

2

5

_

E

F

C

U

0

1

FOR PCI-EXP 16PORT

+12V

4

5 E C

VCC3

SB3V

VCC3

+12V

VCC3

SB3V

7

6

1 B C

2

0

4

0

+12V

2

9

8

0

4

6

0

1

B

C

J8

B1

12V1

B2

12V2

B3

12V3

B4

GND1

B5

SMCLK

B6

SMDAT

B7

GND2

B8

3.3V1

B9

JTAG1

B10

3.4VAUX

B11

WAKE#

B12

RSVD1

B13

GND3

B14

HSOP0

B15

HSON0

B16

GND4

B17

PRSNT2-

B18

GND5

PRSNT1-

12V4 12V5

GND35

JTAG2 JTAG3 JTAG4 JTAG5

3.3V2

3.3V3

PWRGD

GND36

REFCLK+

REFCLK-

GND68

HSIP0

HSIN0

GND37

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11

A12 A13 A14 A15 A16 A17 A18

FOR PCI-EXP 1PORT

PRST_PCIEX1-

CLK_PE_100M_1PORT CLK_PE_100M_1PORT-

HSI_P0 HSI_N0

16 16

19

18 18

PCIE_X1

SB3V

2

5

.

3 P

_ V

6

1

_

F U

0

7

4

2

5

6

0

4

6

0

1

B

C

R

USI

Universal Scientific Industrial Co.,Ltd.

PAGE:SIZE:

REV:

28 30

OF

3.1

TITLE:

PCI-EXP X 16 &PCI-EXP X 1

Document Number:

Prepared by:

XXXXXXXX

I.J. Shen

A3

Jamaica

Date:

2005/4/12

312

AD(0:31)

16

C_BE-(0:3)

16

VCC3

A

29

PTCK

PCI_INTH-

16,29 16,29 16,29

PCI_INTF-

B

18

PCICLK1 P_REQ0-

16

C

16,29

P_IRDY-

P_DEVSEL-

16,29

P_LOCK-

16,29

P_PERR-

16,29 16,29

P_SERR-

D

-P1ACK64

29

AD(29)

AD(25)

C_BE-(3) AD(23)

AD(19)

C_BE-(2)

C_BE-(1) AD(14)

AD(10)

AD(8) AD(7)

AD(5) AD(3)

VCC5

VCC3

-12V

J6

1

-12V

3

TCK

5 7

TDO

9 11 13

INTB#14INTC#

15

INTD#

17

PRSNT1#

19 21

PRSNT2#

23 25 27 29 31

CLK

33 35

REQ#

37 39

AD31

41

AD29

43 45

AD27

47

AD25

49 51

C_BE3#

53

AD23

55 57

AD21

59

AD19

61 63

AD17

65

C_BE2#

67 69

IRDY#

71 73

DEVSEL#

75 77

LOCK#

79

PERR#

81 83

SERR#

85 87

C_BE1

89

AD14

91 93

AD12

95

AD10

97 99

AD08

101

AD07

103 105

AD05

107

AD03

109 111

AD01

113 115

ACK64#

117 119

FRAME#

C_BE0#

REQ64#

TRST#

INTA#

RST#

GNT#

PME# AD30

AD28 AD26

AD24

IDSEL

AD22 AD20

AD18 AD16

TRDY#

STPO#

SDONE

SBO#

AD15

AD13 AD11

+12V

2 4

12V

6

TMS

8

TDI

10 12

16 18 20 22 24 26 28

Vaux

30 32 34 36 38 40 42 44 46 48 50

R46

52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86

PAR

88 90 92 94 96 98

AD9

100 102 104

AD6

106

AD4

108 110

AD2

112

AD0

114 116 118 120

VCC5

V

3 B

S

AD(30)AD(31)

AD(28) AD(26)AD(27)

300R

AD(24)

AD(22) AD(20)AD(21)

AD(18) AD(16)AD(17)

AD(15)

AD(13) AD(11)AD(12)

AD(9)

AD(6) AD(4)

AD(2) AD(0)AD(1)

4K7R47

5 C C V

PCI5V_SLOT120_PCI1

4

-PTRST

29 29

PTMS

29

PTDI PCI_INTG-

PCI_INTE-

PCIRSTP_GNT0-

P_PME-

P_FRAMEP_TRDYP_STOPSMB_CLK_STBY

SMB_DATA_STBY P_PAR

16 16,29

16,29 16,29 16,29

16,29

15,19,25,28,29 15,19,25,28,29

29

16,29 16,29

16,29

29

18 16

5678

VCC5

VCC3

300RR48

R49 4K7

AD(30)

AD(28) AD(26)

AD(24) AD(28)AD(26)

AD(22) AD(20)

AD(18) AD(16)

AD(15)

AD(13) AD(11)

AD(9)

C_BE-(0)

AD(6) AD(4)

AD(2) AD(0)

-PTRST PTMS

PTDI PCI_INTE-

PCI_INTG-

V

3

B

S

PCIRSTP_GNT2-

P_PME-

P_FRAMEP_TRDYP_STOP-

SMB_CLK_STBY SMB_DATA_STBY

P_PAR

5 C C V

29 29

29 16,29

16,29

16,2916,29 16

16,29

16,29 16,29 16,29

15,19,25,28,29 15,19,25,28,29

16,29

PTCK

PCI_INTF-

PCI_INTH-

PCICLK0

P_REQ2-

P_IRDY-

P_DEVSEL-

P_LOCK-

P_PERRP_SERR-

-P2ACK64

AD(31) AD(29)

AD(27) AD(25)

C_BE-(3) AD(23)

AD(21) AD(19)

AD(17) C_BE-(2)

C_BE-(1) AD(14)

AD(12) AD(10)

AD(8)C_BE-(0) AD(7)

AD(5) AD(3)

AD(1)

VCC5

VCC3

-12V

J7

1

-12V

3

TCK

5 7

TDO

9

11

INTB#13INTC#

15

INTD#

17

PRSNT1#

19 21

PRSNT2#

23 25 27 29 31

CLK

33 35

REQ#

37 39

AD31

41

AD29

43 45

AD27

47

AD25

49 51

C_BE3#

53

AD23

55 57

AD21

59

AD19

61 63

AD17

65

C_BE2#

67 69

IRDY#

71 73

DEVSEL#

75 77

LOCK#

79

PERR#

81 83

SERR#

85 87

C_BE1

89

AD14

91 93

AD12

95

AD10

97 99

AD08

101

AD07

103 105

AD05

107

AD03

109 111

AD01

113 115

ACK64#

117 119

TRST#

INTA#

Vaux RST#

GNT#

PME# AD30

AD28 AD26

AD24

IDSEL

AD22 AD20

AD18 AD16

FRAME#

TRDY#

STPO#

SDONE

SBO#

AD15

AD13 AD11

C_BE0#

REQ64#

+12V

2 4

12V

6

TMS

8

TDI

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86

PAR

88 90 92 94 96 98

AD9

100 102 104

AD6

106

AD4

108 110

AD2

112

AD0

114 116 118 120

PCI5V_SLOT120_PCI2

A

B

C

D

PCI SLOT1(Right), IDSEL_AD(26), PCICLK1, REQ0/GNT0/INTG

E

VCC5

R43 4K7

4K7R44

-P1ACK64

-P2ACK64

29

F

1 6

VCC5

12

RN2 8P4R 2K73

RN2 8P4R 2K778

RN3 8P4R 2K734

RN3 8P4R 2K778

2K78P4RRN2

4

2K78P4RRN25

6

2K78P4RRN31 2

2K78P4RRN35 6

P_IRDYP_DEVSELP_LOCKP_SERRP_FRAMEP_TRDYP_STOPP_PERR-

16,29 16,29 16,29 16,29 16,29 16,29 16,29 16,29

4

+12V

2

0

4

0

9

0

6

5

B

C

VCC3

9

1

B C

2

0

4

0

2 B C

2

0

4

2

1

0

2

B

C

2

0

4

3

0

2

B

C

PCI SLOT2(Middle), IDSEL_AD(28), PCICLK1, REQ2/GNT2/INTE

Date:

2005/4/12

VCC5

1 E C

VCC5

5

2 B C

2

0

4

8

7

6

0

2

B

C

USI

TITLE:

Document Number:

Prepared by:

2

0

4

9

0

2

3

B

C

R

Universal Scientific Industrial Co.,Ltd.

Jamaica

PCI Slot X 2

XXXXXXXX

I.J. Shen

A3

723 5

VCC3

5

.

2 P

_ V

0

1

_

2

F

E

U

C

0

7

4

PAGE:SIZE:

5

.

2 P

_ V

0

1

_

F U

0

7

4

SB3V

3 E C

REV:

29 30

OF

E

V

5

2

0

_

4

1

0

F

3 B

U

0

C

0

1

3.1

F

8

PCB Version change from 1.0 to 2.0

DATE:NOV/11/2004

PAGE 3: Change R80 to nopop for design requirement. PAGE 3: Change R396 value to nopop for design requirement. PAGE 3: Change R620 and R621 value to 10R for design requirement. PAGE 4: Change R394 value to 62R for design requirement. PAGE 6: Change R627 value to 1.1K 1% 0603 for design requirement. PAGE 6: Change R373 to 1K 5% 0603 for design requirement. PAGE 6: Change R381 and R382 value from 2.7K to 3K for design requirement. PAGE 6: Change R628 and R629 value from 2.7K to 10K for design requirement. PAGE 14: Delete U13, R99, R102, CP24 and add D7, D9, D10 in order to use discrete video solution. PAGE 14: Delete C50, C51, C52 and add C98, C99, C101, D11 in order to use discrete video solution. PAGE 15: Change R523 from 390K to 330K for design requirement PAGE 18: Change R512 value from 61.9K to 6.2K for design requirement. PAGE 18: Delete U14, R306 for design requirement. PAGE 18: Change R307 value from 15R to 33R for design requirement. PAGE 18: Change R279 value from 33R to 27R for design requirement. PAGE 18: Change R297 value from 33R to 39R for design requirement. PAGE 18: Add one 33pF bypass capacitor on CLK_48M_USB signal and place close clock generator for signal quality issue. PAGE 19: Reserve a 0603 resistor (R117) on U19-125 for design requirement. PAGE 19: Change R160, R161, R163 value from 10K to nopop for design requirement. PAGE 19: Change R167, R168 value from 4.7K to 8.2K for design requirement. PAGE 23: Change R630 value from nopop to 1K for design requirement. PAGE 23: Delete R627, R289, R300, R70, R268, C98, C99, C101, C102, R355, R358, R339, R351 due to we support HD audio only. PAGE 23: Change R66, R631, R632 value from nopop to 2.2K for design requirement.

** Broadcom BCM5753 modification. PAGE 25: Delete R79, R80, R100, R74, L70, CB34, Q2, C16, C20. PAGE 25: Reserve two 0603 pad on location R102, R109. PAGE 25: Change R106 from 10K to nopop. PAGE 25: Change R113, R114 value from 10K to nopop. PAGE 25: Change R116, R140, R553 value from 4.7K to nopop. PAGE 25: Change R559, R560, R561 value from 1K to nopop.

PCB Version change from 2.0 to 2.1

DATE:DEC/22/2004

** Intel Tekoa modification. PAGE 25: Delete R81, L33, L35, L61, L63, C8, C9, C10, C11, CB172, CB173, CB177, CB180, CB183, CB187, R530, R528, R109, R540, R130. PAGE 25: Delete R108, R553, R85, R123, U40, CB196, U41, C21, R559, R560, R561, C156, CB49, CB50, CB53, CB54, CB55, CB56, CB57, CB225. PAGE 25: Change R102 value from nopop to 3.3K. PAGE 25: Change R99 value from nopop to 4.99K 1%. PAGE 25: Change R100 value from nopop to 3.3K. PAGE 25: Add two 0.1uF (CB34, CB48) and two 4.7uF (C8, C9) bypass capacitors for SB1.2V power. PAGE 25: Add one 4.7uF (C21) and four 0.1uF (CB49, CB50, CB53, CB54) bypass capacitors for SB3V_LAN power. PAGE 25: Add one 4.7uF (C31) and three 0.1uF (CB172, CB57, CB173) bypass capacitors for SB2.5V power. PAGE 25: Add two 47R 0603 resistors at location R114 and R139. PAGE 25: Add one 3.3K resistor on location R109 for enable internal 2.5V regulator. PAGE 25: Reserve one pull-down 0603 resistor on location R113 for disable internal 2.5V regulator. PAGE 25: Reserve C33, CB187, Q3, C115, CB190, C114 pad for external 2.5V regulator. PAGE 25: Add two 2R 1206 ressitors on location R115 and R116 for SB1.2V power. PAGE 25: Add one transistor BCP69T1 on location Q7 for SB1.2V power. PAGE 25: Add one 4.7uF (C138) and one 0.1uF (CB180) bypass capacitors for SB3V_LAN power. PAGE 25: Add two 0.1uF (CB177, CB183) and one 4.7uF (C137) bypass capacitors for SB1.2V power. PAGE 25: Reserve three serial flash ROM pads on location (U10, U14, U17) for Tekoa implement. PAGE 25: Add two 0.1uF bypass capacitors on location (CB189, CB188) for serial flash ROM. PAGE 25: Add 17 pcs 0R 0603 resistors for option serial flash ROM, the location of resistor are R289, R425, R306, R339, R355, R372, R406. R351, R358, R405, R407, R413, R412, R159, R267, R268, R140. PAGE 25: Add two 3.3K pull-up resistors on location R408 and R409 for serial flash ROM. PAGE 25: Reserve two pull-up resistors on location R410 and R411 for serial flash ROM.

PAGE 25: Chane U2(82573E) pin M2 connection from SB3V to SB2.5V. PAGE 25: Change R408, R409, CB189, R289, R425, R306, R339, R355, R372, R406, R351, R358, R405, R407, R268 to nopop in order to use non-share serial flash ROM mode. PAGE 25: Change R301 to 8.2K and R410, R411 to 3.3K and CB188 to 0.1uF and R413, R412, R159, R267 to 0R in order to use non-share serial flash ROM mode. PAGE 26: Change R599 to 619R 1% and R10 to 2K 1% in order to get accuracy voltage for VCC1.05V power. PAGE 27: Change R578 to 75K 1% and R583 to 14K 1% 0603 and CP6 to 0.01uF 0402 for power design requirement. PAGE 27: Change CB1 to 0.1uF and R6~R8 to 28K 1% 0603 and CL2, CL3 to 1000uF 6.3V for power design requirement. PAGE 27: Change CT1 and CT2 to 100uF 2.5V for power design requirement. PAGE 27: Change R580 from 10K 5% 0603 to 24.3K 1% 0603 for power design requirement.

PCB Version change from 3.0 to 3.1

DATE:APR/12/2005

PAGE 5: Delete XDP connector (J12) for cost down. PAGE 6: Change R446 and R447 from 220R to 100R in order to fix Casper (ADD2-R card) can't work issue. PAGE 14: Change L33, L35, L36 values from 0.33uH to 0.18uH in ordr to fix VGA signals quality issue. PAGE 16: Reserve one 0603 resistor on location R634 for SPI boot option. PAGE 16: Add two AC coupling capacitors on location CB196 and CB195 for PCIe x1 signals.

** Intel WW09 update for SATAPLL filter circuitry. PAGE 17: Remove R414 and R415 and add one 10UH inductor 0805 on location R415. PAGE 17: Add one 10uF 0805 capacitor on location C143 and Change CP75 value from 0.01uF to 0.1uF.

PAGE 18: Change R448 value from 18R to 33R for improve EMI issue. PAGE 23: Change CM17 and CM23 from 1uF 0603 to 0R 0603 for design requirement. PAGE 26: Change R422 from 18K 0603 to 24K 0603 to change OCP point for fix DC 5.5V hang up issue. PAGE 27: Change R588 from 3.3K to 1.5K 1% and change C174 from 0.022uF to 0.027uF for power design requirement.

PCB Version change from 2.1 to 3.0

DATE:FEB/16/2005

PAGE 3: Add test points on location T156, T157, T158, T154, T155, T159, T160 in order to increase LGA 775 soclet ICT test coverage. PAGE 3: Change R403 value from 60.4R 1% to 62R on TESTHI_O signal for design requirement. PAGE 5: Add test point on location T153 in order to increase LGA 775 socket ICT test coverage. PAGE 6: Add two 220R 0603 ressitors (R446, R447) on SDVO_CTRL_DAT and SDVO_CTRL_CLK signals for design guide requirement. PAGE 6: Change R79 value from 1.1K to nopop in order to fix that ICEman VGA card can't display issue. PAGE 14: Remove R74, R79 for design requirement. PAGE 14: Change L33, L35, L36 value from 0.22uH to 0.33uH for EMI and signal quality issues. PAGE 14: Change C98, C99 and C101 to 6.8pF for EMI and signal quality issues. PAGE 15: Change BRD_ID1 from GPIO13 (Pin U1-E19) to GPIO14 (Pin U1-R4). PAGE 15: Change BRD_ID0 from GPIO31 (Pin U1-B3) to GPIO13 (Pin U1-E9). PAGE 15: Change BRD_ID2 from GPIO30 (Pin U1-A2) to GPIO15 (Pin U1-E22). PAGE 15: Change LAN_DISABLE- signal from GPIO28 to GPIO24. PAGE 15: Change AFP_PRES signal from GPIO24 to GPIO28. PAGE 15: Delete R145, R147 pull-up resistor for design requirement. PAGE 15: Change R123, R300, R130, R81 to nopop due to use non-share serial flash ROM mode. PAGE 15: Connect GPIO30 (Pin U1-A2) and GPIO31 (Pin U1-A3) to USB_ICH_OC3-. PAGE 16: Change ICH7 pin U1-F26 from HSI_N0 to PCI_LAN_RXDN. PAGE 16: Change ICH7 pin U1-F25 from HSI_P0 to PCI_LAN_RXDP. PAGE 16: Change ICH7 pin U1-E28 from HSO_N0 to PCI_LAN_TXDN. PAGE 16: Change ICH7 pin U1-E27 from HSO_P0 to PCI_LAN_TXDP. PAGE 16: Delete CB1 capacitors for design requirement. PAGE 17: Change CB82 to nopop on REF5V_STBY for power sequence issue. PAGE 18: Change C102 from 33pF to 47pF for CLK_48M_USB signal quality issue. PAGE 18: Change R279 value from 22R to 18R for CLK_48M_USB signal quality issue. PAGE 19: Reserve a pull-down resistor (R362) on RSMRST- signal for design requirement. PAGE 19: Add a 0R resistor (R429) between U12-100 (GPIOE16) and NVM_PROT signal. PAGE 21: Reserve a resistor (R3) betweenscrew hole (H5) and U-GROUND for audio ESD issue. PAGE 21: Change R93 to nopop in order to use FAN_TACH1 and FAN_PWM1 for CPU FAN speed control. PAGE 21: Change CE35 and JP11 to nopop in order to use FAN_TACH1 and FAN_PWM1 for CPU FAN speed control. PAGE 21: Change CE33 to 10uF_25V in order to use FAN_TACH1 and FAN_PWM1 for CPU FAN speed control. PAGE 21: Change JP5 to 1x4 lock header in order to use FAN_TACH1 and FAN_PWM1 for CPU FAN speed control. PAGE 21: Change R93 to nopop and add a 4.7K resistor 0603 on location R87 in order to use FAN_TACH1 and FAN_PWM1 for CPU FAN speed control. PAGE 22: Reserve D13 and D14 (nopop) for USB ESD protection. PAGE 22: Add CM6(1uF), L37(FB), CE38(330uF), R426(1K), R427(1.2K), C32(1000pF) for USB power in 4 stack USB ports. PAGE 23: Reserve a capacitor (C146) on AC_BITCLK for design requirement. PAGE 24: Connect P11-1 and P10-1 to U-GROUND for ESD solution. PAGE 24: Reserve D12 (nopop) for USB ESD protection.

R

USI

Universal Scientific Industrial Co.,Ltd.

TITLE:

Document Number:

Prepared by:

A3

Jamaica

Change history

XXXXXXXX

I.J. Shen

Date:

2005/4/12

REV:

3.1

PAGE:SIZE:

OF

3030

Gigabyte Jamaica Schematic REV.3.1

Specifications and Main Features

Frequently Asked Questions

User Manual