Gigabyte GV-RX30S128D-HT Schematic REV.1.1

8

7

6

5

4

3

2

1

+12V_BUS

C5
100uF_16V

DNI DNI DNI

D D

A_HSYNC_DAC1(2,11)

PETp0_GFXRp0(2)
PETn0_GFXRn0(2)

PETp1_GFXRp1(2)

C C

B B

PETn1_GFXRn1(2)

PETp2_GFXRp2(2)
PETn2_GFXRn2(2)

PETp3_GFXRp3(2)
PETn3_GFXRn3(2)

PETp4_GFXRp4(2)
PETn4_GFXRn4(2)

PETp5_GFXRp5(2)
PETn5_GFXRn5(2)

PETp6_GFXRp6(2)
PETn6_GFXRn6(2)

PETp7_GFXRp7(2)
PETn7_GFXRn7(2)

PETp8_GFXRp8(2)
PETn8_GFXRn8(2)

PETp9_GFXRp9(2)
PETn9_GFXRn9(2)

PETp10_GFXRp10(2)
PETn10_GFXRn10(2)

PETp11_GFXRp11(2)
PETn11_GFXRn11(2)

PETp12_GFXRp12(2)
PETn12_GFXRn12(2)

PETp13_GFXRp13(2)
PETn13_GFXRn13(2)

PETp14_GFXRp14(2)
PETn14_GFXRn14(2)

PETp15_GFXRp15(2)
PETn15_GFXRn15(2)

C8
100uF_16V

+3.3V_BUS+3.3V_BUS

USE 47uF TANTALUM

C2

CAPACITOR OR HIGHER

47uF_16V/X

>=6.3V>=6.3V

R1008 0R/X

TP28

TP30

TP29

TP32

TP31

TP34

TP33

TP36

TP35

TP38

TP37

TP40

TP39

TP42

TP41

TP44

TP43

TP46

TP45

TP48

TP47

TP50

TP49

TP52

TP51

TP54

TP53

TP56

TP55

TP58

TP57

PRESENCE

TP59

402

JTAG_TRST#

DNI

PCI-EXPRESS EDGE CONNECTOR

+3.3V_BUS

PRESENT_NULL

PRESENT_NULL

PRESENT_NULL

+12V_BUS

B1
B2
B3
B4
B5
B6
B7
B8

B9
B10
B11

B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82

MPCIE1

+12V#B1
+12V#B2
RSVD#B3
GND#B4
SMCLK
SMDAT
GND#B7
+3.3V#B8
JTAG1

3.3Vaux
WAKE#

RSVD#B12
GND#B13
PETp0
PETn0
GND#B16
PRSNT2#B17
GND#B18
PETp1
PETn1
GND#B21
GND#B22
PETp2
PETn2
GND#B25
GND#B26
PETp3
PETn3
GND#B29
RSVD#B30
PRSNT2#B31
GND#B32
PETp4
PETn4
GND#B35
GND#B36
PETp5
PETn5
GND#B39
GND#B40
PETp6
PETn6
GND#B43
GND#B44
PETp7
PETn7
GND#B47
PRSNT2#B48
GND#B49
PETp8
PETn8
GND#B52
GND#B53
PETp9
PETn9
GND#B56
GND#B57
PETp10
PETn10
GND#B60
GND#B61
PETp11
PETn11
GND#B64
GND#B65
PETp12
PETn12
GND#B68
GND#B69
PETp13
PETn13
GND#B72
GND#B73
PETp14
PETn14
GND#B76
GND#B77
PETp15
PETn15
GND#B80
PRSNT2#B81
RSVD#B82

x16 PCIe

Mechanical Key

PRSNT1#A1

+12V#A2
+12V#A3
GND#A4

+3.3V#A9

+3.3V#A10

PERST#

GND#A12
REFCLK+
REFCLK­GND#A15

GND#A18

RSVD#A19

GND#A20

GND#A23
GND#A24

GND#A27
GND#A28

GND#A31
RSVD#A32
RSVD#A33

GND#A34

GND#A37

GND#A38

GND#A41

GND#A42

GND#A45

GND#A46

GND#A49
RSVD#A50

GND#A51

GND#A54

GND#A55

GND#A58

GND#A59

PERp10

PERn10
GND#A62
GND#A63

PERp11

PERn11
GND#A66
GND#A67

PERp12

PERn12
GND#A70
GND#A71

PERp13

PERn13
GND#A74
GND#A75

PERp14

PERn14
GND#A78
GND#A79

PERp15

PERn15
GND#A82

JTAG2
JTAG3
JTAG4
JTAG5

PERp0
PERn0

PERp1
PERn1

PERp2
PERn2

PERp3
PERn3

PERp4
PERn4

PERp5
PERn5

PERp6
PERn6

PERp7
PERn7

PERp8
PERn8

PERp9
PERn9

+12V_BUS

+3.3V_BUS

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82

PERp0
PERn0

PERp1
PERn1

PERp2
PERn2

PERp3
PERn3

PERp4
PERn4

PERp5
PERn5

PERp6
PERn6

PERp7
PERn7

PERp8
PERn8

PERp9
PERn9

PERp10
PERn10

PERp11
PERn11

PERp12
PERn12

PERp13
PERn13

PERp14
PERn14

PERp15
PERn15

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

PRESENCE

R12440R

DNI

402

RP194A 0R/X

8 1

RP194B 0R/X

7 2

RP194C 0R/X

6 3

RP194D 0R/X

5 4

TP26

TP27

C607
100nF

C608
100nF

C617
100nF

C618
100nF

C626

C627

100nF

100nF

C631
100nF

C632
100nF

C611

C612

100nF

100nF

C622
100nF

C623
100nF

C621

C630

100nF

100nF

C605
100nF

C606
100nF

C615
100nF

C616
100nF

C624
100nF

C625
100nF

C633

C634

100nF

100nF

C609
100nF

C610
100nF

C619

C620

100nF

100nF

C628
100nF

C629
100nF

C603
100nF

C604
100nF

C613

C614

100nF

100nF

DNI

A_VSYNC_DAC1 (2,11)

DNI

CRT1DDCDATA (2,11)

DNI

SCL (2)

DNI

CRT1DDCCLK (2,11)

R701 2.21K/X
R702 2.21K/X

R703 2.21K/X
R704 2.21K/X

R705 2.21K/X
R706 2.21K/X

R707 2.21K/X
R708 2.21K/X

R709 2.21K/X
R710 2.21K/X

R711 2.21K/X
R712 2.21K/X

R713 2.21K/X
R714 2.21K/X

R715 2.21K/X
R716 2.21K/X

R717 2.21K/X
R718 2.21K/X

R719 2.21K/X
R720 2.21K/X

R721 2.21K/X
R722 2.21K/X

R723 2.21K/X
R724 2.21K/X

R725 2.21K/X
R726 2.21K/X

R727 2.21K/X
R728 2.21K/X

R729 2.21K/X
R730 2.21K/X

R731 2.21K/X
R732 2.21K/X

PCIE_REFCLKP (2)
PCIE_REFCLKN (2)

GFXTp0_PERp0 (2)
GFXTn0_PERn0 (2)

GFXTp1_PERp1 (2)
GFXTn1_PERn1 (2)

GFXTp2_PERp2 (2)
GFXTn2_PERn2 (2)

GFXTp3_PERp3 (2)
GFXTn3_PERn3 (2)

GFXTp4_PERp4 (2)
GFXTn4_PERn4 (2)

GFXTp5_PERp5 (2)
GFXTn5_PERn5 (2)

GFXTp6_PERp6 (2)
GFXTn6_PERn6 (2)

GFXTp7_PERp7 (2)
GFXTn7_PERn7 (2)

GFXTp8_PERp8 (2)
GFXTn8_PERn8 (2)

GFXTp9_PERp9 (2)
GFXTn9_PERn9 (2)

GFXTp10_PERp10 (2)
GFXTn10_PERn10 (2)

GFXTp11_PERp11 (2)
GFXTn11_PERn11 (2)

GFXTp12_PERp12 (2)
GFXTn12_PERn12 (2)

GFXTp13_PERp13 (2)
GFXTn13_PERn13 (2)

GFXTp14_PERp14 (2)
GFXTn14_PERn14 (2)

GFXTp15_PERp15 (2)
GFXTn15_PERn15 (2)

PERST#

NOTE: THIS IS A DRAWING. THESE
GROUNDS MUST BE MANUALLY
CONNECTED TO THE GROUND PLANE

+5V

147

1
2

R64 0R/X

DNI

GND_PVSS GND_TXVSSR

C972
100nF

402

SN74ACT86D
U6A

R3 100R

3

402

GND_TPVSSGND_MPVSS

GND_A2VSSN

GND_AVSSQ GND_RSET

GND_R2SETGND_AVSSN

PERST#_buf (2)

R4
180R

402

GND_A2VSSQ

SYMBOL LEGEND

DNI

DO NOT
INSTALL

#

ACTIVE
LOW

A A

Title

Size Document Number Rev
C

8

7

6

5

4

3

Date: Sheet

2

GIGABYTE

PCI-E Edge Connector

GV-RX30S128D-HT

DIGITAL
GROUND

ANALOG
GROUND

1.1

of

01 16Thursday, January 06, 2005

1

5

4

3

2

1

+3.3V_BUS

Mem_Strap1 (10)
Mem_Strap0 (10)

SVHS/YPrPbb (13)
LCDDATA16 (10)

LCDDATA17 (10)

VHAD0 (10)

+3.3V_BUS

C16
100nF

402

A_HSYNC_DAC1

GND_RSET

GPIO[6..0]

GPIO[13..8]

R22 10K/X
R23 10K

Pull-up to 1.8V
12bit-DVO mode for SDR

Ext. TMDS 1.8V DVO I/O

U1A

PETp0_GFXRp0(1)
PETn0_GFXRn0(1)
PETp1_GFXRp1(1)
PETn1_GFXRn1(1)
PETp2_GFXRp2(1)
PETn2_GFXRn2(1)
PETp3_GFXRp3(1)

D D

C C

SCL(1)

C71 15PF

C72 15PF

+3.3V_BUS

R45

R46

4.7K

4.7K

402 402

402

Y1
27_MHZ

2 1

402

OPTION 1: Crystal Circuit

+3.3V_BUS

4

C18

2

100nF/X

402

5015270000

B B

A A

MY1

VCC
GND

27.000MHz/X

A_R/C_DAC2(13)
A_G/Y_DAC2(13)

A_B/COMP_DAC2(13)

R27
220R/X

3

OUT

1

E/D

+3.3V_BUS

PETn3_GFXRn3(1)
PETp4_GFXRp4(1)
PETn4_GFXRn4(1)
PETp5_GFXRp5(1)
PETn5_GFXRn5(1)
PETp6_GFXRp6(1)
PETn6_GFXRn6(1)
PETp7_GFXRp7(1)
PETn7_GFXRn7(1)
PETp8_GFXRp8(1)
PETn8_GFXRn8(1)
PETp9_GFXRp9(1)

PETn9_GFXRn9(1)
PETp10_GFXRp10(1)
PETn10_GFXRn10(1)
PETp11_GFXRp11(1)
PETn11_GFXRn11(1)
PETp12_GFXRp12(1)
PETn12_GFXRn12(1)
PETp13_GFXRp13(1)
PETn13_GFXRn13(1)
PETp14_GFXRp14(1)
PETn14_GFXRn14(1)
PETp15_GFXRp15(1)
PETn15_GFXRn15(1)

GFXTp0_PERp0(1)
GFXTn0_PERn0(1)
GFXTp1_PERp1(1)
GFXTn1_PERn1(1)
GFXTp2_PERp2(1)
GFXTn2_PERn2(1)
GFXTp3_PERp3(1)
GFXTn3_PERn3(1)
GFXTp4_PERp4(1)
GFXTn4_PERn4(1)
GFXTp5_PERp5(1)
GFXTn5_PERn5(1)
GFXTp6_PERp6(1)
GFXTn6_PERn6(1)
GFXTp7_PERp7(1)
GFXTn7_PERn7(1)
GFXTp8_PERp8(1)
GFXTn8_PERn8(1)
GFXTp9_PERp9(1)

GFXTn9_PERn9(1)
GFXTp10_PERp10(1)
GFXTn10_PERn10(1)
GFXTp11_PERp11(1)
GFXTn11_PERn11(1)
GFXTp12_PERp12(1)
GFXTn12_PERn12(1)
GFXTp13_PERp13(1)
GFXTn13_PERn13(1)
GFXTp14_PERp14(1)
GFXTn14_PERn14(1)
GFXTp15_PERp15(1)
GFXTn15_PERn15(1)

PCIE_REFCLKP(1)
PCIE_REFCLKN(1)

+PCIE_VDDR

TP6

R32

1.0M

402

R28
130R/X

R1009 150R
R1010 100R
R1011 10K

R1089 10K

PERST#_buf(1)

R29
0R/X

402

GND_R2SET

R40 715R

R33
1K

402

+3.3V_BUS

R44
10K

402

OPTION 2: Oscillator Circuit

5

AH30

PCIE_RX0P

AG30

PCIE_RX0N

AG29

PCIE_RX1P

AF29

PCIE_RX1N

AE29

PCIE_RX2P

AE30

PCIE_RX2N

AD30

PCIE_RX3P

AD29

PCIE_RX3N

AC29

PCIE_RX4P

AB29

PCIE_RX4N

AB30

PCIE_RX5P

AA30

PCIE_RX5N

AA29

PCIE_RX6P

Y29

PCIE_RX6N

W29

PCIE_RX7P

W30

PCIE_RX7N

V30

PCIE_RX8P

V29

PCIE_RX8N

U29

PCIE_RX9P

T29

PCIE_RX9N

T30

PCIE_RX10P

R30

PCIE_RX10N

R29

PCIE_RX11P

P29

PCIE_RX11N

N29

PCIE_RX12P

N30

PCIE_RX12N

M30

PCIE_RX13P

M29

PCIE_RX13N

L29

PCIE_RX14P

K29

PCIE_RX14N

K30

PCIE_RX15P

J30

PCIE_RX15N

AF26

PCIE_TX0P

AE26

PCIE_TX0N

AC25

PCIE_TX1P

AB25

PCIE_TX1N

AC27

PCIE_TX2P

AB27

PCIE_TX2N

AC26

PCIE_TX3P

AB26

PCIE_TX3N

Y25

PCIE_TX4P

W25

PCIE_TX4N

Y27

PCIE_TX5P

W27

PCIE_TX5N

Y26

PCIE_TX6P

W26

PCIE_TX6N

U25

PCIE_TX7P

T25

PCIE_TX7N

U27

PCIE_TX8P

T27

PCIE_TX8N

U26

PCIE_TX9P

T26

PCIE_TX9N

P25

PCIE_TX10P

N25

PCIE_TX10N

P27

PCIE_TX11P

N27

PCIE_TX11N

P26

PCIE_TX12P

N26

PCIE_TX12N

L25

PCIE_TX13P

K25

PCIE_TX13N

L27

PCIE_TX14P

K27

PCIE_TX14N

L26

PCIE_TX15P

K26

PCIE_TX15N

AF27

PCIE_REFCLKP

AE27

PCIE_REFCLKN

402

AC23

PCIE_CALRP

402

AB24

PCIE_CALRN

402

AB23

PCIE_CALI

402

AE25

PCIE_TEST

AD24

PWRGD_MASK

AD25

PWRGD

AH21

R2SET

402

AJ22

C_R_PR

AK21

Y_G

AK22

COMP_B_PB

AJ24

H2SYNC

AK24

V2SYNC

AG22

DDC3CLK

AG23

DDC3DATA

AJ23

NC#AJ23

AH24

NC#AH24

AH28

XTALIN

AJ29

XTALOUT

TESTEN

AH27

TESTEN

E8

TEST_YCLK

B6

TEST_MCLK

AF25

PLLTEST

AH25

STEREOSYNC

RV370SE

IT IS RECOMMENDED TO ALLOW SERIES RESISTOR
FOOT PRINTS ON THE INDICATED AGP CONTROL SIGNALS

TO ADDRESS ANY LAYOUT NOISE RELATED

SIGNAL DAMPING REQUIREMENTS

4

PCI Express

DAC2CLK

Part 1 of 6

GPIO_PWRCNTL

GPIO_MEMSSIN

DVO / EXT TMDS / GPIOTMDSDAC1

GPIO__AUXWIN

THERM

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8

GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14

DVOVMODE
DVPDATA_0

DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8

DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

DVPCNTL_0

DVPCNTL_1

DVPCNTL_2

DVPCNTL_3

VREFG

NC#AH15
NC#AH16

NC#AJ16
NC#AJ17

NC#AJ18
NC#AK18
NC#AJ20
NC#AJ21
NC#AK19
NC#AJ19

NC#AG16
NC#AG17

NC#AF16
NC#AF17
NC#AE18
NC#AE19
NC#AF19
NC#AF20

NC#AG19
NC#AG20

NC#AE12

NC#AG12

TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP

DDC2CLK

DDC2DATA

HPD1

HSYNC
VSYNC

RSET

DDC1DATA

DDC1CLK

DPLUS

DMINUS

R
G
B

AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2

AE10
AH6

AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10

AJ10
AK10
AJ11
AH11

AG4

AH15
AH16
AJ16
AJ17
AJ18
AK18
AJ20
AJ21
AK19
AJ19
AG16
AG17
AF16
AF17
AE18
AE19
AF19
AF20
AG19
AG20

AE12
AG12

AK13
AJ13
AJ14
AJ15
AK15
AK16
AJ12
AK12

AE13
AE14

AF12
AK27

AJ27
AJ26

AJ25
AK25

AH26
AG25

AF24
AG24

AF11
AE11

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6

GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13

DVOMODE

VID/DVO14
VID/DVO16

VID/DVO17
VID/DVO18
VID/DVO19
VID/DVO20
VID/DVO21
VID/DVO22
VID/DVO23

R43 10K

R39 499R

AUXWIN

402

402

TP11
TP12

3

GPIO[6..0] (10)

GPIO[13..8] (10)

+VDDR4

402
402

R35
1K

402

Both resistors and
capacitor close to ASIC

R34
1K

402

TMDS_TX0N (12)
TMDS_TX0P (12)
TMDS_TX1N (12)
TMDS_TX1P (12)
TMDS_TX2N (12)
TMDS_TX2P (12)
TMDS_TXCN (12)
TMDS_TXCP (12)

HPD (12)
A_R_DAC1 (11)

A_G_DAC1 (11)
A_B_DAC1 (11)

A_HSYNC_DAC1 (1,11)
A_VSYNC_DAC1 (1,11)

TP7

CRT1DDCDATA (1,11)
CRT1DDCCLK (1,11)

BOUNDARY SCAN TEST ACCESS

A_HSYNC_DAC1
SCL
CRT1DDCDATA
CRT1DDCCLK
A_VSYNC_DAC1
TESTEN

DEBUG BUS ACCESS

VID/DVO16
VID/DVO17
VID/DVO18
VID/DVO19
VID/DVO20
VID/DVO21
VID/DVO22
VID/DVO23
GPIO10
GPIO11
GPIO12
GPIO13

ALT

JU2
Header_3_Pin_1X3/X

+3.3V_BUS

R65

4.7K

402

2

P1
PLUG

TRST/

TP1
TP2

TDO

TP3

TDI

TP4

TMS

TP5

TCK

TP8

TESTOUT(0)
TESTOUT(1)
TESTOUT(2)

TP17

TESTOUT(3)
TESTOUT(4)

TP19

TESTOUT(5)

TP20

TESTOUT(6)

TP21

TESTOUT(7)
TESTOUT(8)
TESTOUT(9)
TESTOUT(10)
TESTOUT(11)

+VDDR4

R584
10K

402

1
2
3

R585
10K/X

ALT

402

41

SW1A
DIP_SWX2/X

Title

Size Document Number Rev
Custom

Date: Sheet

GIGABYTE

RV370 main

GV-RX30S128D-HT

1

of

02 16Thursday, January 06, 2005

1.1

1

QSA[7..0]

QSA[7..0](8)

DQMA#[7..0](8)

MAA[14..0](9)

MDA[63..0](8)

A A

B B

C C

DQMA#[7..0]
MAA[14..0]

MDA[63..0]

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

2

U1B

H28

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

RV370SE

Part 2 of 6

MEMORY

INTERFACE A

H29

J28
J29

J26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10

C9

B9
B10
E13
E12
E10
F12
F11

E9

F9

F8

MEMORY CHANNEL A

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8

MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14

DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7

QSA_0

QSA_1

QSA_2

QSA_3

QSA_4

QSA_5

QSA_6

QSA_7

RASAb

CASAb

WEAb
CSAb_0
CSAb_1

CKEA

CLKA0

CLKA0b

CLKA1

CLKA1b

MVREFD
MVREFS

DIMA_0
DIMA_1

3

MAA0

E22

MAA1

B22

MAA2

B23

MAA3

B24

MAA4

C23

MAA5

C22

MAA6

F22

MAA7

F21

MAA8

C21

MAA9

A24

MAA10

C24

MAA11

A25

MAA12

E21

MAA13

B20

MAA14

C19

DQMA#0

J25

DQMA#1

F29

DQMA#2

E25

DQMA#3

A27

DQMA#4

F15

DQMA#5

C15

DQMA#6

C11

DQMA#7

E11

QSA0

J27

QSA1

F30

QSA2

F24

QSA3

B27

QSA4

E16

QSA5

B16

QSA6

B11

QSA7

F10

RASA#

A19

CASA#

E18

WEA#

E19

CSA#0

E20
F20

CKEA

B19

CLKA0

B21

CLKA#0

C20

CLKA1

C18

CLKA#1

A18

B7
B8

D30
B13

RASA# (9)
CASA# (9)
WEA# (9)
CSA#0 (9)

CKEA (9)

CLKA0 (8,9)
CLKA#0 (8,9)

CLKA1 (8,9)
CLKA#1 (8,9)

+MVDDQ

R58
100R

402

C154

R59

100nF

100R

402

402

PLACE C351/152 VERY CLOSE TO ASIC
R56/57/58/59 CLOSE TO ASIC AS WELL

C153
100nF

402

+MVDDQ

R56
100R

402

R57
100R

402

4

D7

F7

E7
G6
G5

F5

E5
C4

B5
C5

A4

B4
C2
D3
D1
D2
G4
H6
H5

J6

K5

K4

L6

L5
G2

F3
H2

E2

F2

J3

F1
H3
U6
U5
U3

V6
W5
W4

Y6

Y5
U2

V2

V1

V3
W3

Y2

Y3

AA2
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
AB2
AB3
AC2
AC3
AD3
AE1
AE2
AE3

5

U1C

DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63

RV370SE

Part 3 of 6

DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
DQMBb_5
DQMBb_6
DQMBb_7

MEMVMODE_0
MEMVMODE_1

MEMTEST

MEMORY

INTERFACE B

MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8

MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14

QSB_0

QSB_1

QSB_2

QSB_3

QSB_4

QSB_5

QSB_6

QSB_7

RASBb

CASBb

CSBb_0
CSBb_1

CLKB0
CLKB0b

CLKB1
CLKB1b

DIMB_0
DIMB_1

ROMCSb

MEMORY CHANNEL B

WEBb

CKEB

6

N5
M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2

E6
B2
J5
G3
W6
W2
AC6
AD2

F6
B3
K6
G1
V5
W1
AC5
AD1

R2
T5
T6
R5
R6
R3
N1

N2
T2

T3

E3
AA3

AF5
C6

C7
C8

R53

4.7K

R55

402 402

47R

402

LAYOUT NOTE: SOME OF THE RESISTORS R51-54 MAY BE
REMOVED IF SPACE IS AN ISSUE, ASK BEFORE REMOVING

R51 4.7K
R52 4.7K/X

R54

4.7K/X

DNI

ROMCS# (10)

402
402

DNI

+VDDC_CT

7

8

VDDR1 MEMVMODE_0 MEMVMODE_1

1.8V

2.5V

2.8V

+VDDC_CT GND

+VDDC_CT +VDDC_CT

+VDDC_CTGND

D D

Title

Size Document Number Rev
Custom

1

2

3

4

5

6

Date: Sheet

7

GIGABYTE

RV370 memory interface

GV-RX30S128D-HT

03 16Thursday, January 06, 2005

of

8

1.1

5

+MVDDQ

D D

+MVDDQ

C38
10uf

+MVDDQ

C32

100nF

100nF

402 402 402

C C

+1.8V

B11
200R/200mA

ALT: 0R

+1.8V

B14
0R/8

ALT: 0R

B B

A A

+1.8V

B13
0R/8

ALT: 0R

C31

100nF

100nF

402 402402

+TPVDD

C50
10uf

OPT

GND_TPVSS

+TXVDDR_PINS

C59

4.7uF

GND_TXVSSR
+A2VDDQ

C63

4.7uF

GND_A2VSSQ

AVDD/A2VDDQ (1st & 2nd
DAC Band Gap) - 200mA

+AVDD

C67

4.7uF

GND_AVSSN

C35

C33

C75

C74

100nF

100nF

C43

C58

2.2uF

2.2uF

ALT:

ALT:

100nF

100nF

C60

C81

100nF

100nF

402

402

C64
100nF

402

C68
100nF

402

5

C73
100nF

402

+1.8V

C94
100nF

B12
0R/8

ALT: 0R

C95
100nF

402402 402402

C96
100nF

+VDDOI_PINS

C66

4.7uF

+PVDD

GND_PVSS

+MPVDD

GND_MPVSS

C97
100nF

+A2VDD

GND_A2VSSN

C65
100nF

402

C54

4.7uF

C52

4.7uF

C62
100nF

402

C53
100nF

402

C51
100nF

402

4

U1D

T7
R4
R1
N8
N7
M4

L8

K23
K24
L23

J8

J7

J4

J1

H10
H13
H15
H17

T8

V4

V7

V8

AA1
AA4
AA7
AA8

A3

A9

A15
A21
A28

B1

B30
D26
D23
D20
D17
D14
D11

D8
D5

E27

F4
G7

G10
G13
G15
G19
G22
G27
H22
H19
AD4

N4

AE15
AE16
AE17
AF15

AH19
AH13 AH12
AF13

AF14

+MVDDQ

F18

N6

AE20
AF21

AF23
AH23

AE23
AE22

AK28 AJ28

A7 A6

RV370SE

Part 4 of 6

VDDR1#T7
VDDR1#R4
VDDR1#R1
VDDR1#N8
VDDR1#N7
VDDR1#M4
VDDR1#L8
VDDR1#K23
VDDR1#K24
VDDR1#L23
VDDR1#J8
VDDR1#J7
VDDR1#J4
VDDR1#J1
VDDR1#H10
VDDR1#H13
VDDR1#H15
VDDR1#H17
VDDR1#T8
VDDR1#V4
VDDR1#V7
VDDR1#V8
VDDR1#AA1
VDDR1#AA4
VDDR1#AA7
VDDR1#AA8
VDDR1#A3
VDDR1#A9
VDDR1#A15
VDDR1#A21
VDDR1#A28
VDDR1#B1
VDDR1#B30
VDDR1#D26
VDDR1#D23
VDDR1#D20
VDDR1#D17
VDDR1#D14
VDDR1#D11
VDDR1#D8
VDDR1#D5
VDDR1#E27
VDDR1#F4
VDDR1#G7
VDDR1#G10
VDDR1#G13
VDDR1#G15
VDDR1#G19
VDDR1#G22
VDDR1#G27
VDDR1#H22
VDDR1#H19
VDDR1#AD4
VDDR1#N4

NC#AE15
NC#AE16
NC#AE17
NC#AF15

NC#AH19
TPVDD TPVSS
TXVDDR#AF13

TXVDDR#AF14

VDDRH0
VDDRH1

A2VDD#AE20
A2VDD#AF21

A2VDDQ
AVDD

VDD1DI

I/O POWER

VDD2DI

PVDD PVSS
MPVDD MPVSS

4

VDDC#AC13
VDDC#AC15
VDDC#AC17
VDDC#AD13
VDDC#AD15

VDD15#H11
VDD15#H20

VDD15#M23

VDD15#P8

VDD15#Y23

VDD15#Y8
VDD15#AC11
VDD15#AC20

VDDR3#AC8
VDDR3#AC19
VDDR3#AC21
VDDR3#AC22

VDDR3#AD7
VDDR3#AD19
VDDR3#AD21

VDDR4#AC9
VDDR4#AC10

VDDR4#AD9
VDDR4#AD10

VDDR4#AG7

PCIE_VDDR_12#AG26
PCIE_VDDR_12#AG27
PCIE_VDDR_12#AG28

PCIE_VDDR_12#AJ30

PCIE_VDDR_12#AK29

PCIE_PVDD_12#N23
PCIE_PVDD_12#N24
PCIE_PVDD_12#P23

PCIE_PVDD_18#T23
PCIE_PVDD_18#U23
PCIE_PVDD_18#V23

PCIE_PVDD_18#W23

TXVSSR#AH14
TXVSSR#AG13
TXVSSR#AG14

A2VSSN#AH20
A2VSSN#AG21

NC#D9
NC#D13
NC#D19
NC#D25

NC#E4

NC#T4
NC#AB4

NC#AF18
NC#AG15
NC#AG18
NC#AH17

NC#AH18

VSSRH0
VSSRH1

A2VSSQ

AVSSN
AVSSQ
VSS1DI
VSS2DI

AC13
AC15
AC17
AD13
AD15

H11
H20
M23
P8
Y23
Y8
AC11
AC20

AC8
AC19
AC21
AC22
AD7
AD19
AD21

AC9
AC10
AD9
AD10
AG7

D9
D13
D19
D25
E4
T4
AB4

AG26
AG27
AG28
AJ30
AK29

N23
N24
P23

T23
U23
V23
W23

AF18
AG15
AG18
AH17

AH18

AH14
AG13
AG14

F19
M6

AH20
AG21

AF22
AH22
AD22
AE24
AE21

+VDDC

+VDDC_CT

+3.3V_BUS

GND_TPVSS

GND_TXVSSR

GND_A2VSSN
GND_A2VSSQ

GND_AVSSN

GND_PVSS

GND_MPVSS

+VDDR4

C69

C70

100nF

4.7uF

402

+PCIE_VDDR

+PCIE_PVDD_12

+PCIE_PVDD_18

GND_AVSSQ

+VDDC

C20
100nF

3

C21

C22

100nF

100nF

402 402402

+3.3V_BUS

B15
0R/8

ALT: 0R

C99

C98

1.0uF

1.0uF

TP9

3

C82

C23

100nF

100nF

402 402 402 402 402 402 402 402402 402 402 402 402

C37

1.0uF

C968

C969

1.0uF

1.0uF

C970

C971

1.0uF

1.0uF

C83
100nF

C44
100nF

+3.3V_BUS

+MVDDQ

C84
100nF

+3.3V_BUS

C39
100nF

402 402

C41
100nF

402 402

C55
100nF

402 402

C983

100nF/X
C984

100nF/X
C985

100nF/X

C46
100nF

C979

100nF/X
C980

100nF/X
C981

100nF/X
C982

100nF/X

C85
100nF

+VDDC_CT

C40
100nF

C42
100nF

C56
100nF

+VDDC

+Vout_Switcher

+MVDDQ

+12V_BUS_F1

+VDDC

+MVDDC

C86
100nF

C45
100nF

402 402 402 402402 402

C76
100nF

402 402

C78
100nF

402 402

C57
100nF

402 402

CAPS C979..C985 are
accross Plane Splits

They are not required
They should be populated
only if EMI issues ar e
found.

C87
100nF

C47
100nF

+VDDC

+VDDC

C77
100nF

C79
100nF

C61
100nF

C26
100nF

C88
100nF

C48
100nF

2

C24
10uf

C28
100nF

C90
100nF

C29
100nF

C91
100nF

C27
100nF

402 402 402 402402

C89
100nF

C49
100nF

2

C30
100nF

C92
100nF

+VDDC

U1F

P17

VDDC#P17

P18

VDDC#P18

P19

VDDC#P19

U12

VDDC#U12

U13

VDDC#U13

U14

VDDC#U14

U17

VDDC#U17

U18

VDDC#U18

U19

VDDC#U19

V19

VDDC#V19

V18

VDDC#V18

V17

VDDC#V17

V14

VDDC#V14

V13

VDDC#V13

V12

VDDC#V12

N18

C93
100nF

VDDC#N18

N17

VDDC#N17

N14

VDDC#N14

W17

VDDC#W17

W18

VDDC#W18

W12

VDDC#W12

W13

VDDC#W13

W14

VDDC#W14

N13

VDDC#N13

N19

VDDC#N19

M19

VDDC#M19

M18

VDDC#M18

M12

VDDC#M12

N12

VDDC#N12

M13

VDDC#M13

M14

VDDC#M14

P12

VDDC#P12

P13 P14

VDDC#P13 VDDC#P14

RV370SE

U1E

A2

VSS#A2

A10

VSS#A10

A16

VSS#A16

A22

VSS#A22

A29

VSS#A29

C1

VSS#C1

C3

VSS#C3

C28

VSS#C28

C30

VSS#C30

D27

VSS#D27

D24

VSS#D24

D21

VSS#D21

D18

VSS#D18

D15

VSS#D15

D12

VSS#D12

D6

VSS#D6

D4

VSS#D4

D10

VSS#D10

F27

VSS#F27

G9

VSS#G9

G12

VSS#G12

G16

VSS#G16

G18

VSS#G18

G21

VSS#G21

G24

VSS#G24

H27

VSS#H27

H23

VSS#H23

H21

VSS#H21

H18

VSS#H18

H16

VSS#H16

H14

VSS#H14

H12

VSS#H12

H9

VSS#H9

H8

VSS#H8

H4

VSS#H4

J23

VSS#J23

J24

VSS#J24

AD12

VSS#AD12

AG5

VSS#AG5

AG9

VSS#AG9

AG11

VSS#AG11

R7

VSS#R7

P4

VSS#P4

M7

VSS#M7

M8

VSS#M8

L4

VSS#L4

K1

VSS#K1

K7

VSS#K7

K8

VSS#K8

R8

VSS#R8

T1

VSS#T1

W8

VSS#W8

W7

VSS#W7

U8

VSS#U8

U4

VSS#U4

Y4

VSS#Y4

RV370SE

ADD ASIC DECOUPLING FOR ALL POWER AS REQUIRED

PLACED CLOSE TO THE POWER/GND PINS

WITH AS MANY AS POSSIBLE PLACED UNDER THE ASIC

Title

Size Document Number Rev
C

Date: Sheet

1

Part 6 of 6

VSS#M16
VSS#N16
VSS#N15
VSS#P15
VSS#P16
VSS#R18
VSS#R17
VSS#R16
VSS#R15
VSS#R14
VSS#R13
VSS#R12

VSS#T13
VSS#T14

VSS#T15
VSS#W15
VSS#V16
VSS#V15
VSS#U15
VSS#U16

VSS#T19

VSS#T18

VSS#T17

VSS#T16

CENTER ARRAY

VDDCI#W16
VDDCI#M15
VDDCI#R19

VDDCI#T12

VDDC#W19

VDDC#M17

Part 5 of 6

VSS#AB8
VSS#AB7
VSS#AB1

VSS#AC4
VSS#AC12
VSS#AC14
VSS#AD16
VSS#AC16
VSS#AC18
VSS#AD18

VSS#AK2

CORE GND

VSS#AJ1

PCIE_VSS#K28
PCIE_VSS#L28
PCIE_VSS#M24
PCIE_VSS#M25
PCIE_VSS#M26
PCIE_VSS#M27

PCIE_VSS#M28

PCIE_VSS#N28
PCIE_VSS#P28
PCIE_VSS#R23
PCIE_VSS#R24
PCIE_VSS#R25
PCIE_VSS#R26
PCIE_VSS#R27
PCIE_VSS#R28
PCIE_VSS#T24
PCIE_VSS#T28
PCIE_VSS#U28
PCIE_VSS#V24
PCIE_VSS#V25
PCIE_VSS#V26
PCIE_VSS#V27

PCIE_VSS#V28
PCIE_VSS#W24
PCIE_VSS#W28

PCIE_VSS#Y28

PCIE_VSS#AA23
PCIE_VSS#AA24
PCIE_VSS#AA25
PCIE_VSS#AA26
PCIE_VSS#AA27
PCIE_VSS#AA28
PCIE_VSS#AB28
PCIE_VSS#AC28
PCIE_VSS#AD26
PCIE_VSS#AD27
PCIE_VSS#AD28
PCIE_VSS#AE28
PCIE_VSS#AF28
PCIE_VSS#AH29

GIGABYTE

RV370 power

GV-RX30S128D-HT

1

M16
N16
N15
P15
P16
R18
R17
R16
R15
R14
R13
R12
T13
T14
T15
W15
V16
V15
U15
U16
T19
T18
T17
T16

W16
M15
R19
T12

W19
M17

AB8
AB7
AB1
AC4
AC12
AC14
AD16
AC16
AC18
AD18
AK2
AJ1

K28
L28
M24
M25
M26
M27
M28
N28
P28
R23
R24
R25
R26
R27
R28
T24
T28
U28
V24
V25
V26
V27
V28
W24
W28
Y28
AA23
AA24
AA25
AA26
AA27
AA28
AB28
AC28
AD26
AD27
AD28
AE28
AF28
AH29

1.1

of

04 16Thursday, January 06, 2005

8

7

6

5

4

3

2

***

Indicate number of power via required for the connection

1

Regulator for VDDC (ASIC Core)

Vout = 1.2V ~ 1.3V

81
72
63
54

+12V_BUS

+Vout_Switcher

C323
22uF_16V

******

OPT OPT

**

C324
22uF_16V

ALT. 1: MAXIM REGULATOR

D D

+5V +12V_BUS

R315

R316

0R/X

0R

C151

1.0uF/X

+VDDC_S

21

R314

D1

BAT254

+VDDC_B

C147
100nF

603
X7R
5%

C C

510K/X

C148

C149

470pF/X

27pF/X

402

ALT. 2: INTERSIL REGULATOR

+VDDC_S

C104
22nf

C312
10nF

402

R358 51K
R359 3K

C111
33pF

R368
15K_1%

402

U41

1
2
3
9

10

2
3
4
5
6
7

HSD

ILIM
COMPFBDL

LX
BST

PGND

MAX1954EUB/X

R357 10K

MU31

OCSET
SS
COMP
FB
EN
GND

ISL6522CB

GND

DH

IN

PVCC

LGATE

PGND

BOOT
UGATE
PHASE

8
6
5

4

7

+3.3V_BUS

VCCRT

141
13
12
11
10
9
8

ISL6522CB : SOIC

+PW_VDDC_HGD
+PW_VDDC_LGD

+12V_BUS_F1

C143

0.22uF

+VDDC_B

R351 0R

402

must be low impedance

must be low impedance

VDDC_FB

+12V_BUS

R99

2.2R

C115
100nF

603
X7R
5%

Alt. 1: Separate MOSFETs

Q24

4 5
3

6

2

7

1

8

IRF7413A

+PW_VDDC_M

4 5
3

6

2

7

1

8

IRF7413A

L21 2.2uH

R15
1R/X

C152

2.2nF/X

C150
10uF

+VDDC_S

***

***

C325
10nF/X

Cc1

R254

1.5K/X

Rc1

C301
470UF

0.019R @ 100kHz

3.5mm LS

R1

R353

1.00K

1%

0.8V Ref

R2

R356
2K

1%

High current path

B17
60R/6A

***

***

***

C321
470uF_10VQ22

***

+Vout_Switcher +VDDC +VDDC

RP1A 0R
RP1B 0R
RP1C 0R
RP1D 0R

Part NOTES

MAX1954

ISL6522

Do not install Cc1, Rc1

Install Cc1, Rc1

Part Vout R1 R2

MAX1954
ISL6522

0.8V Ref

***

C322
470uF_10V

***

1.2V

1.3V

1.00K 1% 2.00K 1%
ATI P/N 3240100100 ATI P/N 3240200100

1.00K 1%
ATI P/N 3240100100

1.6K 1%
ATI P/N 3240162100

+Vout_Switcher

L6 0R/8

+Vout_Switcher

L7 0R/8

B B

ALT: 0R

ALT: 0R

+PCIE_VDDR

+PCIE_PVDD_12

Circuit to hold PCI-E voltage low and wait for +VDDC for proper power sequence

+3.3V_BUS

R153
100K/X

402

1

R396

2 3

CMPT3904/X

100R/X

R395
20K/X

402

402

1

R397
100R/X

402

2 3

Q29

CMPT3904/X
Q27

+VDDC
+1.3V

A A

+1.2V 1.5K 3K

Rq3

1.5K

Rq4

2.4K

+VDDC

Rq3

Rq4

8

7

R393

1.50K/X

R394

3.01K/X

6

CMPT3904/X

Q28

1

+12V_BUS

2 3

5

VDDC_GOOD_PU (7)

VDDC_GOOD (7)

Title

Size Document Number Rev
Custom

4

3

Date: Sheet

2

GIGABYTE

REG (VDDC)

GV-RX30S128D-HT

1

05 16Thursday, January 06, 2005

1.1

of

5

4

3

2

1

Place caps very

+12V_BUS

close to power pin

C13

C12

100nF

+3.3V_BUS

R811
33R

C800

REG9

D D

TL431CDBVR

0.8V

1.25V 100R

1.5V

1.8V

1.84V

C C

1.5

1.6V

1.7V

1.8175V

Voltage Req.

3.3V

2.65V 301R

2.61V 221R (402, 1%) (402, 1%)

B B

2.5V 0R

+MVDDQ +MVDDC

RP2A 0R
RP2B 0R
RP2C 0R
RP2D 0R

+MVDDQ +MVDDC

RP195A 0R
RP195B 0R
RP195C 0R
RP195D 0R

10uF_6.3V

4

NC

1

NC

2

5 3

R1 R2Voltage Req.
150R
P/N 3160150000

P/N 3160100000 402 P/N 3160100000 402
100R

54.9R
P/N 3240054900

49.9R 140R
P/N 3240049900

Rx1 for 1.25V Ref
432R
P/N 3240432000
432R
P/N 3240432000
432R
P/N 3240432000
681R

P/N 3240681000
P/N 3160681000 402

Ry1 for 2.5V Ref Ry2 for 2.5V Ref

1.07K

301R (402, 1%)
P/N 3160301000

(402, 1%) (402, 1%)

P/N 3160301000

P/N 3230000000
P/N 3150000000 402

81
72
63
54

81
72
63
54

R812
100R

1%

402

R813
100R

1%

402

402

402P/N 3160100000

603

603

R1

R2

2.5V_REF2

1.25V_REF2

71.5R
P/N 324075R500
100R

150R

140R
P/N 3240140000

P/N 3240140000
Rx2 for 1.25V RefVoltage Req.

2.15K
P/N 3240215100

1.5K
P/N 3240150100

1.21K
P/N 3240121100

1.5K
P/N 3240015200

3.32K
P/N 3240332100P/N 3240107100

3.32K2.7V
P/N 3240332100

4.99K
P/N 3160499100

4.99K
P/N 3160499100P/N 3160221000
DNI

1.25V_REF2

R101 1K

3

402

2

R102 432R

R103

2.15K

Rx2

1.25V_REF2

R105 1K

5

402

6

R107
0R

R109 1K

DNI

R113 1K

Rx2

10

402

9

R111

4.99K/X

402

3160499100

Ry2

12

402

13

R115
0R

402

Ry2

402P/N 3160150000

2.5V_REF2

2.5V_REF2

1.61V 432R

1.69V

1.718V

1.75V

Alt. regulator for +PVDD
Vout = 1.8V
Iout = 30mA MAX

A A

3 2

R284
33R/X

REG40
AS432S/X

+PVDD

R287

Rt1

681R/X

402

1%

1

R290

1.5K/X

1%

MREG40

4

NC

SC431LC5SK-1/X

1

NC

2

Rt2

5 3

GND_PVSS

5

Alt regulator for +MPVDD

Vout = 1.8V

Iout = 10mA MAX

+MPVDD

+3.3V_BUS +3.3V_BUS+3.3V_BUS

R285
75R/X

REG32
AS432S/X

3 2

R288

Rt1

681R/X

402

1%

R291

1.5K/X

1%

4

NC

1

NC

2

Rt2

402

GND_MPVSS

1

5 3

MREG32
SC431LC5SK-1/X

4

Alt. regulator for +TPVDD
Vout = 1.65V ~ 1.85V
Iout = 20mA MAX

603
X7R
5%

411

U81A

+

1

-

LM324M

U81B

+

7

-

LM324M

R106 681R/X

DNI

U81C

+

8

-

LM324M

R110 0R

U81D

+

14

-

LM324M

R114 301R/X

DNI

3 2

100nF

603
X7R
5%

Rx1

402

3160681000

Rx1

G_MVDDC

402

Ry1

G_MVDDQ

402

3160301000

Ry1

R286
56R

REG39
AS432S

1

+MVDDC +3.3V_BUS

Q31

1

CMPT3904

150mW MAX 350mW MAX

2 3

CMPT3904: 40V 200mA
MMBT2222: 40V 600mA

+3.3V_BUS

402

402402

2

4

Rt1

Rt2

+3.3V_BUS

+3.3V_BUS

4
1
2

Q32

4

BCP68/X

1A SOT-223
350mW MAX

3 2

<ATIPartNumbers>

71

8

Q33A
BSO4804/X

53

6

Q33B
BSO4804/X

<ATIPartNumbers>

Rt2

2.15K

1.5K

1.5K 3160150100

1.21K

1.5K 3160150100

1.5K 3160150100

NC
NC

5 3

GND_TPVSS

1

8A continuous @ 25'C

6.4A continuous @ 70'C
32A pulse drain current @ 25'C
RDS(on) MA X=28.2mR@Vgs=4.5V,Id =6.7A

275mW MAX

8A continuous @ 25'C

6.4A continuous @ 70'C
32A pulse drain current @ 25'C
RDS(on) MA X=28.2mR@Vgs=4.5V,Id =6.7A

275mW MAX

Rt1

32404320001.52V 432R
3160432000 3160215100

3240432000
3240432000432R
3240562000

562R

3160604000604R
3160604000 604R1.8V

+TPVDD

R289
604R

1%

R292

1.37K

1%

1

1A SOT-223200mA, SOT-23

3 2

ALT

+PCIE_PVDD_18

1.8V
175mA MAX

MQ33

4 5
3
2
1

IRF7201

5.8A continuous @ 70'C
58A pulse drain current @ 25'C
RDS(on) MA X = 50mR@Vgs=4.5V,Id=3.7A

550mW MAX

3230015200
3240121100

32300152001.5K

32300152001.5K

31601371001.37K

MREG39
SC431LC5SK-1/X

3

MQ31

4

BCP68/X

L4
0R/8

ALT: 0R

ALT

5260002100

C315
10uF_6.3V/X

+Vout_Switcher

L12

1.8uH/X

+VDDC_CT

6
7
8

ALT

ALT: 0R

5260002100

C302
10uF_6.3V

ALT

+1.8V +VDDR4 +PVDD +TPVDD

C303
10uF_6.3V/X

+3.3V_BUS

1.5V
150mA MAX

+MPVDD

L9

L8

0R/8

1.8uH/X

ALT: 0R ALT: 0R ALT: 0R ALT: 0R

5260002100

5260002100

+VDDR4: 90mA MAX TOTAL

+MPVDD: 10mA MAX

In this case, MVDDQ=MVDDC, and MVDDC=2.5V

+MVDDC

C314
10uF_6.3V/X

+MVDDQ

***

C305
470uF_10V

***

2.5V ~ 2.6V
200mA MAX

+MVDDQ +MVDDC

L11

L10

1.8uH/X

0R/8

5260002100

5260002100

+PVDD: 25mA MAX

+TPVDD: 50mA MAX

2.5V ~ 2.6V
+MVDDC: 500mA MAX
+MVDDC and +MVDDQ: 700mA MAX

***

C304

CONSIDER HEATSINK ON FET

470uF_10V/X

***

Place caps across

C973

+MVDDQ and +MVDDC
Plane Splits

100nF/X

If +MVDDQ and +MVDDC

C974

are shorted, then these
caps should be populated
with 0R Resistors.

100nF/X
C975

100nF/X
C976

100nF/X
C977

100nF/X
C978

100nF/X

Rails derived from +VDDR4

+AVDD: 10mA MAX
+A2VDDQ: 20mA MAX
+VDDOI_PINS: 20mA MAX
+TXVDDR_PINS: 20mA MAX

2

Alt. regulator for +MVDDC
Vout = 2.5V ~ 2.6V
Iout = 500mA MAX

Voltage Req.

3.34V
[-0.04V/+0.04V]

3.45V 2.43K4.32K
[-0.04V/+0.04V]

[-0.03V/+0.03V]

G_MVDDC

Alt regulator for +MVDDQ
Vout = 2.5V ~ 2.6V
Iout = 200mA MAX

Voltage Req.

1.8V
[-0.09V/+0.18V]

2.5V

2.6V

G_MVDDQ

Alt regulator for +VDDC_CT
Vout = 1.5V
Iout = 150mA MAX

Rm1

4.32K

1K2.5V 3240100100 1K 3240100100

C138
100nF/X

603
X7R
5%

REG33
AS432S/X

1

3 2

Rq1
681R

3240681000

3240100100

1K

4.75K

3240475100 4.32K 3240432100

C136
100nF/X

603
X7R
5%

REG34

AS432S/X

1

3 2

+3.3V_BUS

REG31
LT1117CST/X

3 2

IN OUT

CASE

ADJ

1

R293
200R/X

1%

Title

Size Document Number Rev
Custom

Date: Sheet

Rm2

2.55K

+12V_BUS

R949
750R/X

/.25W

MREG33
SC431LC5SK-1/X

4

NC

1

NC

2

5 3

Rq2

1.5K

1K

+12V_BUS

+MVDDQ

R277
750R/X

/.25W

MREG34
SC431LC5SK-1/X

4

NC

1

NC

2

5 3

+VDDC_CT

4

R294

1.0K/X

1%

402

Need at least a 4.7uF
output cap for stability

GIGABYTE

REG (Memory, VDDC_CT)

GV-RX30S128D-HT

1

+MVDDC

R958

1.0K/X

1%

402

R960

1.0K/X

1%

402

3230015200

3240100100

R279

Rq1

1.0K/X

1%

402

R283

1.0K/X

Rq2

1%

402

06 16Thursday, January 06, 2005

of

Rm1

Rm2

1.1

8

7

6

5

4

3

2

1

DNI

DNI

DNI

+12V_BUS

+Vout_Switcher

411

U82A

3

+

402

402

2

-

R118 0R/X

R119
10K/X

Rx2

12

+

13

-

R122 681R/X

R123

1.50K/X

Rx2

LM324M/X

U82D

LM324M/X

1

402

Rx1

14

Rx1

Q35

4 5
3

6

2

7

1

8

IRF7413A/X

ALT

9.6A continuous @ 70'C
96A pulse drain current @ 25'C
RDS(on) MA X=18mR@Vgs=4.5V,Id =6.0A

+3.3V_BUS

1

4

1A SOT-223
350mW MAX

3 2

<ATIPartNumbers>

Q36
BCP68/X

+VDDC

C306
10uF_6.3V/X

ALTALT

+PCIE_PVDD_18

C308
10uF_6.3V

1.3V 2.5V
8A MAX
MIGHT NEED HEATSINK ON FET

MC308
470uF/X

+PCIE_PVDD_18: 1.8V 500mA MAX

120mA

+A2VDD

+MVDDC

L5
0R/8

ALT: 0R

Optional when +Vout_Switcher is above 1.2V

402

Q37_PIN2

8A continuous @ 25'C

MQ37

4 5
3
2
1

IRF7413A/X

RP111A 0R
RP111B 0R
RP111C 0R
RP111D 0R

6
7

+PCIE_VDDR

8

C309
10uF_6.3V

81
72
63
54

+PCIE_PVDD_12

C310
33uF/X

ALT

C160
100uF_16V/X

Multi footprint

+PCIE_VDDR: 1.2V 1300mA MAX

C161

MC160
470uF/X

22uF/X

C162
22uF/X

+PCIE_PVDD_12: 1.2V 250mA MAX

+Vout_Switcher

53

U82B

5

+

402

402

R127
10K/X

402

Rx2

10

R131
10K/X

402

Rx2

6

9

-

LM324M/X

R126 0R/X

U82C

+

-

LM324M/X

R130 0R/X

7

402

Rx1

ALT

MR128

8

0R/X

402

DNI

402

Rx1

ALT

6

Q37B

4

BSO4804/X

ALT

6.4A continuous @ 70'C
32A pulse drain current @ 25'C
2W power dissipation @ 25'C
RDS(on) MA X=28.2mR@Vgs=4.5V,Id =6.7A

+Vout_Switcher

Q37_PIN2

2

R128

0R/X

71

8

Q37A
BSO4804/X

ALT

8A continuous @ 25'C

6.4A continuous @ 70'C
32A pulse drain current @ 25'C
2W power dissipation @ 25'C
RDS(on) MA X=28.2mR@Vgs=4.5V,Id =6.7A

Alt. regulator for +A2VDD
Vout = 2.5V
Iout = 120mA MAX

+A2VDD+3.3V_BUS

REG35

1

VIN

3

SHDN

C139
100nF/X

402

+A2VDD and GND_A2VSSN routed with at least 15 mil
trace and not longer than 1.5 inch.

Alt. regulator for PCIE_PVDD_18
Vout = 1.82V
Iout = 500mA MAX

+3.3V_BUS

MREG36
LT1117CST

3 2

IN OUT

ADJ

1

Need at least a 10uF Tant.
output cap for stability
Min. Load Current: 10mA

Regulator for +5V
Vout = 5V
Iout = 20mA MAX

+12V_BUS

R1042
220R

1206, 1/4W

REG29

TL431CDBVR

NC
NC

5 3

BYPASS

GND

2.5V/X

2

GND_A2VSSN

CASE

R295

49.9R

402

1%

R1

4
1
2

R2

VOUT

4

R1040

1.0K

1%

402

R1041

1.0K

1%

402

5

4

+PCIE_PVDD_18

R296
110R

1%

+5V

Multi-footprint

C917

10uF_6.3V

MC917
10uf/X

Place caps very
close to power pin

C14

C15

100nF/X

100nF/X

603

603

X7R

X7R

D D

C C

B B

REG8

TL431CDBVR/X

+3.3V_BUS

5 3

R814
33R/X

NC
NC

2.5V_REF

4
1

R815

2

324R/X

R1

1%

402

1.2V_REF

R816
301R/X

R2

1%

402

5% 5%

1.2V_REF

1.2V_REF

1.2V_REF

1.2V_REF

R117 1K/X

R121 1K/X

R125 1K/X

R129 1K/X

4

+3.3V_BUS

C166

1.0uF/X

REG37
MAX1935ETA/X

2

IN2

4

SHDN

3

POK

OUT7

TH_GND9
TH_GND10
TH_GND11

81

OUTIN

7

6

SET

5

GND

9
10
11

3

+3.3V_BUS

MREG37

R141

1 5

IN VOUT

VDDC_GOOD(5)

A A

R145 0R/X

8

2.15K/X

4 2

R142

1.24K/X

REFEN GND

RT9173ACL5/X

C157

1.0uF/X

402

+PCIE_VDDR

3

6

TAB

VCNTL

VDDC_GOOD_PU(5)

7

R143
1K/X

402

R144 0R/X

+3.3V_BUS

402

C163

1.0uF/X

REG38
MAX1935ETA/X

2

IN2

4

SHDN

3

POK

6

OUT7

TH_GND9
TH_GND10
TH_GND11

81

OUTIN

7

6

SET

5

GND

9
10
11

+PCIE_PVDD_12

R151

1.0K/X

402

C165

R1

10uf

R152
2K/X

402

R2 R2

5

+PCIE_PVDD_18

R154

6.81K/X

402

R1

R155

5.49K/X

402

Part Vout R1 R2

C167
10uf

MAX1935

0.8V Ref

1.2V

1.79V

Title

Size Document Number Rev
Custom

Date: Sheet

2

402 402

1.00K 1% 2.00K 1%
ATI P/N 3160100100 ATI P/N 3160200100

402

6.81K 1%
ATI P/N 3160681100

5.49K 1%
ATI P/N 3160549100

GIGABYTE

REG (PCI-E)

GV-RX30S128D-HT

07 16Thursday, January 06, 2005

of

1

1.1

5

4

3

2

1

MDA[63..0]

MDA[63..0](3)

D D

C C

QSA[7..0]

QSA[7..0](3)

MDA0

RP122A 56R

MDA1

RP122B 56R

MDA2

RP122C 56R

MDA3

RP122D 56R

MDA4

RP118B 56R
RP118C 56R

MDA5

RP118A 56R

MDA6

RP118D 56R

MDA7

RP120B 56R

MDA8
MDA9

RP119B 56R

MDA10

RP119A 56R

MDA11

RP119C 56R

MDA12

RP120D 56R
RP120A 56R

MDA13
MDA14

RP120C 56R
RP119D 56R

MDA15
MDA16

RP121D 56R

MDA17

RP121C 56R

MDA18

RP121B 56R

MDA19

RP121A 56R

MDA20

RP117A 56R

MDA21

RP117B 56R

MDA22

RP117C 56R

MDA23

RP117D 56R

MDA24

RP123B 56R

MDA25

RP123A 56R

MDA26

RP124B 56R
RP123D 56R

MDA27
MDA28

RP123C 56R

MDA29

RP124A 56R

MDA30 M_MDA30

RP124D 56R

MDA31

RP124C 56R

MDA32

RP127C 56R

MDA33

RP127B 56R
RP127A 56R

MDA35

RP127D 56R

MDA36

RP128D 56R

MDA37

RP128C 56R

MDA38

RP128A 56R

MDA39

RP128B 56R

MDA40

RP125B 56R

MDA41

RP125A 56R

MDA42

RP125C 56R
RP126A 56R

MDA44

RP126D 56R
RP126C 56R

MDA46

RP126B 56R

MDA47 M_MDA47

RP125D 56R

MDA48

RP131A 56R

MDA49

RP131C 56R

MDA50

RP131B 56R

MDA51

RP131D 56R

MDA52

RP132B 56R

MDA53

RP132D 56R

MDA54

RP132C 56R

MDA55

RP132A 56R

MDA56

RP129B 56R

MDA57

RP129C 56R

MDA58

RP130D 56R

MDA59

RP129A 56R

MDA60

RP129D 56R

MDA61

RP130B 56R

MDA62

RP130C 56R

MDA63

RP130A 56R

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

R759 0R
R760 0R
R761 0R
R762 0R
R764 0R
R763 0R
R765 0R
R766 0R

8 1
7 2
6 3
5 4

7 2

5 4
8 1
6 3

5 4
6 3
7 2
8 1

7 2
8 1

5 4
6 3

6 3
7 2
8 1
5 4
5 4
6 3
8 1
7 2
7 2
8 1
6 3
8 1
5 4
6 3
7 2
5 4
8 1
6 3
7 2
5 4
7 2
5 4
6 3
8 1

5 4

7 2
6 3
8 1

M_MDA0
M_MDA1
M_MDA2
M_MDA3
M_MDA4

72

M_MDA5

63

M_MDA6

81

M_MDA7

54

M_MDA8

M_MDA9

72

M_MDA10

81

M_MDA11

63

M_MDA12
M_MDA13
M_MDA14
M_MDA15

54

M_MDA16
M_MDA17
M_MDA18
M_MDA19
M_MDA20

81

M_MDA21

72

M_MDA22

63

M_MDA23

54

M_MDA24
M_MDA25
M_MDA26

72

M_MDA27
M_MDA28
M_MDA29

81
54

M_MDA31

63

M_MDA32
M_MDA33
M_MDA34MDA34
M_MDA35
M_MDA36
M_MDA37
M_MDA38
M_MDA39
M_MDA40
M_MDA41
M_MDA42
M_MDA43MDA43
M_MDA44
M_MDA45MDA45
M_MDA46

M_MDA48
M_MDA49
M_MDA50
M_MDA51
M_MDA52
M_MDA53
M_MDA54
M_MDA55
M_MDA56

72

M_MDA57

63

M_MDA58
M_MDA59

81

M_MDA60

54

M_MDA61
M_MDA62
M_MDA63

M_MDA[63..0]

SERIES Resistors

M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7

M_MDA[63..0] (9)

For Bi-Directional signals,
Series resistors should be
placed close to the memory

M_QSA[7..0]

M_QSA[7..0] (9)

CLOCK
terminations

CLKA0(3,9)

CLKA#0(3,9)

CLKA1(3,9)

CLKA#1(3,9)

M_CLKA0 (3,9)

M_CLKA#0 (3,9)

M_CLKA1

M_CLKA1 (3,9)

M_CLKA#1 (3,9)

M_CLKA0

M_CLKA#0

M_CLKA#1

R797
56R

R798
56R

R799
56R

R800
56R

C778
10nF

C779
10nF

B B

A A

M_DQMA#[7..0](9)

M_MAA[14..0](3,9)

M_RASA#(3,9)

M_CASA#(3,9)

M_WEA#(3,9)
M_CSA#0(3,9)

M_CKEA(3,9)

5

M_DQMA#[7..0]

M_MAA[14..0]

M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7

M_MAA1 MAA1
M_MAA3 MAA3

M_MAA4 MAA4
M_MAA6 MAA6
M_MAA8 MAA8

M_MAA9 MAA9
M_MAA10 MAA10
M_MAA11 MAA11

M_MAA14 MAA14

M_RASA#
M_CASA#
M_WEA#
M_CSA#0
M_CKEA

R775 56R
R776 56R
R777 56R
R778 56R
R780 56R
R779 56R
R781 56R
R782 56R

4

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

MAA0M_MAA0
MAA2M_MAA2

MAA5M_MAA5
MAA7M_MAA7

MAA12M_MAA12
MAA13M_MAA13

RASA# (3,9)
CASA# (3,9)
WEA# (3,9)
CSA#0 (3,9)
CKEA (3,9)

DQMA#[7..0]

MAA[14..0]

DQMA#[7..0] (3)

MAA[14..0] (3,9)

For Uni-Directional
signals, Series
resistors should be
placed close to the
ASIC

3

Title

Size Document Number Rev
Custom

2

Date: Sheet

GIGABYTE

Serial Termination

GV-RX30S128D-HT

1

08 16Thursday, January 06, 2005

1.1

of

8

M_DQMA#[7..0](8)

D D

M_QSA[7..0](8)

C C

M_MAA[14..0](3)

B B

M_DQMA#[7..0]

M_QSA[7..0]

M_CLKA#0(3,8)
M_CLKA#1(3,8)

M_CLKA0(3,8)
M_CLKA1(3,8)

M_CKEA(3)
M_WEA#(3)
M_CASA#(3)
M_RASA#(3)
M_CSA#0(3)

M_MAA[14..0]

M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7

M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7

M_CLKA0#
M_CLKA1#

M_CLKA0
M_CLKA1

M_CKEA
M_WEA#
M_CASA#0
M_RASA#0
M_CSA#0

M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_MAA14

7

C206

100nF
C287
100nF

402

M_MAA0

M_MAA1

M_MAA2

M_MAA3

M_MAA4

M_MAA5

M_MAA6

M_MAA7

M_MAA8

M_MAA9

M_MAA10

M_MAA11

M_CLKA0
M_CLKA#0
M_CKEA

M_CSA#0

M_RASA#0

M_CASA#0

M_WEA#

M_QSA1

M_QSA3

M_DQMA#1

M_DQMA#3

M_MAA13

M_MAA12

+MVDDQ

C226
100nF

+VREF_U33 +VREF_U34

C288
100nF

402

M_MAA0

M_MAA1

M_MAA2

M_MAA3

M_MAA4

M_MAA5

M_MAA6

M_MAA7

M_MAA8

M_MAA9

M_MAA10

M_MAA11

M_CLKA0
M_CLKA0#
M_CKEA

M_CSA#0

M_RASA#0

M_CASA#0

M_WEA#

M_QSA2

M_QSA0

M_DQMA#2

M_DQMA#0

M_MAA13

M_MAA12

M_MDA[63..0](8)

6

Channel A Bottom Down

402

U29

49

VREF

29

A0

30

A1

31

A2

32

A3

35

A4

36

A5

37

A6

38

A7

39

A8

40

A9

28

A10/AP

41

A11

45

CK

46

CK

44

CKE

24

CS

23

RAS

22

CAS

21

WE

16

LDQS

51

UDQS

20

LDM

47

UDM

26

BA0

27

BA1

4MX16X4

<3RD PART FIELD>

402 402

U33

49

VREF

29

A0

30

A1

31

A2

32

A3

35

A4

36

A5

37

A6

38

A7

39

A8

40

A9

28

A10/AP

41

A11

45

CK

46

CK

44

CKE

24

CS

23

RAS

22

CAS

21

WE

16

LDQS

51

UDQS

20

LDM

47

UDM

26

BA0

27

BA1

4MX16X4

<3RD PART FIELD>

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53

VDD#18
VDD#33

VDDQ

VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61

VSS#48
VSS#66

VSSQ#6

VSSQ#12

VSSQ
VSSQ#58
VSSQ#64

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53

VDD#18
VDD#33

VDDQ

VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61

VSS#48
VSS#66

VSSQ#6

VSSQ#12

VSSQ
VSSQ#58
VSSQ#64

M_MDA13

2

DQ0

M_MDA8

4

DQ1

M_MDA14

5

DQ2

M_MDA12

7

DQ3

M_MDA15

8

DQ4

M_MDA11

10

DQ5

M_MDA9

11

DQ6

M_MDA10

13

DQ7

M_MDA25

54

DQ8

M_MDA24

56

DQ9

M_MDA28

57

M_MDA27

59

M_MDA30

60

M_MDA31

62

M_MDA26

63

M_MDA29

65
14

NC

17
19
25

M_MAA14 M_MAA14

42
43

+MVDDC +MVDDC

50
53

1

VDD

+MVDDQ

18
33
3
9
15
55
61

34

VSS

48
66
6
12
52
58
64

M_MDA23

2

DQ0

M_MDA22

4

DQ1

M_MDA21

5

DQ2

M_MDA20

7

DQ3

M_MDA19

8

DQ4

M_MDA18

10

DQ5

M_MDA17

11

DQ6

M_MDA16

13

DQ7

54

DQ8

M_MDA5

56

DQ9

M_MDA4

57

M_MDA6

59

M_MDA0

60

M_MDA1

62

M_MDA2

63

M_MDA3

65
14

NC

17
19
25
42
43
50
53

1

VDD

+MVDDQ

18
33
3
9
15
55
61

34

VSS

48
66
6
12
52
58
64

5

+MVDDQ+MVDDQ

C216
100nF

+VREF_U30+VREF_U29

C289
100nF

402

M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11

M_CLKA1
M_CLKA1#
M_CKEA

M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#

M_QSA5
M_QSA6

M_DQMA#5
M_DQMA#6

M_MAA13
M_MAA12

+MVDDQ

C236

100nF
C290
100nF

402

M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11

M_CLKA1
M_CLKA1#
M_CKEA

M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#

M_QSA7
M_QSA4

M_DQMA#7
M_DQMA#4

M_MAA13
M_MAA12

Channel A Bottom Up

402

U30

49

VREF

29

A0

30

A1

31

A2

32

A3

35

A4

36

A5

37

A6

38

A7

39

A8

40

A9

28

A10/AP

41

A11

CK
CK
CKE

CS
RAS
CAS

VDD#18

WE

VDD#33

LDQS

VDDQ#9

VDDQ#15

UDQS

VDDQ#55

VDDQ#61
LDM
UDM

VSS#48
VSS#66
VSSQ#6

BA0

VSSQ#12

BA1

VSSQ#58

VSSQ#64

4MX16X4

<3RD PART FIELD>

U34

VREF

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11

CK
CK
CKE

CS
RAS
CAS

VDD#18

WE

VDD#33

LDQS

VDDQ#9

VDDQ#15

UDQS

VDDQ#55

VDDQ#61
LDM
UDM

VSS#48
VSS#66
VSSQ#6

BA0

VSSQ#12

BA1

VSSQ#58

VSSQ#64

4MX16X4

<3RD PART FIELD>

Channel A Top UpChannel A Top Down

NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53

NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53

45
46
44

24
23
22
21

16
51

20
47

26
27

49

29
30
31
32
35
36
37
38
39
40
28
41

45
46
44

24
23
22
21

16
51

20
47

26
27

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDDQ

VSSQ

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

VDDQ

VSSQ

4

M_MDA41

2

DQ0

M_MDA40

4

DQ1

M_MDA42

5

DQ2

M_MDA47

7

DQ3

M_MDA43

8

DQ4

M_MDA46

10

DQ5

M_MDA45

11

DQ6

M_MDA44

13

DQ7

M_MDA48

54

DQ8

M_MDA50

56

DQ9

M_MDA49

57

M_MDA51

59

M_MDA55

60

M_MDA52

62

M_MDA54

63

M_MDA53

65
14

NC

17
19
25
42
43
50
53

1

VDD

VSS

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9

VDD

VSS

+MVDDQ

18
33
3
9
15
55
61

34
48
66
6
12
52
58
64

M_MDA63

2

M_MDA61

4

M_MDA62

5

M_MDA58

7

M_MDA60

8

M_MDA57

10

M_MDA56

11

M_MDA59

13

M_MDA38M_MDA7

54

M_MDA39

56

M_MDA37

57

M_MDA36

59

M_MDA34

60

M_MDA33

62

M_MDA32

63

M_MDA35

65
14

NC

17
19
25

M_MAA14M_MAA14

42
43

+MVDDC+MVDDC

50
53

1

+MVDDQ

18
33
3
9
15
55
61

34
48
66
6
12
52
58
64

3

R60

4.7K

402 402

+VREF_U29

R61

4.7K

402

+MVDDQ

R68

4.7K

402 402

+VREF_U33

R69

4.7K

+MVDDQ+MVDDQ

+MVDDQ

R62

4.7K

+VREF_U30

R63

4.7K

402

R70

4.7K

+VREF_U34

R71

4.7K

402402

2

1

Put 1 1uF cap per power pin of m em o r y

+MVDDQ

C572
100nF

402 402 402 402 402

+MVDDQ

C592
100nF

A A

C229
100nF

8

7

C231
100nF

C232
100nF

+MVDDC

C574

C573
100nF

C593
100nF

C575

100nF

100nF

+MVDDC

C594

C595

100nF

100nF

402 402402 402 402

+MVDDQ+MVDDC

C235
100nF

402 402402 402 402 402 402402 402 402 402 402

6

C221
100nF

C576
100nF

C596
100nF

C222
100nF

+MVDDQ

+MVDDQ

C577
100nF

C597
100nF

C223
100nF

C578
100nF

C598
100nF

C224
100nF

C579
100nF

C599
100nF

C237
100nF

+MVDDC

C581

C580
100nF

100nF

402 402402 402 402

+MVDDC

C600

C601

100nF

100nF

402 402402 402 402

C243

C239

C238
100nF

5

100nF

100nF

4

3

DATA GROUP SHOULD BE ASSIGNED TO EACH DQS AN D D QM ACCO RDI NGLY
AND THIS MAPPING IS JUST FOR PLACEMENT AND ROUTING REASONS

All +VDD_MEM_IO and +VDD decoupling caps should be equally distributed
per memory chip. As close to the pin as possible.

Title

Size Document Number Rev
Custom

Date: Sheet

2

GIGABYTE

TSOP 16Mx16 DDR

GV-RX30S128D-HT

09 16Thursday, January 06, 2005

1

1.1

of

8

7

6

5

4

3

2

1

GPIO0

OPTION STRAPS

+3.3V_BUS

D D

C C

Mem_Strap0(2)

Mem_Strap1(2)

B B

LCDDATA16(2)

LCDDATA17(2)

32

SW1B
DIP_SWX2/X

R250 10K/X

VHAD0(2)

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO11

GPIO12

GPIO13

GPIO9

GPIO8

DNI

R201 10K
R202 10K/X
R203 10K
R204 10K/X

R205 10K/X

R206 10K

R207 10K/X

R208 10K

R219 10K
R220 10K/X
R221 10K/X
R222 10K
R223 10K/X
R224 10K
R209 10K/X
R210 10K
R211 10K/X
R212 10K
R213 10K
R214 10K/X
R215 10K
R216 10K/X

R217 10K/X
R218 10K

R235 10K/X
R236 10K
R237 10K/X
R238 10K

R227 10K/X
R228 10K
R229 10K/X
R230 10K

R231 10K/X
R232 10K

DESKTOP
MOBO
DESKTOP
MOBO

DNI

Tumwater

Grantsdale

DNI
DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

DNI

+VDDR4

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6

GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13

STRAPS

STRAP_B_PTX_PWRS_ENB

STRAP_B_PTX_DEEMPH_EN

PCIE_MODE(1:0)

STRAP_FORCE_COMPLIANCE

STRAP_B_PPLL_BW GPIO6

STRAP_DEBUG_ACCESS Strap to set the debug muxes to bring out DEBUG signals

ROMIDCFG(3:0)

STRAP P INTERRUPT

ENABLED (DEFAULT)

LOW

DISABLED

HIGH

MEMORY TYPE STRAPS

Mem_Strap0 Mem_Strap1

SAM

00

INF

1

HYN

0

ELPIDA

11

GPIO[6..0]

GPIO[13..8]

0
1

GPIO[6..0] (2)

GPIO[13..8] (2)

DESCRIPTIONPIN

GPIO0

GPIO1

GPIO(3:2)

GPIO4

GPIO5

GPIO8

GPIO(9,13:11)

DVPDATA_20VIP_DEVICE Indicates if any slave VIP host devices drove this in low during reset.

(VHAD0 net)

Tansmitter Power Savings Enable
0: 50% Tx output swing for mobile mode
1: full Tx output swing

Transmitter De-emphasis Enable
0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled

00: PCI Express 1.0A mode (Grantsdale)
01: Kyrene-compatible mode
10: PCI Express 1.0 mode (Tumwater)
11: PCI Express 1.0A mode and short-circuit internal loopback mode
(Rx connected directly to Tx of PHY)

Transmitter Extra Current
0: normal mode
1: extra current in Tx output stage - potential power savings for mobile mode

Force chip to go to Compliance state quickly for Tester purposes
0: normal operational mode
1: compliance mode

PLL Bandwidth
0: full PLL Bandwidth
1: reduced PLL bandwidth

even if registers are inaccessible.

If no ROM attached, comtrols chip IDis. If rom attached identifies ROM type
0000 - No ROM, CHG_ID=0
0001 - No ROM, CHG_ID=1
0100 - reserved
0110 - reserved
1000 - Parallel ROM, chip IDis from ROM
1001 - Serial AT25F1024 ROM (Atmel), chip IDis from ROM
1010 - Serial AT45DB011 ROM (Atmel), chip IDis from ROM
1011 - Serial M25P10 ROM (ST), chip IDis from ROM

1100 - Serial M25P05 ROM (ST), chip IDis from ROM

1100 - Serial NX25F011B ROM (ISSI), chip IDis from ROM

0 - Slave VIP host port devices present

1 - No slave VIP host port devices reporting presence during reset

GPIO8(2)

GPIO9(2)
GPIO10(2)
ROMCS#(3)

R91
10K

+3.3V_BUS

ASIC DEFAULT

0

0

00

0STRAP_B_PTX_IEXT

0

0

0

SERIAL EEPROM 512K

ROM_SO

SI/A16
SCK/WEb
CSb

HOLD1

+3.3V_BUS

C80
100nF

U11

5

D

6

C

1

S

7

HOLD

3

W

8

VCC

M25P05-AVMN6T

2

Q

4

VSS

A A

Title

Size Document Number Rev
Custom

8

7

6

5

4

3

Date: Sheet

2

GIGABYTE

Strap and BIOS Flashrom

GV-RX30S128D-HT

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OPTIONAL ESD/HOTPLUG PROTECTION DI O DES

PRIMARY CRT

A_R_DVI-I (12)
A_G_DVI-I (12)

L51 47nH
L52 47nH
L53 47nH

C403

3.3pF/X

402 402 402

+5V

1

R405

6.8K

402

DDCDATA_DAC1_5V

32

BSH111

+5V

Q51

1

R407

6.8K

402

DDCCLK_DAC1_5V

32

BSH111
Q52

5
4

U6B
SN74ACT86D

10

9

U6C
SN74ACT86D

13
12

U6D
SN74ACT86D

A_HSYNC_DAC1_B

6

A_VSYNC_DAC1_B

8

11

R401 75.0R
R402 75.0R
R403 75.0R

CRT1DDCDATA(1,2)

CRT1DDCCLK(1,2)

A_HSYNC_DAC1(1,2)

A_VSYNC_DAC1(1,2)

Pr
Y
Pb

C402

C401

3.3pF/X

3.3pF/X

402 402

402

+3.3V_BUS

R404

4.7K

402

+3.3V_BUS

R406

4.7K

402 402

A_R_DAC1(2)
A_G_DAC1(2)

A_B_DAC1(2)

C C

B B

L54 47nH
L55 47nH
L56 47nH

C405

C406

C404

8.0pF

8.0pF

8.0pF

402

Place close to ASIC

R415 33R

R416 33R

R413

R414

402

A_HSYNC_DAC1_R

51R

A_VSYNC_DAC1_R

51R

DDCDATA_DAC1_R

DDCCLK_DAC1_R

A_B_DVI-I (12)

BAT54SLT1/X

D55

3

DDCDATA_DAC1_R
DDCCLK_DAC1_R
A_HSYNC_DAC1_R

A_VSYNC_DAC1_R

BAT54SLT1/X

2

1

BAT54SLT1/X

2

D56

3

1

DDCDATA_DVI-I_R (12)

DDCCLK_DVI-I_R (12)

A_HSYNC_DVI-I_R (12)

A_VSYNC_DVI-I_R (12)

2

D57

3

1

C407
5pF/X

L60
82nH/X

+5V +5V+3.3V_BUS +3.3V_BUS +3.3V_BUS +5V+5V

BAT54SLT1/X

BAT54SLT1/X

2

D51

3

1

C409

C408

5pF/X

5pF/X

L62

L61

82nH/X

82nH/X

2

D52

3

1

2

D54

D53

3

3

1

BAT54SLT1/X

BAT54SLT1/X

Place close to CONNECTOR

2

1

DB15 pin

11
12
4
15

9

Hardware
Support No Yes Yes No Yes

Based on VESA Display Data Channel (DDC) Standard Ver. 3 Dec. 15, 1997

C441
68pF

Close to
Connector

Standard VGA
Monitor ID bit 0

Monitor ID bit 1
Monitor ID bit 2
Monitor ID bit 3

N/C
Mechanical Key

+5V_VESA

DDC1 Host
Monitor ID bit 0

Data from display
Monitor ID bit 2
Open
+5V
50mA min
1A max

MJ2

1

R

2

G

3

B

11

MS0

DDC2_MONID0

12

MS1

DDC2_MONID1(SDA)

4

MS2

DDC2_MONID2

15

MS3

DDC2_MONID3(SCL)

9

NC

13

HS

14

VS

5

VSS

6

VSS#6

7

VSS#7

8

VSS#8

10

VSS#10

16

CASE

17

CASE#17

18

CASE#18

19

CASE#19

DB15F_slim_RA/X

6050003000 Old Slim-VGA connector
6052003000 New horizontally aligned Slim-VGA connector

DDC2AB Host

DDC2B or
DDC2B+ Host

Monitor ID bit 0

Monitor ID bit 0

SDA

SDA

Monitor ID bit 2

Monitor ID bit 2

SCL

SCL
+5V

+5V

50mA min

300mA min

1A max

1A max

DDC1/2 Display
Optional

SDA
Optional
SCL

Optional

A A

Title

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Custom

8

7

6

5

4

3

Date: Sheet

2

GIGABYTE

DAC REG Filter

GV-RX30S128D-HT

1

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PRIMARY DVI-I CONNECTOR

INSTALL TERMINATION RESISTORS CLOSE TO ASIC

R601 330R

D D

C C

TMDS_TX2N(2)
TMDS_TX2P(2)

TMDS_TX1N(2)
TMDS_TX1P(2)

TMDS_TX0N(2)
TMDS_TX0P(2)

TMDS_TXCP(2)
TMDS_TXCN(2)

DDCCLK_DVI-I_R(11)
DDCDATA_DVI-I_R(11)

HPD(2)

402

R602 330R

402

R603 330R

402

R604 330R

402

A_VSYNC_DVI-I_R(11)

A_R_DVI-I(11)
A_G_DVI-I(11)
A_B_DVI-I(11)

R606
20K

A_HSYNC_DVI-I_R(11)

1

LAYOUT NOTE: MAY REMOVE R605-R608 IF THERE'S NO SPACE!

+3.3V_BUS

R605
20K

402 402

Q25

D121

2.5V/X

DNI

CMPT3904
R609
100K/X

2 1

2 3

CMPT3904

1

Q26

2 3

R608 20K/X

402

R607 20K

402402

DDCCLK_DVI-I
DDCDATA_DVI-I

+5V_VESA

Pr
Y
Pb

C510
68pF/X

DNI

J2

25

CASE

1

TMDS Data2-

2

TMDS Data2+

3

TMDS Data2/4 Shield

4

TMDS Data4-

5

TMDS Data4+

6

DDC Clock

7

DDC Data

8

Analog VSYNC

9

TMDS Data1-

10

TMDS Data1+

11

TMDS Data1/3 Shield

12

TMDS Data3-

13

TMDS Data3+

14

+5V Power

15

GND (for +5V)

16

Hot Plug Detect

17

TMDS Data0-

18

TMDS Data0+

19

TMDS Data0/5 Shield

20

TMDS Data5-

21

TMDS Data5+

22

TMDS Clock Shield

23

TMDS Clock+

24

TMDS Clock-

C1

Analog Red

C2

Analog Green

C3

Analog Blue

C4

Analog HYNC

C5

Analog GND

C6

Analog GND#C6

26

CASE#26

27

CASE#27

28

CASE#28

29

CASE#29

30

CASE#30

DVICONNECTOR

B B

Req = 120.7R
Use 845R, 1206, 1/4W

A A

5

+12V_BUS

R911
845R/1206

R912
845R/1206

R913
845R/1206

R914
845R/1206

R915
845R/1206

REG19

TL431CDBVR

4

R916
845R/1206

R917
845R/1206

5 3

+5V_VESA

Multi-footprint

C901

R901

10uF_6.3V

1.0K

1%

4

NC

402

1

NC

R902

2

1.0K

1%

402

Normal +5V regulated operation

If Iload > 55mA, +5V will drop
If Vout is shorted

MC901

4.7uF/X

This circuit provide upto 55mA

Current across each Rx is 12V/845R = 14.2mA
Power dissipated by each Rx is 14.2mA x 12V = 171mW
Each Rx are rated 250mW (1/4W)
Derating 250mW by 70% is 175mW (1/4W)

3

Title

Size Document Number Rev
Custom

2

Date: Sheet

GIGABYTE

TMDS & DVI-I

GV-RX30S128D-HT

1

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6

5

4

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Place Resistors close to ASIC.

A_G/Y_DAC2(2)

A_R/C_DAC2(2)

C C

A_B/COMP_DAC2(2)

B B

A_Y_DAC2

A_C_DAC2

A_COMP_DAC2

R504

75.0R

402

R505

75.0R

402

R506

75.0R

402

L91

1.8uH
C501
82pF

402 402

L92

1.8uH
C503
82pF

L93

1.8uH
C505
82pF

C502
82pF

C504
82pF

402402

C506
82pF

402402

A_Y_DAC2_F
A_C_DAC2_F
A_COMP_DAC2_F

Place near connector
0R leaves footprint for Ferrite
Beads if req'd for EM I

R519 0R
R520 0R
R521 0R

402

A_Y_DAC2_DIN

402

A_C_DAC2_DIN

402

A_COMP_DAC2_DIN

C507
82pF/X

For RCA Connector : remove R377 to RCA Connector avoid short to GND ;
For SVedio Connector add it

+3.3V_BUS

R578
10K

402

R377 0R

PIN7

C508
82pF/X

C509
82pF/X

402402 402

SVHS/YPrPbb(2)

R515
0R

TV Out (SVHS)

PIN6

1

2

PIN7
PIN5

MJ6
Jack_Phono_RCA/X

3

6
3

4
7
5

1
2

8
9

10

402

J6

+12V
Y-OUT

C-OUT
Comp_out
SYNC

GND
GND#2

CASE
CASE#9
CASE#10

Connector_DIN_Miniature_Circular_7_Pin

The 7-pin MiniDIN footprint allows one of the two MiniDINs :

- 7-pin Svideo/Composite MiniDIN P/N 6071001500

- 4-pin Svideo MiniDIN P/N 6070001000

A A

Title

Size Document Number Rev
Custom

8

7

6

5

4

3

Date: Sheet

2

GIGABYTE

VO Filter & Connector

GV-RX30S128D-HT

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DVI/VGA SCREWS MISC. BOARD PARTS

ASSY1

SCREW

JACKSCREW

D D

C C

B B

ASSY2

SCREW

JACKSCREW

MT1
MT_Hole_0.136_in.

Bracket Screws

ASSY3

SCREW

PAN_HEAD

ASSY7

ANTISTATIC
BAG

6_X_11

ASSY8

BLANK
LABEL

9050005900;9050005900;9050005900;9050005900

ATX Brackets

ASSY10

NO TABS, DVI

80200321A0

ASSY11

TOP TAB (LP), DIN, DVI

8020033000

DNE

6052003000 New horizontally aligned Slim-VGA connector

ASSY13

TOP TAB (LP), DIN, VGA

6052003000 New horizontally aligned Slim-VGA connector

ASSY5

ATI LOGO
LABEL

ATI_LOGO_LABEL

BRACKET

BRACKET

BRACKET

ASSY-PCB

ATI LOGO
LABEL

DVI ATX

DVI+MiniDIN ATX

Slim-VGA ATX

Slim-VGA+MiniDIN ATX

LP Brackets

ASSY14

BRACKET

LP, NO TABS, DVI

8020032600

ASSY15

BRACKET

LP, TOP TAB, DIN, DVI

8020032700

ASSY16

BRACKET

LP, NO TABS, VGA

80200326A0
6052003000 New horizontally aligned Slim-VGA connector

ASSY17

BRACKET

LP, TOP TAB, DIN, VGA

80200327A0
6052003000 New horizontally aligned Slim-VGA connector

DVI LP

DVI+MiniDIN LP

Slim-VGA LP
No Top Tab

Slim-VGA+MiniDIN LP

+12V_BUS

H101

1
2

JU1

heatsink

7120005800

MH101

HEATSINK

7120002700

H100

HEATSINK

7120005100

Spring push-pin

MH100

HEATSINK

7120008000

ITW push-pin

A A

Title

Size Document Number Rev
Custom

5

4

3

2

Date: Sheet

GIGABYTE

Heatsink & Mechanicals

GV-RX30S128D-HT

1

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MEMORY CHANNEL A

D D

TSOP 16Mx16 Memory

MEMORY TERMINATIONS A

CLOCK

MEM A

C C

DAC1

PRIMARY CRT

LOGIC

STRAPS

DVI Connector

BIOS

B B

POWER

REGULATION

ROM

RV370

DAC2

TVOUT Filters

TMDS

TMDS Terminations

TVOUT
CONN

Slim-VGA DB15
CONN

AGP

A A

PCI-Express

Title

Size Document Number Rev
B

5

4

3

2

Date: Sheet

GIGABYTE

Block Diagram

GV-RX30S128D-HT

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Model Name: GV-RX30S128D-HT

3

2

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D D

C C

Component history

Date Change Item

Reason

Circuit or PCB layout history

Date

Change Item Reason

B B

A A

Title

Size Document Number Rev
C

5

4

3

2

Date: Sheet

GIGABYTE

History

GV-RX30S128D-HT

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