5
4
3
2
1
MEMORY CHANNEL A
D D
TSOP 16Mx16 Memory
MEMORY TERMINATIONS A
MEM A
CLOCK
MEM B
DAC1
Int. TMDS
C C
STRAPS
VID
VIP
POWER
REGULATION
BIOS
ROM
RV370
DAC2
PCI-E
LCDDATA19
MEMORY CHANNEL B
TSOP 16Mx16 Memory
MEMORY TERMINATIONS B
RageTheater 1
D
E
M
U
SEL
X
TVOUT Filters
Secondary
CRT LOGIC
PRIMARY CRT
LOGIC
INTEGRATED TMDS
LOGIC
VO or
VIVO
CONN
VGA
DB15
CONN
DVI-I CONN
and/or VGA Sl im
DB15 CONN
B B
PCI-Express
A A
Title
Size Document Number Rev
C
5
4
3
2
Date: Sheet
GIGABYTE
Block Diagram
GV-RX30128D
1
1.1
of
01 20Wednesday, October 20, 2004
8
7
6
5
4
3
2
1
TP29
TP31
TP33
TP35
TP37
TP39
TP41
TP43
TP45
TP47
TP49
TP51
TP53
TP55
TP57
TP59
PCI-EXPRESS EDGE CONNECTOR
+12V_BUS
+3.3V_BUS
DNI
PRESENCE
MPCIE1
B1
+12V#B1
B2
+12V#B2
B3
RSVD#B3
B4
GND#B4
B5
SMCLK
B6
SMDAT
B7
GND#B7
B8
402
JTAG_TRST#
PRESENT_NULL
PRESENT_NULL
PRESENT_NULL
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
+3.3V#B8
JTAG1
3.3Vaux
WAKE#
RSVD#B12
GND#B13
PETp0
PETn0
GND#B16
PRSNT2#B17
GND#B18
PETp1
PETn1
GND#B21
GND#B22
PETp2
PETn2
GND#B25
GND#B26
PETp3
PETn3
GND#B29
RSVD#B30
PRSNT2#B31
GND#B32
PETp4
PETn4
GND#B35
GND#B36
PETp5
PETn5
GND#B39
GND#B40
PETp6
PETn6
GND#B43
GND#B44
PETp7
PETn7
GND#B47
PRSNT2#B48
GND#B49
PETp8
PETn8
GND#B52
GND#B53
PETp9
PETn9
GND#B56
GND#B57
PETp10
PETn10
GND#B60
GND#B61
PETp11
PETn11
GND#B64
GND#B65
PETp12
PETn12
GND#B68
GND#B69
PETp13
PETn13
GND#B72
GND#B73
PETp14
PETn14
GND#B76
GND#B77
PETp15
PETn15
GND#B80
PRSNT2#B81
RSVD#B82
x16 PCIe
Mechanical Key
PRSNT1#A1
+12V#A2
+12V#A3
GND#A4
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V#A9
+3.3V#A10
PERST#
GND#A12
REFCLK+
REFCLK-
GND#A15
PERp0
PERn0
GND#A18
RSVD#A19
GND#A20
PERp1
PERn1
GND#A23
GND#A24
PERp2
PERn2
GND#A27
GND#A28
PERp3
PERn3
GND#A31
RSVD#A32
RSVD#A33
GND#A34
PERp4
PERn4
GND#A37
GND#A38
PERp5
PERn5
GND#A41
GND#A42
PERp6
PERn6
GND#A45
GND#A46
PERp7
PERn7
GND#A49
RSVD#A50
GND#A51
PERp8
PERn8
GND#A54
GND#A55
PERp9
PERn9
GND#A58
GND#A59
PERp10
PERn10
GND#A62
GND#A63
PERp11
PERn11
GND#A66
GND#A67
PERp12
PERn12
GND#A70
GND#A71
PERp13
PERn13
GND#A74
GND#A75
PERp14
PERn14
GND#A78
GND#A79
PERp15
PERn15
GND#A82
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
+12V_BUS
+3.3V_BUS
PERp0
PERn0
PERp1
PERn1
PERp2
PERn2
PERp3
PERn3
PERp4
PERn4
PERp5
PERn5
PERp6
PERn6
PERp7
PERn7
PERp8
PERn8
PERp9
PERn9
PERp10
PERn10
PERp11
PERn11
PERp12
PERn12
PERp13
PERn13
PERp14
PERn14
PERp15
PERn15
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
PRESENCE
R12440R
RP194A 0R/X
8 1
RP194B 0R/X
7 2
RP194C 0R/X
6 3
RP194D 0R/X
5 4
TP26
TP27
C607
C608
100nF
100nF
C617
C618
100nF
100nF
C626
100nF
C627
100nF
C631
100nF
C632
100nF
C611
100nF
C612
100nF
C622
100nF
C623
100nF
C621
100nF
C630
100nF
C605
100nF
C606
100nF
C615
100nF
C616
100nF
C624
C625
100nF
100nF
C633
100nF
C634
100nF
C609
100nF
C610
100nF
C619
100nF
C620
100nF
C628
100nF
C629
100nF
C603
C604
100nF
100nF
C613
100nF
C614
100nF
DNI
A_VSYNC_DAC1 (2,13)
DNI
CRT1DDCDATA (2,13)
DNI
SCL (2,17)
DNI
CRT1DDCCLK (2,13)
PCIE_REFCLKP (2)
PCIE_REFCLKN (2)
GFXTp0_PER p0 (2)
GFXTn0_PER n0 (2)
GFXTp1_PER p1 (2)
GFXTn1_PER n1 (2)
GFXTp2_PER p2 (2)
GFXTn2_PER n2 (2)
GFXTp3_PER p3 (2)
GFXTn3_PER n3 (2)
GFXTp4_PER p4 (2)
GFXTn4_PER n4 (2)
GFXTp5_PER p5 (2)
GFXTn5_PER n5 (2)
GFXTp6_PER p6 (2)
GFXTn6_PER n6 (2)
GFXTp7_PER p7 (2)
GFXTn7_PER n7 (2)
GFXTp8_PER p8 (2)
GFXTn8_PER n8 (2)
GFXTp9_PER p9 (2)
GFXTn9_PER n9 (2)
GFXTp10_PERp 10 (2)
GFXTn10_PERn 10 (2)
GFXTp11_PERp 11 (2)
GFXTn11_PERn 11 (2)
GFXTp12_PERp 12 (2)
GFXTn12_PERn 12 (2)
GFXTp13_PERp 13 (2)
GFXTn13_PERn 13 (2)
GFXTp14_PERp 14 (2)
GFXTn14_PERn 14 (2)
GFXTp15_PERp 15 (2)
GFXTn15_PERn 15 (2)
NOTE: THIS IS A DRAWING. THESE
GROUNDS MUST B E MANUALLY
CONNECTED TO THE GROUND PLANE
PERST#
C5
100uF_16V /X
DNI
+3.3V_BUS
C8
100uF_16 V
>=6.3V
PETp0_GFXR p0(2)
PETn0_GFXR n0(2)
PETp1_GFXR p1(2)
PETn1_GFXR n1(2)
PETp2_GFXR p2(2)
PETn2_GFXR n2(2)
PETp3_GFXR p3(2)
PETn3_GFXR n3(2)
PETp4_GFXR p4(2)
PETn4_GFXR n4(2)
PETp5_GFXR p5(2)
PETn5_GFXR n5(2)
PETp6_GFXR p6(2)
PETn6_GFXR n6(2)
PETp7_GFXR p7(2)
PETn7_GFXR n7(2)
PETp8_GFXR p8(2)
PETn8_GFXR n8(2)
PETp9_GFXR p9(2)
PETn9_GFXR n9(2)
PETp10_GFXR p10(2)
PETn10_GFXR n10(2)
PETp11_GFXR p11(2)
PETn11_GFXR n11(2)
PETp12_GFXR p12(2)
PETn12_GFXR n12(2)
PETp13_GFXR p13(2)
PETn13_GFXR n13(2)
PETp14_GFXR p14(2)
PETn14_GFXR n14(2)
PETp15_GFXR p15(2)
PETn15_GFXR n15(2)
A_HSYNC_DAC1(2,13)
C2
47uF_16V /X
>=6.3V
DNI
USE 47uF TANTALUM
CAPACITOR OR HIGHER
R1008 0R/X
TP28
TP30
TP32
TP34
TP36
TP38
TP40
TP42
TP44
TP46
TP48
TP50
TP52
TP54
TP56
TP58
+12V_BUS +3.3V_BUS
D D
C C
B B
GND_TPVSSGND_MPVSS
GND_PVSS GND_TXVSSR
+5V
C972
100nF
402
53
1
2
R64 0R/X
R3 100R
4
U2
TC7SZ08FU
402
GND_A2VSSN
GND_A2VSSQ
GND_AVSSQ GND_RSET
GND_R2SETGND_AVSSN
PERST#_buf (2,16)
R4
180R
402
SYMBOL LEGEND
DO NOT
DNI
INSTALL
ACTIVE
#
LOW
DIGITAL
A A
Title
Size Document Number Rev
C
8
7
6
5
4
3
Date: Sheet
2
GIGABYTE
PCI-EXPRESS EDGE CONNECTOR
GV-RX30128D
GROUND
ANALOG
GROUND
1.1
of
02 20Wednesday, October 20, 2004
1
5
4
3
2
1
BOUNDARY SCAN TEST ACCESS
A_HSYNC_DAC1
SCL
CRT1DDCDATA
CRT1DDCCLK
A_VSYNC_DAC1
TESTEN
DEBUG BUS ACCESS
VID/DVO16
VID/DVO17
VID/DVO18
VID/DVO19
VID/DVO20
VID/DVO21
VID/DVO22
VID/DVO23
GPIO10
GPIO11
GPIO12
GPIO13
R584
10K
402
41
R585
10K/X
ALT
402
SW1A
DIP_SWX2 /X
ThermINT (17)
TRST/
TP1
TDO
TP2
TDI
TP3
TMS
TP4
TCK
TP5
TP8
TESTOUT(0)
TESTOUT(1)
TESTOUT(2)
TESTOUT(3)
TP17
TESTOUT(4)
TESTOUT(5)
TP19
TESTOUT(6)
TP20
TESTOUT(7)
TP21
TESTOUT(8)
TESTOUT(9)
TESTOUT(10)
TESTOUT(11)
Title
Size Document Number Rev
C
Date: Sheet
GIGABYTE
RV370 main
GV-RX30128D
1
of
03 20Wednesday, October 20, 2004
1.1
Mem_Strap1 (12)
Mem_Strap0 (12)
+3.3V_BUS
402
GND_RSET
D+ (17)
D- (17)
GPIO[6..0]
GPIO[13..8]
SVHS/YPrPbb (14)
LCDDATA16 (12)
LCDDATA17 (12)
DEMUX_SEL (14)
VHAD0 (12,16)
VHAD1 (16)
VPHCTL (16)
CLK_VIPCLK (16)
+3.3V_BUS
C16
100nF
402
A_HSYNC_DAC1
3
U1A
AH30
PETp0_GFXR p0(1)
PETn0_GFXR n0(1)
PETp1_GFXR p1(1)
PETn1_GFXR n1(1)
PETp2_GFXR p2(1)
PETn2_GFXR n2(1)
PETp3_GFXR p3(1)
PETn3_GFXR n3(1)
D D
C C
SCL(1,17)
SDA(17)
C71 15PF
C72 15PF
CLK_RT(16)
+3.3V_BUS
R45
R46
4.7K
4.7K
402 402
402
Y1
27_MHZ
2 1
402
OPTION 1: Crystal Circuit
+3.3V_BUS
4
C18
2
100nF/X
402
OPTION 2: Oscillator Circuit
B B
A A
MY1
VCC
GND
27.000MHz /X
5015270 000
5
A_R/C_DAC2(14)
A_G/Y_DAC2(14)
A_B/COMP_DAC2(14)
A_HSYNC_DAC2(13)
A_VSYNC_DAC2(13)
R27
220R/X
3
OUT
1
E/D
+3.3V_BUS
PETp4_GFXR p4(1)
PETn4_GFXR n4(1)
PETp5_GFXR p5(1)
PETn5_GFXR n5(1)
PETp6_GFXR p6(1)
PETn6_GFXR n6(1)
PETp7_GFXR p7(1)
PETn7_GFXR n7(1)
PETp8_GFXR p8(1)
PETn8_GFXR n8(1)
PETp9_GFXR p9(1)
PETn9_GFXR n9(1)
PETp10_GFXR p10(1)
PETn10_GFXR n10(1)
PETp11_GFXR p11(1)
PETn11_GFXR n11(1)
PETp12_GFXR p12(1)
PETn12_GFXR n12(1)
PETp13_GFXR p13(1)
PETn13_GFXR n13(1)
PETp14_GFXR p14(1)
PETn14_GFXR n14(1)
PETp15_GFXR p15(1)
PETn15_GFXR n15(1)
GFXTp0_PER p0(1)
GFXTn0_PER n0(1)
GFXTp1_PER p1(1)
GFXTn1_PER n1(1)
GFXTp2_PER p2(1)
GFXTn2_PER n2(1)
GFXTp3_PER p3(1)
GFXTn3_PER n3(1)
GFXTp4_PER p4(1)
GFXTn4_PER n4(1)
GFXTp5_PER p5(1)
GFXTn5_PER n5(1)
GFXTp6_PER p6(1)
GFXTn6_PER n6(1)
GFXTp7_PER p7(1)
GFXTn7_PER n7(1)
GFXTp8_PER p8(1)
GFXTn8_PER n8(1)
GFXTp9_PER p9(1)
GFXTn9_PER n9(1)
GFXTp10_PER p10(1)
GFXTn10_PER n10(1)
GFXTp11_PER p11(1)
GFXTn11_PER n11(1)
GFXTp12_PER p12(1)
GFXTn12_PER n12(1)
GFXTp13_PER p13(1)
GFXTn13_PER n13(1)
GFXTp14_PER p14(1)
GFXTn14_PER n14(1)
GFXTp15_PER p15(1)
GFXTn15_PER n15(1)
PCIE_REFCLKP(1)
PCIE_REFCLKN(1)
+PCIE_VDDR
TP6
R32
1.0M
402
R28
130R/X
R1009 150R
R1010 100R
R1011 10K
R1089 10K
PERST#_buf(1,16)
R29
0R/X
402
GND_R2SET
R40 715R
R33
1K
402
+3.3V_BUS
R44
10K
402
PCIE_RX0P
AG30
PCIE_RX0N
AG29
PCIE_RX1P
AF29
PCIE_RX1N
AE29
PCIE_RX2P
AE30
PCIE_RX2N
AD30
PCIE_RX3P
AD29
PCIE_RX3N
AC29
PCIE_RX4P
AB29
PCIE_RX4N
AB30
PCIE_RX5P
AA30
PCIE_RX5N
AA29
PCIE_RX6P
Y29
PCIE_RX6N
W29
PCIE_RX7P
W30
PCIE_RX7N
V30
PCIE_RX8P
V29
PCIE_RX8N
U29
PCIE_RX9P
T29
PCIE_RX9N
T30
PCIE_RX10P
R30
PCIE_RX10N
R29
PCIE_RX11P
P29
PCIE_RX11N
N29
PCIE_RX12P
N30
PCIE_RX12N
M30
PCIE_RX13P
M29
PCIE_RX13N
L29
PCIE_RX14P
K29
PCIE_RX14N
K30
PCIE_RX15P
J30
PCIE_RX15N
AF26
PCIE_TX0P
AE26
PCIE_TX0N
AC25
PCIE_TX1P
AB25
PCIE_TX1N
AC27
PCIE_TX2P
AB27
PCIE_TX2N
AC26
PCIE_TX3P
AB26
PCIE_TX3N
Y25
PCIE_TX4P
W25
PCIE_TX4N
Y27
PCIE_TX5P
W27
PCIE_TX5N
Y26
PCIE_TX6P
W26
PCIE_TX6N
U25
PCIE_TX7P
T25
PCIE_TX7N
U27
PCIE_TX8P
T27
PCIE_TX8N
U26
PCIE_TX9P
T26
PCIE_TX9N
P25
PCIE_TX10P
N25
PCIE_TX10N
P27
PCIE_TX11P
N27
PCIE_TX11N
P26
PCIE_TX12P
N26
PCIE_TX12N
L25
PCIE_TX13P
K25
PCIE_TX13N
L27
PCIE_TX14P
K27
PCIE_TX14N
L26
PCIE_TX15P
K26
PCIE_TX15N
AF27
PCIE_REFCLKP
AE27
PCIE_REFCLKN
402
AC23
PCIE_CALRP
402
AB24
PCIE_CALRN
402
AB23
PCIE_CALI
402
AE25
PCIE_TEST
AD24
PWRGD_MASK
AD25
PWRGD
AH21
R2SET
402
AJ22
C_R_PR
AK21
Y_G
AK22
COMP_B_PB
AJ24
H2SYNC
AK24
V2SYNC
AG22
DDC3CLK
AG23
DDC3DATA
AJ23
NC#AJ23
AH24
NC#AH24
AH28
XTALIN
AJ29
XTALOUT
TESTEN
AH27
TESTEN
E8
TEST_YCLK
B6
TEST_MCLK
AF25
PLLTEST
AH25
STEREOSYNC
RV370LE A12B
IT IS RECOMMENDED TO ALLOW SERIES RESISTOR
FOOT PRINTS ON THE INDICATED AGP CONTROL SIGNALS
TO ADDRESS ANY LAYOUT NOISE RELATED
SIGNAL DAMPING REQUIREMENTS
4
PCI Express
DAC2CLK
Part 1 of 6
GPIO_PWRCNTL
GPIO_MEMSSIN
DVOVMODE
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVO / EXT TMDS / GPIOTMDSDAC1
DVPDATA_22
DVPDATA_23
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCNTL_3
DDC2DATA
DDC1DATA
GPIO__AUXWIN
THERM
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
VREFG
NC#AH15
NC#AH16
NC#AJ16
NC#AJ17
NC#AJ18
NC#AK18
NC#AJ20
NC#AJ21
NC#AK19
NC#AJ19
NC#AG16
NC#AG17
NC#AF16
NC#AF17
NC#AE18
NC#AE19
NC#AF19
NC#AF20
NC#AG19
NC#AG20
NC#AE12
NC#AG12
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TXCM
TXCP
DDC2CLK
HPD1
HSYNC
VSYNC
RSET
DDC1CLK
DPLUS
DMINUS
R
G
B
AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2
AE10
AH6
AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10
AJ10
AK10
AJ11
AH11
AG4
AH15
AH16
AJ16
AJ17
AJ18
AK18
AJ20
AJ21
AK19
AJ19
AG16
AG17
AF16
AF17
AE18
AE19
AF19
AF20
AG19
AG20
AE12
AG12
AK13
AJ13
AJ14
AJ15
AK15
AK16
AJ12
AK12
AE13
AE14
AF12
AK27
AJ27
AJ26
AJ25
AK25
AH26
AG25
AF24
AG24
AF11
AE11
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
DVOMODE
VID/DVO0
VID/DVO1
VID/DVO2
VID/DVO3
VID/DVO4
VID/DVO5
VID/DVO6
VID/DVO7
VID/DVO14
VID/DVO16
VID/DVO17
VID/DVO18
VID/DVO19
VID/DVO20
VID/DVO21
VID/DVO22
VID/DVO23
R43 10K
R39 499R
AUXWIN
402
GPIO[6..0] (12)
GPIO[13..8] (12)
CLK_VID/DVO (16)
R35
1K
402
Both resistors and
capacitor close to ASIC
R34
1K
402
TMDS_TX0N (15)
TMDS_TX0P (15)
TMDS_TX1N (15)
TMDS_TX1P (15)
TMDS_TX2N (15)
TMDS_TX2P (15)
TMDS_TXCN (15)
TMDS_TXCP (15)
DVIDDCCLK (13)
DVIDDCDATA (13)
HPD (15)
A_R_DAC1 (13)
A_G_DAC1 (13)
A_B_DAC1 (13)
A_HSYNC_DAC1 (1,13)
A_VSYNC_DAC1 (1,13)
TP7
CRT1DDCDATA (1,13)
CRT1DDCCLK (1,13)
DVOMODE
R22 10K/X
R23 10K
Pull-up to 1.8V
12bit-DVO mode for SDR
Ext. TMDS 1.8V DVO I/O
VID/DVO[7..0]
CMPT3904/X
VID/DVO[7..0] (16)
P1
PLUG/X
ALT
JU2
Header_3_Pin_1 X3/X
+3.3V_BUS
R65
4.7K
402
1
Q43
2 3
+VDDR4
402
402
+VDDR4
1
2
3
2
1
2
3
4
5
6
7
8
QSA[7..0]
QSA[7..0](8)
DQMA#[7..0](8)
MAA[14..0](8,10)
MDA[63..0](8)
A A
B B
C C
DQMA#[7..0]
MAA[14..0]
MDA[63..0]
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
U1B
H28
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
RV370LE A12B
Part 2 of 6
MEMORY
H29
J28
J29
J26
H25
H26
G26
G30
D29
D28
E28
E29
G29
G28
F28
G25
F26
E26
F25
E24
F23
E23
D22
B29
C29
C25
C27
B28
B25
C26
B26
F17
E17
D16
F16
E15
F14
E14
F13
C17
B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10
C9
B9
B10
E13
E12
E10
F12
F11
E9
F9
F8
MEMORY CHANNEL A
DQMB#[7..0](9)
MAB[14..0](9,11)
MDB[63..0](9)
MAA0
E22
MAA_0
MAA1
B22
MAA_1
MAA2
B23
MAA_2
MAA3
B24
MAA_3
MAA4
C23
MAA_4
MAA5
C22
MAA_5
MAA6
F22
MAA_6
MAA7
F21
MAA_7
MAA8
C21
MAA_8
MAA9
A24
MAA_9
MAA10
C24
MAA_10
MAA11
A25
MAA_11
MAA12
E21
MAA_12
MAA13
B20
MAA_13
MAA14
C19
MAA_14
DQMA#0
J25
DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7
MVREFD
MVREFS
QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
RASAb
CASAb
WEAb
CSAb_0
CSAb_1
CKEA
CLKA0
CLKA0b
CLKA1
CLKA1b
DIMA_0
DIMA_1
DQMA#1
F29
DQMA#2
E25
DQMA#3
A27
DQMA#4
F15
DQMA#5
C15
DQMA#6
C11
DQMA#7
E11
QSA0
J27
QSA1
F30
QSA2
F24
QSA3
B27
QSA4
E16
QSA5
B16
QSA6
B11
QSA7
F10
RASA#
A19
CASA#
E18
WEA#
E19
CSA#0
E20
F20
CKEA
B19
CLKA0
B21
CLKA#0
C20
CLKA1
C18
CLKA#1
A18
B7
B8
D30
B13
RASA# (8,10)
CASA# (8,10)
WEA# (8,10)
CSA#0 (8,10)
CKEA (8,10)
CLKA0 (8,10)
CLKA#0 (8,10)
CLKA1 (8,10)
CLKA#1 (8,10)
INTERFACE A
C154
100nF
402
PLACE C351/152 VERY CLOSE TO ASIC
R56/57/58/59 CLOSE TO ASIC AS WELL
QSB[7..0](9)
+MVDDQ
R58
100R
402
R59
100R
402
C153
100nF
402
QSB[7..0]
DQMB#[7..0]
MAB[14..0]
MDB[63..0]
+MVDDQ
R56
100R
402
R57
100R
402
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB57
MDB56
MDB59
MDB58
MDB60
MDB61
MDB62
MDB63
U1C
D7
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63
RV370LE A12B
Part 3 of 6
MEMORY
INTERFACE B
MEMVMODE_0
MEMVMODE_1
F7
E7
G6
G5
F5
E5
C4
B5
C5
A4
B4
C2
D3
D1
D2
G4
H6
H5
J6
K5
K4
L6
L5
G2
F3
H2
E2
F2
J3
F1
H3
U6
U5
U3
V6
W5
W4
Y6
Y5
U2
V2
V1
V3
W3
Y2
Y3
AA2
AA6
AA5
AB6
AB5
AD6
AD5
AE5
AE4
AB2
AB3
AC2
AC3
AD3
AE1
AE2
AE3
MEMORY CHANNEL B
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
DQMBb_5
DQMBb_6
DQMBb_7
QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7
RASBb
CASBb
WEBb
CSBb_0
CSBb_1
CKEB
CLKB0
CLKB0b
CLKB1
CLKB1b
DIMB_0
DIMB_1
ROMCSb
MEMTEST
MAB0
N5
MAB1
M1
MAB2
M3
MAB3
L3
MAB4
L2
MAB5
M2
MAB6
M5
MAB7
P6
MAB8
N3
MAB9
K2
MAB10
K3
MAB11
J2
MAB12
P5
MAB13
P3
MAB14
P2
DQMB#0
E6
DQMB#1
B2
DQMB#2
J5
DQMB#3
G3
DQMB#4
W6
DQMB#5
W2
DQMB#6
AC6
DQMB#7
AD2
QSB0
F6
QSB1
B3
QSB2
K6
QSB3
G1
QSB4
V5
QSB5
W1
QSB6
AC5
QSB7
AD1
RASB#
R2
CASB#
T5
WEB#
T6
CSB#0
R5
R6
CKEB
R3
CLKB0
N1
CLKB#0
N2
CLKB1
T2
CLKB#1
T3
E3
AA3
AF5
C6
C7
C8
R55
47R
402
RASB# (9,11)
CASB# (9,11)
WEB# (9,11)
CSB#0 (9,11)
CKEB (9,11)
CLKB0 (9,11)
CLKB#0 (9,11)
CLKB1 (9,11)
CLKB#1 (9,11)
ROMCS# (12)
R51 4.7K
R52 4.7K/X
DNI
R53
R54
4.7K
4.7K/X
DNI
402 402
LAYOUT NOTE: SOME OF THE RESISTORS R51-54 MAY BE
REMOVED IF SPACE IS AN ISSUE, ASK BEFORE REMOVING
+VDDC_CT
402
402
VDDR1 MEMVMODE_0 MEMVMODE_1
1.8V
2.5V
2.8V
+VDDC_CT GND
+VDDC_CT +VDDC_CT
+VDDC_CTGND
D D
Title
Size Document Number Rev
C
1
2
3
4
5
6
Date: Sheet
7
GIGABYTE
RV370 memory interface
GV-RX30128D
04 20Wednesday, October 20, 2004
8
1.1
of
5
+MVDDQ
D D
+MVDDQ
C38
10uf
+MVDDQ
C32
100nF
402 402 402
C C
B B
A A
100nF
100nF
+TPVDD
GND_TPVSS
+1.8V
B11
200R
+TXVDDR_PINS
ALT: 0R
+1.8V
GND_TXVSSR
B14
+A2VDDQ
0R
ALT: 0R
GND_A2VSSQ
AVDD/A2VDDQ (1st & 2nd
DAC Band Gap) - 200mA
+1.8V
B13
0R
+AVDD
ALT: 0R
GND_AVSSN
C35
C33
C31
100nF
402 402402
C50
10uf
OPT
C59
4.7uF
C63
4.7uF
C67
4.7uF
C74
100nF
C43
2.2uF
C60
100nF
C64
100nF
402
C68
100nF
402
C75
100nF
C58
2.2uF
C81
100nF
402402
C73
100nF
402
+1.8V
C94
100nF
B12
0R
ALT: 0R
C95
100nF
402402 402402
+VDDOI_PINS
C96
100nF
GND_A2VSSN
C66
4.7uF
+PVDD
GND_PVSS
C97
100nF
+A2VDD
C54
4.7uF
C65
100nF
402
C62
100nF
402
C53
100nF
402
4
U1D
T7
R4
R1
N8
N7
M4
L8
K23
K24
L23
J8
J7
J4
J1
H10
H13
H15
H17
T8
V4
V7
V8
AA1
AA4
AA7
AA8
A3
A9
A15
A21
A28
B1
B30
D26
D23
D20
D17
D14
D11
D8
D5
E27
F4
G7
G10
G13
G15
G19
G22
G27
H22
H19
AD4
N4
AE15
AE16
AE17
AF15
AH19
AH13 AH12
AF13
AF14
+MVDDQ
F18
N6
AE20
AF21
AF23
AH23
AE23
AE22
AK28 AJ28
A7 A6
Part 4 of 6
VDDR1#T7
VDDR1#R4
VDDR1#R1
VDDR1#N8
VDDR1#N7
VDDR1#M4
VDDR1#L8
VDDR1#K23
VDDR1#K24
VDDR1#L23
VDDR1#J8
VDDR1#J7
VDDR1#J4
VDDR1#J1
VDDR1#H10
VDDR1#H13
VDDR1#H15
VDDR1#H17
VDDR1#T8
VDDR1#V4
VDDR1#V7
VDDR1#V8
VDDR1#AA1
VDDR1#AA4
VDDR1#AA7
VDDR1#AA8
VDDR1#A3
VDDR1#A9
VDDR1#A15
VDDR1#A21
VDDR1#A28
VDDR1#B1
VDDR1#B30
VDDR1#D26
VDDR1#D23
VDDR1#D20
VDDR1#D17
VDDR1#D14
VDDR1#D11
VDDR1#D8
VDDR1#D5
VDDR1#E27
VDDR1#F4
VDDR1#G7
VDDR1#G10
VDDR1#G13
VDDR1#G15
VDDR1#G19
VDDR1#G22
VDDR1#G27
VDDR1#H22
VDDR1#H19
VDDR1#AD4
VDDR1#N4
NC#AE15
NC#AE16
NC#AE17
NC#AF15
NC#AH19
TPVDD TPVSS
TXVDDR#AF13
TXVDDR#AF14
VDDRH0
VDDRH1
A2VDD#AE20
A2VDD#AF21
A2VDDQ
AVDD
VDD1DI
I/O POWER
VDD2DI
PVDD PVSS
MPVDD MPVSS
RV370LE A12B
VDDC#AC13
VDDC#AC15
VDDC#AC17
VDDC#AD13
VDDC#AD15
VDD15#H11
VDD15#H20
VDD15#M23
VDD15#P8
VDD15#Y23
VDD15#Y8
VDD15#AC11
VDD15#AC20
VDDR3#AC8
VDDR3#AC19
VDDR3#AC21
VDDR3#AC22
VDDR3#AD7
VDDR3#AD19
VDDR3#AD21
VDDR4#AC9
VDDR4#AC10
VDDR4#AD9
VDDR4#AD10
VDDR4#AG7
PCIE_VDDR_12#AG26
PCIE_VDDR_12#AG27
PCIE_VDDR_12#AG28
PCIE_VDDR_12#AJ30
PCIE_VDDR_12#AK29
PCIE_PVDD_12#N23
PCIE_PVDD_12#N24
PCIE_PVDD_12#P23
PCIE_PVDD_18#T23
PCIE_PVDD_18#U23
PCIE_PVDD_18#V23
PCIE_PVDD_18#W23
TXVSSR#AH14
TXVSSR#AG13
TXVSSR#AG14
A2VSSN#AH20
A2VSSN#AG21
NC#D9
NC#D13
NC#D19
NC#D25
NC#E4
NC#T4
NC#AB4
NC#AF18
NC#AG15
NC#AG18
NC#AH17
NC#AH18
VSSRH0
VSSRH1
A2VSSQ
AVSSN
AVSSQ
VSS1DI
VSS2DI
AC13
AC15
AC17
AD13
AD15
H11
H20
M23
P8
Y23
Y8
AC11
AC20
AC8
AC19
AC21
AC22
AD7
AD19
AD21
AC9
AC10
AD9
AD10
AG7
D9
D13
D19
D25
E4
T4
AB4
AG26
AG27
AG28
AJ30
AK29
N23
N24
P23
T23
U23
V23
W23
AF18
AG15
AG18
AH17
AH18
AH14
AG13
AG14
F19
M6
AH20
AG21
AF22
AH22
AD22
AE24
AE21
+VDDC
+VDDC_CT
+3.3V_BUS
GND_TPVSS
GND_TXVSSR
GND_A2VSSN
GND_A2VSSQ
GND_AVSSN
GND_PVSS
GND_MPVSS
+VDDR4
C70
4.7uF
+PCIE_VDDR
+PCIE_PVDD_12
+PCIE_PVDD_18
GND_AVSSQ
+VDDC
C69
100nF
402
C20
100nF
3
C21
C22
+3.3V_BUS
B15
0R/8
ALT: 0R
C98
1.0uF
100nF
C23
100nF
C968
1.0uF
C970
1.0uF
100nF
402 402402
C99
1.0uF
TP9
C84
C82
C83
100nF
100nF
402 402 402 402 402 402 402 402402 402 402 402 402
+3.3V_BUS
C44
100nF
C37
C39
1.0uF
100nF
402 402
C41
C969
100nF
1.0uF
402 402
C971
C55
1.0uF
100nF
402 402
100nF
C46
100nF
C40
100nF
C42
100nF
C56
100nF
C85
100nF
C86
100nF
+VDDC_CT
C45
100nF
402 402 402 402402 402
C76
100nF
402 402
C78
100nF
402 402
C57
100nF
402 402
C77
100nF
C79
100nF
C61
100nF
C87
100nF
C47
100nF
+VDDC
+VDDC
C26
100nF
C88
100nF
C48
100nF
2
C24
10uf
C28
100nF
C90
100nF
C29
100nF
C91
100nF
C27
100nF
402 402 402 402402
C89
100nF
C49
100nF
C30
100nF
C92
100nF
+VDDC
U1F
P17
VDDC#P17
P18
VDDC#P18
P19
VDDC#P19
U12
VDDC#U12
U13
VDDC#U13
U14
VDDC#U14
U17
VDDC#U17
U18
VDDC#U18
U19
VDDC#U19
V19
VDDC#V19
V18
VDDC#V18
V17
VDDC#V17
V14
VDDC#V14
V13
VDDC#V13
V12
VDDC#V12
N18
C93
100nF
VDDC#N18
N17
VDDC#N17
N14
VDDC#N14
W17
VDDC#W17
W18
VDDC#W18
W12
VDDC#W12
W13
VDDC#W13
W14
VDDC#W14
N13
VDDC#N13
N19
VDDC#N19
M19
VDDC#M19
M18
VDDC#M18
M12
VDDC#M12
N12
VDDC#N12
M13
VDDC#M13
M14
VDDC#M14
P12
VDDC#P12
P13 P14
VDDC#P13 VDDC#P14
RV370LE A12B
U1E
A2
VSS#A2
A10
VSS#A10
A16
VSS#A16
A22
VSS#A22
A29
VSS#A29
C1
VSS#C1
C3
VSS#C3
C28
VSS#C28
C30
VSS#C30
D27
VSS#D27
D24
VSS#D24
D21
VSS#D21
D18
VSS#D18
D15
VSS#D15
D12
VSS#D12
D6
VSS#D6
D4
VSS#D4
D10
VSS#D10
F27
VSS#F27
G9
VSS#G9
G12
VSS#G12
G16
VSS#G16
G18
VSS#G18
G21
VSS#G21
G24
VSS#G24
H27
VSS#H27
H23
VSS#H23
H21
VSS#H21
H18
VSS#H18
H16
VSS#H16
H14
VSS#H14
H12
VSS#H12
H9
VSS#H9
H8
VSS#H8
H4
VSS#H4
J23
VSS#J23
J24
VSS#J24
AD12
VSS#AD12
AG5
VSS#AG5
AG9
VSS#AG9
AG11
VSS#AG11
R7
VSS#R7
P4
VSS#P4
M7
VSS#M7
M8
VSS#M8
L4
VSS#L4
K1
VSS#K1
K7
VSS#K7
K8
VSS#K8
R8
VSS#R8
T1
VSS#T1
W8
VSS#W8
W7
VSS#W7
U8
VSS#U8
U4
VSS#U4
Y4
VSS#Y4
RV370LE A12B
ADD ASIC DECOUPLING FOR ALL POWER AS REQUIRED
PLACED CLOSE TO THE POWER/GND PINS
WITH AS MANY AS POSSIBLE PLACED UNDER THE ASIC
Part 6 of 6
VSS#M16
VSS#N16
VSS#N15
VSS#P15
VSS#P16
VSS#R18
VSS#R17
VSS#R16
VSS#R15
VSS#R14
VSS#R13
VSS#R12
VSS#T13
VSS#T14
VSS#T15
VSS#W15
VSS#V16
VSS#V15
VSS#U15
VSS#U16
VSS#T19
VSS#T18
VSS#T17
VSS#T16
CENTER ARRAY
VDDCI#W16
VDDCI#M15
VDDCI#R19
VDDCI#T12
VDDC#W19
VDDC#M17
Part 5 of 6
CORE GND
PCIE_VSS#AA23
PCIE_VSS#AA24
PCIE_VSS#AA25
PCIE_VSS#AA26
PCIE_VSS#AA27
PCIE_VSS#AA28
PCIE_VSS#AB28
PCIE_VSS#AC28
PCIE_VSS#AD26
PCIE_VSS#AD27
PCIE_VSS#AD28
PCIE_VSS#AE28
PCIE_VSS#AF28
PCIE_VSS#AH29
1
M16
N16
N15
P15
P16
R18
R17
R16
R15
R14
R13
R12
T13
T14
T15
W15
V16
V15
U15
U16
T19
T18
T17
T16
W16
M15
R19
T12
W19
M17
VSS#AB8
VSS#AB7
VSS#AB1
VSS#AC4
VSS#AC12
VSS#AC14
VSS#AD16
VSS#AC16
VSS#AC18
VSS#AD18
VSS#AK2
VSS#AJ1
PCIE_VSS#K28
PCIE_VSS#L28
PCIE_VSS#M24
PCIE_VSS#M25
PCIE_VSS#M26
PCIE_VSS#M27
PCIE_VSS#M28
PCIE_VSS#N28
PCIE_VSS#P28
PCIE_VSS#R23
PCIE_VSS#R24
PCIE_VSS#R25
PCIE_VSS#R26
PCIE_VSS#R27
PCIE_VSS#R28
PCIE_VSS#T24
PCIE_VSS#T28
PCIE_VSS#U28
PCIE_VSS#V24
PCIE_VSS#V25
PCIE_VSS#V26
PCIE_VSS#V27
PCIE_VSS#V28
PCIE_VSS#W24
PCIE_VSS#W28
PCIE_VSS#Y28
AB8
AB7
AB1
AC4
AC12
AC14
AD16
AC16
AC18
AD18
AK2
AJ1
K28
L28
M24
M25
M26
M27
M28
N28
P28
R23
R24
R25
R26
R27
R28
T24
T28
U28
V24
V25
V26
V27
V28
W24
W28
Y28
AA23
AA24
AA25
AA26
AA27
AA28
AB28
AC28
AD26
AD27
AD28
AE28
AF28
AH29
+MPVDD
C52
C51
4.7uF
100nF
GND_MPVSS
5
402
4
3
2
Title
Size Document Number Rev
C
Date: Sheet
GIGABYTE
RV370 power
GV-RX30128D
1
1.1
of
05 20Wednesday, October 20, 2004
8
Regulator for VDDC (ASIC Core)
7
6
5
4
3
2
***
Indicate number of power via required for the connection
1
Vout = 1.2V ~ 1.3V
Part NOTES
Do not install Cc1, Rc1
ALT. 1: MAXI M REGULATO R
+5V +12V_BUS
D D
MR315
R315
0R
0R/X
C151
1.0uF
+VDDC_S
21
R314
RB501V-40
+VDDC_B
D1
C147
100nF
603
X7R
5%
510K/X
C148
470pF/X
402
C149
27pF/X
ALT. 2: INTERSIL REGULATOR
C C
+VDDC_S
C104
22nf
C312
10nF
0402
R358 51K
R359 3K
C111
33pF
R368
15K
U41
1
2
3
9
10
MR357 10K/X
R357 10K
2
3
4
5
6
7
HSD
ILIM
COMPFBDL
LX
PGND
BST
MAX1954EUB/X
+12V_BUS_F1
+3.3V_BUS
MU31
OCSET
SS
COMP
FB
EN
GND
ISL6522CB
GND
DH
IN
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
8
6
5
4
7
141
VCCRT
13
12
11
10
9
8
ISL6522CB : SOIC
+PW_VDDC_HGD
+PW_VDDC_LGD
+12V_BUS_F1
C143
0.22uF
+VDDC_B
VDDC_FB
+12V_BUS
R99
2.2R
C115
100nF
603
X7R
5%
Alt. 1: Separate MOSFETs
Q24
4 5
3
6
2
7
1
8
IRF7413A
+PW_VDDC_M
Q22
4 5
3
6
2
7
1
8
IRF7413A
+VDDC
+VDDC
C116
100nF
L21 2.2uH
R15
1R/X
C156
2.2nF/X
L6 0R/8
L7 0R/8
C117
10uF
+VDDC_S
C325
10nF/X
Cc1
R254
1.5K/X
Rc1
ALT: 0R
ALT: 0R
***
C301
470UF
***
+PCIE_VDDR
+PCIE_PVDD_12
High current path
***
C322
470uF_10V
R1
R353
1.00K
1%
0.8V Ref
R2
R356
2K
1%
***
DUAL FOOT P R IN T DUAL F O O TP R IN T
B17
60R
***
***
***
MC322
470uF/X
***
+12V_BUS
+VDDC
**
C321
470uF_10V
**
+VDDC
C323
22uF_16V
******
OPT OPT
**
MC321
470uF/X
**
**
C324
22uF_16V
MAX1954
Install Cc1, Rc1
ISL6522
Part Vout R1 R2
MAX1954
ISL6522
0.8V Ref
1.2V
1.3V
1.00K 1% 2.00K 1%
ATI P/N 3240100100 ATI P/N 3240200100
1.00K 1%
ATI P/N 3240100100
1.6K 1%
ATI P/N 3240162100
Regulator for MVDDC (Memory Core)
Vout = 2.5V ~ 3.3V
**
C184
470uF_10V /X
**
3
+12V_BUS
+MVDDC
**
MC184
470uF/X
**
Title
Size Document Number Rev
C
Date: Sheet
2
GIGABYTE
REG Switcher
GV-RX30128D
of
06 20Wednesday, October 20, 2004
1
1.1
4
High current path
***
C183
470uF_10V
R1
R263
15.8K/X
1%
0.8V Ref
R2
R266
6.19K/X
1%
***
DUAL FOOT P R IN T DUAL F O O TP R IN T
B16
60R/X
***
***
***
MC183
470uF/X
***
B B
ALT. 1: MAXI M REGULATO R
+5V +12V_BUS
MR317
R317
0R/X
0R/X
C168
1.0uF/X
+MVDDC_S
21
R316
D2
RB501V-40/ X
+MVDDC_B
C152
100nF/X
603
X7R
5%
A A
510K/X
C158
C159
470pF/X
27pF/X
402
ALT. 2: INTERSIL REGULATOR
+MVDDC_S
C121
22nf/X
R270 51K/X
R271 3K/X
C123
33pF/X
C724
10nF/X
0402
R272
15K/X
8
U42
1
2
3
9
10
MR269 10K/X
R269 10K/X
2
3
4
5
6
7
ISL6522CB : SOIC
HSD
ILIM
COMPFBDL
LX
PGND
BST
MAX1954EUB/X
MU42
OCSET
SS
COMP
FB
EN
GND
ISL6522CB/X
8
DH
6
5
IN
4
GND
7
+12V_BUS_F2
+3.3V_BUS
VCCRT
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
7
141
13
12
11
10
9
8
+PW_MVDDC_HGD
+PW_MVDDC_LGD
+12V_BUS_F2
C142
0.22uF/X
+MVDDC_B
MVDDC_FB
+12V_BUS
6
R98
2.2R/X
C114
100nF/X
603
X7R
5%
C320
10nF/X
+3.3V_BUS
R326
10K/X
402
R96
10K/X
402
ALT
2
4
71
8
Q23A
BSO4804/X
+PW_MVDDC_M
53
6
Q23B
BSO4804/X
8A continuous @ 25'C
6.4A continuous @ 70'C
32A pul se drain current @ 25'C
5
C182
100nF/X
L64 3.3uH/X
R329
1R/X
C178
2.2nF/X
C181
10uF/X
+MVDDC_S
C120
10nF/X
Cc1
R264
1.5K/X
Rc1
***
C313
470UF/X
***
5
4
3
2
1
Place caps very
+12V_BUS
close to power pin
C13
C12
100nF
+3.3V_BUS
R811
33R
REG9
D D
TL431CDBVR
0.8V
1.25V
1.5V
1.8V
1.84V
C C
1.5
1.55 2K
1.6V
1.7V
1.8175V
Voltage Req.
3.3V
2.65V 301R (402, 1%) (402, 1%)
2.61V 221R (402, 1%) (402, 1%)
B B
2.5V 0R
+MVDDQ +MVDDC
RP2A 0R
RP2B 0R
RP2C 0R
RP2D 0R
+MVDDQ +MVDDC
RP195A 0R
RP195B 0R
RP195C 0R
RP195D 0R
Alt. regulator for +PVDD
Vout = 1.8V
Iout = 30mA MAX
A A
+3.3V_BUS
R284
33R/X
REG40
AS432S/X
1
3 2
C800
10uF_6.3V
4
NC
1
NC
2
5 3
R1
150R
P/N 3160150000
100R
100R
54.9R
P/N 3240054900
49.9R 140R
P/N 3240049900
Rx1 for 1.25V Re f
432R
P/N 3240432000
(402, 1%)
P/N 3160475000
432R
P/N 3240432000
432R
P/N 3240432000
681R
P/N 3240681000
P/N 3160681000 402
Ry1 for 2.5V Ref Ry2 for 2.5V Ref
1.07K
301R (402, 1%)
P/N 3160301000
P/N 3160301000
P/N 3230000000
P/N 3150000000 402
81
72
63
54
81
72
63
54
+PVDD
R287
Rt1
681R/X
402
1%
4
1
R290
2
1.50K/X
Rt2
402 402
1%
NC
NC
5
5 3
GND_PVSS
2.5V_REF2
R812
100R
1%
R1
402
1.25V_REF2
R813
100R
1%
R2
402
402
402P/N 3160100000
603
603
MREG40
SC431LC5SK-1/X
R2Voltage Req.
71.5R
P/N 324075R500
100R
150R
140R
P/N 3240140000
402P/N 3160100000 402 P/N 3160100000
402P/N 3160150000
P/N 3240140000
Rx2 for 1.25V Re fVoltage Req.
2.15K
P/N 3240215100
(402, 1%)475R
P/N 3160200100
1.5K
P/N 3240150100
1.21K
P/N 3240121100
1.5K
P/N 3240015200
3.32K
P/N 3240332100P/N 3240107100
3.32K2.7V
P/N 3240332100
4.99K
P/N 3160499100
4.99K
P/N 3160499100P/N 3160221000
DNI
Alt regulator for +MPVDD
Vout = 1.8V
Iout = 10mA MAX
+3.3V_BUS
R285
75R/X
REG32
AS432S/X
1
3 2
+MPVDD
R288
681R/X
1%
R291
1.50K/X
1%
402
1.25V_REF2
1.25V_REF2
2.5V_REF2
2.5V_REF2
Rt1
Rt2
4
NC
1
NC
2
5 3
GND_MPVSS
R101 1K
402
R105 1K
402
R109 1K
402
R113 1K
402
MREG32
SC431LC5SK-1/X
4
3
2
R103
2.15K
402
Rx2
5
6
R107
1.50K
402
Rx2
10
9
R111
4.99K/X
402
Ry2
12
13
R115
10K
402
Ry2
100nF
603
603
X7R
X7R
5%
5%
411
U81A
+
1
-
LM324DR
R102 432R
402
Rx1
U81B
+
7
-
LM324DR
R106 681R
402
Rx1
U81C
+
G_MVDDC
8
-
LM324DR
R110 0R/4
402
Ry1
U81D
+
G_MVDDQ
14
-
LM324DR
R114 301R/X
402
Ry1
1.61V 432R
1.69V
1.718V
1.75V
+3.3V_BUS
Q31
1
CMPT3904
200mA, SOT-23
150mW MAX
2 3
CMPT3904: 40V 200mA
MMBT2222: 40V 600mA
+3.3V_BUS
Q32
1
CMPT3904
200mA, SOT-23
150mW MAX
2 3
Rt1
32404320001.52V 432R
3160432000 3160215100
3240432000
3240432000432R
562R
3240562000
3160604000604R
3160604000 604R1.8V
Alt. regulator for +TPVDD
Vout = 1.65V ~ 1.85V
Iout = 20mA MAX
+TPVDD+3.3V_BUS
R286
56R
R289
3 2
REG39
AS432S
1
604R
1%
R292
1.37K
1%
Rt1
402
4
NC
1
NC
2
Rt2
402
GND_TPVSS
+3.3V_BUS
Q33
4 5
3
6
2
7
1
8
IRF7201
Q34
4 5
3
6
2
7
1
8
IRF7201/X
Rt2
2.15K
3230015200
1.5K
1.5K 3160150100
3240121100
1.21K
32300152001.5K
1.5K 3160150100
32300152001.5K
1.5K 3160150100
31601371001.37K
MREG39
SC431LC5SK-1/X
5 3
5.8A continuous @ 70'C
58A pul se drain current @ 25'C
RDS(o n) MAX = 50mR@Vgs=4.5V,I d=3.7A
550mW MAX
5.8A continuous @ 70'C
58A pul se drain current @ 25'C
RDS(o n) MAX = 50mR@Vgs=4.5V,I d=3.7A
550mW MAX
3
+PCIE_PVDD_18
L4
0R/6
ALT
+VDDC_CT
1.5V
C302
10uF_6.3V
70mA MAX
ALT
+MPVDD
C303
10uF_6.3V
+MPVDD: 10mA MAX
Capacitor are on Switcher page
+3.3V_BUS
+MVDDC
MR156
R156
0R/X
0R/X
805 805
Alt regulator for +VDDC_CT
Vout = 1.5V
Iout = 70mA MAX
+3.3V_BUS
R297
1206 1/4W
27R/X
REG31
AS432S/X
1
3 2
+VDDR4+1.8V
Rails derived from +VDDR4
+AVDD: 10mA MAX
+A2VDDQ: 20mA MAX
+VDDOI_PINS: 20mA MAX
+TXVDDR_PINS : 20mA MAX
+MVDDQ
C315
10uF_6.3V/ X
+VDDC_CT
R293
Rt1
432R/X
402
1%
4
1
R294
2
2.15K/X
Rt2
402
1%
L8
1.8uH/X
+MVDDC
***
C305
470uF_10V /X
***
DUAL FOOT P R IN T
NC
NC
5 3
2.5V ~ 2.6V
2.5A MAX
MC305
470uF/X
MREG31
SC431LC5SK-1/X
+PVDD +TPVDD
L10
0R/6
ALT: 0R ALT: 0RALT: 0RALT: 0R
+PVDD: 25mA MAX
2.5V ~ 2.6V
1A MAX
2
L11
1.8uH/X
+TPVDD: 50mA MAX
Rt1
Rt2
Alt. regulator for +MVDDC
Vout = 2.5V ~ 2.6V
Iout = 500mA MAX
Voltage Req.
3.34V
[-0.04V/+0.04V]
3.45V 2.43K4.32K
[-0.04V/+0.04V]
[-0.03V/+0.03V]
G_MVDDC
Alt regulator for +MVDDQ
Vout = 2.5V ~ 2.6V
Iout = 200mA MAX
Voltage Req.
1.8V
[-0.09V/+0.18V]
2.5V
2.6V
G_MVDDQ
Regulator for +VTT (Termination)
Vout = 1.25V ~ 1.3V with +2.5V +MVDDQ
Iout = 1000mA MAX
+MVDDQ = +2.5V
R273
1.0K/X
1%
402
R275
1.02K/X
1%
REG21
1 5
IN VOUT
4 2
REFEN GND
RT9173ACL5/ X
C137
100nF/X
402
Rm1
4.32K
1K2.5V 3240100100 1K 3240100100
C138
100nF/X
603
X7R
5%
REG33
AS432S/X
1
3 2
Rq1
681R
3240681000
1K
3240100100
4.75K
3240475100 4.32K 3240432100
C136
100nF/X
603
X7R
5%
REG34
AS432S/X
1
3 2
Rt1 Rt2
1K 1K1.25V
3240100100 3240100100
32401001001.0K 1.02K 32401021001.3V
3160100100 402
3
6
TAB
VCNTL
Title
REG (Memory, VDDC_CT)
Size Document Number Rev
C
Date: Sheet
Rm2
2.55K
+12V_BUS
R949
750R/X
/.25W
MREG33
SC431LC5SK-1/X
4
NC
1
NC
2
5 3
Rq2
1.5K
1K
+12V_BUS
R277
750R/X
/.25W
MREG34
SC431LC5SK-1/ X
4
NC
1
NC
2
5 3
603
C133
R274
10uf/X
1K/X
402
GIGABYTE
GV-RX30128D
1
+MVDDC
3230015200
3240100100
+MVDDQ
R279
1.0K/X
1%
402
R283
1.0K/X
1%
402
+VTT+MVDDQ +3.3V_BUS
***
C134
470uF_10V /X
***
DUAL FOOT P R IN T
07 20Wednesday, October 20, 2004
R958
1.0K/X
1%
402
R960
1.0K/X
1%
402
of
Rq1
Rq2
Rm1
Rm2
MC134
470uF/X
1.1
8
7
6
5
4
3
2
1
D D
2.5V
120mA
+MVDDC
+A2VDD
L5
1.8uH
ALT: 0R
C C
+PCIE_VDDR: 1.2V 13 00mA MAX+PCIE_PVDD_12: 1.2V 25 0mA MAX
+PCIE_PVDD_12
RP1A 0R
81
RP1B 0R
72
RP1C 0R
C310
33uF/X
ALT ALT
63
RP1D 0R
54
+PCIE_VDDR
C309
10uF_6.3V
C160
100uF_16V /X
C161
22uF/X
C162
22uF/X
Multi footprint
B B
Alt. regulator for +A2VDD
Vout = 2.5V
Iout = 120mA MAX
+A2VDD+3.3V_BUS
REG35
1
VIN
3
SHDN
C139
100nF/X
402
+A2VDD and GND_A2VSSN routed with at least 1 5 m i l
trace and not longer than 1.5 inch.
Alt. regulator for PCIE_PVDD_18
Vout = 1.85V
Iout = 500mA MAX
+3.3V_BUS
MREG36
LT1117CST
3 2
IN OUT
CASE
ADJ
1
R295
49.9R
402
1%
Need at least a 10uF Tant.
output cap for stability
Min. Load Current: 10mA
Regulator for +5V
Vout = 5V
Iout = 20mA MAX
+12V_BUS
R1043
REG29
220R
R1042
220R/X
OPT.
NC
NC
5 3
1206
1/4W
TL431CDBVR
BYPASS
GND
2.5V/X
2
GND_A2VSSN
4
R1
4
1
2
R2
5
VOUT
4
+PCIE_PVDD_18
R296
110R
1%
R1040
1.0K
1%
402
R1041
1.0K
1%
402
+5V
C308
10uF_6.3V
C917
10uF_6.3V
C311
100uF_16V /X
4
+3.3V_BUS
C166
1.0uF/X
REG37
MAX1935ETA/X
2
IN2
4
SHDN
3
POK
OUT7
TH_GND9
TH_GND10
TH_GND11
81
OUTIN
7
6
SET
5
GND
9
10
11
R154
6.81K/X
402
R1
R155
5.49K/X
402
R2
3
Part Vout R1 R2
C167
10uf
1.2V
MAX1935
0.8V Ref
1.79V
Title
Size Document Number Rev
C
Date: Sheet
2
402 402
1.00K 1% 2.00K 1%
ATI P/N 3160100100 ATI P/N 3160200100
6.81K 1%
ATI P/N 3160681100
402
5.49K 1%
ATI P/N 3160549100
GIGABYTE
REG (PCI-E, Opt. VDDC)
GV-RX30128D
of
08 20Wednesday, October 20, 2004
1
1.1
+3.3V_BUS
+1.8V
MREG37
R141
1 5
IN VOUT
These resistor values
must be recalculated
A A
8
2.15K/X
4 2
R142
1.24K/X
C157
1.0uF/X
REFEN GND
RT9173ACL5/X
+PCIE_VDDR
3
6
TAB
VCNTL
7
R143
1K/X
402
+3.3V_BUS
C163
1.0uF/X
REG38
MAX1935ETA/X
2
IN2
4
SHDN
3
POK
6
OUT7
TH_GND9
TH_GND10
TH_GND11
81
OUTIN
7
6
SET
5
GND
9
10
11
+PCIE_PVDD_12 +PCIE_PVDD_18
R151
1.0K/X
402
C165
R1
10uf
R152
2K/X
402
R2
5
5
C751
100nF/X
402
C752
100nF/X
402
D D
C C
B B
M_RASA#(3,10)
M_CKEA(3,10)
A A
5
M_CASA#(3,10)
M_WEA#(3,10)
M_CSA#0(3,10)
M_CLKA0(3,10)
M_CLKA#0(3,10)
M_CLKA1(3,10)
M_CLKA#1(3,10)
M_RASA#
M_CKEA
M_CASA#
M_WEA#
M_CSA#0
M_CLKA0
M_CLKA#0
M_CLKA1
M_CLKA#1
C753
100nF/X
402
C754
100nF/X
402
C755
100nF/X
402
C756
100nF/X
402
C757
100nF/X
402
C758
100nF/X
402
C759
100nF/X
402
C760
100nF/X
402
C761
100nF/X
402
C762
100nF/X
402
C763
100nF/X
402
CLKA0 (3,10)
CLKA#0 (3,10)
CLKA1 (3,10)
CLKA#1 (3,10)
+VTT+MVDDQ
RP101D 56R/X
RP101C 56R/X
RP101B 56R/X
C764
RP101A 56R/X
100nF/X
RP102D 56R/X
402
RP102C 56R/X
RP102B 56R/X
RP102A 56R/X
RP104C 56R/X
RP103D 56R/X
RP103C 56R/X
C765
RP103A 56R/X
RP103B 56R/X
100nF/X
402
RP104B 56R/X
RP104A 56R/X
RP104D 56R/X
RP105D 56R/X
RP105C 56R/X
RP105B 56R/X
RP105A 56R/X
C766
100nF/X
RP106D 56R/X
402
RP106C 56R/X
RP106B 56R/X
RP106A 56R/X
RP107B 56R/X
RP107A 56R/X
RP108C 56R/X
RP107D 56R/X
C767
100nF/X
RP107C 56R/X
402
RP108D 56R/X
RP108A 56R/X
RP108B 56R/X
RP111B 56R/X
RP111C 56R/X
RP111D 56R/X
RP111A 56R/X
C768
100nF/X
RP112A 56R/X
402
RP112B 56R/X
RP112C 56R/X
RP112D 56R/X
RP109B 56R/X
RP109A 56R/X
RP109C 56R/X
RP110A 56R/X
C769
100nF/X
RP110D 56R/X
402
RP110C 56R/X
RP110B 56R/X
RP109D 56R/X
RP113A 56R/X
RP113C 56R/X
RP113B 56R/X
RP113D 56R/X
C770
RP114D 56R/X
100nF/X
402
RP114B 56R/X
RP114A 56R/X
RP114C 56R/X
RP115A 56R/X
RP115C 56R/X
RP116A 56R/X
C771
RP115B 56R/X
100nF/X
RP115D 56R/X
402
RP116C 56R/X
RP116B 56R/X
RP116D 56R/X
R751 56R/X
R752 56R/X
R753 56R/X
R754 56R/X
R756
R755 56R/X
R757 56R/X
R758
R767 56R/X
R768 56R/X
R769 56R/X
C772
100nF/X
R770 56R/X
402
R772 56R/X
R771 56R/X
R773 56R/X
R774 56R/X
C773
100nF/X
402
RP133C 56R/X
RP133D 56R/X
RP133A 56R/X
RP133B 56R/X
RP134D 56R/X
RP134C 56R/X
RP134B 56R/X
RP134A 56R/X
RP135A 56R/X
RP135C 56R/X
C774
100nF/X
RP135B 56R/X
402
RP135D 56R/X
RP136D 56R/X
RP136B 56R/X
RP136C 56R/X
RP141A 56R/X
C775
RP141D 56R/X
100nF/X
RP141C 56R/X
402
RP141B 56R/X
RP136A 56R/X
C776
100nF/X
402
C777
10uF_16V /X
4
MDA[63..0]
MDA[63..0](3)
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20 MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
81
MDA37
72
MDA38
63
MDA39
54
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
54
MDA53
72
MDA54
81
MDA55
63
MDA56
81
MDA57
63
MDA58
81
MDA59
72
MDA60
54
MDA61
63
MDA62
72
MDA63
54
QSA[7..0]
QSA[7..0](3) M_QSA[7..0] (10)
QSA0
QSA1
QSA2
QSA3
QSA4
56R/X
QSA5
QSA6
QSA7
56R/X
DNI
M_MAA[14..0](3,10)
DQMA#[7..0]
DQMA#[7..0](3)
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
M_MAA[14..0]
M_MAA0
63
M_MAA1
54
M_MAA2
81
M_MAA3
72
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
81
M_MAA9
63
M_MAA10
72
M_MAA11
54
M_MAA12
54
M_MAA13
72
63
M_RASA#
81
M_CASA#
54
M_WEA#
63
M_CSA#0
72
M_CKEA
81
4
5 4
6 3
7 2
8 1
5 4
6 3
7 2
8 1
6 3
5 4
6 3
8 1
7 2
7 2
8 1
5 4
5 4
6 3
7 2
8 1
5 4
6 3
7 2
8 1
7 2
8 1
6 3
5 4
6 3
5 4
8 1
7 2
7 2
6 3
5 4
8 1
7 2
8 1
6 3
8 1
5 4
6 3
7 2
5 4
8 1
6 3
7 2
5 4
5 4
6 3
7 2
8 1
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
DQMA#0
DQMA#1
DQMA#2
DQMA#4
DQMA#5
DQMA#6
DQMA#7
M_MAA0 MAA0
M_MAA2 MAA2
M_MAA8 MAA8
M_MAA13 MAA13
R893
10K/X
3
RP117D 56R/8P4R
5 4
RP117C 56R/8P4R
6 3
RP117B 56R/8P4R
7 2
RP117A 56R/8P4R
8 1
RP118D 56R/8P4R
5 4
RP118C 56R/8P4R
6 3
RP118B 56R/8P4R
7 2
RP118A 56R/8P4R
8 1
RP119B 56R/8P4R
72
RP120D 56R/8P4R
5 4
RP120C 56R/8P4R
6 3
RP120A 56R/8P4R
8 1
RP120B 56R/8P4R
7 2
RP119C 56R/8P4R
63
RP119D 56R/8P4R
54
RP119A 56R/8P4R
81
RP121D 56R/8P4R
5 4
RP121C 56R/8P4R
6 3
RP121B 56R/8P4R
7 2
RP121A 56R/8P4R
8 1
RP122D 56R/8P4R
5 4
RP122C 56R/8P4R
6 3
RP122B 56R/8P4R
7 2
RP122A 56R/8P4R
8 1
RP123B 56R/8P4R
7 2
RP123A 56R/8P4R
8 1
RP124B 56R/8P4R
72
RP123D 56R/8P4R
5 4
RP123C 56R/8P4R
6 3
RP124A 56R/8P4R
81
RP124D 56R/8P4R
54
RP124C 56R/8P4R
63
RP127B 56R/8P4R
7 2
RP127C 56R/8P4R
6 3
RP127D 56R/8P4R
5 4
RP127A 56R/8P4R
8 1
RP128A 56R/8P4R
81
RP128B 56R/8P4R
72
RP128C 56R/8P4R
63
RP128D 56R/8P4R
54
RP125C 56R/8P4R
63
RP125D 56R/8P4R
54
RP125B 56R/8P4R
72
RP126D 56R/8P4R
54
RP126A 56R/8P4R
81
RP126B 56R/8P4R
72
RP126C 56R/8P4R
63
RP125A 56R/8P4R
81
RP129A 56R/8P4R
8 1
RP129D 56R/8P4R
5 4
RP129B 56R/8P4R
7 2
RP129C 56R/8P4R
6 3
RP130A 56R/8P4R
8 1
RP130C 56R/8P4R
6 3
RP130D 56R/8P4R
5 4
RP130B 56R/8P4R
7 2
RP131A 56R/8P4R
81
RP131C 56R/8P4R
63
RP132D 56R/8P4R
5 4
RP131B 56R/8P4R
72
RP131D 56R/8P4R
54
RP132B 56R/8P4R
7 2
RP132C 56R/8P4R
6 3
RP132A 56R/8P4R
8 1
R759 0R
R760 0R
R761 0R
R762 0R
R763 0R
R764 0R
R765 0R
R766 0R
R775 56R/4
R776 56R/4
R777 56R/4
R778 56R/4
R780 56R/4
R779 56R/4
R781 56R/4
R782 56R/4
3
M_MDA0
M_MDA1
M_MDA2
M_MDA3
M_MDA4
M_MDA5
M_MDA6
M_MDA7
M_MDA8
M_MDA9
M_MDA10
M_MDA11
M_MDA12
M_MDA13
M_MDA14
M_MDA15
M_MDA16
M_MDA17
M_MDA18
M_MDA19
M_MDA20
M_MDA21
M_MDA22
M_MDA23
M_MDA24
M_MDA25
M_MDA26
M_MDA27
M_MDA28
M_MDA29
M_MDA30
M_MDA31
M_MDA32
M_MDA33
M_MDA34
M_MDA35
M_MDA36
M_MDA37
M_MDA38
M_MDA39
M_MDA40
M_MDA41
M_MDA42
M_MDA43
M_MDA44
M_MDA45
M_MDA46
M_MDA47
M_MDA48
M_MDA49
M_MDA50
M_MDA51
M_MDA52
M_MDA53
M_MDA54
M_MDA55
M_MDA56
M_MDA57
M_MDA58
M_MDA59
M_MDA60
M_MDA61
M_MDA62
M_MDA63
M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7
M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7
MAA1M_MAA1
MAA3M_MAA3
MAA4M_MAA4
MAA5M_MAA5
MAA6M_MAA6
MAA7M_MAA7
MAA9M_MAA9
MAA10M_MAA10
MAA11M_MAA11
MAA12M_MAA12
MAA14M_MAA14M_MAA14
RASA# (3,10)
CASA# (3,10)
WEA# (3,10)
CSA#0 (3,10)
CKEA (3,10)
M_MDA[63..0]
SERIES Resistors
For Bi-Directional signals,
Series resistors should be
placed close to the memory
For Uni-Directional signals,
Series resistors should be
placed close to the ASIC
M_QSA[7..0]
M_DQMA#[7..0]
M_MDA[63..0] (10)
MAA[14..0] (3,10)
M_DQMA#[7..0] (10)
2
M_CLKA0
M_CLKA#0
M_CLKA1
M_CLKA#1
Title
Size Document Number Rev
C
2
Date: Sheet
1
R797
56.2R
C778
10nF
R798
56.2R
R799
56.2R
C779
10nF
R800
56.2R
GIGABYTE
VTT Termination CH A
GV-RX30128D
1
1.1
of
09 20Wednesday, October 20, 2004
5
C851
100nF/X
402
C852
100nF/X
402
D D
C C
B B
M_RASB#(3,11)
M_CKEB(3,11)
A A
5
M_CASB#(3,11)
M_WEB#(3,11)
M_CSB#0(3,11)
M_CLKB0(3,11)
M_CLKB#0(3,11)
M_CLKB1(3,11)
M_CLKB#1(3,11)
M_RASB#
M_CKEB
M_CASB#
M_WEB#
M_CSB#0
M_CLKB0
M_CLKB#0
M_CLKB1
M_CLKB#1
C853
100nF/X
402
C854
100nF/X
402
C855
100nF/X
402
C856
100nF/X
402
C857
100nF/X
402
C858
100nF/X
402
C859
100nF/X
402
C860
100nF/X
402
C861
100nF/X
402
C862
100nF/X
402
C863
100nF/X
402
CLKB0 (3,11)
CLKB#0 (3,11)
CLKB1 (3,11)
CLKB#1 (3,11)
4
+VTT+MVDDQ
RP151A 56R/X
RP151B 56R/X
RP151C 56R/X
C864
RP151D 56R/X
100nF/X
RP152D 56R/X
RP152C 56R/X
RP152B 56R/X
RP152A 56R/X
RP153A 56R/X
8 1
RP153B 56R/X
7 2
RP153C 56R/X
6 3
RP153D 56R/X
C865
100nF/X
C866
100nF/X
C867
100nF/X
C868
100nF/X
C869
100nF/X
C870
100nF/X
C871
100nF/X
C872
100nF/X
C873
100nF/X
C874
100nF/X
C875
100nF/X
C876
100nF/X
5 4
RP154A 56R/X
8 1
RP154B 56R/X
7 2
RP154C 56R/X
6 3
RP154D 56R/X
5 4
RP155A 56R/X
RP155B 56R/X
RP155C 56R/X
RP155D 56R/X
RP156A 56R/X
RP156B 56R/X
RP156C 56R/X
RP156D 56R/X
RP158A 56R/X
8 1
RP157B 56R/X
7 2
RP158C 56R/X
6 3
RP157A 56R/X
8 1
RP157C 56R/X
6 3
RP158D 56R/X
5 4
RP157D 56R/X
5 4
RP158B 56R/X
7 2
RP159D 56R/X
5 4
RP159C 56R/X
6 3
RP159B 56R/X
7 2
RP159A 56R/X
8 1
RP160D 56R/X
5 4
RP160C 56R/X
6 3
RP160B 56R/X
7 2
RP160A 56R/X
8 1
RP161D 56R/X
RP161C 56R/X
RP161B 56R/X
RP161A 56R/X
RP162D 56R/X
RP162C 56R/X
RP162B 56R/X
RP162A 56R/X
RP163D 56R/X
5 4
RP163C 56R/X
6 3
RP163B 56R/X
7 2
RP163A 56R/X
8 1
RP164A 56R/X
RP164B 56R/X
RP164C 56R/X
RP164D 56R/X
RP165D 56R/X
RP165C 56R/X
RP165B 56R/X
RP165A 56R/X
RP166D 56R/X
RP166C 56R/X
RP166B 56R/X
RP166A 56R/X
R851 56R/X <3RD PART FIELD>
R852 56R/X <3RD PART FIELD>
R853 56R/X <3RD PART FIELD>
R854 56R/X <3RD PART FIELD>
R855
R856 56R/X <3RD PART FIELD>
R857 56R/X <3RD PART FIELD>
R858
R867 56R/X
R868 56R/X
R869 56R/X
R870 56R/X
R871 56R/X
R872 56R/X
R873 56R/X
R874 56R/X
RP183D 56R/X
RP183C 56R/X
RP183A 56R/X
RP183B 56R/X
RP184B 56R/X
RP184A 56R/X
RP184C 56R/X
RP184D 56R/X
RP185D 56R/X
RP185C 56R/X
RP185B 56R/X
RP185A 56R/X
RP186B 56R/X
RP186A 56R/X
RP186C 56R/X
RP191A 56R/X
RP191B 56R/X
RP191C 56R/X
RP191D 56R/X
RP186D 56R/X
C877
10uF_16V /X
4
MDB[63..0]
MDB[63..0](3)
MDB0
81
MDB1
72
MDB2
63
54
MDB4
54
MDB5
63
MDB6
72
MDB7
81
MDB8
MDB9
MDB10
MDB11
MDB12 MDB12
MDB13
MDB14
MDB15
MDB16
81
MDB17
72
MDB18
63
MDB19
54
MDB20
81
MDB21
72
MDB22
63
MDB23
54
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36 MDB36
MDB37
MDB38
MDB39
MDB40
54
MDB41
63
MDB42
72
MDB43
81
MDB44
54
MDB45
63
MDB46
72
MDB47
81
MDB48
MDB49
MDB51
MDB52
81
MDB53
72
MDB54
63
MDB55
54
MDB56
54
MDB57
63
MDB58
72
MDB59
81
MDB60
54
MDB61
63
MDB62
72
MDB63
81
QSB[7..0](3)
DNI
QSB0
QSB1
QSB2
QSB3
QSB4
56R/X
QSB5
QSB6
QSB7
56R/X
DQMB#[7..0](3)
DQMB#0
DQMB#1
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
M_MAB[14..0](3,11)
M_MAB0
54
M_MAB1
63
M_MAB2
81
M_MAB3
72
M_MAB4
72
M_MAB5
81
M_MAB6
63
M_MAB7
54
M_MAB8
54
M_MAB9
63
M_MAB10
72
M_MAB11
81
M_MAB12
72
M_MAB13
81
M_MAB14
63
M_RASB#
81
M_CASB#
72
M_WEB#
63
M_CSB#0
54
M_CKEB
54
QSB[7..0]
<3RD PART FIELD>
<3RD PART FIELD>
DQMB#[7..0]
M_MAB[14..0]
3
MDB0
RP169D 56R/8P4R
MDB1
MDB2
MDB3MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
DQMB#0
DQMB#1
DQMB#2DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
M_MAB1 MAB1
M_MAB4 MAB4
M_MAB11 MAB11
M_MAB13 MAB13
M_MAB14 MAB14
R895
10K/X
5 4
RP169C 56R/8P4R
6 3
RP169B 56R/8P4R
7 2
RP169A 56R/8P4R
8 1
RP170A 56R/8P4R
8 1
RP170B 56R/8P4R
7 2
RP170C 56R/8P4R
6 3
RP170D 56R/8P4R
5 4
RP167A 56R/8P4R
8 1
RP167B 56R/8P4R
7 2
RP167C 56R/8P4R
6 3
RP167D 56R/8P4R
5 4
RP168A 56R/8P4R
8 1
RP168B 56R/8P4R
7 2
RP168C 56R/8P4R
6 3
RP168D 56R/8P4R
5 4
RP173A 56R/8P4R
81
RP173B 56R/8P4R
72
RP173C 56R/8P4R
63
RP173D 56R/8P4R
54
RP174D 56R/8P4R
5 4
RP174C 56R/8P4R
6 3
RP174B 56R/8P4R
7 2
RP174A 56R/8P4R
8 1
RP172A 56R/8P4R
8 1
RP171C 56R/8P4R
63
RP172C 56R/8P4R
6 3
RP171D 56R/8P4R
54
RP171B 56R/8P4R
72
RP172D 56R/8P4R
5 4
RP171A 56R/8P4R
81
RP172B 56R/8P4R
7 2
RP175D 56R/8P4R
5 4
RP175C 56R/8P4R
6 3
RP175B 56R/8P4R
7 2
RP175A 56R/8P4R
8 1
RP176D 56R/8P4R
5 4
RP176C 56R/8P4R
6 3
RP176B 56R/8P4R
7 2
RP176A 56R/8P4R
8 1
RP177A 56R/8P4R
8 1
RP177B 56R/8P4R
7 2
RP177C 56R/8P4R
6 3
RP177D 56R/8P4R
5 4
RP178D 56R/8P4R
54
RP178C 56R/8P4R
63
RP178B 56R/8P4R
72
RP178A 56R/8P4R
81
RP179D 56R/8P4R
5 4
RP179C 56R/8P4R
6 3
RP179B 56R/8P4R
7 2
RP179A 56R/8P4R
8 1
RP180D 56R/8P4R
5 4
RP180C 56R/8P4R
6 3
RP180B 56R/8P4R
7 2
RP180A 56R/8P4R
8 1
RP181D 56R/8P4R
54
RP181C 56R/8P4R
63
RP181B 56R/8P4R
72
RP181A 56R/8P4R
81
RP182A 56R/8P4R
8 1
RP182B 56R/8P4R
7 2
RP182C 56R/8P4R
6 3
RP182D 56R/8P4R
5 4
R860 0R
R859 0R
R862 0R
R861 0R
R863 0R
R864 0R
R865 0R
R866 0R
R875 56R/4
R876 56R/4
R877 56R/4
R878 56R/4
R879 56R/4
R880 56R/4
R881 56R/4
R882 56R/4
3
M_MDB0
M_MDB1
M_MDB2
M_MDB3
M_MDB4
M_MDB5
M_MDB6
M_MDB7
M_MDB8
M_MDB9
M_MDB10
M_MDB11
M_MDB12
M_MDB13
M_MDB14
M_MDB15
M_MDB16
M_MDB17
M_MDB18
M_MDB19
M_MDB20
M_MDB21
M_MDB22
M_MDB23
M_MDB24
M_MDB25
M_MDB26
M_MDB27
M_MDB28
M_MDB29
M_MDB30
M_MDB31
M_MDB32
M_MDB33
M_MDB34
M_MDB35
M_MDB36
M_MDB37
M_MDB38
M_MDB39
M_MDB40
M_MDB41
M_MDB42
M_MDB43
M_MDB44
M_MDB45
M_MDB46
M_MDB47
M_MDB48
M_MDB49
M_MDB50
M_MDB51
M_MDB52
M_MDB53
M_MDB54
M_MDB55
M_MDB56
M_MDB57
M_MDB58
M_MDB59
M_MDB60
M_MDB61
M_MDB62
M_MDB63
M_QSB0
M_QSB1
M_QSB2
M_QSB3
M_QSB4
M_QSB5
M_QSB6
M_QSB7
M_DQMB#0
M_DQMB#1
M_DQMB#2
M_DQMB#3
M_DQMB#4
M_DQMB#5
M_DQMB#6
M_DQMB#7
MAB0M_MAB0
MAB2M_MAB2
MAB3M_MAB3
MAB5M_MAB5
MAB6M_MAB6
MAB7M_MAB7
MAB8M_MAB8
MAB9M_MAB9
MAB10M_MAB10
MAB12M_MAB12
RASB# (3,11)
CASB# (3,11)
WEB# (3,11)
CSB#0 (3,11)
CKEB (3,11)
M_MDB[63..0]
M_QSB[7..0]
M_DQMB#[7..0]
M_MDB[63..0] (11)
M_QSB[7..0] (11)
MAB[14..0] (3,11)
M_DQMB#[7..0] (11)
2
M_CLKB0
M_CLKB#0
M_CLKB1
M_CLKB#1
Title
Size Document Number Rev
C
2
Date: Sheet
1
R897
56.2R
C878
10nF
R898
56.2R
R899
56.2R
C879
10nF
R900
56.2R
GIGABYTE
VTT Termination CH B
GV-RX30128D
1
1.1
of
10 20Wednesday, October 20, 2004
8
7
6
5
4
3
2
1
M_DQMA#[7..0](8)
D D
M_QSA[7..0](8)
C C
M_MAA[14..0](3,8)
B B
M_DQMA#[7..0]
M_QSA[7..0]
M_CLKA#0(3,8)
M_CLKA#1(3,8)
M_CLKA0(3,8)
M_CLKA1(3,8)
M_CKEA(3,8)
M_WEA#(3,8)
M_CASA#(3,8)
M_RASA#(3,8)
M_CSA#0(3,8)
M_MAA[14..0]
M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7
M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7
M_CLKA0#
M_CLKA1#
M_CLKA0
M_CLKA1
M_CKEA
M_WEA#
M_CASA#0
M_RASA#0
M_CSA#0
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_MAA14
M_MDA[63..0](8)
+MVDDQ
C206
402
U29
100nF
+VREF_U69 +VREF_U66
C287
100nF
402
C288
100nF
402
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CLKA0
M_CLKA#0
M_CKEA
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA2
M_QSA0
M_DQMA#2
M_DQMA#0
M_MAA12
M_MAA13
+MVDDQ
+VREF_U67
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CLKA0
M_CLKA0#
M_CKEA
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA1
M_QSA3
M_DQMA#1
M_DQMA#3
M_MAA12
M_MAA13
C226
100nF
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
8MX16
402
U33
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
8MX16
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
M_MDA23
2
DQ0
M_MDA22
4
DQ1
M_MDA21
5
DQ2
M_MDA20
7
DQ3
M_MDA19
8
DQ4
M_MDA18
10
DQ5
M_MDA17
11
DQ6
M_MDA16
13
DQ7
M_MDA7
54
DQ8
M_MDA6
56
DQ9
M_MDA5
57
M_MDA4
59
M_MDA3
60
M_MDA2
62
M_MDA1
63
M_MDA0
65
14
NC
17
19
25
M_MAA14 M_MAA14
42
43
+MVDDC +MVDDC
50
53
1
VDD
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VDD
VSS
+MVDDQ
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64
M_MDA14
2
M_MDA13
4
M_MDA8
5
M_MDA15
7
M_MDA11
8
M_MDA12
10
M_MDA10
11
M_MDA9
13
M_MDA25
54
M_MDA24
56
M_MDA28
57
M_MDA27
59
M_MDA30
60
M_MDA31
62
M_MDA26
63
M_MDA29
65
14
NC
17
19
25
42
43
50
53
1
+MVDDQ
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64
C289
100nF
402
+MVDDQ
M_CLKA1
M_CLKA1#
M_CKEA
C290
100nF
402
M_CLKA1
M_CLKA1#
M_CKEA
C216
100nF
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA7
M_QSA4
M_DQMA#7
M_DQMA#4
M_MAA12
M_MAA13
+MVDDQ
C236
100nF
+VREF_U68
M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_CSA#0
M_RASA#0
M_CASA#0
M_WEA#
M_QSA5
M_QSA6
M_DQMA#5
M_DQMA#6
M_MAA12
M_MAA13
Channel A Bottom UpChannel A Bottom Down
402
U30
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
8MX16
402
U34
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
8MX16
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
M_MDA63
2
DQ0
M_MDA61
4
DQ1
M_MDA62
5
DQ2
M_MDA58
7
DQ3
M_MDA60
8
DQ4
M_MDA57
10
DQ5
M_MDA59
11
DQ6
M_MDA56
13
DQ7
M_MDA39
54
DQ8
M_MDA38
56
DQ9
M_MDA37
57
M_MDA36
59
M_MDA35
60
M_MDA32
62
M_MDA33
63
M_MDA34
65
14
NC
17
19
25
42
43
50
53
1
VDD
VSS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VDD
VSS
+MVDDQ
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64
M_MDA41
2
M_MDA40
4
M_MDA42
5
M_MDA47
7
M_MDA43
8
M_MDA46
10
M_MDA45
11
M_MDA44
13
M_MDA48
54
M_MDA50
56
M_MDA51
57
M_MDA49
59
M_MDA52
60
M_MDA55
62
M_MDA53
63
M_MDA54
65
14
NC
17
19
25
M_MAA14M_MAA14
42
43
+MVDDC+MVDDC
50
53
1
+MVDDQ
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64
+MVDDQ+MVDDQ
R801
R805
4.7K
4.7K
402
402
+VREF_U66+VREF_U69
R806
R802
4.7K
4.7K
402 402
+MVDDQ+MVDDQ
R905
R901
4.7K
4.7K
402
402
+VREF_U67 +VREF_U68
R902
R906
4.7K
4.7K
402 402
Channel A Top UpChannel A Top Down
Put 1 1uF cap per power pin of memory
+MVDDQ+MVDDQ
C213
C214
C201
C202
100nF
100nF
402 402 402 402
402
+MVDDC
C207
100nF
+MVDDQ
A A
C221
C222
100nF
100nF
402 402 402 402
402 402 402 402 402
+MVDDC +MVDDC
C227
100nF
402 402402
8
C203
100nF
C208
100nF
C223
100nF
C228
100nF
C204
100nF
C209
100nF
402402402
C224
100nF
C229
100nF
100nF
C225
100nF
+MVDDQ
C212
C211
100nF
100nF
402 402 402 402
402
+MVDDC
C217
100nF
402 402402
C231
C232
100nF
100nF
402
C237
100nF
402 402402
7
100nF
C218
100nF
C233
100nF
C238
100nF
C205
100nF
C219
100nF
C234
100nF
C239
100nF
C215
100nF
C235
100nF
+MVDDQ
C283
22uF_16V
TANT
+MVDDQ +MVDDC
C284
C286
22uF_16V
22uF_16V
TANT
TANT
Title
Size Document Number Rev
Custom
6
5
4
3
Date: Sheet
2
GIGABYTE
TSOP 16Mx16 DDR
GV-RX30128D
1.1
of
11 20Wednesday, October 20, 2004
1
8
M_MAB[14..0]
8
M_DQMB#[7..0]
M_QSB[7..0]
M_CLKB#0(3,9)
M_CLKB#1(3,9)
M_CLKB0(3,9)
M_CLKB1(3,9)
M_CKEB(3,9)
M_WEB#(3,9)
M_CASB#(3,9)
M_RASB#(3,9)
M_CSB#0(3,9)
M_DQMB#0
M_DQMB#1
M_DQMB#2
M_DQMB#3
M_DQMB#4
M_DQMB#5
M_DQMB#6
M_DQMB#7
M_QSB0
M_QSB1
M_QSB2
M_QSB3
M_QSB4
M_QSB5
M_QSB6
M_QSB7
M_CLKB0#
M_CLKB1#
M_CLKB0
M_CLKB1
M_CKEB
M_WEB#
M_CASB#0
M_RASB#0
M_CSB#0
M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_MAB12
M_MAB13
M_MAB14
M_MDB[63..0](9)
M_DQMB#[7..0](9)
D D
M_QSB[7..0](9)
C C
M_MAB[14..0](3,9)
B B
A A
7
+MVDDQ
+MVDDQ
7
6
C242
C241
100nF
100nF
402 402 402 402
402
+MVDDC
C247
100nF
402 402402
C262
C261
100nF
100nF
402
402 402
+MVDDC
C267
100nF
402
6
C243
100nF
C248
100nF
C263
100nF
C268
100nF
C244
100nF
C249
100nF
C264
100nF
402
C269
100nF
5
+MVDDQ
C253
C245
100nF
+MVDDQ
C265
100nF
402
402402
100nF
100nF
402
+MVDDC
C257
100nF
C272
C271
100nF
100nF
402 402402402
+MVDDC
C277
100nF
402 402
5
C252
C251
100nF
C258
100nF
C273
100nF
C278
100nF
C254
C255
100nF
100nF
402402402402
C259
100nF
402 402402
C274
C275
100nF
100nF
402
C279
100nF
402
4
+MVDDQ +MVDDQ
Channel B Top Right Channel B Bottom Left
C246
402
U31
100nF
+VREF_U77
C291
100nF/X
402
C292
100nF/X
402
49
C266
100nF
+VREF_U79
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
8MX16
402
U35
49
VREF
29
A0
30
A1
31
A2
32
A3
35
A4
36
A5
37
A6
38
A7
39
A8
40
A9
28
A10/AP
41
A11
45
CK
46
CK
44
CKE
24
CS
23
RAS
22
CAS
21
WE
16
LDQS
51
UDQS
20
LDM
47
UDM
26
BA0
27
BA1
8MX16
M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_CLKB0
M_CLKB0#
M_CKEB
M_CSB#0
M_RASB#0
M_CASB#0
M_WEB#
M_QSB2
M_QSB0
M_DQMB#2
M_DQMB#0
M_MAB12
M_MAB13
+MVDDQ +MVDDQ
M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_CLKB0
M_CLKB0#
M_CKEB
M_CSB#0
M_RASB#0
M_CASB#0
M_WEB#
M_QSB1
M_QSB3
M_DQMB#1
M_DQMB#3
M_MAB12
M_MAB13
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
NC#17
NC#19
NC#25
NC#42
NC#43
NC#50
NC#53
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
M_MDB23
2
DQ0
M_MDB22
4
DQ1
M_MDB21
5
DQ2
M_MDB20
7
DQ3
M_MDB19
8
DQ4
M_MDB18
10
DQ5
M_MDB17
11
DQ6
M_MDB16
13
DQ7
M_MDB4
54
DQ8
M_MDB5
56
DQ9
M_MDB6
57
M_MDB7
59
M_MDB3
60
M_MDB2
62
M_MDB1
63
M_MDB0
65
14
NC
17
19
25
M_MAB14 M_MAB14
42
43
50
53
1
VDD
18
33
3
9
15
55
61
34
VSS
48
66
6
12
52
58
64
M_MDB8
2
DQ0
M_MDB9
4
DQ1
M_MDB10
5
DQ2
M_MDB11
7
DQ3
M_MDB12
8
DQ4
M_MDB13
10
DQ5
M_MDB14
11
DQ6
M_MDB15
13
DQ7
M_MDB27
54
DQ8
M_MDB25
56
DQ9
M_MDB28
57
M_MDB30
59
M_MDB24
60
M_MDB31
62
M_MDB26
63
M_MDB29
65
14
NC
17
19
25
42
43
+MVDDC
50
53
1
VDD
18
33
3
9
15
55
61
34
VSS
48
66
6
12
52
58
64
3
C293
100nF/X
402
+MVDDQ +MVDDQ
C294
100nF/X
402
+MVDDQ
Channel B Bottom Left
+MVDDQ +MVDDC
C281
C285
22uF_16V
22uF_16V
TANT
TANT
+MVDDQ
C282
22uF_16V
TANT
4
3
C256
402
U32
100nF
+VREF_U78
49
M_MAB0
29
M_MAB1
30
M_MAB2
31
M_MAB3
32
M_MAB4
35
M_MAB5
36
M_MAB6
37
M_MAB7
38
M_MAB8
39
M_MAB9
40
M_MAB10
28
M_MAB11
41
M_CLKB1
45
M_CLKB1#
46
M_CKEB
44
M_CSB#0
24
M_RASB#0
23
M_CASB#0
22
M_WEB#
21
M_QSB5
16
M_QSB7
51
M_DQMB#5
20
M_DQMB#7
47
M_MAB12
26
M_MAB13
27
8MX16
C276
402
100nF
U36
+VREF_U76
49
M_MAB0
29
M_MAB1
30
M_MAB2
31
M_MAB3
32
M_MAB4
35
M_MAB5
36
M_MAB6
37
M_MAB7
38
M_MAB8
39
M_MAB9
40
M_MAB10
28
M_MAB11
41
M_CLKB1
45
M_CLKB1#
46
M_CKEB
44
M_CSB#0
24
M_RASB#0
23
M_CASB#0
22
M_WEB#
21
M_QSB6
16
M_QSB4
51
M_DQMB#6
20
M_DQMB#4
47
M_MAB12
26
M_MAB13
27
8MX16
Channel B Top Left
VREF
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
CK
CK
CKE
CS
RAS
CAS
WE
LDQS
UDQS
LDM
UDM
BA0
BA1
VREF
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
CK
CK
CKE
CS
RAS
CAS
WE
LDQS
UDQS
LDM
UDM
BA0
BA1
2
M_MDB40
2
DQ0
M_MDB41
4
DQ1
M_MDB42
5
DQ2
M_MDB43
7
DQ3
M_MDB44
8
DQ4
M_MDB45
10
DQ5
M_MDB46
11
DQ6
M_MDB47
13
DQ7
M_MDB56
54
DQ8
M_MDB57
56
DQ9
M_MDB58
57
DQ10
M_MDB59
59
DQ11
M_MDB60
60
DQ12
M_MDB61
62
DQ13
M_MDB62
63
DQ14
M_MDB63
65
DQ15
14
NC
17
NC#17
19
NC#19
25
NC#25
42
NC#42
43
NC#43
+MVDDC+MVDDC
50
NC#50
53
NC#53
1
VDD
18
VDD#18
33
VDD#33
3
VDDQ
9
VDDQ#9
15
VDDQ#15
55
VDDQ#55
61
VDDQ#61
34
VSS
48
VSS#48
66
VSS#66
6
VSSQ#6
12
VSSQ#12
52
VSSQ
58
VSSQ#58
64
VSSQ#64
M_MDB55
2
DQ0
M_MDB54
4
DQ1
M_MDB53
5
DQ2
M_MDB52
7
DQ3
M_MDB51
8
DQ4
M_MDB50
10
DQ5
M_MDB49
11
DQ6
M_MDB48
13
DQ7
M_MDB39
54
DQ8
M_MDB38
56
DQ9
M_MDB37
57
DQ10
M_MDB36
59
DQ11
M_MDB35
60
DQ12
M_MDB34
62
DQ13
M_MDB33
63
DQ14
M_MDB32
65
DQ15
14
NC
17
NC#17
19
NC#19
25
NC#25
M_MAB14M_MAB14
42
NC#42
43
NC#43
+MVDDC
50
NC#50
53
NC#53
1
VDD#18
VDD#33
VDDQ
VDDQ#9
VDDQ#15
VDDQ#55
VDDQ#61
VSS#48
VSS#66
VSSQ#6
VSSQ#12
VSSQ
VSSQ#58
VSSQ#64
VDD
VSS
+MVDDQ
18
33
3
9
15
55
61
34
48
66
6
12
52
58
64
Title
Size Document Number Rev
Custom
Date: Sheet
2
GIGABYTE
TSOP 16Mx16 DDR
GV-RX30128D
1
+MVDDQ+MVDDQ
R803
R807
4.7K
4.7K
402
402
+VREF_U77 +VREF_U78
R804
R808
4.7K
4.7K
402 402
+MVDDQ+MVDDQ
R903
R907
4.7K
4.7K
402
402
+VREF_U76
+VREF_U79
R904
R908
4.7K
4.7K
402 402
of
12 20Wednesday, October 20, 2004
1
1.1
8
7
6
5
4
3
2
1
GPIO0
OPTION STRAPS
+3.3V_BUS
D D
C C
Mem_Strap0(2)
Mem_Strap1(2)
B B
LCDDATA16(2)
LCDDATA17(2)
32
SW1B
DIP_SWX2 /X
R250 10K/X
VHAD0(2,16)
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO11
GPIO12
GPIO13
GPIO9
GPIO8
DNI
R201 10K
R202 10K/X
R203 10K
R204 10K/X
R205 10K/X
R206 10K
R207 10K/X
R208 10K
R219 10K
R220 10K/X
R221 10K/X
R222 10K
R223 10K/X
R224 10K
R209 10K/X
R210 10K
R211 10K/X
R212 10K
R213 10K
R214 10K/X
R215 10K
R216 10K/X
R217 10K/X
R218 10K
R235 10K/X
R236 10K
R237 10K/X
R238 10K
R227 10K/X
R228 10K
R229 10K/X
R230 10K
R231 10K/X
R232 10K
DESKTOP
MOBO
DESKTOP
MOBO
DNI
Tumwater
Grantsdale
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
+VDDR4
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
STRAPS
STRAP_B_PTX_PWRS_EN B
STRAP_B_PTX_DEEMPH_E N
PCIE_MODE(1:0)
STRAP_FORCE_COMPLIANCE
STRAP_B_PPLL_B W GPIO6
STRAP_DEBUG_ACCESS Strap to set the debug muxes to bring out DEBUG signals
ROMIDCFG(3:0)
STRAP P INTERRUPT
LOW
ENABLED (DEFAULT)
DISABLED
HIGH
MEMORY TYPE STRAPS
Mem_Strap0 Mem_Strap1
SAM
00
INF
1
HYN
0
ELPIDA
11
GPIO[6..0]
GPIO[13..8]
0
1
GPIO[6..0] (2)
GPIO[13..8] (2)
DESCRIPTIONPIN
GPIO0
GPIO1
GPIO(3:2)
GPIO4
GPIO5
GPIO8
GPIO(9,13:11)
DVPDATA_20VIP_DEVICE Indicates if any slave VIP host devices drove this in low during reset.
(VHAD0 net)
Tansmitter Power Savings Enable
0: 50% Tx output swing for mobile mode
1: full Tx output swing
Transmitter De-emphasis Enable
0: Tx de-emphasis disabled for mobile mode
1: Tx de-emphasis enabled
00: PCI Express 1.0A mode (Grantsdale)
01: Kyrene-compatible mode
10: PCI Express 1.0 mode (Tumwater)
11: PCI Express 1.0A mode and short-circuit internal loopback mode
(Rx connected directly to Tx of PHY)
Transmitter Extra Current
0: normal mode
1: extra current in Tx output stage - potential power savings for mobile mode
Force chip to go to Compliance state quickly for Tester purposes
0: normal operational mode
1: compliance mode
PLL Bandwidth
0: full PLL Bandwidth
1: reduced PLL bandwidth
even if registers are inaccessible.
If no ROM attached, comtrols chip IDis. If rom attached identifies ROM type
0000 - No ROM, CHG_ID=0
0001 - No ROM, CHG_ID=1
0100 - reserved
0110 - reserved
1000 - Parallel ROM, chip IDis from ROM
1001 - Serial AT25F1024 ROM (Atmel), chip IDis from ROM
1010 - Serial AT45DB011 ROM (Atmel), chip IDis from ROM
1011 - Serial M25P10 ROM (ST), chip IDis from ROM
1100 - Serial M25P05 ROM (ST), chip IDis from ROM
1100 - Serial NX25F011B ROM (ISSI), chip IDis from ROM
0 - Slave VIP host port devices present
1 - No slave VIP host port devices reporting presence during reset
GPIO8(2)
GPIO9(2)
GPIO10(2)
ROMCS#(3)
R91
10K
+3.3V_BUS
ASIC DEFAULT
0
0
00
0STRAP_B_PTX_IEXT
0
0
0
SERIAL EEPROM 512K
ROM_SO
SI/A16
SCK/WEb
CSb
HOLD1
+3.3V_BUS
C80
100nF
U11
5
D
6
C
1
S
7
HOLD
3
W
8
VCC
M25P05-AVMN 6T
2
Q
4
VSS
A A
Title
Size Document Number Rev
Custom
8
7
6
5
4
3
Date: Sheet
2
GIGABYTE
Straps and BIOS Flashrom
GV-RX30128D
13 20Wednesday, October 20, 2004
1
1.1
of
8
7
6
5
4
3
2
1
OPTIONAL ESD/HOTPLUG PROTECTION DIODES
PRIMARY CRT
D D
A_R_DAC1(2)
A_G_DAC1(2)
A_B_DAC1(2)
C C
R401 75.0R
R402 75.0R
R403 75.0R
CRT1DDCDATA(1,2)
CRT1DDCCLK(1,2)
A_HSYNC_DAC1(1,2)
A_VSYNC_DAC1(1,2)
Pr
Y
Pb
C402
C401
3.3pF/X
3.3pF/X
402
402402
+3.3V_BUS
R404
4.7K
402
+3.3V_BUS
R406
4.7K
402
10
C403
3.3pF/X
5
4
9
L51 47nH
L52 47nH
L53 47nH
+5V
1
32
BSN20
+5V
Q51
1
32
BSN20
Q52
6
U6B
SN74ACT86D
8
U6C
SN74ACT86D
R405
6.8K
402
R407
6.8K
402
DDCCLK_DAC1_5V
A_HSYNC_DAC1_B
A_VSYNC_DAC1_B
L54 47nH
L55 47nH
L56 47nH
C405
C406
C404
8.0pF
8.0pF
8.0pF
402
402
402402
Place close to ASIC
R415 33R
R416 33R
R413
R414
402
402
A_HSYNC_DAC1_R
51R
51R
A_VSYNC_DAC1_R
DDCDATA_DAC1_RDDCDATA_DAC1_5V
DDCCLK_DAC1_R
A_R_DB15
A_G_DB15
A_B_DB15
+3.3V_BUS +3.3V_BUS +3.3V_BUS +5V+5V
BAT54SLT1/X
D55
3
DDCDATA_DAC1_R
DDCCLK_DAC1_R
A_HSYNC_DAC1_R
A_VSYNC_DAC1_R
BAT54SLT1/X
2
1
BAT54SLT1/X
2
D57
D56
3
3
1
C407
5pF/X
L60
82nH/X
BAT54SLT1/X
C409
5pF/X
L62
82nH/X
BAT54SLT1/X
2
D51
D52
3
3
1
DNI
2
1
C408
5pF/X
L61
82nH/X
Place close to CONNECTOR
+5V
+5V
2
1
BAT54SLT1/X
D53
3
BAT54SLT1/X
2
1
2
D54
3
C441
68pF
+5V_VESA
J1
1
R
2
G
3
B
11
DDC2_MONID0
MS0
12
DDC2_MONID1(SDA)
MS1
4
DDC2_MONID2
MS2
15
MS3
DDC2_MONID3(SCL)
9
NC
13
HS
14
VS
5
VSS
6
VSS#6
7
VSS#7
8
VSS#8
10
VSS#10
16
CASE
17
CASE#17
Connector_DB15_Female_VGA_Blue
1
OPTIONAL ESD/HOTPLUG PROTECTION DIODES
SECONDARY CRT
A_R_DVI-I (15)
A_G_DVI-I (15)
B B
A A
A_R_DAC2(14)
A_G_DAC2(14)
A_B_DAC2(14)
8
R451 75.0R
R452 75.0R
R453 75.0R
DVIDDCDATA(2)
DVIDDCCLK(2)
A_HSYNC_DAC2(2)
A_VSYNC_DAC2(2)
Pr
Y
Pb
C452
C451
3.3pF/X
3.3pF/X
402
402402
+3.3V_BUS +5V
R454
4.7K
402
+3.3V_BUS +5V
R456
4.7K
402
7
13
12
C453
3.3pF/X
1
2
1
1
+5V
147
L71 47nH
L72 47nH
L73 47nH
R455
6.8K
402
DDCDATA_DAC2_5V
32
BSN20
Q71
R457
6.8K
DDCCLK_DAC2_5V
32
BSN20
Q72
SN74ACT86D
U6A
A_HSYNC_DAC2_B
3
A_VSYNC_DAC2_B
11
U6D
SN74ACT86D
L74 47nH
L75 47nH
L76 47nH
C456
C454
C455
8.0pF
8.0pF
8.0pF
402
402
402402
Place close to ASIC
R465 33R
R466 33R
R463
R464
6
402
402402
A_HSYNC_DAC2_R
33R/6
33R/6
A_VSYNC_DAC2_R
DDCDATA_DAC2_R
DDCCLK_DAC2_R
5
A_B_DVI-I (15)
+3.3V_BUS +3.3V_BUS +5V +5V+3.3V_BUS +5V+5V
BAT54SLT1/X
D65
3
DDCDATA_DAC2_R
DDCCLK_DAC2_R
A_HSYNC_DAC2_R
A_VSYNC_DAC2_R
BAT54SLT1/X
2
1
BAT54SLT1/X
2
D66
3
1
BAT54SLT1/X
BAT54SLT1/X
C458
5pF/X
L81
82nH/X
C459
5pF/X
L82
82nH/X
2
D61
D62
3
3
1
DNI
2
D67
3
1
C457
5pF/X
L80
82nH/X
Place close to CONNECTOR
DDCDATA_DVI-I_R (15)
DDCCLK_DVI-I_R (15)
A_HSYNC_DVI-I_R (15)
A_VSYNC_DVI-I_R (15)
4
3
2
1
BAT54SLT1/X
D63
3
BAT54SLT1/X
2
2
D64
3
1
1
Title
Size Document Number Rev
C
Date: Sheet
2
+5V_VESA2
GIGABYTE
DAC RGB Filters
GV-RX30128D
MJ2
1
R
2
G
3
B
11
DDC2_MONID0
MS0
12
DDC2_MONID1(SDA)
MS1
4
DDC2_MONID2
MS2
15
DDC2_MONID3(SCL)
MS3
9
NC
13
HS
14
VS
5
VSS
6
VSS#6
7
VSS#7
8
VSS#8
10
VSS#10
16
CASE
17
CASE#17
18
CASE#18
19
CASE#19
DB15F_slim_RA/X
6052003000
14 20Wednesday, October 20, 2004
1
1.1
of
8
7
6
5
4
3
2
1
Component
D D
Pr
A_R/C_DAC2
Y
A_G/Y_DAC2
Pb
A_B/COMP_DAC2
C C
Y
A_Y_DAC2_F
A_C_DAC2_F
Pr
A_COMP_DAC2_F
Pb
B B
Place close to ASIC
Pr
A_R/C_DAC2(2)
Y
A_G/Y_DAC2(2)
A_B/COMP_DAC2(2)
Pb
MUX BYPASS
R519 0R
R520 0R
R521 0R
A_R/C_DAC2
A_G/Y_DAC2
A_B/COMP_DAC2
+3.3V_BUS
R582
10K
DEMUX_SEL(2)
R9280R/X
R9290R/X
R9300R/X
R9700R/X
R9710R/X
R9720R/X
402
Pr
A_R_DAC2
402
402
402
402
402
402
402
402
402
Y
A_G_DAC2
Pb
A_B_DAC2
Pr
A_C_DAC2
Y
A_Y_DAC2
Pb
A_COMP_DAC2
A_Y_DAC2_DIN
A_C_DAC2_DIN
A_COMP_DAC2_DIN PIN7
SVHS/YPrPbb(2)
U96
1
SEL
2
1A0
3
1A1
5
1B0
6
1B1
11
1C0
10 14
1C1 1D0
15
E
QS3257S1
+3.3V_BUS
R578
10K
402
16
VCC
4
YA
7
YB
9
YC
12
YD
13
1D1
8
GND
R377 0R
Pr
A_R_DAC2
A_G_DAC2
+5V
C155
100nF
402
A_C_DAC2
A_Y_DAC2 A_COMP_DAC2
A_COMP_DAC2
TV Out (SVHS)
J5
PIN6
402
CompR_F
PIN1
PIN2
Jm4
6
+12V
3
Y-OUT
4
C-OUT
7
Comp_out
5
SYNC
1
GND
2
GND#2
8
CASE
9
CASE#9
10
CASE#10
Connector_DIN_Miniature_Circular_7_Pin
A_R_DAC2 (13)
A_G_DAC2 (13)
A_B_DAC2 (13)
Pr
Y
Pb
Place close to connector
Y
A_Y_DAC2
Pb
A_C_DAC2
R504
75.0R
402
R505
75.0R
402
R506
75.0R
402
C501
82pF
C503
82pF
C505
82pF
L91
1.8uH
L92
1.8uH
L93
1.8uH
A_Y_DAC2_FA_B_DAC2
C502
82pF
A_C_DAC2_F
C504
82pF
A_COMP_DAC2_F
C506
82pF
Cm3
Cm4
Cm5
MC502
82pF/X
MC504
82pF/X
MC506
82pF/X
VIVO MiniDIN 9-pin
Jm2
PIN6
6
A_Y_DAC2_DIN
A_C_DAC2_DIN
A_COMP_DAC2_DIN
C100
0R/6
Put 0R on Cx if
9-pin MiniDIN is
not used
CompR_F
LumaR_F
ChromaR_F
5
CompR(16)
LumaR(16)
ChromaR(16)
C102
C101
330pF/X
A A
8
7
330pF/X
6
+12V
3
Y-OUT
4
C-OUT
7
Comp-out
5
Comp-in
PIN1
1
GND
PIN2
2
GND#2
11
Luma-in
12
Chroma-in
8
CASE
9
CASE#9
10
CASE#10
MJ5
Connector_DIN_Miniature_Circular_9_Pin/X
Title
Size Document Number Rev
C
4
3
Date: Sheet
2
GIGABYTE
VIVO Filter & Connect ors
GV-RX30128D
15 20Wednesday, October 20, 2004
1
1.1
of
5
4
3
2
1
PRIMARY DVI-I CONNECTOR
INSTALL TERMINATION RESISTORS CLOSE TO ASIC
R601 330R
D D
C C
TMDS_TX2N(2)
TMDS_TX2P(2)
TMDS_TX1N(2)
TMDS_TX1P(2)
TMDS_TX0N(2)
TMDS_TX0P(2)
TMDS_TXCP(2)
TMDS_TXCN(2)
DDCCLK_DVI-I_R(13)
DDCDATA_DVI-I_R(13)
HPD(2)
402
R602 330R
402
R603 330R
402
R604 330R
402
D121
2.5V/X
DNI
DDCCLK_DVI-I
DDCDATA_DVI-I
A_VSYNC_DVI-I_R(13)
A_R_DVI-I(13)
A_G_DVI-I(13)
A_B_DVI-I(13)
A_HSYNC_DVI-I_R(13)
+3.3V_BUS
R606
R605
20K
20K
402 402
Q25
2 3
CMPT3904
1
Q26
1
2 3
CMPT3904
R609
100K/X
2 1
R608 20K /X
402
R607 20K
402402
HPD_R
+5V_VESA2
Pr
Y
Pb
C510
68pF/X
DNI
J2
25
CASE
1
TMDS Data2-
2
TMDS Data2+
3
TMDS Data2/4 Shield
4
TMDS Data4-
5
TMDS Data4+
6
DDC Clock
7
DDC Data
8
Analog VSYNC
9
TMDS Data1-
10
TMDS Data1+
11
TMDS Data1/3 Shield
12
TMDS Data3-
13
TMDS Data3+
14
+5V Power
15
GND (for +5V)
16
Hot Plug Detect
17
TMDS Data0-
18
TMDS Data0+
19
TMDS Data0/5 Shield
20
TMDS Data5-
21
TMDS Data5+
22
TMDS Clock Shield
23
TMDS Clock+
24
TMDS Clock-
C1
Analog Red
C2
Analog Green
C3
Analog Blue
C4
Analog HYNC
C5
Analog GND
C6
Analog GND#C6
26
CASE#26
27
CASE#27
28
CASE#28
29
CASE#29
30
CASE#30
DVICONNECTOR
B B
A A
Req = 120.7R
Use 845R, 1206, 1/4W
Req = 120.8R
Use 845R, 1206, 1/4W
5
+12V_BUS
+12V_BUS
R911
845R/1206
R921
845R/1206
R912
845R/1206
R922
845R/1206
R913
845R/1206
R923
845R/1206
R914
845R/1206
R924
845R/1206
R915
845R/1206
REG19
TL431CDBVR
R925
845R/1206
REG20
TL431CDBVR
4
R951
845R/1206
R953
845R/1206
R952
845R/1206
NC
NC
5 3
R954
845R/1206
NC
NC
5 3
+5V_VESA
Multi-footprint
C911
10uF_6.3V
MC911
4.7uF/X
R916
1.0K
1%
4
402
1
R917
2
1.0K
1%
402
+5V_VESA2
Multi-footprint
R918
C912
10uF_6.3V
MC912
4.7uF/X
1.0K
1%
4
402
1
R919
2
1.0K
1%
402
Normal +5V regulated operation
This circuit provide upto 55 m A
If Iload > 55mA, +5V will drop
If Vout is shorted
Current across each Rx is 12V/845R = 14.2mA
Power dissipated by each Rx is 14.2mA x 12V = 171mW
Each Rx are rated 250mW (1/4W)
Derating 250mW by 70% is 175mW (1/4W)
Normal +5V regulated operation
This circuit provide upto 55 m A
If Iload > 55mA, +5V will drop
If Vout is shorted
Current across each Rx is 12V/845R = 14.2mA
Power dissipated by each Rx is 14.2mA x 12V = 171mW
Each Rx are rated 250mW (1/4W)
Derating 250mW by 70% is 175mW (1/4W)
3
Title
Size Document Number Rev
Custom
2
Date: Sheet
GIGABYTE
TMDS & DVI-I
GV-RX30128D
1
1.1
of
16 20Wednesday, October 20, 2004
8
D D
L32
1 2
CompR(14)
LumaR(14)
ChromaR(14)
C C
L36
3.3uH/X
C543
22uF_16V /X
3.3uH/X
L34
1 2
3.3uH/X
L35
1 2
3.3uH/X
+RTAVDD
12
R615
10R/X
402
C542
100nF/X
402
C522
330pF/X
402
C525
330pF/X
402
C526
330pF/X
402
R616
75.0R/X
402
R617
75.0R/X
402
R618
75.0R/X
402
C541 2.2uF/X
PERST#_buf(1,2)
7
22uF_16V /X
12
R613
L33
10R/X
3.3uH/X
402
C524
22uF_16V /X
VINGND
C539 0.1uF/X
Place close t o
RT
C529
22pF/X
C544
100nF/X
402
C540
0.068uF/X
C528 2.2uF/X
Y3
27_MHZ/X
+RTAVDD
L31
3.3uH/X
C545
C527
22nf/X
21
6
12
R612
10R/X
402
VADCFILTER
C523
100nF/X
402
VADCFILTER
VADCFILTER
R625
330R/X
402 402
C530
22pF/X
R622
4.7K/X
47
VAGCVDD
49
VAGCVSS#49
48
VAGCVSS
66
VDACVDD
60
VDACBVSS
61
VDACJVSS
33
VIND0
34
VIND1
35
VIND2
36
VIND3
37
VIND4
38
VIND5
39
VIND6
40
VIND7
27
VINGATEA
28
VINGATEB
58
CF
59
CR
57
VAGCCAP
56
VIDEOGNDSENSE
55
VCLAMPCAP
43
VADCDVDD
45
VADCAVDD
44
VADCDVSS
46
VADCAVSS
50
COMP0
51
COMP1
52
COMP2
53
YF_COMP3
54
YR_COMP4
69
XTALIN
70
XTALOUT
73
TESTEN
74
RESETB
67
PLLVDD
68
PLLVSS
18
VSSC
VSSC#26
26
VSSC#77
83
+RTVDDC
1
29
VDDR
VSSC#100
VSSC#83
100
VDDR#29
2
5
C531
C532
100nF/X
100nF/X
402 402 402
25
41
99
31
767771
81
VDDC
VDDR#81
VDDC#99
VDDR#31
VDDC#76
VDDR#71
CLKOUT0_GPIO0
CLKOUT1_GPIO1
CLKOUT2_GPIO2
VSSR
VSSR#12
VSSR#30
VSSR#32
VSSR#90
VSSR#2
VSSR#72
82
42
72
12
30
32
90
VDDC#41
DS_VIPCLK
AS_HCTL
SRDY_IRQB
C_GREEN
COMP_BLUE
VSSC#42
RAGE_THEATER/X
C534
C533
100nF/X
U3
SAD0
SAD1
SAD2
SAD3
SAD4
SAD5
SAD6
SAD7
HAD0
HAD1
ADIO
BITCLK
SPDIF
BYTCLK
SYNC
Y_RED
RSET
GPIO3
GPIO4
GPIO5
GPIO6
PDATA0
PDATA1
PDATA2
PDATA3
PDATA4
PDATA5
PDATA6
PDATA7
PCLK
SDA
SCL
ADO
C535
100nF/X
100nF/X
402 402 402 402 402
91
92
93
94
95
96
97
98
RP3A 33R/X
88
RP3B 33R/X
87
R614 47K/X
86
RP3D 33R/X
84
RP3C 33R/X
85
15
16
22
24
23
WS
21
19
89
75
62
63
64
R611 383R/X
65
78
79
20
13
14
17
80
4
5
6
7
8
9
10
11
3
VID/DVO0
VID/DVO1
VID/DVO2
VID/DVO3
VID/DVO4
VID/DVO5
VID/DVO6
VID/DVO7
402
C536
100nF/X
4
+3.3V_BUS
C537
C538
100nF/X
100nF/X
81
72
402
54
63
R619
10K/X
402
CLK_VIPCLK (2)
VPHCTL (2)
VHAD0 (2,12)
VHAD1 (2)
R621
R620
10K/X
4.7K/X
402402
+3.3V_BUS
CLK_RT (2)
3
+RTAVDD
Vout = 3.3V
Iout = 125mA MAX, 80mA RMS
+12V_BUS
REG1
LT1117CST/X
3 2
C521
100nF/X
402
Change to 1%
VID/DVO[7..0] (2)
CLK_VID/DVO (2)
IN OUT
4
CASE
ADJ
1
R627
200R/X
1%
402
R626
121R/X
1%
+RTAVDD
2
C520
10uF_6.3V/ X
1
B B
Footprint can be r e placed w i t h z e r o ohm or ot h e r .
B8
VINGND
IMPORTANT
Layout Guide line of THEATER
#1 : C27 and C28 have to be placed as close as possible to the respective pins of Rage THEATER
#2 : VINGND should be seperated from Digital or Chassis Ground and have no loops
#3 : VINGND should be connected to Digital GND plane at one point as close as p os s i b l e t o
pin 56 of THEATER
A A
8
7
Put 2D line as close as possible to pin 56 of Rage Theater
VINGND
6
5
Title
Size Document Number Rev
Custom
4
3
Date: Sheet
2
GIGABYTE
Rage Theater
GV-RX30128D
1.1
of
17 20Wednesday, October 20, 2004
1
8
7
6
5
4
3
2
1
D D
C C
SCL(1,2)
SDA(2)
ThermINT(2)
B B
R946 0R/X
402
R934
10K/X
402
C907
C908
56pF/X
56pF/X
+3.3V_BUS
R937
402
10K/X
DNI
R938
402 402
10K/X
DNI
DNI
DNI
TEMPERATURE SENSE AND SPEED CONTROLLED FAN
+3.3V_BUS
C903
tach
pwm
DÂSCL
R939 0R/X
R940 0R/X
C902
0.1uF/X
10uF/X
U91
8
SMBCLK
7
SMBDAT
6
ALERT
5 4
GND PWM
LM63CIMAX/X
DNI
U92
TACHNC#3
4
NC#4
INT
1
PWM
5
GND
NC
9
D-
13
NC#11
ADD
16
SCL
D+
7
THERM
402
8
VCC
FAULT
SDA
ADM1030ARQ/ X
C904
100pF/X
1
VDD
2
D+
3
D-
PWM
tach
23
R936 0R/X
14
DNI
12
11
D+
10
+3.3V_BUS
6
SDA
15
C905
2.2nF/X
R927 10R/X
tach
402
402
C906
10nF/X
R933
10K/X
402
D+
D-
R926 0R/X
DNI
+3.3V_BUS +12V_BUS
402
1
R944 0R/X
R945
10K/X
402
D+ (2)
D- (2)
R931
1K/X
402
CMPT3904/X
Q42
2 3
+3.3V_BUS
402
+12V_BUS
C901
100nF/X
603
X7R
5%
R941
1K/X
402
C900
100nF/X
+12V_BUS
R943
10K/X
402 402
R947
10K/X
B31
Bead/X
2N7002E/X
Q41
R932
0R/X
402
JU1
1
2
JUl2
DUAL FOOT P R IN T
ACTIVE_HEATSINK/X
MJU1
1
2
JUl1
3
Header_1X3/X
32
1
R935
0R/X
402
C909
10nF/X
H101
heatsink/X
7120005 800
MH101
HEATSINK/X
H100
HEATSINK/X
7120005 100
Spring push-pin
MH100
HEATSINK
7120008 000
ITW push-pin
A A
Title
Size Document Number Rev
Custom
8
7
6
5
4
3
Date: Sheet
2
GIGABYTE
Thermal Management
GV-RX30128D
18 20Wednesday, October 20, 2004
1
1.1
of
5
4
3
2
1
ASSY1
SCREW
JACKSCREW
ASSY2
SCREW
D D
C C
JACKSCREW
ASSY10
DVI, DIN, VGA
ASSY11
DI-V
DVI, DIN, VGA
MT1
MT_Hole_0.136_in.
BRACKET
BRACKET
ASSY3
ASSY4
SCREW
JACKSCREW
SCREW
JACKSCREW
8020037100
SV-VO-V
80200371A0 80200370A0
SV-V
ASSY12
BRACKET
Slim VGA, DIN, VGA, 347
8020034 700
ASSY13
BRACKET
Slim VGA, DIN, VGA, 347
MISC. BOARD PARTS
ASSY7
ANTISTATIC
BAG
6_X_11
ASSY8
BLANK
LABEL
ASSY5
ATI LOGO
LABEL
ATI_LOGO_LAB EL
ASSY-PCB
ATI LOGO
LABEL
B B
A A
Title
Size Document Number Rev
C
5
4
3
2
Date: Sheet
GIGABYTE
Mechanicals
GV-RX30128D
1
1.1
of
19 20Wednesday, October 20, 2004
5
Model Name: GV-RX30128D
4
3
2
1
D D
C C
B B
Component history
Date
1.1A
1.1B Add packing PVT
1.1B ECN Add 2nd source and Heatsink update
1.1B ECN2 Add 2nd source
Change Item
RELEASE REV1.1A
New BOM
Reason
Circuit or PCB layout history
Date
1.1
Change Item Reason
RELEASE
A A
Title
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet
GIGABYTE
History
GV-RX30128D
1
1.1
of
20 20Wednesday, October 20, 2004
Loading...