Gigabyte GV-R9700 Schematic rev.1.1

5

4

3

2

1

MEMORY CHANNEL A B

D D

DDR 4M X 32 (BGA)

MEMORY TERMINATIONS A B

SHT 13

SHT 11

MEMORY CHANNEL C D

DDR 4M X 32 (BGA)

MEMORY TERMINATIONS C D

SHT 14

SHT 12

VGA1

PRIMARY CRT

LOGIC

SHEET 19

INTEG TMDS

LOGIC

HDH

SHT 23

TVout
CONN

RASA/B#

WEA/B#

ROMCS#

QSA/B[7..0]

CS0A/B#MDA/B[63..0]

DQMA/B[0..7]

CLKA/B01CKEA/B

CLKA/B01#

MEM A B

MEM C D

DAC1

TMDS

MDC/D[63..0] QSC/D[7..0] CS0C/D#

MC/D[14..0]
CASC/D#

WEA/B#RASC/D#

CKEC/D CLKC/D01

R G B HSY VSY DDC1DATA DDC1CLK

TMDS_TX[C,2..0]N TMDS_TX[C,2..0]P HPD, DDC2CLK DDC2DATA

DQMC/D[0..7]

CLKC/D01#

ROM

R300

SHEET 3, 4, 5, 09, 10

AGP

TVO
DVO
VIP

DAC2

DVO, VIP Host, VIP Data

Y/R C/G COMP/B H2SYNC

GPIO

CRT2DDCDATA CRT2DDCCLK V2SYNC

D
E
M
U

SEL

X

SHT 22

TVOUT
LOGIC

SHT 22

SECONDARY

CRT LOGIC

SHT 19

MA/B[14..0]
CASA/B#

C C

STRAPS

SHT 15

BIOS

SHT 17

External
power

B B

POWER

REGULATION

SHT 6,7,8

FAN

SHT 16

VDDC VDDC18 VDD VTT VDDQ
PVDD TPVDD MPVDD
A2VDD Vref

DB15
CONN

SHT 19

DVI-I1
CONN

SHT 18

CBE3..0

GNT#

CLK

SBA[7..0]

AD_STB1#

CPUCLK

TRDY#

INTR

ST2..0

SUSPEND#

AD_STB0

DEVSEL#
SB_STB

AD_STB0#

RESET#

SERR#

SB_STB#

RBF#

Title

Size Document Number Rev
B

3

2

Date: Sheet of

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

1 27Tuesday, March 11, 2003

1

1.1

AD31..0

IRDY#
FRAME#
AGPREF

+5V

+3.3V

A A

5

+12V

AD_STB1

AGP BUS
2X/4X/8X

SHT 2

4

REQ#

PAR

STOP#

8

7

6

5

4

3

2

1

2X/4X/8X AGP BUS

GND_TPVSSGND_MPVSS

GND_PVSS GND_TXVSSR

NOTE: THIS IS A DRAWING. THESE
GROUNDS MUST BE MANUALLY

D D

CONNECTED TO THE GROUND PLANE

AGP_MB_8X_DET#(3)

C C

B B

A A

8

GND_A2VSSN

AGP_GNT#(3)

AGP_DBI_HI(3)

AGP_WBF#(3)

AGP_SBSTB#(3)

AGP_ADSTB1#(3)

AGP_FRAME#(3)

AGP_TRDY#_R(24)

AGP_TRDY#(3,24)

AGP_STOP#(3,24)

AGP_STOP#_R(24)

AGP_PAR(3)

AGP_ADSTB0#(3) AGP_ADSTB0 (3)

AGP_VREFGC(3,24)

AGP_RESET#(3,9,10,23,24)

GND_A2VSSQ

+VDDQ_BUS

+VDDQ_BUS

+VDDQ_BUS

DNI

R854
180R

GND_AVSSQ GND_RSET

GND_R2SETGND_AVSSN

AGP_INTR#(3)

AGP_GC_8X_DET#

R2 0R

AGP_RST#

R4 0R
R5 0R

R7 8K2

R9 8K2

DNI

R13 0R

DNI

R15 0R

R16 8K2

AGP_VREFGC

R22 100R

74ACT08MTC

R25
180R

7

GND_TVVSSN

U2A

3

+5V_BUS

147

+12V_BUS

+3.3V_BUS +3.3V_BUS

A1

TYDET

A2
A3
A4

GND_TY

A5
A6
A7
A8

AGP_ST1

AGP_DBI_HI_R

AGP_SBA1 AGP_SBA0
AGP_SBA3

AGP_SBSTB#_R

AGP_SBA5
AGP_SBA7

AGP_AD30
AGP_AD28

AGP_AD26
AGP_AD24

AGP_ADSTB1#_R
AGP_C/BE#3
AGP_AD22

AGP_AD20
AGP_AD18

AGP_AD16

AGP_TRDY#_R
AGP_STOP#_R

AGP_PAR_R
AGP_AD15
AGP_AD13

AGP_AD11
AGP_AD9

AGP_C/BE#0

AGP_ADSTB0#_R

AGP_AD6
AGP_AD4

AGP_AD2

C5

R19

100nF

10K

1
2

AGP_RST#

DNI

C731
100nF

6

A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66

PWGOOD_VDDC (6)

5

R1 0R

MAGP1

12V
TYPEDET#
GC_DET#/RESEVED
USB­GND
INTA#
RST#
GNT#
VCC3.3
ST1
MB_DET#/RESERVED
DBI_HI/PIPE#
GND
WBF#
SBA1
VCC3.3
SBA3
SB_STB#
GND
SBA5
SBA7
KEY
KEY
KEY
KEY
AD30
AD28
VCC3.3
AD26
AD24
GND
AD_STB1#
C/BE3#
VDDQ
AD22
AD20
GND
AD18
AD16
VDDQ
FRAME#
KEY
KEY
KEY
KEY
TRDY#
STOP#
PME#
GND
PAR
AD15
VDDQ
AD13
AD11
GND
AD9
C/BE0#
VDDQ
AD_STB0#
AD6
GND
AD4
AD2
VDDQ
AD0
VREFGC

UNIVERSAL AGP BUS

GND_TYTYDET

OVRCNT#

5.0V

5.0V

USB+

GND

INTB#

CLK

REQ#

VCC3.3

ST0
ST2

RBF#

GND

DBI_LO/RESERVED

SBA0

VCC3.3

SBA2

SB_STB

GND
SBA4
SBA6

KEY

KEY

KEY

KEY
AD31
AD29

VCC3.3

AD27
AD25

GND

AD_STB1

AD23

VDDQ

AD21
AD19

GND
AD17

C/BE2#

VDDQ
IRDY#

KEY

KEY

KEY

KEY

DEVSEL#

VDDQ

PERR#

GND

SERR#
C/BE1#

VDDQ

AD14
AD12

GND
AD10

AD8

VDDQ

AD_STB0

AD7

GND

AD5

AD3

VDDQ

AD1

VREFCG

SYMBOL LEGEND

DNI

4

AGP_C/BE#[3..0]
AGP_AD[31..0]
AGP_SBA[7..0]
AGP_ST[2..0]

+5V_BUS+VDDQ_BUS

+VDDQ_BUS
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66

#

DO NOT
INSTALL

ACTIVE
LOW

DIGITAL
GROUND

ANALOG
GROUND

AGP_ST0
AGP_ST2

AGP_DBI_LO_R

AGP_SBA2

AGP_SBA4
AGP_SBA6

AGP_AD31
AGP_AD29

AGP_AD27
AGP_AD25

AGP_AD23
AGP_AD21

AGP_AD19
AGP_AD17

AGP_C/BE#2

AGP_C/BE#1
AGP_AD14

AGP_AD12
AGP_AD10

AGP_AD8

AGP_AD7
AGP_AD5

AGP_AD3
AGP_AD1AGP_AD0

AGP_AGPCLK_R

R6 0R

AGP_SBSTB_R

AGP_ADSTB1_R

AGP_DEVSEL#_R

AGP_ADSTB0_R

3

+12V_BUS

AGP_C/BE#[3..0] (3)
AGP_AD[31..0] (3)
AGP_SBA[7..0] (3)
AGP_ST[2..0] (3)

R3 0R

AGP_REQ# (3)

AGP_RBF# (3)
AGP_DBI_LO (3)

R8 0R

R10 0R

R17 0R

C1127

1.0uF

Title

Size Document Number Rev
B

Date: Sheet of

+5V_BUS

C1
100uF 16V

ALU

C2
100uF 16V

AGP_SBSTB (3)

AGP_ADSTB1 (3)

AGP_IRDY# (3)

AGP_DEVSEL#_R (3,24)

AGP_AGPREF (3)

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

2

+3.3V_BUS

AGP_AGPCLK (3,24)

C4
10pF

DNI

C3
100uF 16V

2 27Tuesday, March 11, 2003

1

1.1

8

7

6

5

4

3

2

1

D D

PLACE
CLOSE TO
THE ASIC

1

PIN

C14
100nF

DNI

R895 0R

32

Q19

NDS335N

AGP_C/BE#[3..0](2)

AGP_ST[2..0](2)

AGP_SBA[7..0](2)

AGPREFCG

AGP_C/BE#[3..0]

AGP_ST[2..0]

AGP_SBA[7..0]

AGP_SBSTB(2)
AGP_SBSTB#(2)
AGP_ADSTB0(2)

AGP_ADSTB0#(2)

AGP_ADSTB1(2)

AGP_ADSTB1#(2)

TEST

AGPREFCG

C C

AGP_AGPREF(2)

AGP_RESET#(2,9,10,23,24)

B B

AGP_DEVSEL#_R(2,24)

2N7002E

AGP_AGPCLK(2,24)

AGP_GNT#(2)
AGP_REQ#(2)
AGP_RBF#(2)
AGP_INTR#(2)

AGP_RESET#(2,9,10,23,24)

AGP_WBF#(2)

AGP_FRAME#(2)

AGP_TRDY#(2,24)
AGP_IRDY#(2)

AGP_STOP#(2,24)

AGP_PAR(2)

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

+VDDQ_BUS

1

Q2

AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3

AGP_ST0
AGP_ST1
AGP_ST2

AGP_SBSTB
AGP_SBSTB#
AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#

32

R39 169R

R40 71.5R

AV39
AP38

AU39

AM39

AU37

AP35
AM36
AG35

AE35

AH35

AD35

AB35

AA35
AG34

AL36

AF36

AL37

AA39

AD38

AP39

AN39

AN38

AT37

AT38

AT39

AR39

AP36

AP37

AN36

AN37

AR38

AR37

AE37

AD36

AF39

AE38

U42A

PCICLK
GNT#

REQ#
RBF#
INTA#
RST#
WBF#
FRAME#
TRDY#
IRDY#
DEVSEL#
STOP#
PAR
AGPREF
AGPTEST

CBE#0
CBE#1
CBE#2
CBE#3

ST0
ST1
ST2

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

SB_STBF
SB_STBS
AD_STBF0
AD_STBS0
AD_STBF1
AD_STBS1

R300

PART 1 OF 8

A
G
P
/
P
C
I

I
N
T
E
R
F
A
C
E

AGP 8X

TEST_AGPCLK

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

DBI_HI

DBI_LO

AGP8X_DET#

Y36
Y37
AA36
AA37
AB36
AB37
AC36
AD37
AF37
AG36
AG37
AH36
AH37
AJ36
AK37
AK36
Y39
AB39
AA38
AC39
AB38
AD39
AC38
AE39
AG39
AG38
AH39
AH38
AJ39
AJ38
AK39
AK38

AL38
AL39

AL35

AP33

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21

AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

AGP_DBI_HI
AGP_DBI_LO

AGP_MB_8X_DET#

TEST_AGPCLK

AGP_AD[31..0]

AGP_DBI_HI (2)
AGP_DBI_LO (2)

AGP_MB_8X_DET# (2)

TP1

AGP_AD[31..0] (2)

2N7002E

R23
1K

1

Q1

5

+VDDQ_BUS+3.3V_BUS

32

R21 1.47K

R20

3.32K

R24

1.02K

*

AGP_VREFGC

C6
10nF

4

AGP_VREFGC (2,24)

3

Title

Size Document Number Rev
B

Date: Sheet of

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

2

3 27Tuesday, March 11, 2003

1

1.1

8X_DET#(24)

R18
47K

AGP_MB_8X_DET#(2)

AGP_MB_8X_DET#

+5V_BUS

4
5

U2B

6

74ACT08MTC

TEST

UNIVERSAL VREFGC CIRCUIT (2X, 4X, 8X)

A A

8

7

6

8

APPLICATION

D D

TVout w/ Rage Theatre
ext 24b DDR TMDS
ext 12b DDR TMDS&TVout
24b SDR TMDS

Note1 : PVSS, and MPVSS go to ground plane directly through their own
dedicated via. No connection with other VSS..

Note2 : Separate vias for AVSSQ (A2VSSQ), and AVSSN (A2VSSN) to

C C

ground plane.
Note3 : AVDD/AVSSN power need to use a pair of short traces (20mil at
least) and direct to link to AVDD & AVSSN balls, the ground return point
should be near the ground trace start point.

Note4: Rset resistor ground point should link to AVSSQ trace, or have via
at resistor directly to ground plane.
Note5 : Populate Ra9 and Ra10 only if they are not populated on page
24 or 25 or 31 or 32.

B B

TVOVMODE DVOVMODE

0V
VDDC18 VDDC18
0V
0V 0V

1uF
C29

1uF
C35

CLOCK SOURCE SELECTION

XTAL/OSC.

R300 alone

A A

CRYSTAL

OSC (OPTION 1)
OSC (OPTION 2)

DEFAULT

X

VDDC18

+VDDC_CT

DNI
DNI

+VDDDI

C30
100nF

+VDD2DI

C36
100nF

INSTALL
Ra1,Ra4

Crystal Circuit(27M)
Ra1 = 0R

Oscillator circuit(27M)
Ra4,Ra8

Oscillator circuit(27M)

7

R45 0R
R46 0R

R47 0R
R48 0R

DVO[11..0](23)

C28

22uF 16V

C34

22uF 16V

+VDDDI

+VDD2DI

VID[7..0](15,23)

DVO[11..0]

Ra4,Ra8
Crystal Circuit
Ra1
Crystal Circuit

VID[7..0]

CLK_VIDCLK(23)

DVALID(15,23)
PSYNC(15)

TVO0(22,23)
TVO1(23)
TVO2(22,23)
TVO3(23)
TVO4(23)
TVO5(23)
TVO6(15)
TVO7(15)
TVO8(15)

ROMSCK(15,17)
ROMSO(15,17)
ROMSI(15,17)
ROMCS#(15,17)

TP3
TP4

+VDDC_CT

B7

Bead

+VDDC_CT

B8

Bead

NOT INSTALL
Ra8

Oscillator circuit

CLK_DVOCLK0(23)
CLK_DVOCLK1(23)

6

VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7

R43 1K

TVO0
TVO1
TVO2
TVO3
TVO4
TVO5
TVO6
TVO7
TVO8

DVOCNTL0(23)
DVOCNTL1(23)
DVOCNTL2(23)

TEST_MCLK
TEST_YCLK

TESTEN

TP7
TP27
TP28

DVO0
DVO1
DVO2
DVO3
DVO4
DVO5
DVO6
DVO7
DVO8
DVO9
DVO10
DVO11

ROMCS#

+VDDDI

+VDD2DI

Crystal Circuit

U42B

AW35

VID0

AV35

VID1

AU35

VID2

AT35

VID3

AW34

VID4

AV34

VID5

AU34

VID6

AT34

VID7

AW36

VPCLK0

AU36

DVALID

AV36

PSYNC

AT36

TESTEN

AW21

TVOCLKO

AV21

TVOCLKI

AW19

TVODATA0

AV19

TVODATA1

AU19

TVODATA2

AT19

TVODATA3

AW20

TVODATA4

AV20

TVODATA5

AU20

TVODATA6

AT20

TVODATA7

AU21

TVODATA8

AT21

TVODATA9

AR19

TVOVMODE

AT18

DVOVMODE

AW17

DVOCLK0

AV17

DVOCLK1

AU15

DVOCNTL0

AV15

DVOCNTL1

AW15

DVOCNTL2

AT15

DVODATA0

AR15

DVODATA1

AW16

DVODATA2

AV16

DVODATA3

AU16

DVODATA4

AT16

DVODATA5

AU17

DVODATA6

AT17

DVODATA7

AR17

DVODATA8

AW18

DVODATA9

AV18

DVODATA10

AU18

DVODATA11

AP30

ROMSCK

AP29

ROMSO

AR29

ROMSI

AR30

ROMCS#

F9

TEST_MCLK

G6

TEST_YCLK

AU23

VDD1DI

AU27

VDD2DI

AU24

VSS1DI

AT26

VSS2DI

R300

DNI

C40

10pF

C41

10pF

DNI

Oscillator Circuit

+3.3V_BUS

8

C47

4

100nF

2 1

Y1

VDD
GND

27.000MHz

5

PART 2 OF 8

V

Video Capture & Test

I
D
E
O

&

TMDS / Flat PanelDAC / VGAXTAL

M
U
L
T
I
M
E
D
I

STEREOSYNC

A

TVOut, DVOut & ROM

VIP HostI2C

DNI

R56 0R

DNI

MY1
27 MHZ

DNI

R58 0R

5

OUT

1

E/D

TXCM

TXCP
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P

TPVDD

TPVSS
TXVDDR
TXVDDR
TXVSSR
TXVSSR
TXVSSR

HPD1
HPD2

DDC1DATA

DDC1CLK

AUXWIN

VSYNC

HSYNC

G
B

AVDD

AVDD
AVSSN
AVSSN

AVSSQ

RSET

VIPCLK

VPHCTL

VHAD0
VHAD1

SCL
SDA

XTALOUT

XTALIN

PVDD

PVSS

MPVDD
MPVSS

R2SET

C-R

Y-G
COMP_B
H2SYNC
V2SYNC

DDC2CLK

DAC2 PLL

DDC2DATA

A2VDD

A2VDD
A2VSSN
A2VSSN

A2VDDQ
A2VSSQ

R63 107R

+3.3V_BUS

4

AV29
AW29
AV30
AW30
AV31
AW31
AV32
AW32

AW28
AV28
AT29
AT28
AU28
AU29
AU30

AR31

HPD1 (18)

AR33

HPD2 (23)

AU32

CRT1DDCDATA (20)

AU31

CRT1DDCCLK (20)

TP2

AP31
AT30

VSYNC_DAC1 (20)

AT31

HSYNC_DAC1 (20)

AP32

STEREOSYNC (22)

AW24

R

AW23
AW22

AV23
AV24
AR24
AT24
AU22

R52 499R

AV22
AV33

CLK_VIPCLK (23)

AW33

VPHCTL (23)

AU33

VHAD0 (15,23)

AT33

VHAD1 (23)

AR27
AR28

R300_XOUT

AW38

R300_XIN

AV38
AW37

AV37

+MPVDD

C7

GND_MPVSS

C6
AV25
AW27

AW26
AW25
AR32
AT32

AR34
AR35
AV26
AV27
AT25
AU26

AU25
AT27

DNI

Ra1

R66
150R

TXCM (18)
TXCP (18)
TX0M (18)
TX0P (18)
TX1M (18)
TX1P (18)
TX2M (18)
TX2P (18)

R55 715R

R/C_DAC2 (22)
G/Y_DAC2 (22)
B/COMP_DAC2 (22)

HSYNC_DAC2 (21)

VSYNC_DAC2 (21)
CRT2DDCCLK (21)

CRT2DDCDATA (21)

R57
1M

Ra4

R59 0R

TP34

GND_RSET

C738

SCL
SDA

R300_XOUT

1uF

1uF
C15

C19
22uF 16V

R53

4.7K

GND_R2SET

3

C17
100pF

TXVDDR

+3.3V_BUS+3.3V_BUS

TP35

C20
100pF

R54

4.7K

Ra10Ra9

R300_XIN

R65
0R

Ra8

C16

C18

22uF 16V

100nF

GND_TPVSS

C21
100nF

GND_TXVSSR

GND_AVSSQ

SCL (23)
SDA (23)

1uF
C25

DNI

1uF
C37

+MPVDD

GND_MPVSS

Rk

TP33

+A2VDDQ

C38
100nF

C26
100nF

Ba1

B3

Bead

R44
0R

DNI

Ba2

B4

Bead

C27

22uF 16V

C39

22uF 16V

GND_A2VSSQ

1uF
C42

DNI DNI DNI

2

+VDDC_CT+TPVDD

DNI

+VDDC_CT

Ba4

GND_PVSS

1uF
C31

DNI

Ba5

1uF
C43

B6

200R

B9

Bead

1uF
C44

R_DAC1 (20)
G_DAC1 (20)
B_DAC1 (20)

1uF
C22

DNI

+VDDC_CT+PVDD

DNI

C33
100nF

GND_A2VSSN

+AVDD

C23
C24
100nF

GND_AVSSN

+A2VDD

C32

22uF 16V

+VDDC_CT

+MPVDD +VDDC_CT

C45

C46

100nF

22uF 16V

GND_MPVSS

22uF 16V

Ba6

B10

200R

1

B5

Bead

Ba3

DNI

+VDDC_CT

Title

Size Document Number Rev
B

8

7

6

5

4

3

Date: Sheet of

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

2

4 27Tuesday, March 11, 2003

1

1.1

5

U42G

M34

VDDR1

F33

VDDR1

H33

VDDR1

R6

VDDR1

U34

VDDR1

L34

VDDR1

N34

VDDR1

T33

REGULATOR

+5V_BUS

DNI

B11 200R

D D

DNI

3 2

AS432S

MREG1

R68
47R

R69
681R

1%

1

R70

1.50K

1%

FOR
DVO/TVO(+1.8V)

DNI

+VTVO/DVO

SC431LC5SK-1

DNI

4

NC

1

NC

2

5 3

DNI DNI

REG1

USE ONLY IF TVO OR DVO MODES ARE 1.8V

C C

VTERM2(16)

B B

+VDDTVO

B12 200R

B13 200R

C709

C74

A A

1uF

100nF

+VDDDVO

B14 200R

C75
1uF

C710

100nF

B15 200R

5

+3.3V_BUS

+VDDTVO

+VDDDVO

+VDDQ_BUS

+3.3V_BUS

+VTVO/DVO

DNI

+3.3V_BUS

+VTVO/DVO

DNI

W33
W34

AP12

AN12
AP11
AN13

AP10

AN14

AR25
AN29
AP26
AN28
AN25
AR22
AR23
AP24
AP27

AP19
AN21
AP20

AN17
AN18
AP15
AR16
AP16

AN34
AM34
AN33
AK33

AJ33
AC33
AB33
AA33

AL33

AJ34
AF34
AB34
AH33
AG33
AF33
AE33
AD33

VDDR1

V33

VDDR1
VDDR1
VDDR1

F11

VDDR1

F28

VDDR1

G13

VDDR1

F14

VDDR1

F16

VDDR1

F17

VDDR1

G23

VDDR1

F25

VDDR1

F27

VDDR1

T34

VDDR1

F31

VDDR1

G8

VDDR1

G26

VDDR1

G10

VDDR1

G11

VDDR1

G17

VDDR1

G18

VDDR1

F19

VDDR1

F20

VDDR1

F21

VDDR1

F22

VDDR1

G25

VDDR1

G29

VDDR1

G30

VDDR1

R33

VDDR1

G32

VDDR1

H7

VDDR1

K6

VDDR1

J7

VDDR1

L6

VDDR1

T7

VDDR1

V6

VDDR1

V7

VDDR1

W6

VDDR1

AF7

VDDR1

D6

VDDR1

AA6

VDDR1

AA7

VDDR1

AB7

VDDR1

AB6

VDDR1

AE6

VDDR1

AD6

VDDR1

AG7

VDDR1

AJ6

VDDR1

AP8

VDDR1

AH6

VDDR1
VDDR1

AN6

VDDR1

AL6

VDDR1

AN8

VDDR1
VDDR1
VDDR1
VDDR1

AN9

VDDR1
VDDR1

G14

VDDR1

F12

VDDR1
VDDR1

F32

VDDR1

H34

VDDR1

M5

VDDR1

G33

VDDR1

U7

VDDR1

AM6

VDDR1

AP7

VDDR1

L33

VDDRH

G22

VDDRH

L7

VDDRH

AL7

VDDRH

VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3

VDDR2
VDDR2
VDDR2

VDDR4
VDDR4
VDDR4
VDDR4
VDDR4

VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP

Y33

VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP

R300

PART 7 OF 8

P
O
W
E
R

DISPLAY I/O PWR

4

VDDC18
VDDC18
VDDC18
VDDC18
VDDC18
VDDC18
VDDC18

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

MEMORY I/O

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

CORE

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

AGP / PCI I/O

VDDCI
VDDCI
VDDCI
VDDCI

VSSRH
VSSRH
VSSRH
VSSRH

4

J33
N7
AK7
G20
AN22
AN27
AN32

AV2
AU3
AT4
AR5
AP6
AN7
N13
P13
R13
T13
U13
N14
P14
R14
T14
U14
P15
R15
T15
U15
N16
P16
R16
T16
U16
N17
P17
R17
T17
U17
AC23
AD23
AE23
AF23
AC24
AD24
AE24
AF24
AG24
AC25
AD25
AE25
AF25
AG25
AC26
AD26
AE26
AF26
AG26
AD27
AE27
AF27
AG27
N24
N25
N26
N27
P23
P24
P25
P26
P27
R23
R24
R25
R26
R27
T23
T24
T25
T26
T27
U23
U24
U25
U26
U27
AC14
AC15
AC16
AC17
AD13
AD14
AD15
AD16
AD17
AE13
AE14
AE15
AE16
AE17
AF13
AF14
AF15
AF16
AF17
AG13
AG14
AG15
AG16
AG17
N15

AC27
AG23
AC13
N23

M33
G21
M7
AM7

+VDDC_CT+MVDDQ

+VDDC

3

U42H

AM38
AF38

Y38

AM37

AJ37
AC37
AR36
AE36
AU38
AM35

AJ35
AF35

Y35

AM33

AL34
AN35
AK34
AH34
AE34
AD34
AC34
AA34

Y34
AC35
AK35

AA26

Y26

U37

U33

F29

P35

V35

V13

AU6

N37

T3
B20
AR2
K35

U6
W13
C35
C31
E32
E28
C27
Y13

AA13

E24

G7
E20

AB13

V14
C16
C37
C23
E18
E14

D4
C13

E5

C9
E10

C3

F3

N6

AU13

AR12
AA14
AB14

AA15
AB15

AA16
AB16

AA17
AB17

AA18
AB18

AA19
AB19

AA20
AB20

AA21
AB21

AA22

AG5
AD3
AP5
AH3

N3

W5

Y3
AU9
AM3

K5
AC5

W14
AL5

B2
F35
H38
Y14

F6

V15
W15
Y15

V16
W16
Y16

V17
W17
Y17

V18
W18
Y18

V19
W19
Y19

V20
W20
Y20

V21
W21
Y21

V22
W22
Y22

R300

VTERM1(16)

VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB22

Part 8 of 8

CORE GND

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

N18

P18

VSS

R18

T18

U18

N19

P19

R19

T19

U19

N20

3

P21

VSS

R21

VSS

T21

VSS

U21

VSS

N22

VSS

P22

VSS

R22

VSS

T22

VSS

U22

VSS

V23

VSS

W23

VSS

Y23

VSS

AA23

VSS

AB23

VSS

V24

VSS

W24

VSS

Y24

VSS

AA24

VSS

AB24

VSS

V25

VSS

W25

VSS

Y25

VSS

AA25

VSS

AB25

VSS

V26

VSS

W26

VSS

AB26

VSS

V27

VSS

W27

VSS

Y27

VSS

AA27

VSS

AB27

VSS

AP28

VSS

AR26

VSS

AG22

VSS

AT22

VSS

AP34

VSS

AR20

VSS

AT23

VSS

AR21

VSS

AN31

VSS

AF22

VSS

AN23

VSS

AP25

VSS

AE22

VSS

AN30

VSS

AD22

VSS

AP22

VSS

AP17

VSS

AR18

VSS

AN19

VSS

AP21

VSS

AC22

VSS

AC21

VSS

AN24

VSS

AN16

VSS

AK6

VSS

AN10

VSS

AN15

VSS

AN20

VSS

AP13

VSS

AP14

VSS

AP18

VSS

AP9

VSS

AN11

VSS

AH7

VSS

AJ7

VSS

AP23

VSS

AF6

VSS

AG6

VSS

AD7

VSS

AE7

VSS

Y6

VSS

W7

VSS

M6

VSS

Y7

VSS

R7

VSS

P7

VSS

T6

VSS

K7

VSS

G12

VSS

F10

VSS

G9

VSS

F13

VSS

F15

VSS

G19

VSS

G15

VSS

G16

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

P20

R20

T20

U20

N21

F18
F23
AN26
AC7
F26
G27
G28
F30
G31
J34
K34
K33
J6
N33

P34
V34
R34
P33
AC18
AD18
AE18
AF18
AG18
AG19
AF19
AE19
AD19
AC19
AC20
AD20
AE20
AF20
AG20
AG21
AF21
AE21
AD21
F8
H6
D7
K2

PLACE DIRECTLY
UNDERNEATH
CHANNELS A
AND B

PLACE DIRECTLY
UNDERNEATH
CHANNELS C
AND D

+VDDC_CT

C48

100nF

+VDDC

USE 47uF
TANTALUM
CAPACITOR OR
HIGHER

2

CP1A
10nF

8 1

CP2A
10nF

8 1

+VDDQ_BUS

+3.3V_BUS

+MVDDQ

2

C49

100nF

8 1

7 2

7 2

C64
47uF 16V

CP12A
10nF

CP1B
10nF

CP2B
10nF

C67
22uF 16V

C68
47uF 6.3V

1

C53

5 4

5 4

CP5A
10nF

7 2

C73
10uf

C54

C52

10uf

1uF

C55

CP1D

1uF

10nF

CP3A

CP2D

10nF

10nF

8 1

7 2

CP4C

CP4D

10nF

10nF

6 3

5 4

C61

C62

10uf

10uf

CP5B

CP5C

10nF

10nF

7 2

6 3

CP11A

CP11B

10nF

10nF

8 1

7 2

CP6B

CP6C

10nF

10nF

5 4

6 3

CP8A

CP8B

10nF

10nF

8 1

7 2

CP9B

CP9A

10nF

10nF

7 2

8 1

CP12D

CP13A

10nF

10nF

5 4

8 1

R300 128M DVII VGA2 VO

Diodes Da1
and Da2 are

22uF 16V

needed to
protect ASIC
during power
ramping.

C57

C56

1uF

1uF

CP3B

CP3C

10nF

10nF

6 3

C59

C58

10uf

10uf

C63
10uf

C674

CP5D
10nF

CP11C
10nF

100nF

CP11D
10nF

5 4

CP7A
10nF

8 1

CP8C
10nF

5 4

6 3

CP9C

CP9D

10nF

10nF

6 3

5 4

CP13B

CP13C

10nF

10nF

7 2

6 3

5 4

6 3

CP6D
10nF

GIGABYTE

GV-R9700

1

C50

C51

100nF

100nF

CP1C
10nF

6 3

CP2C
10nF

6 3

CP4B

CP4A

10nF

10nF

7 2

8 1

C60
10uf

PLACE DIRECTLY
UNDERNEATH ASIC
AT THE OPPOSITE
CORNER OF THE
VDDC FEED.

PLACE DIRECTLY UNDERNEATH
VDDP SECTION OF ASIC.

C65
10uf

8 1

C66
1uF

CP6A
10nF

8 1

C70

C71

10uf

10uf

C72
10uf

CP12B

CP12C

10nF

10nF

7 2

6 3

Title

Size Document Number Rev
Custom

Date: Sheet of

5 4

7 2

CP8D
10nF

C673
1uF

CP3D
10nF

CP7B
10nF

C675

5 4

5 27Tuesday, March 11, 2003

+3.3V_BUS

+3.3V_BUS

100nF

6 3

C69
1uF

C707

100nF

CP13D
10nF

CP7C
10nF

Da1

D2

1.8V

2 1

Da2

D3

2.4V

2 1

CP7D
10nF

5 4

C708
100nF

C676
100nF

1.1

8

+5V_BUS

R72

D D

C C

2.2R

R910

100K

+12V_BUS

DNI DNI

R73

2.2R

1uF

C90
1uF

R81 0RC87
R83 0R

R911

100K

R1552 56R

Rb9
Rb10

Rb7 Rb8

DNI

R74
33K

Cb1

DNI

C78

2.2nF

Regulator for VTT Termination

+12V_BUS

+12V_BUS

+5V_BUS

SS_VTT

C102 2.2nF

DNI

DNIDNI

R96
27K

SS_VTT

DNI

R938
0R

BOOT

COMP_VTT

R99 10K

R939
0R

U44

2

Vcc

6

Vc

7

Comp

4

GND

IRU3037ACS

Alternate part
IRU3037CS

DNI

U45

2

OCSET

3

SS

4

COMP

5

FB

6

EN

7

GND

ISL6522CB

B B

C95
100nF

C103
150nF

A A

+PW_VTT

DNI

COMP_VTT

C104 33pF

C105
10nF

R102 15K

C762
100nF

R100 51K
R101 3K

DNI

8

7

CORE REGULATOR VDDC

C77 1nf

U43

DNI

R75
100K

Cb2

DNI

C79
150pF

Alternative 1

HDrv

LDrvSS

Fb

DNI

VCCRT

PVCC

LGATE

PGND

BOOT
UGATE
PHASE

1

VREF

2

+IN2

3

-IN2

4

VCC

5

CL2-

6

CL2+

7

BST2

8

DH2

9

DL2

10 11

PGND BSTC

SC1175CSW

Alternate part IRU3047

R93 10R

5

38

1

141
13
12
11

BOOT

10
9
8

7

20

GND

19

PWRGD

18

-IN1

17

SS/ENA

16

CL1-

15

CL1+

14

BST1

13

DH1

12

DL1

C742

1.0uF

2

4

Alternative 2

6

R873 0R

DNI

C85
1nF

R80 0R

R84 0R

+5V_BUS

B19

***

60R

+PW_VTT

71

8

Q5A

STS8DNF3LL

53

6

Q5B

STS8DNF3LL

6

Rb5

Rb6

C94
470uF 6.3V

L3 3.3uH

1 2

5

PWGOOD_VDDC (2)

DNI

DNI

C100

Cb5

10nF

DNI

R95

Rb14

1.5K

PW1

R82 0R

1 2

MBRS340T3

R94
825R

1%

Rb11

R98

1.10K

1%

C89 10nF

C93
10nF

D25

R97 1.40K

Rb12

*

C10, C11, C12, and C7 are the alternate surface
mount components for C80, C81, C82, C97
respectively.

5

R71 5.1R

FDS6898A

R79 5.1R

FDS6898A

Rb4

C741

R88 5.1R

R91 5.1R

FDS6898A

DNI

+3.3V_BUS

C7
470uF

DUAL FOOTPRINT

DNI

Rb13

C740

1.0uF

2

Q3B

4

R85 100R

1.0uF

2

FDS6898A

Q4B

4

R92 100R

JUb2

JU2

***

+3.3V_BUS

***

71

53

PW1

71

53

C1128
22uF 16V

C97

470uF 10V

B16

60R

PW

8

Q3A

6

R76 51.1R

8

Q4A

6

R89 51.1R

HEADER 1X4 RA

1
2
3
4

+MPVDD

4

C76
470uF 6.3V

L1 1.5uH

1 2

B18

C91
470uF

L2 1.5uH

1 2

C1129

2.2uF

** *****

**

4

60R

Bb1

C98
22uF 16V

R77 150R
C86 2.2uF

Cb4

C88 0.22uF

+5VEXT

R90 150R
C92 2.2uF

+5VEXT

C101
22uF 16V

6.8uF 25V

+VTT

C99
22uF 16V

**

3

2

Layout Guide Lines for switching regulators

1) Feedback trace from the voltage divider resistors to the controller as short as possible.

2) Trace from VIN to Qb1 should be in the same layer, with no via, width no less than 2MM

3) VIN_SOURCE should be a 2-3" snaked trace (with at least 6 bends.) The trace width
should be 2 MM.

4) Components with " ** " should have two vias on each pad

5) Components with " *** " should have three vias on each pad.

6) Connections indicated by bold thick line are high current path. Short, thick traces (at
least 30 mil) should be used.

R78
511R

1%

Rb1

R87

2.43K

***

DNI DNI DNI

C80

* * *

C10

470uF 10V

470uF

***

DUAL FOOTPRINT DUAL FOOTPRINT DUAL FOOTPRINT

1%

C11
470uF

***

C81

470uF 10V

***

C12
470uF

***

C82

470uF 10V

***

Rb2

Rb1

110R 1% DNI

511R 1%

2.43k 1%

INSTALL

Db1, Db2

VTT

Rb11

0.9V

1.25V DNI

0.9V

1.25V

0R

1.07K 1%

576R 1%

8.45K 1%

1.02K 1%

DO NOT INSTALL

Rb7, Rb8, Rb5, Cb1,
Cb2, Db2, Db1

Rb4, Rb6, Rb9, Rb10,

Rb12 Rb13

DNI47.5K 1%

75K 1%

C739

+12VEXT

C737

6.8uF 25V

Part

SC1175
IRU3047

Part

SC1175

IRU3047

Part

IRU3037

IRU3037A
ISL6522CB

VDDC Rb2

1.2V

1.5V

Rb4, Rb6, Rb9, Rb10, Cb4

Rb7, Rb8, Rb5, Cb1, Cb2

1.40V 825R 1% 1.0K 1% DNI

Part

IRU3037
IRU3037A

ISL6522CB

3

INSTALL

Alternative1

Alternative2

Title

Size Document Number Rev
B

Date: Sheet of

R300 128M DVII VGA2 VO

2

DO NOT INSTALL

Cb5, Rb14,
Alternative2

Alternative1

GIGABYTE

GV-R9700

1

+VDDC

**

***

***

C732
470uF

C84
22uF 16V

**

Cb4

DNI

DNI

DNI

6 27Tuesday, March 11, 2003

1

1.1

8

7

6

5

4

3

2

1

MVDDC Switching Regulator for
Memory Core for 128M
configuration

C121 100nF

+PW_VDD

71

8

Q8A

R954
10K

2

53

6

Q8B

4

DNI

R113 10R

5

HDrv

38

LDrvSS

1

Fb

141

VCCRT

13

PVCC

12

LGATE

11

PGND

10

BOOT

9

UGATE

8

PHASE

Alternative 2

C764 10nF

BOOT1

C744
220nF

STS8DNF3LL

STS8DNF3LL

C745
220nF

L5 2.2uH

1 2

Cd1

Rd4

D24

S3AB

B21

60R

C120
180uF 16V

C125
10nF

R115

1.5K

Part

IRU3037

IRU3037A
ISL6522CB

IRU3037A
ISL6522CB

21

+12V_BUS

***

+12VEXT

R114

1%

1.33K

Rd1

R117
499R

1%

Rd2

MVDDC

2.5V

2.5V

2.9V

Rd1

1.21K
1%

2.55K
1%

1.33K1%499R

C8 is an alternate surface

*

mount component for C122.

C746
10uF

DNI

C8

DNI

*

470uF

DUAL FOOTPRINT

**

**

**

** ***

Rd2

1.21K
1%

1.21K
1%

1%

+MVDDC

***

C122

470uF 10V

***

C736
470uF

***

Layout Guide Lines for VDD switching regulator

The same rules apply as for VDDC regulator.

C763
220nF

R937
0R

+12V_BUS

1

2

C734

1uF

DNI

DNI

C747 1nf

COMP_VDD

C128 33pF

C129
10nF

R122 15K

D6

BAT54SLT1

3

R112
0R

BOOT1

C126

2.2nF
R116
27K

DNI

R121 3K

SS_VDD

SS_VDD
COMP_VDD

DNI

U48

2

Vcc

6

Vc

7

Comp

4

GND

IRU3037ACS

Alternate part IRU3037CS

Alternative 1

R118 10K

U49

2

OCSET

3

SS

4

COMP

5

FB

6

EN

7

GND

ISL6522CB

D D

+12V_BUS

+5V_BUS

DNI

R936
0R

C743
220nF

C C

B B

C119
220nF

C127
22nf

R120 51K

+PW_VDD

Part

IRU3037
IRU3037A

INSTALL

Alternative1

ISL6522CB

A A

8

7

6

5

DO NOT INSTALL

Cd1, Rd4, Alternative2

Alternative1Alternative2

4

Title

Size Document Number Rev
B

3

Date: Sheet of

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

2

7 27Tuesday, March 11, 2003

1

1.1

8

7

Regulator for MVDDQ (Memory I/O)

6

+5V_BUS

B22

***

60R

5

4

3

2

1

+1.8V Regulator for VDDC_CT (Core Transform)

D D

+12V_BUS

C133
100nF

C765

C142
150nF

C C

B B

A A

100nF

+PW_VDDQ

DNI

+5V_BUS

8

BOOT2

C141

2.2nF
R128
27K

DNI

R133 51K
R134 3K

DNI

SS_VDDQ

COMP_VDDQ

C143 33pF

DNI

C144
10nF

R135 15K

Part

IRU3037
IRU3037A

ISL6522CB

B26 200R

AS432S

MREG5

3 2

+12V_BUS

+5V_BUS

DNI

R935

R934

0R

0R

Alternative 1

U50

SS_VDDQ
COMP_VDDQ

DNI

R132 10K

2

Vcc

6

Vc

7

Comp

4

GND

IRU3037ACS

Alternate part IRU3037CS

U51

2

OCSET

3

SS

4

COMP

5

FB

6

EN

7

GND

ISL6522CB

HDrv

LDrvSS

Alternative 2

DNI

LGATE

PGND

BOOT
UGATE
PHASE

Fb

VCCRT

PVCC

5

38

1

Alternative1 Ce1, Re8, Alternative2

REGULATOR
FOR
MVDD(+1.8V)

REG5

SC431LC5SK-1

5 3

Alternative1

Alternative2

R142
47R

+MPVDD +TPVDD

R144
681R

1%

1

R146

1.50K

1%

4

NC

1

NC

2

GND_MPVSS GND_TPVSS

7

+PW_VDDQ

71

8

53

6

C130
470uF 6.3V

Q9A

STS8DNF3LL

Q9B

STS8DNF3LL

L6 3.3uH

1 2

Ce1

Re8

C13 is an alternate surface

*

mount component for C136.

R124

4.99K

C140
10nF

1%

Re4

R127

1.5K

DUAL FOOTPRINT

*

C13

DNI

470uF

+MVDDQ

***

***

C136

470uF 10V

C137

C138

**

22uF 16V

**

**

22uF 16V

**

C748

1.0uF

2

4

Re5

R131
2K

1%

141
13
12
11

BOOT2

10
9
8

Part

IRU3037

IRU3037A
ISL6522CB

IRU3037A
ISL6522CB

MVDDQ

2.5V

2.5V

2.8V

DO NOT INSTALLINSTALL

IRU3037

IRU3037A
ISL6522CB

+3.3V_BUS

B27 200R

R143

R145
681R

AS432S

1%

1

R147

MREG6

1.50K

1%

3 2

6

1.8V

1.8V

18R

4

NC

1

NC

2

5

REGULATOR
FOR TPVDD
(+1.8V)

REG6

SC431LC5SK-1

5 3

Re4

1.21K
1%

2.55K
1%

4.99K1%2.0K

681R
1%

1.87K
1%

Re5

1.21K
1%

1.21K
1%

1%

1.5K
1%

1.5K
1%

4

+3.3V_BUS

B23

REG2

60R

LT1117CST

3 2

IN OUT

C135

C134
22uF 16VR123 10R

100nF

1

+3.3V_BUS

CASE

ADJ

USE ONLY IF VDD IS +3.3V

B24
200R

1uF
C145

GND_A2VSSN GND_A2VSSN

+3.3V_BUS

B25 200R

AS432S

MREG4

3 2

Title

Size Document Number Rev
B

3

Date: Sheet of

+VDDC_CT

GND

2

R130

1.33K

1%

R126
562R

1%

+PVDD

VOUT

BYPASS

REGULATOR
FOR PVDD
(+1.8V)

4

NC

1

NC

2

GND_PVSS

C131
100nF

5 3

4

REG3

1

VIN

3

SHDN

2.5V

R139

18R

R140
681R

1%

1

R141

1.50K

1%

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

2

C132
100uF 16V

REGULATOR
FOR
A2VDD(+2.5V)

5

4

C147
470pF

DNI

REG4

SC431LC5SK-1

+A2VDD

1uF
C146

8 27Tuesday, March 11, 2003

1

1.1

5

4

3

2

1

R-300
MEMORY CHANNELS A and B

MAA8X
MAA9X

D D

R883 0R
R884 0R
R880 0R
R879 0R

MAA8

MAA9 MAB9

MAB8X
MAB9X

R885 0R
R886 0R
R882 0R
R881 0R

MAB8

+MVDDQ

R137

75.0R

R138

75.0R

MAB[14..0]

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5

MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

U42D

E25

DQB0

D25

DQB1

C25

DQB2

D24

DQB3

D23

DQB4

E22

DQB5

D22

DQB6

C22

DQB7

B26

DQB8

A26

DQB9

B25

DQB10

A25

DQB11

B23

DQB12

A23

DQB13

B22

DQB14

A22

DQB15

E29

DQB16

D29

DQB17

C29

DQB18

D28

DQB19

D27

DQB20

E26

DQB21

D26

DQB22

C26

DQB23

B31

DQB24

A31

DQB25

B30

DQB26

A30

DQB27

B28

DQB28

A28

DQB29

B27

DQB30

A27

DQB31

B15

DQB32

A15

DQB33

B14

DQB34

A14

DQB35

B12

DQB36

A12

DQB37

B11

DQB38

A11

DQB39

E15

DQB40

D15

DQB41

C15

DQB42

D14

DQB43

D13

DQB44

E12

DQB45

D12

DQB46

C12

DQB47

B10

DQB48

A10

DQB49

B9

DQB50

A9

DQB51

B7

DQB52

A7

DQB53

B6

DQB54

A6

DQB55

E11

DQB56

D11

DQB57

C11

DQB58

D10

DQB59

D9

DQB60

E8

DQB61

D8

DQB62

C8

DQB63

R300

Part 4 of 8

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

MEMORY INTERFACE

B

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8

MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

QSB0

QSB1

QSB2

QSB3

QSB4

QSB5

QSB6

QSB7
RASB#
CASB#

WEB#

CSB#

CKEB
CLKB0

CLKB0#

CLKB1

CLKB1#

DIMB0
DIMB1

MAB0

C18

MAB1

C19

MAB2

E19

MAB3

D20

MAB4

C20

MAB5

D19

MAB6MDB6

D18

MAB7

B18

MAB8X

D17

MAB9X

C21

MAB10

D21

MAB11

E21

MAB12

A18

MAB13

C17

MAB14

E17

DQMB#0

C24

DQMB#1

B24
C28

DQMB#3

B29

DQMB#4

B13

DQMB#5

C14

DQMB#6

B8

DQMB#7DQMA#6

C10

QSB0

E23

QSB1

A24

QSB2

E27

QSB3

A29

QSB4

A13

QSB5

E13

QSB6

A8

QSB7

E9

RASB#

D16

CASB#

A16

WEB#

B16

CSB#

B17

CKEB

A17
A20

B21
B19

A19

R710 0R

A21

R711 0R

E16

MAB8
MAB9

DQMB#[7..0] (11)

DIMB0 (13)
DIMB1 (13)

Only for BGA Elpida memory

QSB[7..0] (11)

RASB# (11,13)
CASB# (11,13)
WEB# (11,13)
CSB# (11,13)

M_CLKB0 (11,13)
M_CLKB#0 (11,13)

M_CLKB1 (11,13)
M_CLKB#1 (11,13)

MAA[14..0](11,13)

MDA[63..0](11)

C C

B B

MAA[14..0]
MDA[63..0]

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

W35
W36
W37

W38
W39

U42C

R35

DQA0

R36

DQA1

R37

DQA2

P36

DQA3

N36

DQA4

M35

DQA5

M36

DQA6

M37

DQA7

P38

DQA8

P39

DQA9

N38

DQA10

N39

DQA11

L38

DQA12

L39

DQA13

K38

DQA14

K39

DQA15
DQA16
DQA17
DQA18

V36

DQA19

U36

DQA20

T35

DQA21

T36

DQA22

T37

DQA23
DQA24
DQA25

V38

DQA26

V39

DQA27

T38

DQA28

T39

DQA29

R38

DQA30

R39

DQA31

E38

DQA32

D39

DQA33

D38

DQA34

C39

DQA35

B38

DQA36

A38

DQA37

B37

DQA38

A37

DQA39

E37

DQA40

D37

DQA41

E36

DQA42

D36

DQA43

D35

DQA44

E34

DQA45

D34

DQA46

C34

DQA47

B36

DQA48

A36

DQA49

B35

DQA50

A35

DQA51

B33

DQA52

A33

DQA53

B32

DQA54

A32

DQA55

E33

DQA56

D33

DQA57

C33

DQA58

D32

DQA59

D31

DQA60

E30

DQA61

D30

DQA62

C30

DQA63

R300

Part 3 of 8

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

MEMORY INTERFACE

A

MAA10
MAA11
MAA12
MAA13
MAA14

RASA#
CASA#

WEA#

CLKA0

CLKA0#

CLKA1

CLKA1#

VREF2

DIMA0
DIMA1

MAA0

H36

MAA0

MAA1

J37

MAA1

MAA2

J35

MAA2

MAA3

K36

MAA3

MAA4

K37

MAA4

MAA5

J36

MAA5

MAA6

H35

MAA6

MAA7

H37

MAA7
MAA8
MAA9

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

CSA#
CKEA

MAA8X

G36

MAA9X

L37

MAA10

L36

MAA11

L35

MAA12

G35

MAA13

G37

MAA14

G34

DQMA#0

P37

DQMA#1 DQMB#2

M38

DQMA#2

V37

DQMA#3

U38

DQMA#4

C38

DQMA#5

C36
B34

DQMA#7

C32

QSA0

N35

QSA1

M39

QSA2

U35

QSA3

U39

QSA4

B39

QSA5

E35

QSA6

A34

QSA7

E31

RASA#

F39

CASA#

E39

WEA#

F36

CSA#

F37

CKEA

F38

H39
J38

G38
G39

G24

R708 0R

J39

R709 0R

F34

MAA8
MAA9

DIMA0 (13)
DIMA1 (13)

Only for BGA Elpida memory

+MVDDQ+MVDDQ

MAB[14..0](11,13)

MDB[63..0](11)

DQMA#[7..0] (11)

QSA[7..0] (11)

RASA# (11,13)
CASA# (11,13)
WEA# (11,13)
CSA# (11,13)

M_CLKA0 (11,13)
M_CLKA#0 (11,13)

M_CLKA1 (11,13)
M_CLKA#1 (11,13)

C148
10uF 16V

B - size

C149
100nF

C727
100nF

53

A A

AGP_RESET#(2,3,10,23,24)

CKEA

AGP_RESET#

5

TC7SZ08FU

1
2

M_CKEA M_CKEB

4

U89

DNI DNI

R855 0R R856 0R

M_CKEA (11,13) M_CKEB (11,13)

4

CKEB

AGP_RESET#

C728
100nF

53

TC7SZ08FU

1
2

4

U90

Title

Size Document Number Rev
B

3

2

Date: Sheet of

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

9 27Tuesday, March 11, 2003

1

1.1

5

(2,3,9,23,24)

4

3

2

1

R-300
MEMORY CHANNELS C and D

MAC8X
MAC9X

D D

R905 0R
R907 0R
R889 0R
R887 0R

MAC8

MAC9

MAD8X MAD8
MAD9X

R906 0R
R908 0R
R890 0R
R888 0R

MAD9

MAC[14..0](12,14)

MDC[63..0](12)

C C

B B

A A

AGP_RESET#

MAC[14..0]

MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8 MAC8X
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63

CKEC

U42E

G4

DQC0

G3

DQC1

H5

DQC2

H4

DQC3

J4

DQC4

J3

DQC5

K4

DQC6

K3

DQC7

D2

DQC8

D1

DQC9

E2

DQC10

E1

DQC11

G2

DQC12

G1

DQC13

H2

DQC14

H1

DQC15

C5

DQC16

C4

DQC17

D5

DQC18

D3

DQC19

E6

DQC20

F5

DQC21

F4

DQC22

G5

DQC23

B5

DQC24

A5

DQC25

B4

DQC26

A4

DQC27

A2

DQC28

B1

DQC29

C2

DQC30

C1

DQC31

P2

DQC32

P1

DQC33

R2

DQC34

R1

DQC35

U2

DQC36

U1

DQC37

V2

DQC38

V1

DQC39

U4

DQC40

U3

DQC41

V5

DQC42

V4

DQC43

W3

DQC44

Y5

DQC45

Y4

DQC46

AA5

DQC47

W2

DQC48

W1

DQC49

Y2

DQC50

Y1

DQC51

AB2

DQC52

AB1

DQC53

AC2

DQC54

AC1

DQC55

AA4

DQC56

AA3

DQC57

AB5

DQC58

AB4

DQC59

AC3

DQC60

AD5

DQC61

AD4

DQC62

AE5

DQC63

R300

53

1
2

C729
100nF

TC7SZ08FU

M_CKEC

4

U91

Part 5 of 8

MEMORY

M_CKEC (12,14) M_CKED (12,14)

INTERFACE C

MAC0
MAC1
MAC2
MAC3
MAC4
MAC5
MAC6
MAC7
MAC8

MAC9
MAC10
MAC11
MAC12
MAC13
MAC14

DQMC#0
DQMC#1
DQMC#2
DQMC#3
DQMC#4
DQMC#5
DQMC#6
DQMC#7

QSC0

QSC1

QSC2

QSC3

QSC4

QSC5

QSC6

QSC7
RASC#
CASC#

WEC#

CSC#

CKEC
CLKC0

CLKC0#

CLKC1

CLKC1#

DIMC0
DIMC1

MAC0

N2

MAC1

N5

MAC2

M2

MAC3

M4

MAC4

M3

MAC5

M1

MAC6

N4

MAC7

N1
P4

MAC9X

L3

MAC10

L4

MAC11

L5

MAC12

P5

MAC13

P3

MAC14

P6

DQMC#0

H3
F2

DQMC#2

E4

DQMC#3

B3

DQMC#4

T2

DQMC#5

V3

DQMC#6

AA2

DQMC#7

AB3

QSC0

J5

QSC1

F1

QSC2

E3

QSC3

A3

QSC4

T1

QSC5

W4

QSC6

AA1

QSC7

AC4

RASC#

R4

CASC#

T4

WEC#

T5

CSC#

R3

CKEC

R5
K1

J2
L2

L1

R712 0R

J1

R713 0R

U5

CKED

AGP_RESET#AGP_RESET#

MAC8
MAC9

DIMC0 (14)

C730
100nF

TC7SZ08FU

M_CKED

4

U92

DIMC1 (14)

Only for Elpida
memory

53

1
2

MAD[14..0](12,14)

MDD[63..0](12)

DQMC#[7..0] (12)

QSC[7..0] (12)

RASC# (12,14)
CASC# (12,14)
WEC# (12,14)
CSC# (12,14)

M_CLKC0 (12,14)
M_CLKC#0 (12,14)

M_CLKC1 (12,14)
M_CLKC#1 (12,14)

MAD[14..0]

MDD0
MDD1
MDD2
MDD3
MDD4
MDD5

MDD7
MDD8
MDD9
MDD10
MDD11
MDD12
MDD13
MDD14
MDD15
MDD16
MDD17
MDD18
MDD19
MDD20
MDD21
MDD22
MDD23
MDD24
MDD25
MDD26
MDD27
MDD28
MDD29
MDD30
MDD31
MDD32
MDD33
MDD34
MDD35
MDD36
MDD37
MDD38
MDD39
MDD40
MDD41
MDD42
MDD43
MDD44
MDD45
MDD46
MDD47
MDD48
MDD49
MDD50
MDD51
MDD52
MDD53
MDD54
MDD55
MDD56
MDD57
MDD58
MDD59
MDD60
MDD61
MDD62
MDD63

MEMVMODE[1:0]

MEMORY IO VOLTAGE

0 1

1 0 1.8V (DDR)

1 1

2.5V (DDR)

3.3V (SDR)

AK5
AK4
AL3
AM5
AM4
AN5

AK2
AK1
AM2
AM1
AN2
AN1
AE4
AE3
AF5
AF4
AG3
AH5
AH4

AD2
AD1
AE2
AE1
AG2
AG1
AH2
AH1
AV5

AW5

AV6

AW6

AV8

AW8

AV9

AW9

AT7
AU7
AR8
AT8

AT9
AR10
AT10
AU10
AV10

AW10

AV11

AW11

AV13

AW13

AV14

AW14

AR11
AT11
AU11
AT12
AT13
AR14
AT14
AU14

U42F

AJ4

DQD0

AJ3

DQD1
DQD2
DQD3
DQD4
DQD5
DQD6
DQD7

AJ2

DQD8

AJ1

DQD9
DQD10
DQD11
DQD12
DQD13
DQD14
DQD15
DQD16
DQD17
DQD18
DQD19
DQD20
DQD21
DQD22

AJ5

DQD23
DQD24
DQD25
DQD26
DQD27
DQD28
DQD29
DQD30
DQD31
DQD32
DQD33
DQD34
DQD35
DQD36
DQD37
DQD38
DQD39
DQD40
DQD41
DQD42
DQD43
DQD44
DQD45
DQD46
DQD47
DQD48
DQD49
DQD50
DQD51
DQD52
DQD53
DQD54
DQD55
DQD56
DQD57
DQD58
DQD59
DQD60
DQD61
DQD62
DQD63

R300

MEMMODE0
MEMMODE1

R167

4.7K

Part 6 of 8

MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MAD8

MAD9
MAD10
MAD11
MAD12
MAD13
MAD14

DQMD#0
DQMD#1
DQMD#2
DQMD#3
DQMD#4
DQMD#5
DQMD#6
DQMD#7

QSD0

QSD1

QSD2

QSD3

QSD4

QSD5

QSD6

QSD7
RASD#
CASD#

WED#

CSD#

MEMORY

INTERFACE D

CKED
CLKD0

CLKD0#

CLKD1

CLKD1#

VREF1

DIMD0
DIMD1

MEMVMODE0
MEMVMODE1

MEMTEST

R164 4.7K
R165 4.7K

R168

4.7K

AT3
AT6
AR4
AP3
AR6
AR3
AT5
AU5
AU2
AP4
AN3
AN4
AU4
AU1
AV4

AK3
AL2
AF3
AF2
AV7
AU8
AV12
AU12

AL4
AL1
AG4
AF1
AW7
AR9
AW12
AR13

AW4
AW2
AW3
AV3
AV1
AR1

AP2
AT2

AT1

AC6

AP1
AR7

E7
F7

F24

MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6MDD6
MAD7

MAD8X

MAD9X
MAD10
MAD11
MAD12
MAD13
MAD14

DQMD#0
DQMD#1
DQMD#2
DQMD#3DQMC#1
DQMD#4
DQMD#5
DQMD#6
DQMD#7

QSD0
QSD1
QSD2
QSD3
QSD4
QSD5
QSD6
QSD7

RASD#

CASD#

WED#

CSD#

CKED

R166

47R

+VDDC_CT+MVDDQ +MVDDQ

MAD8
MAD9

MEMMODE0
MEMMODE1

R714 0R
R715 0R

DQMD#[7..0] (12)

QSD[7..0] (12)

RASD# (12,14)
CASD# (12,14)
WED# (12,14)
CSD# (12,14)

M_CLKD0 (12,14)
M_CLKD#0 (12,14)

M_CLKD1 (12,14)
M_CLKD#1 (12,14)

C150
10uF 16V

Only for Elpida
memory

DIMD0 (14)
DIMD1 (14)

C151
100nF

+MVDDQ

R773

75.0R

R774

75.0R

DNI DNI

R857 0R

5

4

R858 0R

Title

Size Document Number Rev
B

3

2

Date: Sheet of

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

10 27Tuesday, March 11, 2003

1

1.1

8

+MVDDQ

100nF

D D

100nF

+MVDDQ

100nF

C158

100nF

+MVDDQ

100nF

C C

100nF

+MVDDQ

C164

100nF

C166

100nF

+MVDDQ

100nF

B B

100nF

+MVDDQ

100nF

100nF

A A

+MVDDQ

C177

100nF

+VTT

RP1A 56R
RP1B 56R
RP1C 56R

C152

RP1D 56R
RP2A 56R
RP2B 56R
RP2C 56R
RP2D 56R
RP3A 56R
RP3B 56R
RP3C 56R
RP3D 56R
RP4A 56R

C154

RP4B 56R
RP4C 56R
RP4D 56R
RP5A 56R
RP5B 56R
RP5C 56R
RP5D 56R
RP6A 56R

C156

RP6B 56R
RP6C 56R
RP6D 56R
RP7A 56R
RP7B 56R
RP7C 56R
RP7D 56R
RP8A 56R
RP8B 56R
RP8C 56R
RP8D 56R
RP9A 56R

8 1

RP9B 56R

7 2

RP9C 56R

6 3

RP9D 56R

5 4

RP10A 56R

C161

C162

C168

C170

C173

C175

Rf Rff

8 1

RP10B 56R

7 2

RP10C 56R

6 3

RP10D 56R

5 4

RP11A 56R

8 1

RP11B 56R

7 2

RP11C 56R

6 3

RP11D 56R

5 4

RP12A 56R

8 1

RP12B 56R

7 2

RP12C 56R

6 3

RP12D 56R

5 4

RP13A 56R

8 1

RP13B 56R

7 2

RP13C 56R

6 3

RP13D 56R

5 4

RP14A 56R

8 1

RP14B 56R

7 2

RP14C 56R

6 3

RP14D 56R

5 4

RP15A 56R
RP15B 56R
RP15C 56R
RP15D 56R
RP16A 56R

8 1

RP16B 56R

7 2

RP16C 56R

6 3

RP16D 56R

5 4

RP18D 56R
RP19A 56R

8 1

RP18C 56R
RP17C 56R

6 3

RP17B 56R

7 2

RP18B 56R
RP19B 56R

7 2

RP20B 56R
RP20A 56R
RP18A 56R
RP17D 56R

5 4

RP17A 56R

8 1

RP19C 56R

6 3

RP19D 56R

5 4

RP20D 56R
R189 56R

R190 56R
R192 56R
R194 56R
R196 56R
R198 56R
R200 56R
R202 56R

RP23B 56R

7 2

RP23C 56R

6 3

RP20C 56R
RP23A 56R

8 1

R776 56R
R778 56R
R780 56R
R782 56R

R718 56R
R719 56R
R720 56R
R721 56R
R722 56R
R723 56R
R724 56R
R725 56R

8

C179
22uF

MDA0

81

MDA1

72

MDA2

63

MDA3

54

MDA4

81

MDA5

72

MDA6

63

MDA7

54

MDA8

81

MDA9

72

MDA10

63

MDA11

54

MDA12

81

MDA13

72

MDA14

63

MDA15

54

MDA16

81

MDA17

72

MDA18

63

MDA19

54

MDA20

81

MDA21

72

MDA22

63

MDA23

54

MDA24

81

MDA25

72

MDA26

63

MDA27

54

MDA28

81

MDA29

72

MDA30

63

MDA31

54

MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56

81

MDA57

72

MDA58

63

MDA59

54

MDA60
MDA61
MDA62
MDA63
MAA0

54

MAA1
MAA2

63

MAA3
MAA4
MAA5

72

MAA6
MAA7

72

MAA8

81

MAA9

81

MAA10
MAA11
MAA12
MAA13

54

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

WEA#
CASA#
RASA#

63

CSA#
M_CLK0

M_CLK#0
M_CLK1
M_CLK#1

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

7

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

DQMA#[7..0] (9)
WEA# (9,13)
CASA# (9,13)
RASA# (9,13)
CSA# (9,13)

M_CLKA0 (9,13)
M_CLKA#0 (9,13)
M_CLKA1 (9,13)
M_CLKA#1 (9,13)

R208 47R
R210 47R
R212 47R
R214 47R
R216 47R
R218 47R
R220 47R
R222 47R

7

RP25A 47R

8 1

RP25B 47R

7 2

RP25C 47R

6 3

RP25D 47R

5 4

RP26A 47R

8 1

RP26B 47R

7 2

RP26C 47R

6 3

RP26D 47R

5 4

RP27A 47R

8 1

RP27B 47R

7 2

RP27C 47R

6 3

RP27D 47R

5 4

RP28A 47R

8 1

RP28B 47R

7 2

RP28C 47R

6 3

RP28D 47R

5 4

RP29A 47R

8 1

RP29B 47R

7 2

RP29C 47R

6 3

RP29D 47R

5 4

RP30A 47R

8 1

RP30B 47R

7 2

RP30C 47R

6 3

RP30D 47R

5 4

RP31A 47R

8 1

RP31B 47R

7 2

RP31C 47R

6 3

RP31D 47R

5 4

RP32A 47R

8 1

RP32B 47R

7 2

RP32C 47R

6 3

RP32D 47R

5 4

RP33A 47R
RP33B 47R
RP33C 47R
RP33D 47R
RP34A 47R
RP34B 47R
RP34C 47R
RP34D 47R
RP35A 47R
RP35B 47R
RP35C 47R
RP35D 47R
RP36A 47R
RP36B 47R
RP36C 47R
RP36D 47R
RP37A 47R
RP37B 47R
RP37C 47R
RP37D 47R
RP38A 47R
RP38B 47R
RP38C 47R
RP38D 47R
RP39A 47R
RP39B 47R
RP39C 47R
RP39D 47R
RP40A 47R
RP40B 47R
RP40C 47R
RP40D 47R

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
WEA#
RASA#
CASA#

CSA#

M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5
M_QSA6
M_QSA7

6

MDA[63..0]
MAA[14..0]

M_MDA[63..0]

M_MDA0
M_MDA1
M_MDA2
M_MDA3
M_MDA4
M_MDA5
M_MDA6
M_MDA7
M_MDA8
M_MDA9
M_MDA10
M_MDA11
M_MDA12
M_MDA13
M_MDA14
M_MDA15
M_MDA16
M_MDA17
M_MDA18
M_MDA19
M_MDA20
M_MDA21
M_MDA22
M_MDA23
M_MDA24
M_MDA25
M_MDA26
M_MDA27
M_MDA28
M_MDA29
M_MDA30
M_MDA31
M_MDA32

81

M_MDA33

72

M_MDA34

63

M_MDA35

54

M_MDA36

81

M_MDA37

72

M_MDA38

63

M_MDA39

54

M_MDA40

81

M_MDA41

72

M_MDA42

63

M_MDA43

54

M_MDA44

81

M_MDA45

72

M_MDA46

63

M_MDA47

54

M_MDA48

81

M_MDA49

72

M_MDA50

63

M_MDA51

54

M_MDA52

81

M_MDA53

72

M_MDA54

63

M_MDA55

54

M_MDA56

81

M_MDA57

72

M_MDA58

63

M_MDA59

54

M_MDA60

81

M_MDA61

72

M_MDA62

63

M_MDA63

54

+VTT

R832 56R R833 10K

M_QSA[7..0] (13)

Vtt
TERMINATION
for DDR

M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_MAA14

M_WEA# (9,13)
M_RASA# (9,13)
M_CASA# (9,13)

M_CSA# (9,13)

M_CKEA

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

RP23D 56R

5 4

RP66D 56R

5 4

6

MDA[63..0] (9)
MAA[14..0] (9,13)
M_MDA[63..0] (13)

M_MAA[14..0] (9,13)

M_CKEA (9,13)

QSA[7..0] (9)

+MVDDQ

100nF

C155

100nF

+MVDDQ

100nF

C159

100nF

+MVDDQ

100nF

C163

100nF

+MVDDQ

100nF

100nF

+MVDDQ

100nF

C171

100nF

+MVDDQ

100nF

C174

100nF

+MVDDQ

100nF

C153

C157

C160

C165

C167

C169

C172

C176

5

+VTT

RP46A 56R
RP46B 56R
RP46C 56R
RP46D 56R
RP47A 56R
RP47B 56R
RP47C 56R
RP47D 56R
RP48A 56R
RP48B 56R
RP48C 56R
RP48D 56R
RP49A 56R
RP49B 56R
RP49C 56R
RP49D 56R
RP50A 56R

8 1

RP50B 56R

7 2

RP50C 56R

6 3

RP50D 56R

5 4

RP51A 56R

8 1

RP51B 56R

7 2

RP51C 56R

6 3

RP51D 56R

5 4

RP52A 56R
RP52B 56R
RP52C 56R
RP52D 56R
RP53A 56R

8 1

RP53B 56R

7 2

RP53C 56R

6 3

RP53D 56R

5 4

RP54A 56R
RP54B 56R
RP54C 56R
RP54D 56R
RP55A 56R

8 1

RP55B 56R

7 2

RP55C 56R

6 3

RP55D 56R

5 4

RP56A 56R

8 1

RP56B 56R

7 2

RP56C 56R

6 3

RP56D 56R

5 4

RP57A 56R

8 1

RP57B 56R

7 2

RP57C 56R

6 3

RP57D 56R

5 4

RP58A 56R

8 1

RP58B 56R

7 2

RP58C 56R

6 3

RP58D 56R

5 4

RP59A 56R

8 1

RP59B 56R

7 2

RP59C 56R

6 3

RP59D 56R

5 4

RP60A 56R

8 1

RP60B 56R

7 2

RP60C 56R

6 3

RP60D 56R

5 4

RP61A 56R

8 1

RP61B 56R

7 2

RP61C 56R

6 3

RP61D 56R

5 4

RP63D 56R
RP64A 56R

8 1

RP63C 56R
RP62C 56R

6 3

RP62B 56R

7 2

RP63B 56R
RP64B 56R

7 2

RP65B 56R
RP65A 56R
RP63A 56R
RP62D 56R

5 4

RP62A 56R

8 1

RP64C 56R

6 3

RP64D 56R

5 4

RP65D 56R

R191 56R
R193 56R
R195 56R
R197 56R
R199 56R
R201 56R
R203 56R
R204 56R

RP66B 56R

7 2

RP66C 56R

6 3

RP65C 56R
RP66A 56R

8 1

R775 56R
R777 56R
R779 56R
R781 56R

R726 56R
R727 56R
R728 56R
R729 56R
R730 56R
R731 56R
R732 56R
R733 56R

C178
22uF

5

81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54

81
72
63
54

81
72
63
54

54
63

72
72

81
81

54

63

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50

MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14MAA14

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

WEB#
CASB#
RASB#

M_CLKB0
M_CLKB#0
M_CLKB1
M_CLKB#1

QSB0

R207 47R

QSB1

R209 47R

QSB2

R211 47R

QSB3

R213 47R

QSB4

R215 47R

QSB5

R217 47R

QSB6

R219 47R

QSB7

R221 47R

4

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48MDB51
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

WEB#
RASB#
CASB#

CSB#

4

RP75A 47R
RP75B 47R
RP75C 47R
RP75D 47R
RP76A 47R
RP76B 47R
RP76C 47R
RP76D 47R
RP77A 47R
RP77B 47R
RP77C 47R
RP77D 47R
RP78A 47R
RP78B 47R
RP78C 47R
RP78D 47R
RP79A 47R
RP79B 47R
RP79C 47R
RP79D 47R
RP80A 47R
RP80B 47R
RP80C 47R
RP80D 47R
RP81A 47R
RP81B 47R
RP81C 47R
RP81D 47R
RP82A 47R
RP82B 47R
RP82C 47R
RP82D 47R
RP83A 47R
RP83B 47R
RP83C 47R
RP83D 47R
RP84A 47R
RP84B 47R
RP84C 47R
RP84D 47R
RP85A 47R
RP85B 47R
RP85C 47R
RP85D 47R
RP86A 47R
RP86B 47R
RP86C 47R
RP86D 47R
RP87A 47R
RP87B 47R
RP87C 47R
RP87D 47R
RP88A 47R
RP88B 47R
RP88C 47R
RP88D 47R
RP89A 47R
RP89B 47R
RP89C 47R
RP89D 47R
RP90A 47R
RP90B 47R
RP90C 47R
RP90D 47R

+VTT

R830 56R

DQMB#[7..0] (9)
WEB# (9,13)
CASB# (9,13)
RASB# (9,13)
CSB# (9,13)

M_CLKB0 (9,13)
M_CLKB#0 (9,13)
M_CLKB1 (9,13)
M_CLKB#1 (9,13)

M_QSB0
M_QSB1
M_QSB2
M_QSB3
M_QSB4
M_QSB5
M_QSB6
M_QSB7

8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4

M_MDB0
M_MDB1
M_MDB2
M_MDB3
M_MDB4
M_MDB5
M_MDB6
M_MDB7
M_MDB8
M_MDB9
M_MDB10
M_MDB11
M_MDB12
M_MDB13
M_MDB14
M_MDB15
M_MDB16
M_MDB17
M_MDB18
M_MDB19
M_MDB20
M_MDB21
M_MDB22
M_MDB23
M_MDB24
M_MDB25
M_MDB26
M_MDB27
M_MDB28
M_MDB29
M_MDB30
M_MDB31
M_MDB32

81

M_MDB33

72

M_MDB34

63

M_MDB35

54

M_MDB36

81

M_MDB37

72

M_MDB38

63

M_MDB39

54

M_MDB40

81

M_MDB41

72

M_MDB42

63

M_MDB43

54

M_MDB44

81

M_MDB45

72

M_MDB46

63

M_MDB47

54

M_MDB48

81

M_MDB49

72

M_MDB50

63

M_MDB51

54

M_MDB52

81

M_MDB53

72

M_MDB54

63

M_MDB55

54

M_MDB56

81

M_MDB57

72

M_MDB58

63

M_MDB59

54

M_MDB60

81

M_MDB61

72

M_MDB62

63

M_MDB63

54

M_CKEB

R831 10K

3

M_WEB# (9,13)
M_RASB# (9,13)
M_CASB# (9,13)

M_CSB# (9,13)

M_CKEB (9,13)

M_QSB[7..0] (13)

3

MDB[63..0]
MAB[14..0]
M_MDB[63..0]

2

MDB[63..0] (9)
MAB[14..0] (9,13)
M_MDB[63..0] (13)

Differential CLOCK termination

Either Rf or Rf1,Rf2, Rf3, Rf4, Cf1, Cf2 should be
mounted. Differential termination should be placed close
to the memory.

M_CLKA1 M_CLKA0

R826
56R

Cf1 Cf2

C711 10nF

R169

Rf2

56R

M_CLKA#1

Differential CLOCK termination

Either Rff or Rf5,Rf6, Rf7, Rf8, Cf3, Cf4 should be
mounted. Differential termination should be placed close
to the memory.

M_CLKB1

R828

Rf5

56R

Cf3

C713 10nF

R172

Rf6

56R

M_CLKB#1

DQMA#0

R173 47R

DQMA#1

R174 47R

DQMA#2

R175 47R
R176 47R

DQMA#4

R177 47R

DQMA#5

R178 47R

DQMA#6

R179 47R

DQMA#7

R180 47R

DQMB#0

R181 47R

DQMB#1

R182 47R

DQMB#2

R183 47R

DQMB#3

R184 47R

DQMB#4

R185 47R
R186 47R

DQMB#6

R187 47R

DQMB#7

R188 47R

MAB0 M_MAB0
MAB1 M_MAB1
MAB2 M_MAB2
MAB3 M_MAB3
MAB4 M_MAB4
MAB5 M_MAB5
MAB6 M_MAB6
MAB7 M_MAB7
MAB8 M_MAB8
MAB9 M_MAB9
MAB10 M_MAB10
MAB11 M_MAB11
MAB12 M_MAB12
MAB13 M_MAB13
MAB14 M_MAB14

QSB0
QSB1
QSB2
QSB3CSB#
QSB4
QSB5
QSB6
QSB7

Title

Size Document Number Rev
B

Date: Sheet of

R300 128M DVII VGA2 VO

2

Rf3Rf1

Rf4

M_CLKA#0

M_CLKB0

Rf7

Rf8

M_CLKB#0

M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3DQMA#3
M_DQMA#4
M_DQMA#5
M_DQMA#6
M_DQMA#7

M_DQMB#0
M_DQMB#1
M_DQMB#2
M_DQMB#3
M_DQMB#4
M_DQMB#5DQMB#5
M_DQMB#6
M_DQMB#7

QSB[7..0] (9)

GIGABYTE

GV-R9700

1

R827
56R

C712 10nF

R170
56R

R829
56R

Cf4

C714 10nF

R171
56R

M_MAB[14..0] (9,13)

11 27Tuesday, March 11, 2003

1

M_DQMA#[7..0] (13)

M_DQMB#[7..0] (13)

1.1

8

+MVDDQ

100nF

D D

100nF

+MVDDQ

100nF

C186

100nF

+MVDDQ

100nF

C C

100nF

+MVDDQ

100nF

100nF

+MVDDQ

B B

100nF

C199

100nF

+MVDDQ

100nF

C203

100nF

A A

+MVDDQ

C205

100nF

+VTT

RP91A 56R
RP91B 56R
RP91C 56R
RP91D 56R

C180

RP92A 56R
RP92B 56R
RP92C 56R
RP92D 56R
RP93A 56R
RP93B 56R
RP93C 56R
RP93D 56R

C182

RP94A 56R
RP94B 56R
RP94C 56R
RP94D 56R
RP95A 56R
RP95B 56R
RP95C 56R
RP95D 56R

C184

RP96A 56R

8 1

RP96B 56R

7 2

RP96C 56R

6 3

RP96D 56R

5 4

RP97A 56R
RP97B 56R
RP97C 56R
RP97D 56R
RP98A 56R
RP98B 56R
RP98C 56R
RP98D 56R
RP99A 56R

8 1

RP99B 56R

7 2

RP99C 56R

6 3

RP99D 56R

C189

C190

C192

C194

C197

C200

Rp Rpp

5 4

RP100A 56R
RP100B 56R
RP100C 56R
RP100D 56R
RP101A 56R

8 1

RP101B 56R

7 2

RP101C 56R

6 3

RP101D 56R

5 4

RP102A 56R

8 1

RP102B 56R

7 2

RP102C 56R

6 3

RP102D 56R

5 4

RP103A 56R
RP103B 56R
RP103C 56R
RP103D 56R
RP104A 56R
RP104B 56R
RP104C 56R
RP104D 56R
RP105A 56R
RP105B 56R
RP105C 56R
RP105D 56R
RP106A 56R
RP106B 56R
RP106C 56R
RP106D 56R

RP108D 56R
RP109A 56R

8 1

RP108C 56R
RP107C 56R

6 3

RP107B 56R

7 2

RP108B 56R
RP109B 56R

7 2

RP110B 56R
RP110A 56R
RP108A 56R
RP107D 56R

5 4

RP107A 56R

8 1

RP109C 56R

6 3

RP109D 56R

5 4

RP110D 56R

R244
R246 56R
R248
R250 56R
R252 56R
R254 56R
R256
R258

RP132B 56R

7 2

RP132C 56R

6 3

RP110C 56R
RP132A 56R

8 1

R784 56R
R786 56R
R788 56R
R790 56R

R734 56R
R735 56R
R736 56R
R737 56R
R738 56R
R739 56R
R740 56R
R741 56R

8

MDC0

81

MDC1

72

MDC2

63

MDC3

54

MDC4

81

MDC5

72

MDC6

63

MDC7

54

MDC8

81

MDC9

72

MDC10

63

MDC11

54

MDC12

81

MDC13

72

MDC14

63

MDC15

54

MDC16

81

MDC17

72

MDC18

63

MDC19

54

MDC20
MDC21
MDC22
MDC23
MDC24

81

MDC25

72

MDC26

63

MDC27

54

MDC28

81

MDC29

72

MDC30

63

MDC31

54

MDC32
MDC33
MDC34
MDC35
MDC36

81

MDC37

72

MDC38

63

MDC39

54

MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48

81

MDC49

72

MDC50

63

MDC51

54

MDC52

81

MDC53

72

MDC54

63

MDC55

54

MDC56

81

MDC57

72

MDC58

63

MDC59

54

MDC60

81

MDC61 DQMC#7

72

MDC62

63

MDC63

54

MAC0

54

MAC1
MAC2

63

MAC3
MAC4
MAC5

72

MAC6
MAC7

72

MAC8

81

MAC9

81

MAC10
MAC11
MAC12
MAC13

54

56R

DQMC#0
DQMC#1
DQMC#2

56R

DQMC#3
DQMC#4
DQMC#5
DQMC#6

56R

DQMC#7

56R

WEC#
CASC#
RASC#

63

CSC#
M_CLKC0

M_CLKC#0
M_CLKC1
M_CLKC#1

QSC0

R262 47R

QSC1

R264 47R

QSC2

R266 47R

QSC3

R268 47R

QSC4

R270 47R

QSC5

R272 47R

QSC6

R274 47R

QSC7

C207
22uF

R276 47R

7

MDC0

RP111A 47R

MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63

DQMC#[7..0] (10)
WEC# (10,14)
CASC# (10,14)
RASC# (10,14)
CSC# (10,14)

M_CLKC0 (10,14)
M_CLKC#0 (10,14)
M_CLKC1 (10,14)
M_CLKC#1 (10,14)

8 1

RP111B 47R

7 2

RP111C 47R

6 3

RP111D 47R

5 4

RP112A 47R

8 1

RP112B 47R

7 2

RP112C 47R

6 3

RP112D 47R

5 4

RP113A 47R

8 1

RP113B 47R

7 2

RP113C 47R

6 3

RP113D 47R

5 4

RP114A 47R

8 1

RP114B 47R

7 2

RP114C 47R

6 3

RP114D 47R

5 4

RP115A 47R

8 1

RP115B 47R

7 2

RP115C 47R

6 3

RP115D 47R

5 4

RP116A 47R

8 1

RP116B 47R

7 2

RP116C 47R

6 3

RP116D 47R

5 4

RP117A 47R

8 1

RP117B 47R

7 2

RP117C 47R

6 3

RP117D 47R

5 4

RP118A 47R

8 1

RP118B 47R

7 2

RP118C 47R

6 3

RP118D 47R

5 4

RP119A 47R
RP119B 47R
RP119C 47R
RP119D 47R
RP120A 47R
RP120B 47R
RP120C 47R
RP120D 47R
RP121A 47R
RP121B 47R
RP121C 47R
RP121D 47R
RP122A 47R
RP122B 47R
RP122C 47R
RP122D 47R
RP123A 47R
RP123B 47R
RP123C 47R
RP123D 47R
RP124A 47R
RP124B 47R
RP124C 47R
RP124D 47R
RP125A 47R
RP125B 47R
RP125C 47R
RP125D 47R
RP126A 47R
RP126B 47R
RP126C 47R
RP126D 47R

MAC0 M_MAC0
MAC1 M_MAC1
MAC2 M_MAC2
MAC3 M_MAC3
MAC4 M_MAC4
MAC5 M_MAC5
MAC6 M_MAC6
MAC7 M_MAC7
MAC8 M_MAC8
MAC9 M_MAC9 MAD3 M_MAD3
MAC10 M_MAC10
MAC11 M_MAC11
MAC12 M_MAC12
MAC13 M_MAC13
MAC14 M_MAC14
WEC#
RASC#
CASC#
CSC#

+VTT

M_QSC0
M_QSC1
M_QSC2
M_QSC3
M_QSC4
M_QSC5
M_QSC6
M_QSC7

7

M_MDC0
M_MDC1
M_MDC2
M_MDC3
M_MDC4
M_MDC5
M_MDC6
M_MDC7
M_MDC8
M_MDC9
M_MDC10
M_MDC11
M_MDC12
M_MDC13
M_MDC14
M_MDC15
M_MDC16
M_MDC17
M_MDC18
M_MDC19
M_MDC20
M_MDC21
M_MDC22
M_MDC23
M_MDC24
M_MDC25
M_MDC26
M_MDC27
M_MDC28
M_MDC29
M_MDC30
M_MDC31
M_MDC32

81

M_MDC33

72

M_MDC34

63

M_MDC35

54

M_MDC36

81

M_MDC37

72

M_MDC38

63

M_MDC39

54

M_MDC40

81

M_MDC41

72

M_MDC42

63

M_MDC43

54

M_MDC44

81

M_MDC45

72

M_MDC46

63

M_MDC47

54

M_MDC48

81

M_MDC49

72

M_MDC50

63

M_MDC51

54

M_MDC52

81

M_MDC53

72

M_MDC54

63

M_MDC55

54

M_MDC56

81

M_MDC57

72

M_MDC58

63

M_MDC59

54

M_MDC60

81

M_MDC61

72

M_MDC62

63

M_MDC63

54

R840 56R

M_QSC[7..0] (14)

6

MDC[63..0]
MAC[14..0]
M_MDC[63..0]

Vtt
TERMINATION
for DDR

M_MAC[14..0] (10,14)

M_WEC# (10,14)
M_RASC# (10,14)
M_CASC# (10,14)
M_CSC# (10,14)

M_CKEC

R841 10K

QSC0
QSC1
QSC2
QSC3
QSC4
QSC5
QSC6
QSC7

RP132D 56R

5 4

RP156D 56R

5 4

6

+MVDDQ

100nF

C183

100nF

+MVDDQ

100nF

C187

100nF

+MVDDQ

100nF

C191

100nF

+MVDDQ

100nF

C195

100nF

+MVDDQ

100nF

C198

100nF

+MVDDQ

100nF

C202

100nF

+MVDDQ

100nF

5

C181

C185

C188

C193

C196

C201

C204

5

+VTT

RP136A 56R
RP136B 56R
RP136C 56R
RP136D 56R
RP137A 56R
RP137B 56R
RP137C 56R
RP137D 56R
RP138A 56R
RP138B 56R
RP138C 56R
RP138D 56R
RP139A 56R
RP139B 56R
RP139C 56R
RP139D 56R
RP140A 56R
RP140B 56R
RP140C 56R
RP140D 56R
RP141A 56R
RP141B 56R
RP141C 56R
RP141D 56R
RP142A 56R
RP142B 56R
RP142C 56R
RP142D 56R
RP143A 56R
RP143B 56R
RP143C 56R
RP143D 56R
RP144A 56R
RP144B 56R
RP144C 56R
RP144D 56R
RP145A 56R
RP145B 56R
RP145C 56R
RP145D 56R
RP146A 56R
RP146B 56R
RP146C 56R
RP146D 56R
RP147A 56R
RP147B 56R
RP147C 56R
RP147D 56R
RP148A 56R
RP148B 56R
RP148C 56R
RP148D 56R
RP149A 56R
RP149B 56R
RP149C 56R
RP149D 56R
RP150A 56R
RP150B 56R
RP150C 56R
RP150D 56R
RP151A 56R
RP151B 56R
RP151C 56R
RP151D 56R

RP153D 56R
RP154A 56R
RP153C 56R
RP152C 56R
RP152B 56R
RP153B 56R
RP154B 56R
RP155B 56R
RP155A 56R
RP153A 56R
RP152D 56R
RP152A 56R
RP154C 56R
RP154D 56R
RP155D 56R

R243 56R
R245 56R
R247 56R
R249 56R
R251 56R
R253 56R
R255 56R
R257 56R

RP156B 56R
RP156C 56R
RP155C 56R
RP156A 56R

R783 56R
R785 56R
R787 56R
R789 56R

R742 56R
R743 56R
R744 56R
R745 56R
R746 56R
R747 56R
R748 56R
R749 56R

8 1
7 2
6 3
5 4

8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4

8 1
7 2
6 3
5 4

8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4

8 1
6 3

7 2
7 2

5 4
8 1
6 3
5 4

7 2
6 3

8 1

C206
22uF

81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54

81
72
63
54
81
72
63
54

81
72
63
54

81
72
63
54
81
72
63
54

54
63

72
72

81
81

54

63

MDD0
MDD1
MDD2
MDD3
MDD4
MDD5
MDD6
MDD7
MDD8
MDD9
MDD10
MDD11
MDD12
MDD13
MDD14
MDD15
MDD16
MDD17
MDD18
MDD19
MDD20
MDD21
MDD22
MDD23
MDD24
MDD25
MDD26
MDD27
MDD28
MDD29
MDD30
MDD31
MDD32

MDD34
MDD35
MDD36
MDD37
MDD38
MDD39
MDD40
MDD41
MDD42
MDD43
MDD44
MDD45
MDD46
MDD47
MDD48
MDD49
MDD50
MDD51
MDD52
MDD53
MDD54
MDD55
MDD56
MDD57
MDD58

MDD60
MDD61
MDD62
MDD63

MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MAD8
MAD9
MAD10
MAD11
MAD12
MAD13
MAD14

DQMD#0
DQMD#1
DQMD#2
DQMD#3
DQMD#4
DQMD#5
DQMD#6
DQMD#7

WED#
CASD#
RASD#
CSD#

M_CLKD0
M_CLKD#0
M_CLKD1
M_CLKD#1

QSD0
QSD1
QSD2
QSD3
QSD4
QSD5
QSD6
QSD7

MDC[63..0] (10)
MAC[14..0] (10,14)
M_MDC[63..0] (14) M_MDD[63..0] (14)

M_CKEC (10,14)

QSC[7..0] (10)

4

R261 47R
R263 47R
R265 47R
R267 47R
R269 47R
R271 47R
R273 47R
R275 47R

4

MDD0

RP160A 47R

MDD1

RP160B 47R

MDD2

RP160C 47R

MDD3

RP160D 47R

MDD4

RP161A 47R

MDD5

RP161B 47R

MDD6

RP161C 47R

MDD7

RP161D 47R

MDD8

RP162A 47R

MDD9

RP162B 47R

MDD10

RP162C 47R

MDD11

RP162D 47R

MDD12

RP163A 47R

MDD13

RP163B 47R

MDD14

RP163C 47R

MDD15

RP163D 47R

MDD16

RP164A 47R

MDD17

RP164B 47R

MDD18

RP164C 47R

MDD19

RP164D 47R

MDD20

RP165A 47R

MDD21

RP165B 47R

MDD22

RP165C 47R

MDD23

RP165D 47R

MDD24

RP166A 47R

MDD25

RP166B 47R

MDD26

RP166C 47R

MDD27

RP166D 47R

MDD28

RP167A 47R

MDD29

RP167B 47R

MDD30MDD33

RP167C 47R

MDD31

RP167D 47R

MDD32

RP168A 47R

MDD33

RP168B 47R

MDD34

RP168C 47R

MDD35

RP168D 47R

MDD36

RP169A 47R

MDD37

RP169B 47R

MDD38

RP169C 47R

MDD39

RP169D 47R

MDD40

RP170A 47R

MDD41

RP170B 47R

MDD42

RP170C 47R

MDD43

RP170D 47R

MDD44

RP171A 47R

MDD45

RP171B 47R

MDD46

RP171C 47R

MDD47

RP171D 47R

MDD48

RP172A 47R

MDD49

RP172B 47R

MDD50

RP172C 47R

MDD51

RP172D 47R

MDD52

RP173A 47R

MDD53

RP173B 47R

MDD54

RP173C 47R

MDD55

RP173D 47R

MDD56MDD59

RP174A 47R

MDD57

RP174B 47R

MDD58

RP174C 47R

MDD59

RP174D 47R

MDD60

RP175A 47R

MDD61

RP175B 47R

MDD62

RP175C 47R

MDD63

RP175D 47R

WED#
RASD#
CASD#

CSD#

+VTT

R838 56R

DQMD#[7..0] (10)
WED# (10,14)

CASD# (10,14)
RASD# (10,14)
CSD# (10,14)

M_CLKD0 (10,14)
M_CLKD#0 (10,14)
M_CLKD1 (10,14)
M_CLKD#1 (10,14)

M_QSD0
M_QSD1
M_QSD2
M_QSD3
M_QSD4
M_QSD5
M_QSD6
M_QSD7

8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4

81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54

M_CKEDMAC14

3

M_MDD0
M_MDD1
M_MDD2
M_MDD3
M_MDD4
M_MDD5
M_MDD6
M_MDD7
M_MDD8
M_MDD9
M_MDD10
M_MDD11
M_MDD12
M_MDD13
M_MDD14
M_MDD15
M_MDD16
M_MDD17
M_MDD18
M_MDD19
M_MDD20
M_MDD21
M_MDD22
M_MDD23
M_MDD24
M_MDD25
M_MDD26
M_MDD27
M_MDD28
M_MDD29
M_MDD30
M_MDD31
M_MDD32
M_MDD33
M_MDD34
M_MDD35
M_MDD36
M_MDD37
M_MDD38
M_MDD39
M_MDD40
M_MDD41
M_MDD42
M_MDD43
M_MDD44
M_MDD45
M_MDD46
M_MDD47
M_MDD48
M_MDD49
M_MDD50
M_MDD51
M_MDD52
M_MDD53
M_MDD54
M_MDD55
M_MDD56
M_MDD57
M_MDD58
M_MDD59
M_MDD60
M_MDD61
M_MDD62
M_MDD63

M_WED# (10,14)
M_RASD# (10,14)
M_CASD# (10,14)

M_CSD# (10,14)

R839 10K

M_QSD[7..0] (14)

3

MDD[63..0]
MAD[14..0]

M_MDD[63..0]

Either Rp or Rg1,Rg2, Rg3, Rg4, Cg1, Cg2 should be
mounted. Differential termination should be placed close
to the memory.

M_CLKC1 M_CLKC0

Rg1

Rg2

M_CLKC#1

Either Rpp or Rg5,Rg6, Rg7, Rg8, Cg3, Cg4 should be
mounted. Differential termination should be placed close
to the memory.

M_CLKD1 M_CLKD0

Rg5

Rg6

M_CLKD#1

DQMC#0
DQMC#1
DQMC#2
DQMC#3
DQMC#4
DQMC#5
DQMC#6

DQMD#0
DQMD#1
DQMD#2
DQMD#3
DQMD#4
DQMD#5
DQMD#6
DQMD#7

M_CKED (10,14)

Title

Size Document Number Rev
B

Date: Sheet of

MAD0 M_MAD0
MAD1 M_MAD1
MAD2 M_MAD2

MAD4 M_MAD4
MAD5 M_MAD5
MAD6 M_MAD6
MAD7 M_MAD7
MAD8 M_MAD8
MAD9 M_MAD9
MAD10 M_MAD10
MAD11 M_MAD11
MAD12 M_MAD12
MAD13 M_MAD13
MAD14 M_MAD14

2

MDD[63..0] (10)
MAD[14..0] (10,14)

Differential CLOCK termination

R834
56R

Cg1 Cg2

C715 10nF

R224
56R

Differential CLOCK termination

R836
56R

Cg3

C717 10nF

R226
56R

R227 47R
R228 47R
R229 47R
R230 47R
R231 47R
R232 47R
R233 47R
R234 47R

R235 47R
R236 47R
R237 47R
R238 47R
R239 47R
R240 47R
R241 47R
R242 47R

QSD0
QSD1
QSD2
QSD3
QSD4
QSD5
QSD6
QSD7

2

1

R835

Rg3

56R

C716 10nF

R223

Rg4

Rg7

Rg8

M_DQMC#0
M_DQMC#1
M_DQMC#2
M_DQMC#3
M_DQMC#4
M_DQMC#5
M_DQMC#6
M_DQMC#7

M_DQMD#0
M_DQMD#1
M_DQMD#2
M_DQMD#3
M_DQMD#4
M_DQMD#5
M_DQMD#6
M_DQMD#7

56R

R837
56R

Cg4

C718 10nF

R225
56R

M_DQMC#[7..0] (14)

M_DQMD#[7..0] (14)

M_MAD[14..0] (10,14)

M_CLKC#0

M_CLKD#0

QSD[7..0] (10)

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

12 27Tuesday, March 11, 2003

1

1.1

8

M_DQMA#[7..0](11)

M_DQMA#0
M_DQMA#1
M_DQMA#2
M_DQMA#3
M_DQMA#4 M_MAA12

M_DQMA#6

M_DQMB#[7..0](11)

D D

M_QSA[7..0](11)

M_QSB[7..0](11)

C C

Only for
BGA
Elpida
memory

M_MAA[14..0](9,11)

B B

M_MAB[14..0](9,11)

+MVDDQ +MVDDC

A A

C216

C217

100nF

100nF

M_DQMA#7

M_DQMB#0
M_DQMB#1
M_DQMB#2
M_DQMB#3
M_DQMB#4
M_DQMB#5
M_DQMB#6
M_DQMB#7

M_QSA0
M_QSA1
M_QSA2
M_QSA3
M_QSA4
M_QSA5

+MVDDQ

M_QSA6
M_QSA7

M_QSB0
M_QSB1
M_QSB2
M_QSB3
M_QSB4
M_QSB5
M_QSB6
M_QSB7

C218
100nF

M_CKEA
M_WEA#
M_CASA#
M_RASA#
M_CSA#
M_CLKA0
M_CLKA1
M_CLKA#0
M_CLKA#1
M_CKEB
M_WEB#
M_CASB#
M_RASB#
M_CSB#
M_CLKB0
M_CLKB1
M_CLKB#0
M_CLKB#1

DIMA0
DIMA1
DIMB0
DIMB1

M_MAA0
M_MAA1
M_MAA2
M_MAA3
M_MAA4
M_MAA5
M_MAA6
M_MAA7
M_MAA8
M_MAA9
M_MAA10
M_MAA11
M_MAA12
M_MAA13
M_MAA14

M_MAB0
M_MAB1
M_MAB2
M_MAB3
M_MAB4
M_MAB5
M_MAB6
M_MAB7
M_MAB8
M_MAB9
M_MAB10
M_MAB11
M_MAB12
M_MAB13
M_MAB14

C219
100nF

M_CKEA(9,11)
M_WEA#(9,11)
M_CASA#(9,11)
M_RASA#(9,11)

M_CSA#(9,11)
M_CLKA0(9,11)
M_CLKA1(9,11)

M_CLKA#0(9,11)
M_CLKA#1(9,11)

M_CKEB(9,11)

M_WEB#(9,11)
M_CASB#(9,11)
M_RASB#(9,11)

M_CSB#(9,11)
M_CLKB0(9,11)
M_CLKB1(9,11)

M_CLKB#0(9,11)
M_CLKB#1(9,11)

DIMA0(9)
DIMA1(9)
DIMB0(9)
DIMB1(9)

+MVDDQ +MVDDC

C239

C237
100nF

C238

100nF

100nF

8

C236
100nF

C220
100nF

C240
100nF

R281

4.99K

R277

4.99K

M_MAA13M_DQMA#5
M_MAA11

M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0

M_MAA14

C208

100nF

+MVDDQ

+MVDDQ

7

DIMA0

M_CLKA#0
M_CSA#
M_RASA#
M_CASA#
M_WEA#
M_DQMA#1
M_DQMA#2
M_DQMA#0
M_DQMA#3
M_CLKA0
M_CKEA

M_QSA1
M_QSA2
M_QSA0
M_QSA3

M_MDA[63..0](11)
M_MDB[63..0](11)

C221
100nF

C241
100nF

7

M10

G10
K11
K12

M12

G11

M11

G12

C222
100nF

C242
100nF

6

5

4

3

2

1

64MBytes DDR 128Mbit 1Mx32x4 uBGA Channels A and B - rank 1

U52

M3

BA0

L4

BA1

L6

A11

K5

A10

L7

A9
A8/AP

M9

A7

M8

A6

L8

A5

M7

A4

M6

A3

L5

A2

M5

A1

M4

A0

B3

NC

B10

NC

G3

NC
NC
NC
NC

L2

NC

L3

NC

M2

NC

L12

MCL
VREF

L9

RFU

K8

RFU

L11

CLK

M1

CS

L1

RAS

K1

CAS

K2

WE

A11

DM3

G2

DM2
DM1

A2

DM0

L10

CLK

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CKE

VSSQ

A12

DQS3

G1

DQS2
DQS1

A1

DQS0

E5

TH GND

E6

TH GND

E7

TH GND

E8

TH GND

F5

TH GND

F6

TH GND

F7

TH GND

F8

TH GND

G5

TH GND

G6

TH GND

G7

TH GND

G8

TH GND

H5

TH GND

H6

TH GND

H7

TH GND

H8

TH GND

1Mx32x4

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M_MDA8

A7

M_MDA9

B8

M_MDA10

A8

M_MDA11

A9

M_MDA12

B12

M_MDA13

C11

M_MDA14

C12

M_MDA15

D12

M_MDA16

J2

M_MDA17

J1

M_MDA18

H1

M_MDA19

H2

M_MDA20

F1

M_MDA21

F2

M_MDA22

E1

M_MDA23

E2

M_MDA0

E11

M_MDA1

E12

M_MDA2

F11

M_MDA3

F12

M_MDA4

H11

M_MDA5

H12

M_MDA6

J11

M_MDA7

J12

M_MDA24

D1

M_MDA25

C1

M_MDA26

C2

M_MDA27

B1

M_MDA28

A4

M_MDA29

A5

M_MDA30

B5

M_MDA31

A6
B2

B4

+MVDDQ

B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6
C7

+MVDDC

D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8

+MVDDQ

C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9

+MVDDC

J4
J9

D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

C679
10uF

C683
10uF

R282

4.99K

M_MAA12
M_MAA13

M_MAA11
M_MAA10
M_MAA9
M_MAA8
M_MAA7
M_MAA6
M_MAA5
M_MAA4
M_MAA3
M_MAA2
M_MAA1
M_MAA0

R278

4.99K

C214
10uF

M_MAA14

C209

100nF

M_CLKA#1
M_CSA#
M_RASA#
M_CASA#
M_WEA#
M_DQMA#5
M_DQMA#6
M_DQMA#4
M_DQMA#7
M_CLKA1
M_CKEA

M_QSA5
M_QSA6
M_QSA4
M_QSA7

U53

M3

BA0

L4

BA1

L6

A11

K5

A10

L7

A9

M10

A8/AP

M9

A7

M8

A6

L8

A5

M7

A4

M6

A3

L5

A2

M5

A1

M4

A0

B3

NC

B10

NC

G3

NC

G10

NC

K11

NC

K12

NC

L2

NC

L3

NC

M2

NC

L12

MCL

M12

VREF

L9

RFU

K8

RFU

L11

CLK

M1

CS

L1

RAS

K1

CAS

K2

WE

A11

DM3

G2

DM2

G11

DM1

A2

DM0

L10

CLK

M11

CKE

A12

DQS3

G1

DQS2

G12

DQS1

A1

DQS0

E5

TH GND

E6

TH GND

E7

TH GND

E8

TH GND

F5

TH GND

F6

TH GND

F7

TH GND

F8

TH GND

G5

TH GND

G6

TH GND

G7

TH GND

G8

TH GND

H5

TH GND

H6

TH GND

H7

TH GND

H8

TH GND

1Mx32x4

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M_MDA47

A7

M_MDA46

B8

M_MDA45

A8

M_MDA44

A9

M_MDA43

B12

M_MDA42

C11

M_MDA41

C12

M_MDA40

D12

M_MDA55

J2

M_MDA54

J1

M_MDA53

H1

M_MDA52

H2

M_MDA51

F1

M_MDA50

F2

M_MDA49

E1

M_MDA48

E2

M_MDA39

E11

M_MDA38

E12

M_MDA37

F11

M_MDA36

F12

M_MDA35

H11

M_MDA34

H12

M_MDA33

J11

M_MDA32

J12

M_MDA63

D1

M_MDA62

C1

M_MDA61

C2

M_MDA60

B1

M_MDA59

A4

M_MDA58

A5

M_MDA57

B5

M_MDA56

A6
B2

+MVDDQ

B4
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10

+MVDDC

C6
C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8

+MVDDQ

C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9

D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

C680
10uF

M_MAB12
M_MAB13

M_MAB11
M_MAB10
M_MAB9
M_MAB8
M_MAB7
M_MAB6
M_MAB5
M_MAB4
M_MAB3
M_MAB2
M_MAB1
M_MAB0

+MVDDQ +MVDDQ+MVDDQ

M_MAB14 M_MAB14

R279

4.99K

C210

R283

4.99K
100nF

M_CLKB#0
M_CSB#
M_RASB#
M_CASB#
M_WEB#
M_DQMB#1
M_DQMB#2
M_DQMB#0
M_DQMB#3
M_CLKB0
M_CKEB

M_QSB1
M_QSB2
M_QSB0
M_QSB3

C212
22uF 16V

+MVDDQ

C215
10uF

U54

M3

BA0

L4

BA1

L6

A11

K5

A10

L7

A9

M10

A8/AP

M9

A7

M8

A6

L8

A5

M7

A4

M6

A3

L5

A2

M5

A1

M4

A0

B3

NC

B10

NC

G3

NC

G10

NC

K11

NC

K12

NC

L2

NC

L3

NC

M2

NC

L12

MCL

M12

VREF

L9

RFU

K8

RFU

L11

CLK

M1

CS

L1

RAS

K1

CAS

K2

WE

A11

DM3

G2

DM2

G11

DM1

A2

DM0

L10

CLK

M11

CKE

A12

DQS3

G1

DQS2

G12

DQS1

A1

DQS0

E5

TH GND

E6

TH GND

E7

TH GND

E8

TH GND

F5

TH GND

F6

TH GND

F7

TH GND

F8

TH GND

G5

TH GND

G6

TH GND

G7

TH GND

G8

TH GND

H5

TH GND

H6

TH GND

H7

TH GND

H8

TH GND

1Mx32x4

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M_MDB8

A7

M_MDB9

B8

M_MDB10

A8

M_MDB11

A9

M_MDB12

B12

M_MDB13

C11

M_MDB14

C12

M_MDB15

D12

M_MDB16

J2

M_MDB17

J1

M_MDB18

H1

M_MDB19

H2

M_MDB20

F1

M_MDB21

F2

M_MDB22

E1

M_MDB23

E2

M_MDB0

E11

M_MDB1

E12

M_MDB2

F11

M_MDB3

F12

M_MDB4

H11

M_MDB5

H12

M_MDB6

J11

M_MDB7

J12

M_MDB24

D1

M_MDB25

C1

M_MDB26

C2

M_MDB27

B1

M_MDB28

A4

M_MDB29

A5

M_MDB30

B5

M_MDB31

A6
B2

B4

+MVDDQ

B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6

+MVDDC +MVDDC

C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4

+MVDDC

E9
F4
F9
G4
G9
H4
H9
J4
J9

D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

C682
10uF

R284

4.99K

M_MAB12
M_MAB13

M_MAB11
M_MAB10
M_MAB9
M_MAB8
M_MAB7
M_MAB6
M_MAB5
M_MAB4
M_MAB3
M_MAB2
M_MAB1
M_MAB0

R280

4.99K

+MVDDC+MVDDC +MVDDQ

C211

100nF

M_CLKB#1
M_CSB#
M_RASB#
M_CASB#
M_WEB#
M_DQMB#4
M_DQMB#6
M_DQMB#5
M_DQMB#7
M_CLKB1
M_CKEB

M_QSB4
M_QSB6
M_QSB5
M_QSB7

C213
10uF

M_MDA[63..0]
M_MDB[63..0]

+MVDDC

C224

C223

100nF

100nF

+MVDDC +MVDDQ

C244

C243

100nF

100nF

C225
100nF

C245
100nF

6

+MVDDQ

+MVDDQ

C226
100nF

C246
100nF

C227
100nF

C247
100nF

C228
100nF

C248
100nF

+MVDDC

5

C229
100nF

C249
100nF

+MVDDQ +MVDDC

C230

C231
100nF

C251
100nF

C232
100nF

C252
100nF

4

100nF

C250
100nF

C233
100nF

C253
100nF

C235

C234

100nF

100nF

+MVDDC+MVDDC

C255

C254

100nF

100nF

3

Title

Size Document Number Rev
B

Date: Sheet of

2

U55

M3

BA0

L4

BA1

L6

A11

K5

A10

L7

A9

M10

A8/AP

M9

A7

M8

A6

L8

A5

M7

A4

M6

A3

L5

A2

M5

A1

M4

A0

B3

NC

B10

NC

G3

NC

G10

NC

K11

NC

K12

NC

L2

NC

L3

NC

M2

NC

L12

MCL

M12

VREF

DIMB1DIMA1 DIMB0

L9

RFU

K8

RFU

L11

CLK

M1

CS

L1

RAS

K1

CAS

K2

WE

A11

DM3

G2

DM2

G11

DM1

A2

DM0

L10

CLK

M11

CKE

A12

DQS3

G1

DQS2

G12

DQS1

A1

DQS0

E5

TH GND

E6

TH GND

E7

TH GND

E8

TH GND

F5

TH GND

F6

TH GND

F7

TH GND

F8

TH GND

G5

TH GND

G6

TH GND

G7

TH GND

G8

TH GND

H5

TH GND

H6

TH GND

H7

TH GND

H8

TH GND

1Mx32x4

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M_MDB39

A7

M_MDB38

B8

M_MDB37

A8

M_MDB36

A9

M_MDB35

B12

M_MDB34

C11

M_MDB33

C12

M_MDB32

D12

M_MDB55

J2

M_MDB54

J1

M_MDB53

H1

M_MDB52

H2

M_MDB51

F1

M_MDB50

F2

M_MDB49

E1

M_MDB48

E2

M_MDB47

E11

M_MDB46

E12

M_MDB45

F11

M_MDB44

F12

M_MDB43

H11

M_MDB42

H12

M_MDB41

J11

M_MDB40

J12

M_MDB63

D1

M_MDB62

C1

M_MDB61

C2

M_MDB60

B1

M_MDB59

A4

M_MDB58

A5

M_MDB57

B5

M_MDB56

A6
B2

B4

+MVDDQ

B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6
C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8

+MVDDQ

E4
E9
F4

C681

F9

10uF

G4
G9
H4
H9
J4
J9

D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

13 27Tuesday, March 11, 2003

1

1.1

8

M_DQMC#[7..0](12)

M_DQMC#0
M_DQMC#1
M_DQMC#2
M_DQMC#3
M_DQMC#4
M_DQMC#5
M_DQMC#6

M_DQMD#[7..0](12)

D D

M_QSC[7..0](12)

M_QSD[7..0](12)

C C

Only for BGA Elpida memory

M_MAC[14..0](10,12)

B B

M_MAD[14..0](10,12)

+MVDDQ +MVDDC

A A

C265

C264

100nF

100nF

M_DQMC#7

M_DQMD#0
M_DQMD#1
M_DQMD#2
M_DQMD#3
M_DQMD#4
M_DQMD#5
M_DQMD#6
M_DQMD#7

M_QSC0
M_QSC1
M_QSC2
M_QSC3
M_QSC4
M_QSC5

+MVDDQ

M_QSC6
M_QSC7

M_QSD0
M_QSD1
M_QSD2
M_QSD3
M_QSD4
M_QSD5
M_QSD6
M_QSD7

C266
100nF

M_CKEC
M_WEC#
M_CASC#
M_RASC#
M_CSC#
M_CLKC0
M_CLKC1
M_CLKC#0
M_CLKC#1
M_CKED
M_WED#
M_CASD#
M_RASD#
M_CSD#
M_CLKD0
M_CLKD1
M_CLKD#0
M_CLKD#1

DIMC0
DIMC1
DIMD0
DIMD1

M_MAC0
M_MAC1
M_MAC2
M_MAC3
M_MAC4
M_MAC5
M_MAC6
M_MAC7
M_MAC8
M_MAC9
M_MAC10
M_MAC11
M_MAC12
M_MAC13
M_MAC14

M_MAD0
M_MAD1
M_MAD2
M_MAD3
M_MAD4
M_MAD5
M_MAD6
M_MAD7
M_MAD8
M_MAD9
M_MAD10
M_MAD11
M_MAD12
M_MAD13
M_MAD14

C267
100nF

M_CKEC(10,12)
M_WEC#(10,12)
M_CASC#(10,12)
M_RASC#(10,12)

M_CSC#(10,12)
M_CLKC0(10,12)
M_CLKC1(10,12)

M_CLKC#0(10,12)
M_CLKC#1(10,12)

M_CKED(10,12)

M_WED#(10,12)
M_CASD#(10,12)
M_RASD#(10,12)

M_CSD#(10,12)
M_CLKD0(10,12)
M_CLKD1(10,12)

M_CLKD#0(10,12)
M_CLKD#1(10,12)

DIMC0(10)
DIMC1(10)
DIMD0(10)
DIMD1(10)

+MVDDQ +MVDDC

C285
100nF

C286

C287

100nF

100nF

8

C284
100nF

7

6

5

4

3

64MBytes DDR 128Mbit 1Mx32x4 uBGA Channels C and D - rank1

M_MAC12
M_MAC13

M_MAC11
M_MAC10
M_MAC9
M_MAC8
M_MAC7
M_MAC6
M_MAC5
M_MAC4
M_MAC3
M_MAC2
M_MAC1
M_MAC0

M_MAC14 M_MAC14 M_MAD14 M_MAD14

R285

4.99K

C256

R289

DIMC0 DIMC1 DIMD0 DIMD1

4.99K
100nF

M_CLKC#0
M_CSC#
M_RASC#
M_CASC#
M_WEC#
M_DQMC#1
M_DQMC#2
M_DQMC#0
M_DQMC#3

M_CKEC

M_QSC1
M_QSC2
M_QSC0
M_QSC3

U56

M3

BA0

L4

BA1

L6

A11

K5

A10

L7

A9

M10

A8/AP

M9

A7

M8

A6

L8

A5

M7

A4

M6

A3

L5

A2

M5

A1

M4

A0

B3

NC

B10

NC

G3

NC

G10

NC

K11

NC

K12

NC

L2

NC

L3

NC

M2

NC

L12

MCL

M12

VREF

L9

RFU

K8

RFU

L11

CLK

M1

CS

L1

RAS

K1

CAS

K2

WE

A11

DM3

G2

DM2

G11

DM1

A2

DM0

L10

CLK

M11

CKE

A12

DQS3

G1

DQS2

G12

DQS1

A1

DQS0

E5

TH GND

E6

TH GND

E7

TH GND

E8

TH GND

F5

TH GND

F6

TH GND

F7

TH GND

F8

TH GND

G5

TH GND

G6

TH GND

G7

TH GND

G8

TH GND

H5

TH GND

H6

TH GND

H7

TH GND

H8

TH GND

1Mx32x4

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M_MDC8

A7

M_MDC9

B8

M_MDC10

A8

M_MDC11

A9

M_MDC12

B12

M_MDC13

C11

M_MDC14

C12

M_MDC15

D12

M_MDC16

J2

M_MDC17

J1

M_MDC18

H1

M_MDC19

H2

M_MDC20

F1

M_MDC21

F2

M_MDC22

E1

M_MDC23

E2

M_MDC0

E11

M_MDC1

E12

M_MDC2

F11

M_MDC3

F12

M_MDC4

H11

M_MDC5

H12

M_MDC6

J11

M_MDC7

J12

M_MDC24

D1

M_MDC25

C1

M_MDC26

C2

M_MDC27

B1

M_MDC28

A4

M_MDC29

A5

M_MDC30

B5

M_MDC31

A6
B2

B4

+MVDDQ

B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6

+MVDDC +MVDDC

C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4

+MVDDQ

C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9

+MVDDC

H4
H9
J4
J9

D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

M_MAC12
M_MAC13

M_MAC11
M_MAC10
M_MAC9
M_MAC8
M_MAC7
M_MAC6
M_MAC5
M_MAC4
M_MAC3
M_MAC2
M_MAC1
M_MAC0

+MVDDQ +MVDDQ

R286

4.99K

R290

C258

4.99K
100nF

M_CLKC#1
M_CSC#
M_RASC#
M_CASC#
M_WEC#
M_DQMC#5
M_DQMC#6
M_DQMC#4
M_DQMC#7
M_CLKC1
M_CKEC

M_QSC5
M_QSC6

C684
10uF

M_QSC4
M_QSC7

+MVDDC

C262
10uF

C688
10uF

U57

M3

BA0

L4

BA1

L6

A11

K5

A10

L7

A9

M10

A8/AP

M9

A7

M8

A6

L8

A5

M7

A4

M6

A3

L5

A2

M5

A1

M4

A0

B3

NC

B10

NC

G3

NC

G10

NC

K11

NC

K12

NC

L2

NC

L3

NC

M2

NC

L12

MCL

M12

VREF

L9

RFU

K8

RFU

L11

CLK

M1

CS

L1

RAS

K1

CAS

K2

WE

A11

DM3

G2

DM2

G11

DM1

A2

DM0

L10

CLK

M11

CKE

A12

DQS3

G1

DQS2

G12

DQS1

A1

DQS0

E5

TH GND

E6

TH GND

E7

TH GND

E8

TH GND

F5

TH GND

F6

TH GND

F7

TH GND

F8

TH GND

G5

TH GND

G6

TH GND

G7

TH GND

G8

TH GND

H5

TH GND

H6

TH GND

H7

TH GND

H8

TH GND

1Mx32x4

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M_MDC47

A7

M_MDC46

B8

M_MDC45

A8

M_MDC44

A9

M_MDC43

B12

M_MDC42

C11

M_MDC41

C12

M_MDC40

D12

M_MDC55

J2

M_MDC54

J1

M_MDC53

H1

M_MDC52

H2

M_MDC51

F1

M_MDC50

F2

M_MDC49

E1

M_MDC48

E2

M_MDC39

E11

M_MDC38

E12

M_MDC37

F11

M_MDC36

F12

M_MDC35

H11

M_MDC34

H12

M_MDC33

J11

M_MDC32

J12

M_MDC63

D1

M_MDC62

C1

M_MDC61

C2

M_MDC60

B1

M_MDC59

A4

M_MDC58

A5

M_MDC57

B5

M_MDC56

A6
B2

B4

+MVDDQ +MVDDQ

B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6
C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10

+MVDDQ

D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9

D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

C685
10uF

M_MAD12
M_MAD13

M_MAD11
M_MAD10
M_MAD9
M_MAD8
M_MAD7
M_MAD6
M_MAD5
M_MAD4
M_MAD3
M_MAD2
M_MAD1
M_MAD0

+MVDDQ

R288

4.99K

R291

4.99K

+MVDDQ

+MVDDQ

C257

100nF

M_CLKD#0
M_CSD#
M_RASD#
M_CASD#
M_WED#
M_DQMD#1
M_DQMD#2
M_DQMD#0
M_DQMD#3
M_CLKD0M_CLKC0
M_CKED

M_QSD1

M_QSD2

M_QSD0
M_QSD3

C260
22uF 16V

C263
10uF

M_MDC[63..0](12)
M_MDD[63..0](12)

C268
100nF

C288
100nF

+MVDDQ

+MVDDQ

C269
100nF

C289
100nF

7

C270
100nF

C290
100nF

+MVDDC

C272

C271

100nF

100nF

+MVDDC +MVDDQ

C291

C292

100nF

100nF

C273
100nF

C293
100nF

6

+MVDDQ

+MVDDQ

C274
100nF

C294
100nF

C275
100nF

C295
100nF

C276
100nF

C296
100nF

+MVDDC

5

C277
100nF

C297
100nF

C278
100nF

C298
100nF

+MVDDQ +MVDDC

C280
100nF

C281
100nF

C279
100nF

+MVDDC+MVDDC

C299

C300
100nF

C301
100nF

4

100nF

C282
100nF

C302
100nF

U58

M3

BA0

L4

BA1

L6

A11

K5

A10

L7

A9

M10

A8/AP

M9

A7

M8

A6

L8

A5

M7

A4

M6

A3

L5

A2

M5

A1

M4

A0

B3

NC

B10

NC

G3

NC

G10

NC

K11

NC

K12

NC

L2

NC

L3

NC

M2

NC

L12

MCL

M12

VREF

L9

RFU

K8

RFU

L11

CLK

M1

CS

L1

RAS

K1

CAS

K2

WE

A11

DM3

G2

DM2

G11

DM1

A2

DM0

L10

CLK

M11

CKE

A12

DQS3

G1

DQS2

G12

DQS1

A1

DQS0

E5

TH GND

E6

TH GND

E7

TH GND

E8

TH GND

F5

TH GND

F6

TH GND

F7

TH GND

F8

TH GND

G5

TH GND

G6

TH GND

G7

TH GND

G8

TH GND

H5

TH GND

H6

TH GND

H7

TH GND

H8

TH GND

1Mx32x4

C283
100nF

C303
100nF

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

3

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M_MDD8

A7

M_MDD9

B8

M_MDD10

A8

M_MDD11

A9

M_MDD12

B12

M_MDD13

C11

M_MDD14

C12

M_MDD15

D12

M_MDD16

J2

M_MDD17

J1

M_MDD18

H1

M_MDD19

H2

M_MDD20

F1

M_MDD21

F2

M_MDD22

E1

M_MDD23

E2

M_MDD0

E11

M_MDD1

E12

M_MDD2

F11

M_MDD3

F12

M_MDD4

H11

M_MDD5

H12

M_MDD6

J11

M_MDD7

J12

M_MDD24

D1

M_MDD25

C1

M_MDD26

C2

M_MDD27

B1

M_MDD28

A4

M_MDD29

A5

M_MDD30

B5

M_MDD31

A6
B2

B4
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6

+MVDDC +MVDDC

C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4

+MVDDC +MVDDQ

E9
F4
F9
G4
G9
H4
H9
J4
J9

D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

2

U59

M3

BA0

L4

BA1

L6

A11

K5

A10

L7

A9

M10

A8/AP

M9

A7

M8

A6

L8

A5

M7

A4

M6

A3

L5

A2

M5

A1

M4

A0

B3

NC

B10

NC

G3

NC

G10

NC

K11

NC

K12

NC

L2

NC

L3

NC

M2

NC

L12

MCL

M12

VREF

L9

RFU

K8

RFU

L11

CLK

M1

CS

L1

RAS

K1

CAS

K2

WE

A11

DM3

G2

DM2

G11

DM1

A2

DM0

L10

CLK

M11

CKE

A12

DQS3

G1

DQS2

G12

DQS1

A1

DQS0

R292

4.99K

M_MAD12
M_MAD13

M_MAD11
M_MAD10
M_MAD9
M_MAD8
M_MAD7
M_MAD6
M_MAD5
M_MAD4
M_MAD3
M_MAD2
M_MAD1
M_MAD0

R287

4.99K

C259

100nF

M_CLKD#1
M_CSD#
M_RASD#
M_CASD#
M_WED#
M_DQMD#5
M_DQMD#6
M_DQMD#4
M_DQMD#7
M_CLKD1
M_CKED

M_QSD5
M_QSD6
M_QSD4
M_QSD7

+MVDDC

C686
10uF

C261
10uF

E5

TH GND

E6

TH GND

E7

TH GND

E8

TH GND

F5

TH GND

F6

TH GND

F7

TH GND

F8

TH GND

G5

TH GND

G6

TH GND

G7

TH GND

G8

TH GND

H5

TH GND

H6

TH GND

H7

TH GND

H8

TH GND

1Mx32x4

Title

Size Document Number Rev
B

Date: Sheet of

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

2

DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

1

M_MDD47

A7

M_MDD46

B8

M_MDD45

A8

M_MDD44

A9

M_MDD43

B12

M_MDD42

C11

M_MDD41

C12

M_MDD40

D12

M_MDD55

J2

M_MDD54

J1

M_MDD53

H1

M_MDD52

H2

M_MDD51

F1

M_MDD50

F2

M_MDD49

E1

M_MDD48

E2

M_MDD39

E11

M_MDD38

E12

M_MDD37

F11

M_MDD36

F12

M_MDD35

H11

M_MDD34

H12

M_MDD33

J11

M_MDD32

J12

M_MDD63

D1

M_MDD62

C1

M_MDD61

C2

M_MDD60

B1

M_MDD59

A4

M_MDD58

A5

M_MDD57

B5

M_MDD56

A6
B2

B4

+MVDDQ

B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6
C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9

D4
D6
D7
D9
J5
J6
J7
J8
K4
K9

14 27Tuesday, March 11, 2003

1

C687
10uF

1.1

8

7

6

5

4

3

2

1

STRAPS

X0CLK_SKEW --VID(3:2)

Ra3

Ra4 Ri5

DNI

DNI

10K

DNI

10K

10K

BUSTYPE_1

Ra6

DNI
DNI 10K
10K
10K

BUSTYPE_0

VID5

VID4

Ra5

10K

DNI

10K
DNI
DNI

10K

10K
10K

10K DNIDNI DNI

10K 10K

DNI
10K

10K

10K
DNI

DNI
DNI10K

10K DNI

Rj2 Rk2 Rj3

10K

DNI DNI
DNI

10K

DNI DNI

DNI
DNI

DNI
10K 10K

10K

10K

10K

10K

10K

DNI DNI

DNI

10K

10K

DNI
10K

10K

10K

10K

DNI

DNI

DNI

DNI

DNI

10K 10K

10K

DNI

DNI

Ri6

x0clk to agpclk 0 tap delay

10K
DNIDNI

10K

DNI

10K10K

DNIDNI

DNI

Ri1

10K

AGP 8X, 0.8V signaling PLL CLK, IDSEL = AD16

DNI

AGP 8X, 0.8V signaling PLL CLK, IDSEL = AD17

10KDNI

AGP 4X, 0.8V signaling PLL CLK, IDSEL = AD16

DNI

AGP 4X, 0.8V signaling PLL CLK, IDSEL = AD17

DEFAULT

x0clk to agpclk 1 tap delay

x0clk to agpclk 2 taps delay

x0clk to agpclk 3 taps delay

AGP8X_DET = 0 (both GC and MB 8x capable)

DESCRIPTION

AGP8X_DET = 1 (either GC or MB not 8x capable)

AGP 4X, PLL CLK, IDSEL = AD16

10K

AGP 4X, PLL CLK, IDSEL = AD17
AGP 1X/2X, PLL CLK, IDSEL = AD16

10K

AGP 1X/2X, PLL CLK, IDSEL = AD17
PCI 66MHz, PLL CLK

DNI

PCI 33MHz, 3.3V, REF CLK
AGP 1X, REF CLK, IDSEL = AD16

10K

AGP 1X, REF CLK, IDSEL = AD17

Rk3

Rj4 Rk4

10K

DNI

DNI

DNI

10K

DNI10K

DNI
10K

DNI

10K

10K

DNI

DNI

10K

DNI

10K

10K

DNI

DNI

10K

DNI

ROMIDCFG[3:0]

10K

No ROM, CHG ID = 00

10K

No ROM, CHG ID = 01

10K

No ROM, CHG ID = 10

10K

No ROM, CHG ID = 11

10K

Parallel ROM on TVO

DNI

Serial AT25F1024, ID's from ROM

10K

Serial AT45DB011, ID's from ROM

DNI

Serial ST M25P10, ID's from ROM

10K

Serial ST M25P05, ID's from ROM

DNI

Serial SST45LF010, ID's from ROM
Parallel ROM on DVO

DNI

Serial ISSI NX25F011B, ID's from ROM

(default)

ROMSO(4,17)

ROMSI(4,17)

AGPFBSKEW -- VID(1:0)

INSTALL

Rh4

Rh3

Rh10 Rh3 Rh4

C

Ra2

DNI
DNI

10K

10K

Ri7Ra1

Ri8

refclk slightly earlier than feedback

DNI 10K

10K

DNI

10K

10K

10K

10K

DNI

refclk 1 tap earlier than feedback

DNI

refclk 1 tap later than feedback

10K

refclk 2 taps earlier than feedback

DNI

DEFAULT

(00)

(01)

(10)

(11)

BUSCFG -- VID(6:4)

BUSTYPE_2

VID6

Ra7 Ri2

Ri3

DNI

10K
10K

DNI

10K

DNI

10K

DNI

Rh10

Rh10

ID_DISABLE

Normal operation

CHIP SHUTS DOWN

Circuitry for external
power detection.

(DEFAULT)

DNI

DNI DNI DNI

10K

DNI DNI DNI10K

10K
10K

DNI DNI10K DNI10K

10K

DNI10K DNIDNI
10K DNI
10K DNI
10K DNI

Rj1 Rk1

10K

DNI
DNI

10K
10K 10K

DNI DNI

DNI

DNI

10K 10K

10K

DNI

10K

DNI

10K

DNI

10K

DNI

10K

DNI

10K

DNI

10K

DNI

Rj1

R352 10K

Rk1

R353 10K

Rj2

R354 10K

Rk2

R355 10K

Rj3

R357 10K

Rk3

R358 10K

Rj4

R359 10K

Rk4

R360 10K

DNI

DNI

DNI

DNI

+3.3V_BUS

ROMIDCFG3

ROMIDCFG2

ROMIDCFG1

ROMIDCFG0

Ri5

R333 10K

Ri6

R334 10K

Ri7

DNI

R335 10K

Ri8

D D

C C

B B

R336 10K

+3.3V_BUS

Ra1

R337 10K

Ra2

R338 10K

Ra3

R339 10K

Ra4

R340 10K

Ra5

R341 10K

Ra6

R342 10K

Ra7

R343 10K

Ri1

R344 10K

Ri2

R345 10K

Ri3

R346 10K

DVALID(4,23)

PSYNC(4)

VHAD0(4,23)

DNI

DNI
DNI
DNI
DNI
DNI

VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7

INSTALL

Rh1

VID[7..0]

Rh1

R347 10K

Rh2

R348 10K

Rh3

R349 10K

DNI

Rh10

R874 10K

DNI

Rh4

R350 10K

Rh5

R351 10K

TVO8(4)

R909 10K

+3.3V_BUS

+3.3V_BUS

+3.3V_BUS

EXT_PWR

Rh2

U93

EXT_PWR

MEMORY TYPE STRAPS

TVO6(4)

TVO7(4)

Rh6

Rh7

Rh8

Rh9

DNI

R850 10K

DNI

R851 10K

DNI

R852 10K

DNI

R853 10K

VID[7..0] (4,23)

DEVICE ID

NORMAL ID

Install it all the time when it is normal
device ID

Use workstation DEVICE_ID when
WSEN = 1

+3.3V_BUS

C733
100nF

24

NC7S04M5

3 5

INSTALL

VIP DEVICE

NO SLAVE VIP

Rh5

Install it when internal
pull-up doesn't work

SLAVE VIP --­VIP device will drive low when
VIP is attached.

+3.3V_BUS

+3.3V_BUS

(default)

R876

1.8K

(DEFAULT)

R875 1K

+5VEXT

C

ROMCS#(4,17)

ROMSCK(4,17)

A A

8

MEMORY TYPE

TBD

TBD

TBD

TBD

MEMORY TYPE STRAPS

Rh6 Rh8Rh7 Rh9

TBD TBD TBD TBD

TBD TBD TBD TBD

TBD TBD TBD TBD

TBD TBD TBD TBD

7

Title

Size Document Number Rev
B

6

5

4

3

Date: Sheet of

R566

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

2

15 27Tuesday, March 11, 2003

1

1.1

8

D D

7

6

5

4

3

2

1

SPEED CONTROLED FAN

+5V_BUS+12V_BUS

R362

Install when +12V fan is used. Install when +5V fan is used.

R361

0R

0R

Rl2Rl3

H1

Rl2Rl3

DNI

C C

VTERM2(5)

VTERM1(5)

B B

A A

8

DNI

R921 0R

C491
10nF

DNI

Fan_VDD

DNI

R892

R893 100K

100K

DNI DNI

R904
100K

THERM

7

R365
10K
R368

5.11K

THERM

DNI

C489
10nF

DNI

DNI

DNI

R891 100K

Fan_VDD

411

U95A

3

+

2

-

LM324M

R897 100K

DNI

U95C

10

+

9

-

LM324M

R903 0R

DNI

DNI

C493
10nF

1

8

DNI

R363
100K

DNI

R364
100K

DNI

Fan_VDD

VT1

DNI

R894 100K

DNI

6

DNI

U76

1

VT1

VDD

2

CF

OUT

3

VSLP

OTF

4 5

GND VT2

MC502BM

R896
100K

DNI

R898 100K

R899 100K

DNI

JU1

1
2

C490
10uF 16V

MMBT2222ALT1

8

R366 270R

7
6

Fan_VDD

R768

24.3K

RT1

t

DNI

100K

DNI

0R if RT1 not used.

R769
10K

DNI

U95B

5

+

R900

6

-

LM324M

100K

R901 100K

R902
100K

DNI

5

1

C492

0.1uF

DNI

Place directly
underneath R300
thermal balls.

DNI

7

DNI

3

Q11

2

DNIDNI

R367

0R

Rl1

VT1

Title

Size Document Number Rev
B

4

3

Date: Sheet of

R566

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

2

16 27Tuesday, March 11, 2003

1

1.1

8

7

6

5

4

3

2

1

D D

ROM_SO

RP192A33R

ROMSO(4,15)
ROMSI(4,15)
ROMSCK(4,15)
ROMCS#(4,15)

ROM_CSb(24)

C C

B B

81
72
63

RP192D33R

54

+3.3V_BUS

SI/A16
SCK/WEb
CSb HOLD1

HOLD1

SERIAL EEPROM 512K/1M

Ub

Ua

U80

5

D

6

C

1

S

7

C497
100nF

HOLD

3

W

8

VCC

M25P05-VMN6T

+3.3V_BUS +3.3V_BUS

VSS

ROM_SO

2

Q

4

DNI

U81

HOLD# R/B#

NX25F011B-3S

ALTERNATIVE PART : AT45DB011ALTERNATIVE PART :M25P05(512Kbit)

SCK

CS#
WP#
VCCGND

18

SISO

2
3
4
5
67

A A

Title

Size Document Number Rev
B

8

7

6

5

4

3

Date: Sheet of

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

2

17 27Tuesday, March 11, 2003

1

1.1

8

D D

7

6

5

4

3

2

1

PRIMARY DVI-I CONNECTOR (DVI-I1)

DDCCLK_DVI_R(19)
DDCDATA_DVI_R(19)

VSYNC_DVI-I_R(19)

B38 Bead

+5V_DIN

Place close to
the connector

C558
100nF

TX2M
TX2P

TX1M
TX1P

+5V_DIN

TX0M
TX0P

TXCP
TXCM

c

DVI-I1

J4

M1

CASE

M3

CASE

1

TMDS Data2-

2

TMDS Data2+

3

TMDS Data2/4 Shield

4

TMDS Data4-

5

TMDS Data4+

6

DDC Clock

7

DDC Data

8

Analog VSYNC

9

TMDS Data1-

10

TMDS Data1+

11

TMDS Data1/3 Shield

12

TMDS Data3-

13

TMDS Data3+

14

+5V Power

15

GND (for +5V)

16

Hot Plug Detect

17

TMDS Data0-

18

TMDS Data0+

19

TMDS Data0/5 Shield

20

TMDS Data5-

21

TMDS Data5+

22

TMDS Clock Shield

23

TMDS Clock+

24

TMDS Clock-

C1

Analog Red

C2

Analog Green

C3

Analog Blue

C4

Analog HYNC

C5

Analog GND

C6

Analog GND

M4

CASE

M2

CASE

DVI A/D

R459 0R
R460 0R
R461 0R
R462 0R

c

+5V_DIN(19)

INSTALL TERMINATION RESISTORS

TX2M(4)
TX2P(4)

C C

B B

TX1M(4)
TX1P(4)

TX0M(4)
TX0P(4)

TXCP(4)
TXCM(4)

CLOSE TO ASIC

R794 330R

R795 330R

R796 330R

R797 330R

INSTALL TERMINATION RESISTORS
CLOSE TO CONNECTOR

R451 330R

DNI

R453 330R

DNI

R455 330R

DNI

R456 330R

DNI

HPD1(4)

D9

2.5V

+5VCON1(20,22)

R_DVI-I(19)
G_DVI-I(19)
B_DVI-I(19)

HSYNC_DVI-I_R(19)

R457 20K

R458
100K

2 1

A A

Title

Size Document Number Rev
B

8

7

6

5

4

3

Date: Sheet of

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

2

18 27Tuesday, March 11, 2003

1

1.1

8

7

6

5

4

3

2

1

D D

R469 0R
R471 0R
R472 0R
R473 0R

C C

DDCCLK_DAC1_5V(20)

DDCDATA_DAC1_5V(20)

HSYNC_DAC1_B(20)

B B

VSYNC_DAC1_B(20)

R822 33R

R823 33R

R799 51R

R802 51R

R815 0R

R816 0R

ADDED DUE
TO LONG
TRACES

c

R824 33R

R825 33R

R800 0R

R803 0R

DDCCLK_DVI_R

DDCCLK_DAC2_5V (21)

DDCDATA_DVI_R

DDCDATA_DAC2_5V (21)

HSYNC_DAC2_B (21,22,23)

VSYNC_DAC2_B (21,23)

HSYNC_DVI-I_R

VSYNC_DVI-I_R

R_DVI-I
G_DVI-I
B_DVI-I

DDCDATA_DVI_R
DDCCLK_DVI_R
HSYNC_DVI-I_R

VSYNC_DVI-I_R

DNI DNI DNI

DNI DNI DNI

OPTIONAL ESD/HOTPLUG PROTECTION DIODES

2

2

2

D17

D18

3

1

DNI DNI DNI DNI DNI DNI DNI

C574

C573

C575

5pF

5pF

5pF

L17

L18

L16

82nH

82nH

82nH

1 2

1 2

1 2

c

Cox + Loy

D19

3

3

1

1

C749
22pF

2

3

1

C750
22pF

DNIDNI

+5V_BUS+5V_BUS +5V_BUS+5V_BUS+3.3V_BUS+3.3V_BUS +3.3V_BUS

2

2

D21

D20

3

3

1

1

PLACE CLOSE TO
CONNECTOR

2

D23

D22

3

1

+5V_DIN

DNI

MJ4

1

R

2

G

3

B

11

MS0

12

MS1

4

MS2

15

MS3

9

NC

13

HS

14

VS

5

VSS

6

VSS

7

VSS

8

VSS

10

VSS

16

CASE

17

CASE

18

CASE

19

CASE

DB15F slim RA

c

6050003000
Thin-DB15

DDC2_MONID0
DDC2_MONID1(SDA)
DDC2_MONID2
DDC2_MONID3(SCL)

DDCCLK_DVI_R (18)
DDCDATA_DVI_R (18)

R_DVI-I (18)
G_DVI-I (18)
B_DVI-I (18)

HSYNC_DVI-I_R (18)
VSYNC_DVI-I_R (18)

+5V_DIN (18)

L57 68nH

R_DAC1_F1(20)

G_DAC1_F1(20)

B_DAC1_F1(20)

A A

8

1 2

L58 68nH

1 2

L59 68nH

1 2

Place close to the output
of the DAC1 filters

7

Keep length short,
or another set of
resistor may be
needed

R26 0R

R27 0R

R28 0R

Place close to the
High-Density
Header

6

R_DVI-I

R/C_DAC2_F (21)

G_DVI-I

G/Y_DAC2_F (21)

B_DVI-I

B/COMP_DAC2_F (21)

Title

Size Document Number Rev
C

5

4

3

Date: Sheet of

2

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

19 27Tuesday, March 11, 2003

1

1.1

8

7

6

5

4

3

2

1

PRIMARY CRT INTERFACE

D D

OPTIONAL ESD/HOTPLUG PROTECTION DIODES

+3.3V_BUS +5V_BUS

+3.3V_BUS

+3.3V_BUS +5V_BUS +5V_BUS

2

2

D10

BAT54SLT1

C559

3pF

L7
82nH

1 2

L8
82nH

1 2

c

C560

3pF

3

3pF

82nH

1 2

R_DAC1_F1 (19)
G_DAC1_F1 (19)

C C

R_DAC1(4)
G_DAC1(4)

B_DAC1(4)

+3.3V_BUS

CRT1DDCDATA(4)

B B

CRT1DDCCLK(4)

HSYNC_DAC1(4)

VSYNC_DAC1(4)

+3.3V_BUS

+5V_BUS

4.7K

R468

4.7K

+3.3V_BUS

1

+3.3V_BUS

BSN20

1

BSN20
Q13

32

Q12

32

10

9

13
12

+5V_BUS

R463

6.8k

+5V_BUS

R464

6.8k

74ACT08MTC

U2C

U2D

74ACT08MTC

8

11

PLACE CLOSE TO ASIC

L43
L44
L45

R51

R50

R49

75.0R

75.0R

GND_AVSSN

75.0R

1%1% 1%

C564 3pF
C567 3pF C568 1pF
C570 3pF

1 2
1 2
1 2

DNI
DNI
DNI

82nH
82nH
82nH

L46

1 2

L47 82nH

1 2

L48

1 2

C565 1pF
C571 1pF

B_DAC1_F1 (19)

82nH

82nH

R859

56R

R_DAC1_F
G_DAC1_F
B_DAC1_F

DDCDATA_DAC1_5V
DDCCLK_DAC1_5V

VSYNC_DAC1_R1

DDCDATA_DAC1_5V (19)
DDCCLK_DAC1_5V (19)

R860

56R

HSYNC_DAC1_B (19)

VSYNC_DAC1_B (19)

D11

3

3

1

1

DNI DNI DNI DNI DNI DNI DNI

R465 33R
R466 33R
R470 0R

R474 0R

C561

DNIDNIDNI

DNIDNIDNI

L9

+5V_BUS

2

2

2

D12

3

1

HSYNC_DAC1_RHSYNC_DAC1_R1
VSYNC_DAC1_R

D14

D13

3

1

1

C751
22pFR467

DNI DNI

PLACE CLOSE TO
CONNECTOR

2

2

D15

3

D16

3

1

1

C752
22pF

C562

100nF

PRIMARY VGA
CONNECTOR

F1

750mA

+5VCON1 (18,22)

B39
Bead

J5

1

R

2

G

3

B

11

MS0

12

MS1

4

MS2

15

MS3

9

NC

13

HS

14

VS

5

VSS

6

VSS

7

VSS

8

VSS

10

VSS

16

CASE

17

CASE

Connector DB15 Female VGA Blue

c

+5V_BUS

A A

Title

Size Document Number Rev
B

8

7

6

5

4

3

Date: Sheet of

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

2

20 27Tuesday, March 11, 2003

1

1.1

8

D D

7

6

5

4

3

2

1

PLACE CLOSE TO ASIC

C577 8pF
C579 8pF
C581 8pF

L60 56nH

1 2

L61 56nH

1 2

L62 56nH

1 2

R/C_DAC2_F (19)
G/Y_DAC2_F (19)
B/COMP_DAC2_F (19)

SECONDARY CRT LOGIC

SECONDARY CRT LOGIC
CRT2

DDCDATA_DAC2_5V (19)
DDCCLK_DAC2_5V (19)

DDCDATA_DAC2_HDH (23)
DDCCLK_DAC2_HDH (23)

HSYNC_DAC2_B (19,22,23)
VSYNC_DAC2_B (19,23)

L10 68nH

R_DAC2(22)
G_DAC2(22)

B_DAC2(22)

BSN20

Q14

32

Q15

+5V_BUS

6.8k
R480

32

+5V_BUS

6.8k
R482

U3B

6

U3C

8

R31 47R
R32 47R

R791 75.0R
R792 75.0R
R793 75.0R

R29 33R
R30 33R

DNI

GND_A2VSSN

+3.3V_BUS

R479

4.7K

CRT2DDCDATA(4)

C C

CRT2DDCCLK(4)

HSYNC_DAC2(4)

VSYNC_DAC2(4)

B B

+3.3V_BUS

R481

4.7K

R877
10K

DNI

1

1

BSN20

4
5

SN74ACT86PW

9

10

SN74ACT86PW

1 2

L12 68nH

1 2

L14 68nH

1 2

C576 3.3pF
C578 3.3pF
C580 3.3pF

A A

Title

Size Document Number Rev
B

8

7

6

5

4

3

Date: Sheet of

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

2

21 27Tuesday, March 11, 2003

1

1.1

5

4

3

2

1

TV-OUT

STEREOSCOPIC DISPLAY
CONNECTOR

Rm21

R763 0R

F

DNIInstall

A

E

C D

CRT2 logic (page21)

B C D E G Uv1

A CB E

A B

A B

CRT2 logic (page21)

Uv1

A CB E

D E

C

D

TVO2(4,23)

R606 0R
R608 0R
R504 0R

Connector Jm1 uses the
same footprint as Jm2
and Jm3

2

H

STEREOSYNC(4)

TBLuma
TBChroma

HSYNC_DAC2_B(19,21,23)

D D

Y_DAC2

R912

75.0R

R925 0R

G

GND_TVVSSN

C_DAC2

R913

75.0R

GND_TVVSSN

COMP_DAC2

C C

R/C_DAC2(4)
G/Y_DAC2(4)

B/COMP_DAC2(4)

GND_TVVSSN

R914

75.0R

Uv1

U96

TVO0(4,23)
B_DAC2(21)

G_DAC2(21)

B B

A A

COMP_DAC2
B_DAC2
Y_DAC2
G_DAC2

R/C_DAC2_HDH(23)
G/Y_DAC2_HDH(23)

B/COMP_DAC2_HDH(23)

5

1
2
3
5

6
11
10 14
15

R_DAC2
G_DAC2
B_DAC2

C_DAC2
Y_DAC2
COMP_DAC2

SEL

VCC
1A0
1A1
1B0
1B1
1C0

1D1
1C1 1D0
E

GND

PI5V330

R915 0R
R916 0R
R917 0R

R918 0R
R919 0R
R920 0R

R922 0R
R923 0R
R924 0R

R928 0R
R929 0R
R930 0R

R931 0R
R932 0R
R933 0R

YA
YB
YC
YD

16
4
7
9
12
13

8

C

D

E

A

B

+5V_BUS

R926 0R

ADDED TO REMOVE
STUBS WHEN VO
USED ON HDH

R927 0R

C735
100nF

R_DAC2
C_DAC2

DNI

DNI

DNI

DNI

DNI

4

R_DAC2
G_DAC2
B_DAC2

C_DAC2
Y_DAC2

COMP_DAC2

R/C_DAC2
G/Y_DAC2

B/COMP_DAC2

R/C_DAC2
G/Y_DAC2
B/COMP_DAC2

R_DAC2 (21)

TVO0 VGA2 TV out

"1"
"0"

L20

1.8uH

C583
82pF

C585
82pF

C588
82pF

L21

1.8uH

L22

1.8uH

c

c

c

TV-OUT only (main board)

VGA2 only (main board)

VGA2 & TV-OUT (main board)

VGA2 (main board)
& TV-OUT (daughter card)

TV-OUT (main board)
& VGA2 (daughter card)

VGA2 (daughter card)
& TV-OUT (daughter card)

enable
disable

disable
enable

3

C584
82pF

TBChroma

C586
82pF

C587
82pF

TBLuma

TBComp

B

CRT2 logic (page21)

A

G Uv1

Uv1

D

C

E

G

CRT2 logic (page21)

G

Uv1

12

DNI

13

Connector Jm3 uses the
same footprint as Jm1
and Jm2

COMP

Connector Jm2 uses the
same footprint as Jm1
and Jm3

D

G

G

Uv1

Rm22
Rm23
Rm24

R513 330R

DNI

Rm7

Title

Size Document Number Rev
B

Date: Sheet of

+5VCON1(18,20)

U3D

11

SN74ACT86PW

R878 0R

TBLuma_R
TBChroma_R
COMPTBComp
SYNC

Cm1

DNI

C589
470pF

R300 128M DVII VGA2 VO

DNI

B50 Bead

Bm4

Rm3

R517 0R

COMP

DNI

TV Out (Comp)

Jm2

J8
Jack Phono RCA

1

DNI

32

c

TV Out (SVHS)

Connector DIN Miniature Circular 7 Pin

PIN1

Rm1

R509

0R

cc c

GIGABYTE

GV-R9700

DNI

Jm3

MJ7

PIN1

1

1

2

2

7

7

8

CASE

9

CASE

10

CASE

MiniDIN 3 Pin

c

B

Jm1

J7

6

+12V

3

Y-OUT

4

C-OUT

7

Comp_out

5

SYNC

1

GND

2

GND

8

CASE

9

CASE

10

CASE

22 27Tuesday, March 11, 2003

1

1.1

8

7

6

5

4

3

2

1

HIGH-DENSITY HEADER

D D

DVO/VID Data Bus

DVO[11..0]

VID[7..0]

VPHCTL
VHAD1

SOCKET STRIP 2x35 0.05x.1

JU5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66
67 68
69 70

+3.3V_BUS+3.3V_BUS +5V_BUS

R818
R820

CLK_VIPCLK

VHAD0

NTSC/PAL

AGP_RESET#
DVO0
DVO2
DVO4
DVO6
DVO8
DVO10

VID7
VID5
VID3
VID1

I2C_DATA

0R

DNI

0R

C C

B B

3.3V I2C CLK

G/Y_DAC2_HDH(22)

HSYNC_DAC2_B(19,21,22)
VSYNC_DAC2_B(19,21)

DDCDATA_DAC2_HDH(21)

SCL(4)

TVO0(4,22)
TVO2(4,22)
TVO4(4)

R806 0R

+3.3V_BUS

Daughter Card Straps

R861 10K
R862 10K
R863 10K

DC_Strap5
DC_Strap3
DC_Strap1

R864 10K
R865 10K
R866 10K

Analog Display from DAC2

DDC DATA

R809 0R
R811 0R
R813 0R

DVO1
DVO3
DVO5
DVO7
DVO9
DVO11

CLK_VIDCLK
VID6
VID4
VID2
VID0

I2C_CLK

R808 0R

R810 0R
R812 0R
R814 0R

Daughter Card Straps

DC_Strap4
DC_Strap2

Use to reset Si168 External TMDS

DVALID(4,15)

R821 0R

DVO[11..0] (4)
CLK_VIDCLK (4)
VID[7..0] (4,15)

VIP Host Bus

CLK_VIPCLK (4)
VHAD0 (4,15)
VHAD1 (4)
VPHCTL (4)

SDA (4)

R867 10K
R868 10K
R869 10K

TVO3 (4)
TVO5 (4)

R870 10K
R871 10K
R872 10K

DDC CLK

DDCCLK_DAC2_HDH (21)

Analog Display from DAC2

R/C_DAC2_HDH (22)
B/COMP_DAC2_HDH (22)

AGP_RESET# (2,3,9,10,24)
HPD2 (4)

DVO Bus control lines for
External DDR TMDS

CLK_DVOCLK1 (4)
CLK_DVOCLK0 (4)

DVOCNTL2 (4)
DVOCNTL1 (4)
DVOCNTL0 (4)

3.3V I2C DATA

+3.3V_BUS

41

SW1A
DIP_SWX2

TVO1 (4)

32

SW1B
DIP_SWX2

A A

Title

Size Document Number Rev
C

8

7

6

5

4

3

Date: Sheet of

2

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

23 27Tuesday, March 11, 2003

1

1.1

8

MU106
TK11819M

IN-

1

Vin

2

OSC

IN+

3

D D

AGP_VREFGC(2,3)

AGP_DEVSEL#_R(2,3)

C C

Block_DEVSEL#

Place closest possible to AGP
connector with minimum possible
stub on AGP_DEVSEL#_R signal.

Minimum possible stub on
this signal.

DK

USED FOR THE FOOTPRINT

DEVSEL_TTL

C761
100nF

R1550 4.99K

R1548 1.0K

U107

1

VDD

2

OUT

3

GND

4 5

LATCH VEE

MAX9203EKA-T

AGP_RESET#(2,3,9,10,23)

AGP_AGPCLK(2,3)

VCC

IN+

IN-

GND
Vout

8
7
6

6

T1

5
4

3
4

IN-

7

DEVSEL_TTL

+5V_BUS

+5V_BUS

U106

+

1

-

LMV7219M7

R1547

2 5

100K

IN+

DNI

HighSpeed Comparator

R946 220R

R1551
100K

DNI

+5V_BUS

8X_DET#(3)

R943 0R

C760
100nF

6

1
2

SN74ACT86PW

ROM_CSb(17)

+5V_BUS

147

C753
100nF

U3A

3

SN74HCT02PWR

U99B

5
6

SN74HCT02PWR

2
3

+5V_BUS

14

7

4

5

C759
100nF

U99A

R952 0R

1

U99C

8
9

C1126
100nF

DNI

10

SN74HCT02PWR

4

3

2

1

Hijack Circuit

R947 0R

+5V_BUS

C757
100nF

2

D

3

C

5V

PR

G

CL

74VHCT74MTC

7

1

5

Q

6

Q

U103A

14

4

R951 0R

12

D

11

C

U103B

1013

9

Q

PRCL

8

Q

74VHCT74MTC

Block_DEVSEL#

11
12

U99D

13

SN74HCT02PWR

SWAP

B B

SWAP

C755

100nF

A A

C756

100nF

8

+5V_BUS

MK1

1

SELECT

NO

2

V+

COM

3 4

GND NC

NLAS4599DF

K1
MAX4625EUT-T

1

+

3

-

K2
MAX4625EUT-T

1

+

3

-

MK2

1

SELECT

NO

2

V+

COM

3 4

GND NC

NLAS4599DF

7

6
5

6
52
4

6
52
4

6
5

Place closest possible to AGP connector with absolute
minimum possible trace lengths and vias.

AGP_TRDY#_R (2)

AGP_STOP#_R (2)

SIDE

6

AGP_TRDY# (2,3)

AGP_STOP# (2,3)

R300 SIDEAGP CONNECTOR

5

Title

Size Document Number Rev
B

4

3

Date: Sheet of

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

2

24 27Tuesday, March 11, 2003

1

1.1

5

4

3

2

1

DVI SCREWSCRT SCREWS

ASSY1

SCREW

JACKSCREW

D D

C C

<3rd part field>
7020000800

ASSY4

SCREW

JACKSCREW

<3rd part field>
7020000800

ASSY6

SCREW

PAN HEAD

ASSY8

BRACKET

VGA, VID OUT, DVI, 301

<3rd part field>

ASSY2

ASSY5

ASSY11

BRACKET

VGA, DVI, 308

ALT

SCREW

JACKSCREW

<3rd part field>
7020000800

SCREW

JACKSCREW

<3rd part field>
7020000800

ASSY10

DVI, 251

ALT

BRACKET

MISC. BOARD PARTS

ASSY3

BLANK
LABEL

1.50W X 0.50H

ASSY

ASSY7

ANTISTATIC
BAG

6 X 11

<3rd part field>

REF1

SCHEMATIC

105-942XX-30

<3rd part field>

REF3

ATI LOGO
LABEL

ATI LOGO LABEL

REF2

PCB

109-942XX-30

<3rd part field>

B B

A A

Title

Size Document Number Rev
B

5

4

3

2

Date: Sheet of

GIGABYTE

R300 128M DVII VGA2 VO

GV-R9700

25 27Tuesday, March 11, 2003

1

1.1

8

<Variant Na

me>

Title

7

6

5

4

3

2

1

Date:Schematic No.

AGP R300 128MB BGA DVII VGA VO

REVISION HISTORY

D D

Sch

PCB

Rev

Rev

0 PROTOTYPE I.i.00A

1 00B PROTOTYPE I.i.i.

C C

2 00C

B B

Date

06/28/2 002

REVISION DESCRIPTION

BASED ON 109-94200-00A.
Sheet 2: Added C731 to input 2 of U2 to provide RC circuit for RESET.
Sheet 3: Added MOSFET Q19 to AGPREF pin of the ASIC to disconnect VREF from the motherboard during RESET time.
Replaced values for R39 (180R) and R40 (68R)
Sheet 4: Added C738 to TPVDD.
Sheet 6: Added header JU2 , capacitor C101, C739,C737 for external +5V power source, B18 connected to external +5V, added C732 to the output of the core regulator.

Added R910, R91 1.
Replaced values f or Q3, Q4, L1, L2, R76, R89, R77, R90, C86, C92.

Removed diodes D4, D5.
Sheet 7: Added C734, and C736. Replaced internal +12V with external 12V. Replaced C120 with the bigger value 470uF. Removed C123, C124. Removed resistor R112 from U48-6 to 12V, that is not used. Added option to short one diode in D6
with R112.

Added diode D24 to provide +12v power to MVDDC regulator when external power is not connected.
Sheet 8: Regulator circuit for VDDC_CT replaced with one regulator. Changed source voltage for PVDD, and TPVDD regulators from +5V to +3.3V.
Sheet 9: Added resi stors for selection between 4MX32 and 8MX32 memories.
Sheet 10: Added res istors for selection between 4MX32 and 8MX32 memories.
Sheet 11: Connected address lines MAA14 and MAB14 .
Sheet 12: Connected address lines MAC14 and MAD14 .
Sheet 13: Added MAA14, MAB14 as chip selects for Hynix 8MX32 memory.
Sheet 14: Added MAC14, MAD14 as chip selects for Hynix 8MX32 memory.
Sheet 15: Added circuit for detection of external power supply connection.
Sheet 16: Added fail-safe circuit for fan control, and connected internal thermistor from ASIC, VTERM1 is connected through the 0R resistor, R912, to have an option to use A11. Removed 3-pin
header.
Sheet 21: Added pull down resistor R877 on VSYNC_DAC2 for TVout filter enable.
Sheet 22: Added resistor R878 on connector J7. Removed MOSFET switch, and replaced with demultiplexer U96. Added also resistors to bridge the demultiplexer.
Sheet 23: Chang e GPIO used for Si168 reset to DVALID.

PROTOTYPE I.i.i.I

BASED ON 109-94200-00B.
Sheet 3: Replaced Q2 and Q1 with different type 2N7002E.
Sheet 6: Added capacitors C740, C742 to the drains of the Q3A and Q5A. Added diode D25 to the second phase of the core regulator. Changed resistors values R94, and R98.
Sheet 7: Added cap acitors C743, C744, C745, C746 and C747. Changed values for R114 and R117.
Sheet 8: Added capac itors C748. Changed values for R124, R131, R130, R126, R143, R139 and C133.
Sheet 9: Changed value for R138 to 75R.
Sheet10: Changed value for R774 to 75R.
Sheet19: Changed values for R800 and R803 to 0R. Replaced L11, L13, and L15 with R26, R27 and R28 respectively 0R. Added capacitors for HSYNC and VSYNC C749, and
C750.
Sheet20: Added capacitors at HSYNC and VSYNC, at C751, C752.
Sheet21: Added R29, R30, R31 and R32.
Sheet22: Added R925, R926, R927 to remove stubs when VO is used on HDH. Added R928, R929, and R930 to short DMUX (U96) when no VO is installed on the main board. Added R931, R932, and R933 to short DMUX (U96) when
no second VGA is installed.
Sheet23: Removed resistors R805 and R807.

105-942XX-30_11

Tuesday, March 11, 2003

Rev

1.1

3 00 07/08/2 002

A A

10 07/10/2002

4

5 01 07/19/2 002

8

PRODUCTION RELEASE

Sheet 6: Replaced diode D25 with Scottkey diode. C91 replaced with 10MM footprint, better quality part.

PRODUCTION RELEASE II

Sheet 2: Removed series resistors R7 on AGP_SBSTB#, R9 on AGP_ADSTB1#, and R16 on AGP_ADSTB0#. Added instead pull-up 10K resistors to +VDDQ_BUS with the same designators.

PRODUCTION RELEASE III
Adjusted trace on AGP to give clearance for fingers. Remove N625 declaration. Changed soldermask requirement to red.

7

6

5

4

3

2

1

8

<Variant Na

me>

Title

7

6

5

4

3

2

1

Date:Schematic No.

AGP R300 128MB BGA DVII VGA VO

REVISION HISTORY

D D

Sch

PCB

Rev

Rev

8 20 08/24/02

C C

9 30A PROTOTYPE IV

10 30B PROTOTYPE V

11 30 09/26/02 PRODUCTION RELEASE VI

B B

Date

07/26/02116

08/19/02127

09/06/02

09/18/02

REVISION DESCRIPTION

PRODUCTION RELEASE IIII
PCB silkscreen update only. No schematic changes.

PRODUCTION RELEASE IV
PCB silkscreen update only. No schematic changes.

1. Rev letter changed from 109-94200-11 to 109-94200-12

2. Remove CGND flood on L1 and L6 for MJ4.18

PRODUCTION RELEASE V
Sheet 1: Added traces to hijack circuit (sheet 24), AGP_TRDY#_R, and AGP_STOP#_R. Removed R12.
Sheet 6: Added R938 and R939 for selection of either 12V or 5V for Vtt regulator.
Sheet 7: Added R936 and R937 for selection of either 12V or 5V for MVDDC regulator.
Sheet 8: Added R934 and R935 for selection of either 12V or 5V for MVDDQ regulator.
Sheet 24: Added Hijack Circuit to compensate for R300 cold boot issues.

Sheet 1: Added C112 7.
Sheet 2: Added trace 8X_DET# to hijack circuit (sheet 24).
Sheet 6: Added C76 2 to Vc pin of Vtt regulator.
Sheet 7: Added C763 to 12V for MVDDC regulator. Added R954 and C764 to low gate of Q8B.
Sheet 8: Added C76 5 to Vc pin of MVDDQ regulator.
Sheet 24: Changed Hijack Circuit to compensate for R300 cold boot issues.

PCB silkscreen update. Changed some component location in order to shorten the AGP_CLK lentgh after R946 resistor. No schematic changes.

Sheet 6: Added R1552 between pins 2 and 3 of VDDC regulator.

105-942XX-30_11

Tuesday, March 11, 2003

Rev

1.1

A A

8

7

6

5

4

3

2

1