5
4
3
2
1
MEMORY CHANNEL C D
D D
DDR 4M X 32 (BGA)
SHT 14
MEMORY TERMINATIONS C D
SHT 12
VGA1
MDC/D[63..0] QSC/D[7..0] CS0C/D#
MC/D[14..0]
CASC/D#
MEM A B
C C
STRAPS
SHT 15
MEM C D
DAC1
TMDS
BIOS
SHT 17
ROMCS#
ROM
TVO
External
power
B B
POWER
REGULATION
SHT 6,7,8
FAN
SHT 16
VDDC VDDC18 VDD VTT VDDQ
PVDD TPVDD MPVDD
A2VDD Vref
R300
SHEET 3, 4, 5, 09, 10
DVO
VIP
DAC2
AGP
WEA/B#RASC/D#
CKEC/D CLKC/D01
R G B HSY VSY DDC1DATA DDC1CLK
TMDS_TX[C,2..0]N TMDS_TX[C,2..0]P HPD, DDC2CLK DDC2DATA
DVO, VIP Host, VIP Data
Y/R C/G COMP/B H2SYNC
GPIO
SEL
SHT 22
DQMC/D[0..7]
CLKC/D01#
CRT2DDCDATA CRT2DDCCLK V2SYNC
D
E
M
TVOUT
LOGIC
SHT 22
U
X
SECONDARY
CRT LOGIC
SHT 19
PRIMARY CRT
LOGIC
SHEET 19
INTEG TMDS
LOGIC
HDH
SHT 23
TVout
CONN
DB15
CONN
SHT 19
DVI-I1
CONN
SHT 18
CBE3..0
GNT#
CLK
SBA[7..0]
AD_STB1#
CPUCLK
TRDY#
INTR
ST2..0
SUSPEND#
AD_STB0
DEVSEL#
SB_STB
AD_STB0#
RESET#
SERR#
SB_STB#
RBF#
Title
Size Document Number Rev
B
3
2
Date: Sheet of
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
1 25Tuesday, March 11, 2003
1
2.1
AD31..0
IRDY#
FRAME#
AGPREF
+5V
+3.3V
A A
5
+12V
AD_STB1
AGP BUS
2X/4X/8X
SHT 2
4
REQ#
PAR
STOP#
8
7
6
5
4
3
2
1
2X/4X/8X AGP BUS
GND_TPVSSGND_MPVSS
GND_PVSS GND_TXVSSR
NOTE: THIS IS A DRAWING. THESE
GROUNDS MUST BE MANUALLY
D D
CONNECTED TO THE GROUND PLANE
AGP_MB_8X_DET#(3)
C C
B B
A A
8
GND_A2VSSN
AGP_GNT#(3)
AGP_DBI_HI(3)
AGP_WBF#(3)
AGP_SBSTB#(3)
AGP_ADSTB1#(3)
AGP_FRAME#(3)
AGP_TRDY#_R(23)
AGP_TRDY#(3,23)
AGP_STOP#(3,23)
AGP_STOP#_R(23)
AGP_PAR(3)
AGP_ADSTB0#(3) AGP_ADSTB0 (3)
AGP_VREFGC(3,23)
AGP_RESET#(3,22,23)
GND_AVSSQ GND_RSET
GND_A2VSSQ
R2 0R
AGP_RST#
R4 0R
R5 0R
+VDDQ_BUS
R7 8K2
+VDDQ_BUS
R9 8K2
+VDDQ_BUS
R16 8K2
R22 100R
R854
DNI
180R C731
7
GND_R2SETGND_AVSSN
AGP_INTR#(3)
AGP_GC_8X_DET#
DNI
R13 0R
DNI
R15 0R
AGP_VREFGC
74ACT08MTC
R25
180R
GND_TVVSSN
U2A
3
+5V_BUS
147
AGP_SBSTB#_R
C5
100nF
1
2
6
+12V_BUS
+3.3V_BUS +3.3V_BUS
A1
TYDET
A2
A3
A4
GND_TY
A5
A6
A7
A8
AGP_ST1
AGP_DBI_HI_R
AGP_SBA1 AGP_SBA0
AGP_SBA3
AGP_SBA5
AGP_SBA7
AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24
AGP_ADSTB1#_R
AGP_C/BE#3
AGP_AD22
AGP_AD20
AGP_AD18
AGP_AD16
AGP_TRDY#_R
AGP_STOP#_R
AGP_PAR_R
AGP_AD15
AGP_AD13
AGP_AD11
AGP_AD9
AGP_C/BE#0
AGP_ADSTB0#_R
AGP_AD6
AGP_AD4
AGP_AD2
R19
10K
AGP_RST#
DNI
100nF
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
PWGOOD_VDDC (6)
5
R1 0R
MAGP1
12V
TYPEDET#
GC_DET#/RESEVED
USBÂGND
INTA#
RST#
GNT#
VCC3.3
ST1
MB_DET#/RESERVED
DBI_HI/PIPE#
GND
WBF#
SBA1
VCC3.3
SBA3
SB_STB#
GND
SBA5
SBA7
KEY
KEY
KEY
KEY
AD30
AD28
VCC3.3
AD26
AD24
GND
AD_STB1#
C/BE3#
VDDQ
AD22
AD20
GND
AD18
AD16
VDDQ
FRAME#
KEY
KEY
KEY
KEY
TRDY#
STOP#
PME#
GND
PAR
AD15
VDDQ
AD13
AD11
GND
AD9
C/BE0#
VDDQ
AD_STB0#
AD6
GND
AD4
AD2
VDDQ
AD0
VREFGC
UNIVERSAL AGP BUS
GND_TYTYDET
OVRCNT#
5.0V
5.0V
USB+
GND
INTB#
CLK
REQ#
VCC3.3
ST0
ST2
RBF#
GND
DBI_LO/RESERVED
SBA0
VCC3.3
SBA2
SB_STB
GND
SBA4
SBA6
KEY
KEY
KEY
KEY
AD31
AD29
VCC3.3
AD27
AD25
GND
AD_STB1
AD23
VDDQ
AD21
AD19
GND
AD17
C/BE2#
VDDQ
IRDY#
KEY
KEY
KEY
KEY
DEVSEL#
VDDQ
PERR#
GND
SERR#
C/BE1#
VDDQ
AD14
AD12
GND
AD10
AD8
VDDQ
AD_STB0
AD7
GND
AD5
AD3
VDDQ
AD1
VREFCG
+5V_BUS+VDDQ_BUS
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
SYMBOL LEGEND
DO NOT
DNI
INSTALL
ACTIVE
#
LOW
DIGITAL
GROUND
ANALOG
GROUND
4
+VDDQ_BUS
AGP_ST0
AGP_ST2
AGP_DBI_LO_R
AGP_SBA2
AGP_SBA4
AGP_SBA6
AGP_AD31
AGP_AD29
AGP_AD27
AGP_AD25
AGP_AD23
AGP_AD21
AGP_AD19
AGP_AD17
AGP_C/BE#2
AGP_C/BE#1
AGP_AD14
AGP_AD12
AGP_AD10
AGP_AD8
AGP_AD7
AGP_AD5
AGP_AD3
AGP_AD1AGP_AD0
AGP_C/BE#[3..0]
AGP_AD[31..0]
AGP_SBA[7..0]
AGP_ST[2..0]
AGP_AGPCLK_R
R6 0R
AGP_SBSTB_R
AGP_ADSTB1_R
AGP_DEVSEL#_R
AGP_ADSTB0_R
3
+12V_BUS
AGP_C/BE#[3..0] (3)
AGP_AD[31..0] (3)
AGP_SBA[7..0] (3)
AGP_ST[2..0] (3)
R3 0R
AGP_REQ# (3)
AGP_RBF# (3)
AGP_DBI_LO (3)
R8 0R
R10 0R
R17 0R
C1127
1.0uF
Title
Size Document Number Rev
B
Date: Sheet of
C1
100uF 16V
ALU
+5V_BUS
AGP_SBSTB (3)
AGP_ADSTB1 (3)
AGP_IRDY# (3)
AGP_DEVSEL#_R (3,23)
AGP_AGPREF (3)
C2
100uF 16V
+3.3V_BUS
AGP_AGPCLK (3,23)
C4
10pF
DNI
C3
100uF 16V
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
2 25Tuesday, March 11, 2003
1
2.1
8
7
6
5
4
3
2
1
D D
PLACE
CLOSE TO
THE ASIC
AGPREFCG
C C
B B
PIN
AGP_C/BE#[3..0]
AGP_ST[2..0]
AGP_SBA[7..0]
AGP_SBSTB(2)
AGP_SBSTB#(2)
AGP_ADSTB0(2)
AGP_ADSTB0#(2)
AGP_ADSTB1(2)
AGP_ADSTB1#(2)
TEST
C14
100nF
AGP_C/BE#[3..0](2)
AGP_ST[2..0](2)
AGP_SBA[7..0](2)
AGP_DEVSEL#_R(2,23)
2N7002E
AGP_AGPCLK(2,23)
AGP_GNT#(2)
AGP_REQ#(2)
AGP_RBF#(2)
AGP_INTR#(2)
AGP_RESET#(2,22,23)
AGP_WBF#(2)
AGP_FRAME#(2)
AGP_TRDY#(2,23)
AGP_IRDY#(2)
AGP_STOP#(2,23)
AGP_PAR(2)
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
+VDDQ_BUS
1
Q2
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
AGP_ST0
AGP_ST1
AGP_ST2
AGP_SBSTB
AGP_SBSTB#
AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
32
R39 169R
R40 71.5R
AV39
AP38
AU39
AM39
AU37
AP35
AM36
AG35
AE35
AH35
AD35
AB35
AA35
AG34
AL36
AF36
AL37
AA39
AD38
AP39
AN39
AN38
AT37
AT38
AT39
AR39
AP36
AP37
AN36
AN37
AR38
AR37
AE37
AD36
AF39
AE38
U42A
PCICLK
GNT#
REQ#
RBF#
INTA#
RST#
WBF#
FRAME#
TRDY#
IRDY#
DEVSEL#
STOP#
PAR
AGPREF
AGPTEST
CBE#0
CBE#1
CBE#2
CBE#3
ST0
ST1
ST2
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
SB_STBF
SB_STBS
AD_STBF0
AD_STBS0
AD_STBF1
AD_STBS1
R300
PART 1 OF 8
A
G
P
/
P
C
I
I
N
T
E
R
F
A
C
E
AGP 8X
TEST_AGPCLK
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
DBI_HI
DBI_LO
AGP8X_DET#
Y36
Y37
AA36
AA37
AB36
AB37
AC36
AD37
AF37
AG36
AG37
AH36
AH37
AJ36
AK37
AK36
Y39
AB39
AA38
AC39
AB38
AD39
AC38
AE39
AG39
AG38
AH39
AH38
AJ39
AJ38
AK39
AK38
AL38
AL39
AL35
AP33
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_DBI_HI
AGP_DBI_LO
AGP_MB_8X_DET#
TEST_AGPCLK
AGP_AD[31..0]
AGP_DBI_HI (2)
AGP_DBI_LO (2)
AGP_MB_8X_DET# (2)
TP1
AGP_AD[31..0] (2)
2N7002E
R23
1K
1
Q1
+VDDQ_BUS+3.3V_BUS
32
R21 1.47K
5
R20
3.32K
R24
1.02K
*
AGP_VREFGC
C6
10nF
AGP_VREFGC (2,23)
4
DNI
AGP_AGPREF(2)
AGP_RESET#(2,22,23)
Title
Size Document Number Rev
B
3
Date: Sheet of
R895 0R
32
Q19
NDS335N
1
AGPREFCG
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
3 25Tuesday, March 11, 2003
1
2.1
8X_DET#(23)
R18
47K
AGP_MB_8X_DET#(2)
AGP_MB_8X_DET#
+5V_BUS
4
5
U2B
6
74ACT08MTC
TEST
UNIVERSAL VREFGC CIRCUIT (2X, 4X, 8X)
A A
8
7
6
8
+VDDDI
1uF
C30
C29
100nF
D D
C C
B B
+VDD2DI
1uF
C36
C35
100nF
APPLICATION
TVout w/ Rage Theatre
ext 24b DDR TMDS
ext 12b DDR TMDS&TVout
24b SDR TMDS
Note1 : PVSS, and MPVSS go to ground plane directly through their own
dedicated via. No connection with other VSS..
Note2 : Separate vias for AVSSQ (A2VSSQ), and AVSSN (A2VSSN) to
ground plane.
Note3 : AVDD/AVSSN power need to use a pair of short traces (20mil at
least) and direct to link to AVDD & AVSSN balls, the ground return point
should be near the ground trace start point.
Note4: Rset resistor ground point should link to AVSSQ trace, or have via
at resistor directly to ground plane.
Note5 : Populate Ra9 and Ra10 only if they are not populated on page
24 or 25 or 31 or 32.
+VDDDI
C28
22uF 16V
+VDD2DI
C34
22uF 16V
TVOVMODE DVOVMODE
0V
VDDC18 VDDC18
0V
0V 0V
B7
Bead
B8
Bead
+VDDC_CT
X
VDDC18
DNI
DNI
+VDDC_CT
+VDDC_CT
7
R45 0R
R46 0R
R47 0R
R48 0R
DVO[11..0](22)
VID[7..0](14,22)
DVO[11..0]
6
VID[7..0]
VID0
VID1
VID2
VID3
VID4
VID5
VID6
TVO0(21,22)
TVO1(22)
TVO2(21,22)
TVO3(22)
TVO4(22)
TVO5(22)
TVO6(14)
TVO7(14)
TVO8(14)
CLK_DVOCLK0(22)
CLK_DVOCLK1(22)
VID7
R43 1K
TVO0
TVO1
TVO2
TVO3
TVO4
TVO5
TVO6
TVO7
TVO8
DVOCNTL0(22)
DVOCNTL1(22)
DVOCNTL2(22)
TEST_MCLK
TEST_YCLK
TP7
TP27
TP28
CLK_VIDCLK(22)
DVALID(14,22)
PSYNC(14)
ROMSCK(14,16)
ROMSO(14,16)
ROMSI(14,16)
ROMCS#(14,16)
TP3
TP4
TESTEN
DVO0
DVO1
DVO2
DVO3
DVO4
DVO5
DVO6
DVO7
DVO8
DVO9
DVO10
DVO11
ROMCS#
+VDDDI
+VDD2DI
Crystal Circuit
DNI
AW35
AV35
AU35
AT35
AW34
AV34
AU34
AT34
AW36
AU36
AV36
AT36
AW21
AV21
AW19
AV19
AU19
AT19
AW20
AV20
AU20
AT20
AU21
AT21
AR19
AT18
AW17
AV17
AU15
AV15
AW15
AT15
AR15
AW16
AV16
AU16
AT16
AU17
AT17
AR17
AW18
AV18
AU18
AP30
AP29
AR29
AR30
AU23
AU27
AU24
AT26
DNI
F9
G6
U42B
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VPCLK0
DVALID
PSYNC
TESTEN
TVOCLKO
TVOCLKI
TVODATA0
TVODATA1
TVODATA2
TVODATA3
TVODATA4
TVODATA5
TVODATA6
TVODATA7
TVODATA8
TVODATA9
TVOVMODE
DVOVMODE
DVOCLK0
DVOCLK1
DVOCNTL0
DVOCNTL1
DVOCNTL2
DVODATA0
DVODATA1
DVODATA2
DVODATA3
DVODATA4
DVODATA5
DVODATA6
DVODATA7
DVODATA8
DVODATA9
DVODATA10
DVODATA11
ROMSCK
ROMSO
ROMSI
ROMCS#
TEST_MCLK
TEST_YCLK
VDD1DI
VDD2DI
VSS1DI
VSS2DI
R300
C40
10pF
C41
10pF
5
PART 2 OF 8
V
Video Capture & Test
I
D
E
O
&
M
U
L
T
I
M
E
D
I
A
TVOut, DVOut & ROM
DNI
DNI
MY1
27 MHZ
DNI
2 1
TXCM
TXCP
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TPVDD
TPVSS
TMDS / Flat PanelDAC / VGAXTAL
TXVDDR
TXVDDR
TXVSSR
TXVSSR
TXVSSR
HPD1
HPD2
DDC1DATA
DDC1CLK
AUXWIN
VSYNC
HSYNC
STEREOSYNC
AVDD
AVDD
AVSSN
AVSSN
AVSSQ
RSET
VIPCLK
VPHCTL
VHAD0
VHAD1
VIP HostI2C
SCL
SDA
XTALOUT
XTALIN
PVDD
PVSS
MPVDD
MPVSS
R2SET
C-R
Y-G
COMP_B
H2SYNC
V2SYNC
DDC2CLK
DAC2 PLL
DDC2DATA
A2VDD
A2VDD
A2VSSN
A2VSSN
A2VDDQ
A2VSSQ
R56 0R
R58 0R
4
AV29
AW29
AV30
AW30
AV31
AW31
AV32
AW32
AW28
AV28
AT29
AT28
AU28
AU29
AU30
AR31
HPD1 (17)
AR33
HPD2 (22)
AU32
CRT1DDCDATA (19)
AU31
CRT1DDCCLK (19)
TP2
AP31
AT30
VSYNC_DAC1 (19)
AT31
HSYNC_DAC1 (19)
AP32
STEREOSYNC (21)
AW24
R
AW23
G
AW22
B
AV23
AV24
AR24
AT24
AU22
R52 499R
AV22
AV33
CLK_VIPCLK (22)
AW33
VPHCTL (22)
AU33
VHAD0 (14,22)
AT33
VHAD1 (22)
AR27
AR28
R300_XOUT
AW38
R300_XIN
AV38
AW37
AV37
+MPVDD
C7
GND_MPVSS
C6
AV25
AW27
AW26
AW25
AR32
AT32
AR34
AR35
AV26
AV27
AT25
AU26
AU25
AT27
DNI
Ra1
TXCM (17)
TXCP (17)
TX0M (17)
TX0P (17)
TX1M (17)
TX1P (17)
TX2M (17)
TX2P (17)
R55 715R
R/C_DAC2 (21)
G/Y_DAC2 (21)
B/COMP_DAC2 (21)
HSYNC_DAC2 (20)
VSYNC_DAC2 (20)
CRT2DDCCLK (20)
CRT2DDCDATA (20)
R57
1M
Ra4
R59 0R
TP34
GND_RSET
C738
SCL
SDA
R300_XOUT
1uF
1uF
C15
C19
22uF 16V
R53
4.7K
GND_R2SET
3
C17
100pF
TXVDDR
+3.3V_BUS+3.3V_BUS
TP35
C20
100pF
R54
4.7K
Ra10Ra9
R300_XIN
R65
0R
Ra8
C16
C18
22uF 16V
100nF
GND_TPVSS
C21
100nF
GND_TXVSSR
GND_AVSSQ
SCL (22)
SDA (22)
1uF
C25
DNI
1uF
C37
Rk
TP33
+A2VDDQ
C38
100nF
B3
R44
0R
DNI
B4
C26
100nF
GND_A2VSSQ
Bead
Ba2
Bead
C27
22uF 16V
C39
22uF 16V
2
Ba1
Ba4
GND_PVSS
1uF
C31
DNI
Ba5
+VDDC_CT+TPVDD
DNI
+VDDC_CT
B6
200R
B9
Bead
1uF
C22
DNI
+VDDC_CT+PVDD
DNI
+A2VDD
C33
100nF
GND_A2VSSN
+VDDC_CT
C24
100nF
C32
22uF 16V
R_DAC1 (19)
G_DAC1 (19)
B_DAC1 (19)
+AVDD
C23
22uF 16V
GND_AVSSN
1
B5
Bead
Ba3
+VDDC_CT
CLOCK SOURCE SELECTION
XTAL/OSC.
CRYSTAL
R300 alone
A A
8
OSC (OPTION 1)
OSC (OPTION 2)
DEFAULT
INSTALL
Ra1,Ra4
Crystal Circuit(27M)
Ra1 = 0R
Oscillator circuit(27M)
Ra4,Ra8
Oscillator circuit(27M)
7
NOT INSTALL
Ra8
Oscillator circuit
Ra4,Ra8
Crystal Circuit
Ra1
Crystal Circuit
6
Oscillator Circuit
+3.3V_BUS
8
C47
4
100nF
Y1
VDD
GND
27.000MHz
R63 107R
5
OUT
1
E/D
+3.3V_BUS
R66
150R
5
4
3
+MPVDD
GND_MPVSS
1uF
1uF
C42
DNI DNI DNI
1uF
C43
C44
Title
Size Document Number Rev
B
Date: Sheet of
+MPVDD +VDDC_CT
C45
100nF
GIGABYTE
R300 128M dual rank DVI VGA VO
2
Ba6
C46
22uF 16V
GND_MPVSS
GV-R9500
B10
200R
DNI
4 25Tuesday, March 11, 2003
1
2.1
5
U42G
M34
VDDR1
F33
VDDR1
H33
VDDR1
R6
VDDR1
U34
VDDR1
L34
VDDR1
N34
VDDR1
T33
REGULATOR
+5V_BUS
DNI
B11 200R
D D
DNI
3 2
AS432S
MREG1
R68
47R
R69
681R
1%
1
R70
1.50K
1%
FOR
DVO/TVO(+1.8V)
DNI
+VTVO/DVO
SC431LC5SK-1
DNI
4
NC
1
NC
2
5 3
DNI DNI
REG1
USE ONLY IF TVO OR DVO MODES ARE 1.8V
C C
VTERM2(15)
B B
+VDDTVO
B12 200R
B13 200R
C709
C74
A A
1uF
100nF
+VDDDVO
B14 200R
C75
1uF
C710
100nF
B15 200R
5
+3.3V_BUS
+VDDTVO
+VDDDVO
+VDDQ_BUS
+3.3V_BUS
+VTVO/DVO
DNI
+3.3V_BUS
+VTVO/DVO
DNI
W33
W34
AP12
AN12
AP11
AN13
AP10
AN14
AR25
AN29
AP26
AN28
AN25
AR22
AR23
AP24
AP27
AP19
AN21
AP20
AN17
AN18
AP15
AR16
AP16
AN34
AM34
AN33
AK33
AJ33
AC33
AB33
AA33
AL33
AJ34
AF34
AB34
AH33
AG33
AF33
AE33
AD33
VDDR1
V33
VDDR1
VDDR1
VDDR1
F11
VDDR1
F28
VDDR1
G13
VDDR1
F14
VDDR1
F16
VDDR1
F17
VDDR1
G23
VDDR1
F25
VDDR1
F27
VDDR1
T34
VDDR1
F31
VDDR1
G8
VDDR1
G26
VDDR1
G10
VDDR1
G11
VDDR1
G17
VDDR1
G18
VDDR1
F19
VDDR1
F20
VDDR1
F21
VDDR1
F22
VDDR1
G25
VDDR1
G29
VDDR1
G30
VDDR1
R33
VDDR1
G32
VDDR1
H7
VDDR1
K6
VDDR1
J7
VDDR1
L6
VDDR1
T7
VDDR1
V6
VDDR1
V7
VDDR1
W6
VDDR1
AF7
VDDR1
D6
VDDR1
AA6
VDDR1
AA7
VDDR1
AB7
VDDR1
AB6
VDDR1
AE6
VDDR1
AD6
VDDR1
AG7
VDDR1
AJ6
VDDR1
AP8
VDDR1
AH6
VDDR1
VDDR1
AN6
VDDR1
AL6
VDDR1
AN8
VDDR1
VDDR1
VDDR1
VDDR1
AN9
VDDR1
VDDR1
G14
VDDR1
F12
VDDR1
VDDR1
F32
VDDR1
H34
VDDR1
M5
VDDR1
G33
VDDR1
U7
VDDR1
AM6
VDDR1
AP7
VDDR1
L33
VDDRH
G22
VDDRH
L7
VDDRH
AL7
VDDRH
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR2
VDDR2
VDDR2
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
Y33
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
R300
PART 7 OF 8
P
O
W
E
R
DISPLAY I/O PWR
4
VDDC18
VDDC18
VDDC18
VDDC18
VDDC18
VDDC18
VDDC18
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
MEMORY I/O
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
CORE
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
AGP / PCI I/O
VDDCI
VDDCI
VDDCI
VDDCI
VSSRH
VSSRH
VSSRH
VSSRH
4
J33
N7
AK7
G20
AN22
AN27
AN32
AV2
AU3
AT4
AR5
AP6
AN7
N13
P13
R13
T13
U13
N14
P14
R14
T14
U14
P15
R15
T15
U15
N16
P16
R16
T16
U16
N17
P17
R17
T17
U17
AC23
AD23
AE23
AF23
AC24
AD24
AE24
AF24
AG24
AC25
AD25
AE25
AF25
AG25
AC26
AD26
AE26
AF26
AG26
AD27
AE27
AF27
AG27
N24
N25
N26
N27
P23
P24
P25
P26
P27
R23
R24
R25
R26
R27
T23
T24
T25
T26
T27
U23
U24
U25
U26
U27
AC14
AC15
AC16
AC17
AD13
AD14
AD15
AD16
AD17
AE13
AE14
AE15
AE16
AE17
AF13
AF14
AF15
AF16
AF17
AG13
AG14
AG15
AG16
AG17
N15
AC27
AG23
AC13
N23
M33
G21
M7
AM7
+VDDC_CT+MVDDQ
+VDDC
3
U42H
AM38
AF38
Y38
AM37
AJ37
AC37
AR36
AE36
AU38
AM35
AJ35
AF35
Y35
AM33
AL34
AN35
AK34
AH34
AE34
AD34
AC34
AA34
Y34
AC35
AK35
AA26
Y26
U37
U33
F29
P35
V35
V13
AU6
N37
T3
B20
AR2
K35
U6
W13
C35
C31
E32
E28
C27
Y13
AA13
E24
G7
E20
AB13
V14
C16
C37
C23
E18
E14
D4
C13
E5
C9
E10
C3
F3
N6
AU13
AR12
AA14
AB14
AA15
AB15
AA16
AB16
AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20
AA21
AB21
AA22
AG5
AD3
AP5
AH3
N3
W5
Y3
AU9
AM3
K5
AC5
W14
AL5
B2
F35
H38
Y14
F6
V15
W15
Y15
V16
W16
Y16
V17
W17
Y17
V18
W18
Y18
V19
W19
Y19
V20
W20
Y20
V21
W21
Y21
V22
W22
Y22
R300
VTERM1(15)
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB22
Part 8 of 8
CORE GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N18
P18
VSS
R18
T18
U18
N19
P19
R19
T19
U19
N20
3
P21
VSS
R21
VSS
T21
VSS
U21
VSS
N22
VSS
P22
VSS
R22
VSS
T22
VSS
U22
VSS
V23
VSS
W23
VSS
Y23
VSS
AA23
VSS
AB23
VSS
V24
VSS
W24
VSS
Y24
VSS
AA24
VSS
AB24
VSS
V25
VSS
W25
VSS
Y25
VSS
AA25
VSS
AB25
VSS
V26
VSS
W26
VSS
AB26
VSS
V27
VSS
W27
VSS
Y27
VSS
AA27
VSS
AB27
VSS
AP28
VSS
AR26
VSS
AG22
VSS
AT22
VSS
AP34
VSS
AR20
VSS
AT23
VSS
AR21
VSS
AN31
VSS
AF22
VSS
AN23
VSS
AP25
VSS
AE22
VSS
AN30
VSS
AD22
VSS
AP22
VSS
AP17
VSS
AR18
VSS
AN19
VSS
AP21
VSS
AC22
VSS
AC21
VSS
AN24
VSS
AN16
VSS
AK6
VSS
AN10
VSS
AN15
VSS
AN20
VSS
AP13
VSS
AP14
VSS
AP18
VSS
AP9
VSS
AN11
VSS
AH7
VSS
AJ7
VSS
AP23
VSS
AF6
VSS
AG6
VSS
AD7
VSS
AE7
VSS
Y6
VSS
W7
VSS
M6
VSS
Y7
VSS
R7
VSS
P7
VSS
T6
VSS
K7
VSS
G12
VSS
F10
VSS
G9
VSS
F13
VSS
F15
VSS
G19
VSS
G15
VSS
G16
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P20
R20
T20
U20
N21
F18
F23
AN26
AC7
F26
G27
G28
F30
G31
J34
K34
K33
J6
N33
P34
V34
R34
P33
AC18
AD18
AE18
AF18
AG18
AG19
AF19
AE19
AD19
AC19
AC20
AD20
AE20
AF20
AG20
AG21
AF21
AE21
AD21
F8
H6
D7
K2
PLACE DIRECTLY
UNDERNEATH
CHANNELS A
AND B
PLACE DIRECTLY
UNDERNEATH
CHANNELS C
AND D
+VDDC_CT
C48
100nF
+VDDC
USE 47uF
TANTALUM
CAPACITOR OR
HIGHER
2
CP1A
10nF
8 1
CP2A
10nF
8 1
+VDDQ_BUS
+3.3V_BUS
+MVDDQ
2
C49
100nF
8 1
7 2
7 2
C64
47uF 16V
CP12A
10nF
CP1B
10nF
CP2B
10nF
C67
22uF 16V
C68
47uF 6.3V
1
C53
C50
C51
100nF
100nF
CP1C
10nF
6 3
CP2C
10nF
6 3
CP4A
CP4B
10nF
10nF
8 1
7 2
C60
10uf
PLACE DIRECTLY
UNDERNEATH ASIC
AT THE OPPOSITE
CORNER OF THE
VDDC FEED.
PLACE DIRECTLY UNDERNEATH
VDDP SECTION OF ASIC.
C65
10uf
8 1
C66
1uF
CP6A
10nF
8 1
C70
C71
10uf
10uf
C72
10uf
CP12B
CP12C
10nF
10nF
7 2
6 3
Title
Size Document Number Rev
Custom
Date: Sheet of
C54
5 4
5 4
CP5A
10nF
7 2
C73
10uf
CP1D
10nF
CP2D
10nF
C61
10uf
8 1
CP6B
10nF
C52
1uF
CP11A
10nF
10uf
C55
1uF
CP3A
10nF
8 1
CP4D
CP4C
10nF
10nF
5 4
6 3
C62
10uf
CP5B
CP5C
10nF
10nF
7 2
6 3
CP11B
10nF
7 2
CP6C
10nF
6 3
CP8A
10nF
8 1
7 2
CP9B
CP9A
10nF
10nF
7 2
8 1
CP12D
CP13A
10nF
10nF
5 4
8 1
7 2
5 4
CP8B
10nF
C56
1uF
CP3B
10nF
5 4
6 3
CP6D
10nF
22uF 16V
C63
10uf
CP5D
10nF
CP11C
10nF
6 3
7 2
C58
10uf
6 3
CP9C
10nF
CP13B
10nF
6 3
8 1
CP8C
10nF
C57
1uF
CP3C
10nF
5 4
CP7A
10nF
Diodes Da1
and Da2 are
needed to
protect ASIC
during power
ramping.
CP11D
10nF
5 4
6 3
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
1
C674
C59
10uf
100nF
5 4
CP9D
10nF
CP13C
10nF
5 4
7 2
CP8D
10nF
C673
1uF
CP3D
10nF
CP7B
10nF
C675
5 4
5 25Tuesday, March 11, 2003
+3.3V_BUS
+3.3V_BUS
100nF
6 3
C69
1uF
C707
100nF
CP13D
10nF
CP7C
10nF
Da1
D2
1.8V
2 1
Da2
D3
2.4V
2 1
CP7D
10nF
5 4
C708
100nF
C676
100nF
2.1
8
7
6
5
4
3
2
1
Layout Guide Lines for switching regulators
1) Feedback trace from the voltage divider resistors to the controller as short as possible.
2) Trace from VIN to Qb1 should be in the same layer, with no via, width no less than 2MM
3) VIN_SOURCE should be a 2-3" snaked trace (with at least 6 bends.) The trace width
should be 2 MM.
4) Components with " ** " should have two vias on each pad
5) Components with " *** " should have three vias on each pad.
6) Connections indicated by bold thick line are high current path. Short, thick traces (at
least 30 mil) should be used.
R77
150R
C86
2.2uF
C88
0.22uF
Cb4
+3.3V_BUS
R90
150R
C92
2.2uF
C152
0.22uF
R78
511R
1%
Rb1
R87
2.43K
1%
Rb2
***
DNI DNI DNI
C80
* * *
C10
470uF 10V
470uF
***
DUAL FOOTPRINT DUAL FOOTPRINT DUAL FOOTPRINT
*
Part
SC1175
IRU3047
SC1175
IRU3047
***
C81
C11
470uF 10V
470uF
***
C10, C11, C12, and C7 are the alternate surface
mount components for C80, C81, C82, C97
respectively.
VDDC Rb2
1.2V
1.5V
Part
INSTALL
Rb4, Rb6, Rb9, Rb10,
Cb4
Rb7, Rb8, Rb5, Cb1, Cb2
Db1, Db2
***
C82
C12
470uF
470uF 10V
*** ***
Rb1
110R 1% DNI
511R 1%
2.43k 1%
DO NOT INSTALL
Rb7, Rb8, Rb5, Cb1,
Cb2, Db2, Db1
Rb4, Rb6, Rb9, Rb10,
Cb4
+VDDC
**
***
C732
470uF
C84
22uF 16V
**
C740
1.0uF
FDS6898A
Q3B
FDS6898A
+5V_BUS
B28
60R
C741
1.0uF
FDS6898A
FDS6898A
+3.3V_BUS
***
PW
71
8
2
53
6
4
R85 100R
+5VEXT
B18
60R
71
8
2
Q4A
53
6
4
Q4B
R92 100R
B16
60R
Q3A
2 1
D25
MBRS340T3
1 2
PW1
2 1
C76
470uF 6.3V
1 2
D26
SK14
C139
10uF
1 2
R89
51.1R
D27
SK14
L1
1.5uH
R76
51.1R
1.5uH
B17
60R
L2
CORE REGULATOR VDDC
+5V_BUS
D D
R72
2.2R
R911
100KR910
10K
DNI
+12V_BUS
R73
2.2R
C87
1uF
C C
C90
1uF
B B
R81 0R
R83 0R
Rb9
Rb10
Rb7 Rb8
DNI
R74
33K
Cb1
DNI
C78
2.2nF
R940
75R
Cb2
DNI
R75
100K
C79
150pF
DNI
C77 1nf
U43
1
VREF
2
+IN2
3
-IN2
4
VCC
5
CL2-
6
CL2+
7
BST2
8
DH2
9
DL2
10 11
PGND BSTC
SC1175CSW
Alternate part IRU3047
PWRGD
SS/ENA
GND
CL1-
CL1+
BST1
R873
DNI
0R
20
C85
19
1nF
18
-IN1
17
16
15
14
13
DH1
12
DL1
PWGOOD_VDDC (2)
DNI
Rb5
R80 0R R82
R84 0R
Rb6
Rb4
0R
place close to U43
place close to U43
C93
10nF
C89
10nF
R71
5.1R
R79
5.1R
C91
470uF
Bb1
R88
5.1R
R91
5.1R
EXTERNAL POWER DETECT
+5V_BUS
Q10
MMBT3906
2
1
3
R876
680R
A A
8
R875
1K
C96
1nf
7
+5VEXT
R879
4.7K
EXT_PWR (14)
6
HEADER 1X4 RA
JUb2
JU2
22uF 16V
1
2
3
4
C101
+5VEXT +12VEXT
B30 60R
B31
60R
C124
C123
2.2uF
22uF 16V
5
C739
6.8uF 25V
C737
6.8uF 25V
4
Title
Size Document Number Rev
B
3
Date: Sheet of
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
6 25Tuesday, March 11, 2003
1
2.1
8
C763
C127
22nf
+PW_VDD
SS_VDD
C129
10nF
R122
15K
220nF
R121
3K
D D
C C
+12V_BUS
C743
220nF
+5V_BUS
DNI
R936
0R
R937
0R
C119
220nF
+12V_BUS
1
2
C734
1uF
DNI
C747
1nf
DNI
COMP_VDD
C128
33pF
7
MVDDC Switching Regulator for
Memory Core for 128M configuration
D6
BAT54SLT1
3
R112
0R C120
U48
2
DNI
Vcc
6
Vc
7
Comp
4
GND
IRU3037ACS
Alternate part IRU3037CS
Alternative 1
R118 10K
U49
2
OCSET
3
SS
4
COMP
5
FB
6
EN
7
GND
ISL6522CB
C107
10nF
BOOT1
C126
2.2nF
R116
27K
DNI
R120
51K
SS_VDD
COMP_VDD
C121 100nF
DNI
HDrv
LDrvSS
Fb
VCCRT
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
6
+PW_VDD
71
Q8A
C764
10nF
R954
10K
2
Q8B
4
53
R113
10R L5 2.2uH
5
38
1
+12V_BUS
141
13
12
11
BOOT1
10
9
8
C744
8
220nF
STS8DNF3LL
6
STS8DNF3LL
5
C745
220nF
Alternative 2
1 2
Cd1
Rd4
D24
S3AB
180uF 16V
C125
10nF
R115
1.5K
4
B29
60R
21
+12V_BUS
B21
***
+12VEXT
60R
**
R114
1%
1.33K
**
C746
10uF
DNI
**
** ***
Rd1
R117
499R
1%
Rd2
3
2
Layout Guide Lines for VDD switching regulator
The same rules apply as for VDDC regulator.
C8 is an alternate surface
*
mount component for C122.
+MVDDC
***
C8
DNI
*
470uF
DUAL FOOTPRINT
C122
470uF 10V
***
C736
470uF
***
Part
IRU3037
IRU3037A
ISL6522CB
IRU3037A
ISL6522CB
MVDDC
2.5V
2.5V
2.9V
Part
IRU3037
IRU3037A
Alternative1
ISL6522CB
Rd1
1.21K
1%
2.55K
1%
1.33K1%499R
INSTALL
1
Rd2
1.21K
1%
1.21K
1%
1%
DO NOT INSTALL
Cd1, Rd4, Alternative2
Alternative1Alternative2
Regulator for VTT Termination
+5V_BUS
+12V_BUS
+12V_BUS
B B
C103
150nF
+MVDDQ
A A
8
+PW_VTT
COMP_VTT
DNI
C105
10nF
R102
15K
C95
100nF
C762
100nF
R103 0R
R100 51K
R101 3K
DNI
C104
33pF
DNI
DNI
7
SS_VTT
C102 2.2nF
R96
27K
DNI
SS_VTT
DNI
R938
0R
BOOT
COMP_VTT
R939
0R
Alternative 1
U44
2
Vcc
6
Vc
7
Comp
4
GND
IRU3037ACS
Alternate part
IRU3037CS
DNI
R99 10K
U45
2
OCSET
3
SS
4
COMP
5
FB
6
EN
7
GND
ISL6522CB
C106
10nF
R93 10R
5
HDrv
38
LDrvSS
1
Fb
DNI
141
VCCRT
13
PVCC
12
LGATE
11
PGND
10
BOOT
9
UGATE
8
PHASE
6
C742
1.0uF
+12V_BUS
BOOT
Alternative 2
+PW_VTT
71
8
Q5A
2
STS8DNF3LL
53
6
Q5B
4
STS8DNF3LL
***
C94
470uF 6.3V
L3 3.3uH
1 2
5
Rb14
Cb5
B19
60R
+5V_BUS
Part
+VTT
** *****
DNI
DNI
C100
10nF
R95
1.5K
R94
825R
1%
Rb11
R97 1.40K
R98
1.10K
1%
DNI
Rb13
C7
470uF
***
DUAL FOOTPRINT
C97
470uF 10V
C98
22uF 16V
** **
+MPVDD
C99
22uF 16V
Rb12
4
3
IRU3037
IRU3037A
ISL6522CB
ISL6522CB
VTT
0.9V
1.25V DNI
0.9V
1.25V
1.40V 825R 1% 1.0K 1% DNI
Part
IRU3037
IRU3037A
Title
Size Document Number Rev
B
Date: Sheet of
Rb11
0R
1.07K 1%
576R 1%
INSTALL
Alternative1
Alternative2
R300 128M dual rank DVI VGA VO
2
Rb12 Rb13
DNI47.5K 1%
8.45K 1%
1.02K 1%
Cb5, Rb14,
Alternative2
Alternative1
GIGABYTE
GV-R9500
75K 1%
DNI
DNI
DNI
DO NOT INSTALL
7 25Tuesday, March 11, 2003
1
2.1
8
7
Regulator for MVDDQ (Memory I/O)
6
+5V_BUS
B22
***
60R
5
4
3
2
1
+1.8V Regulator for VDDC_CT (Core Transform)
D D
+12V_BUS
C133
100nF
C765
C142
150nF
C C
100nF
+MVDDC
+PW_VDDQ
COMP_VDDQ
C143 33pF
DNI
C144
10nF
R135 15K
Alternative 2
B B
+5V_BUS
A A
8
BOOT2
C141
2.2nF
R128
27K
R136 0R
DNI
R133 51K
R134 3K
DNI
SS_VDDQ
DNI
Part
IRU3037
IRU3037A
ISL6522CB
B26 200R
AS432S
MREG5
3 2
+12V_BUS
+5V_BUS
DNI
R9340RR935
0R
Alternative 1
U50
SS_VDDQ
COMP_VDDQ
R132 10K
C108
10nF
2
Vcc
6
Vc
7
Comp
4
GND
IRU3037ACS
Alternate part IRU3037CS
U51
2
OCSET
3
SS
4
COMP
5
FB
6
EN
7
GND
ISL6522CB
5
HDrv
38
LDrvSS
1
Fb
DNI
VCCRT
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
Alternative1 Ce1, Re8, Alternative2
REGULATOR
FOR
MVDD(+1.8V)
REG5
SC431LC5SK-1
5 3
Alternative1
Alternative2
R142
47R
+MPVDD +TPVDD
R144
681R
1%
1
R146
1.50K
1%
4
NC
1
NC
2
GND_MPVSS GND_TPVSS
7
141
13
12
11
10
9
8
DO NOT INSTALLINSTALL
R123 10R
+12V_BUS
BOOT2
+PW_VDDQ
71
8
53
6
C130
470uF 6.3V
Q9A
STS8DNF3LL
Q9B
STS8DNF3LL
L6 3.3uH
1 2
Ce1
Re8
C13 is an alternate surface
*
mount component for C136.
R124
4.99K
C140
10nF
1%
Re4
R127
1.5K
DUAL FOOTPRINT
*
C13
DNI
470uF
+MVDDQ
***
***
C136
470uF 10V
C137
C138
**
22uF 16V
**
**
22uF 16V
**
C748
1.0uF
2
4
Re5
R131
2K
1%
REGULATOR
FOR TPVDD
(+1.8V)
REG6
SC431LC5SK-1
5 3
Re4
1.21K
1%
2.55K
1%
4.99K1%2.0K
681R
1%
1.87K
1%
Part
MVDDQ
IRU3037
IRU3037A
ISL6522CB
IRU3037A
ISL6522CB
IRU3037
IRU3037A
ISL6522CB
+3.3V_BUS
B27 200R
R143
R145
681R
AS432S
1%
1
R147
MREG6
1.50K
1%
3 2
6
2.5V
2.5V
2.8V
1.8V
1.8V
18R
4
NC
1
NC
2
5
Re5
1.21K
1%
1.21K
1%
1%
1.5K
1%
1.5K
1%
4
3
C134
22uF 16V
+3.3V_BUS
B23
REG2
60R
LT1117CST
3 2
IN OUT
C135
100nF
ADJ
1
+3.3V_BUS
USE ONLY IF VDD IS +3.3V
B24
200R
1uF
C145
GND_A2VSSN GND_A2VSSN
+3.3V_BUS
B25 200R
3 2
Title
Size Document Number Rev
B
Date: Sheet of
+VDDC_CT
GND
2
R130
1.33K
1%
R126
562R
1%
+PVDD
VOUT
BYPASS
REGULATOR
FOR PVDD
(+1.8V)
4
NC
1
NC
2
GND_PVSS
C131
100nF
5 3
5
4
REGULATOR
FOR
A2VDD(+2.5V)
C147
470pF
DNI
REG4
SC431LC5SK-1
CASE
AS432S
MREG4
4
REG3
1
VIN
3
SHDN
2.5V
R139
18R
R140
681R
1%
1
R141
1.50K
1%
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
C132
100uF 16V
+A2VDD
1uF
C146
8 25Tuesday, March 11, 2003
1
2.1
5
4
3
2
1
R-300
MEMORY CHANNELS A and B
D D
U42C
R35
DQA0
R36
DQA1
R37
DQA2
P36
DQA3
N36
DQA4
M35
DQA5
M36
DQA6
M37
DQA7
P38
DQA8
P39
DQA9
N38
DQA10
N39
DQA11
L38
DQA12
L39
DQA13
K38
DQA14
K39
DQA15
W35
DQA16
W36
DQA17
W37
C C
B B
V36
U36
W38
W39
V38
V39
R38
R39
E38
D39
D38
C39
B38
A38
B37
A37
E37
D37
E36
D36
D35
E34
D34
C34
B36
A36
B35
A35
B33
A33
B32
A32
E33
D33
C33
D32
D31
E30
D30
C30
DQA18
DQA19
DQA20
T35
DQA21
T36
DQA22
T37
DQA23
DQA24
DQA25
DQA26
DQA27
T38
DQA28
T39
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52
DQA53
DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60
DQA61
DQA62
DQA63
R300
Part 3 of 8
MEMORY INTERFACE
A
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
RASA#
CASA#
WEA#
CSA#
CKEA
CLKA0
CLKA0#
CLKA1
CLKA1#
VREF2
DIMA0
DIMA1
H36
J37
J35
K36
K37
J36
H35
H37
G36
L37
L36
L35
G35
G37
G34
P37
M38
V37
U38
C38
C36
B34
C32
N35
M39
U35
U39
B39
E35
A34
E31
F39
E39
F36
F37
F38
H39
J38
G38
G39
G24
J39
F34
10uF 16V
C149
100nF
+MVDDQ
R137
75.0R
R138
75.0RC148
U42D
E25
DQB0
D25
DQB1
C25
DQB2
D24
DQB3
D23
DQB4
E22
DQB5
D22
DQB6
C22
DQB7
B26
DQB8
A26
DQB9
B25
DQB10
A25
DQB11
B23
DQB12
A23
DQB13
B22
DQB14
A22
DQB15
E29
DQB16
D29
DQB17
C29
DQB18
D28
DQB19
D27
DQB20
E26
DQB21
D26
DQB22
C26
DQB23
B31
DQB24
A31
DQB25
B30
DQB26
A30
DQB27
B28
DQB28
A28
DQB29
B27
DQB30
A27
DQB31
B15
DQB32
A15
DQB33
B14
DQB34
A14
DQB35
B12
DQB36
A12
DQB37
B11
DQB38
A11
DQB39
E15
DQB40
D15
DQB41
C15
DQB42
D14
DQB43
D13
DQB44
E12
DQB45
D12
DQB46
C12
DQB47
B10
DQB48
A10
DQB49
B9
DQB50
A9
DQB51
B7
DQB52
A7
DQB53
B6
DQB54
A6
DQB55
E11
DQB56
D11
DQB57
C11
DQB58
D10
DQB59
D9
DQB60
E8
DQB61
D8
DQB62
C8
DQB63
R300
Part 4 of 8
MEMORY INTERFACE
B
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7
RASB#
CASB#
WEB#
CSB#
CKEB
CLKB0
CLKB0#
CLKB1
CLKB1#
DIMB0
DIMB1
C18
C19
E19
D20
C20
D19
D18
B18
D17
C21
D21
E21
A18
C17
E17
C24
B24
C28
B29
B13
C14
B8
C10
E23
A24
E27
A29
A13
E13
A8
E9
D16
A16
B16
B17
A17
A20
B21
B19
A19
A21
E16
A A
Title
Size Document Number Rev
B
5
4
3
2
Date: Sheet of
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
9 25Tuesday, March 11, 2003
1
2.1
5
4
3
2
1
R-300
MEMORY CHANNELS C and D
MAC8X
MAC9X
D D
R905 0R
R907 0R
R889 0R
R887 0R
MAC8
MAC9
MAD8X MAD8
MAD9X
R906 0R
R908 0R
R890 0R
R888 0R
MAD9
MAC[14..0](11,12,13)
MDC[63..0](11)
C C
B B
A A
MAC[14..0]
MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8 MAC8X
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63
U42E
G4
DQC0
G3
DQC1
H5
DQC2
H4
DQC3
J4
DQC4
J3
DQC5
K4
DQC6
K3
DQC7
D2
DQC8
D1
DQC9
E2
DQC10
E1
DQC11
G2
DQC12
G1
DQC13
H2
DQC14
H1
DQC15
C5
DQC16
C4
DQC17
D5
DQC18
D3
DQC19
E6
DQC20
F5
DQC21
F4
DQC22
G5
DQC23
B5
DQC24
A5
DQC25
B4
DQC26
A4
DQC27
A2
DQC28
B1
DQC29
C2
DQC30
C1
DQC31
P2
DQC32
P1
DQC33
R2
DQC34
R1
DQC35
U2
DQC36
U1
DQC37
V2
DQC38
V1
DQC39
U4
DQC40
U3
DQC41
V5
DQC42
V4
DQC43
W3
DQC44
Y5
DQC45
Y4
DQC46
AA5
DQC47
W2
DQC48
W1
DQC49
Y2
DQC50
Y1
DQC51
AB2
DQC52
AB1
DQC53
AC2
DQC54
AC1
DQC55
AA4
DQC56
AA3
DQC57
AB5
DQC58
AB4
DQC59
AC3
DQC60
AD5
DQC61
AD4
DQC62
AE5
DQC63
R300
Part 5 of 8
MEMORY
INTERFACE C
MAC0
MAC1
MAC2
MAC3
MAC4
MAC5
MAC6
MAC7
MAC8
MAC9
MAC10
MAC11
MAC12
MAC13
MAC14
DQMC#0
DQMC#1
DQMC#2
DQMC#3
DQMC#4
DQMC#5
DQMC#6
DQMC#7
QSC0
QSC1
QSC2
QSC3
QSC4
QSC5
QSC6
QSC7
RASC#
CASC#
WEC#
CSC#
CKEC
CLKC0
CLKC0#
CLKC1
CLKC1#
DIMC0
DIMC1
MAC0
N2
MAC1
N5
MAC2
M2
MAC3
M4
MAC4
M3
MAC5
M1
MAC6
N4
MAC7
N1
P4
MAC9X
L3
MAC10
L4
MAC11
L5
MAC12
P5
MAC13
P3
MAC14
P6
DQMC#0
H3
F2
DQMC#2
E4
DQMC#3
B3
DQMC#4
T2
DQMC#5
V3
DQMC#6
AA2
DQMC#7
AB3
QSC0
J5
QSC1
F1
QSC2
E3
QSC3
A3
QSC4
T1
QSC5
W4
QSC6
AA1
QSC7
AC4
RASC#
R4
CASC#
T4
WEC#
T5
CSC#
R3
R5
K1
J2
L2
L1
R712 0R
J1
R713 0R
U5
MAC8
MAC9
Only for Elpida
memory
DIMC0 (12,13)
DIMC1 (12,13)
MEMVMODE[1:0]
0 1
1 0 1.8V (DDR)
1 1
MAD[14..0](11,12,13)
MDD[63..0](11)
DQMC#[7..0] (11)
QSC[7..0] (11)
RASC# (11,12,13)
CASC# (11,12,13)
WEC# (11,12,13)
CSC# (11,12)
M_CKEC (11,12,13)
M_CLKC0 (11,12,13)
M_CLKC#0 (11,12,13)
M_CLKC1 (11,12,13)
M_CLKC#1 (11,12,13)
MEMORY IO VOLTAGE
2.5V (DDR)
3.3V (SDR)
MAD[14..0]
MDD0
MDD1
MDD2
MDD3
MDD4
MDD5
MDD7
MDD9
MDD10
MDD11
MDD12
MDD13
MDD14
MDD15
MDD16
MDD17
MDD18
MDD19
MDD20
MDD21
MDD22
MDD23
MDD24
MDD25
MDD26
MDD27
MDD28
MDD29
MDD30
MDD31
MDD32
MDD33
MDD34
MDD35
MDD36
MDD37
MDD38
MDD39
MDD40
MDD41
MDD42
MDD43
MDD44
MDD45
MDD46
MDD47
MDD48
MDD49
MDD50
MDD51
MDD52
MDD53
MDD54
MDD55
MDD56
MDD57
MDD58
MDD59
MDD60
MDD61
MDD62
MDD63
AJ4
AJ3
AK5
AK4
AL3
AM5
AM4
AN5
AJ2
AJ1
AK2
AK1
AM2
AM1
AN2
AN1
AE4
AE3
AF5
AF4
AG3
AH5
AH4
AJ5
AD2
AD1
AE2
AE1
AG2
AG1
AH2
AH1
AV5
AW5
AV6
AW6
AV8
AW8
AV9
AW9
AT7
AU7
AR8
AT8
AT9
AR10
AT10
AU10
AV10
AW10
AV11
AW11
AV13
AW13
AV14
AW14
AR11
AT11
AU11
AT12
AT13
AR14
AT14
AU14
MEMMODE0
MEMMODE1
U42F
DQD0
DQD1
DQD2
DQD3
DQD4
DQD5
DQD6
DQD7
DQD8
DQD9
DQD10
DQD11
DQD12
DQD13
DQD14
DQD15
DQD16
DQD17
DQD18
DQD19
DQD20
DQD21
DQD22
DQD23
DQD24
DQD25
DQD26
DQD27
DQD28
DQD29
DQD30
DQD31
DQD32
DQD33
DQD34
DQD35
DQD36
DQD37
DQD38
DQD39
DQD40
DQD41
DQD42
DQD43
DQD44
DQD45
DQD46
DQD47
DQD48
DQD49
DQD50
DQD51
DQD52
DQD53
DQD54
DQD55
DQD56
DQD57
DQD58
DQD59
DQD60
DQD61
DQD62
DQD63
R300
R167
4.7K
Part 6 of 8
MEMORY
INTERFACE D
MEMVMODE0
MEMVMODE1
R164 4.7K
R165 4.7K
R168
4.7K
MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MAD8
MAD9
MAD10
MAD11
MAD12
MAD13
MAD14
DQMD#0
DQMD#1
DQMD#2
DQMD#3
DQMD#4
DQMD#5
DQMD#6
DQMD#7
QSD0
QSD1
QSD2
QSD3
QSD4
QSD5
QSD6
QSD7
RASD#
CASD#
WED#
CSD#
CKED
CLKD0
CLKD0#
CLKD1
CLKD1#
VREF1
DIMD0
DIMD1
MEMTEST
AT3
AT6
AR4
AP3
AR6
AR3
AT5
AU5
AU2
AP4
AN3
AN4
AU4
AU1
AV4
AK3
AL2
AF3
AF2
AV7
AU8
AV12
AU12
AL4
AL1
AG4
AF1
AW7
AR9
AW12
AR13
AW4
AW2
AW3
AV3
AV1
AR1
AP2
AT2
AT1
AC6
AP1
AR7
E7
F7
F24
+VDDC_CT
MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6MDD6
MAD7
MAD8XMDD8
MAD9X
MAD10
MAD11
MAD12
MAD13
MAD14
DQMD#0
DQMD#1
DQMD#2
DQMD#3DQMC#1
DQMD#4
DQMD#5
DQMD#6
DQMD#7
QSD0
QSD1
QSD2
QSD3
QSD4
QSD5
QSD6
QSD7
RASD#
CASD#
WED#
CSD#
R166
47R
MAD8
MAD9
MEMMODE0
MEMMODE1
R714 0R
R715 0R
DQMD#[7..0] (11)
QSD[7..0] (11)
RASD# (11,12,13)
CASD# (11,12,13)
WED# (11,12,13)
CSD# (11,12)
M_CKED (11,12,13)
M_CLKD0 (11,12,13)
M_CLKD#0 (11,12,13)
M_CLKD1 (11,12,13)
M_CLKD#1 (11,12,13)
C150
10uF 16V
Only for Elpida
memory
DIMD0 (12,13)
DIMD1 (12,13)
C151
100nF
+MVDDQ
R773
75.0R
R774
75.0R
Title
Size Document Number Rev
B
5
4
3
2
Date: Sheet of
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
10 25Tuesday, March 11, 2003
1
2.1
8
+MVDDQ
100nF
D D
100nF
+MVDDQ
100nF
C186
100nF
+MVDDQ
100nF
C C
100nF
+MVDDQ
100nF
100nF
+MVDDQ
B B
100nF
C199
100nF
+MVDDQ
100nF
C203
100nF
A A
+MVDDQ
C205
100nF
+VTT
RP91A 56R
RP91B 56R
RP91C 56R
RP91D 56R
C180
RP92A 56R
RP92B 56R
RP92C 56R
RP92D 56R
RP93A 56R
RP93B 56R
RP93C 56R
RP93D 56R
C182
RP94A 56R
RP94B 56R
RP94C 56R
RP94D 56R
RP95A 56R
RP95B 56R
RP95C 56R
RP95D 56R
C184
RP96A 56R
RP96B 56R
RP96C 56R
RP96D 56R
RP97A 56R
RP97B 56R
RP97C 56R
RP97D 56R
RP98A 56R
RP98B 56R
RP98C 56R
RP98D 56R
RP99A 56R
RP99B 56R
RP99C 56R
RP99D 56R
RP100A 56R
C189
RP100B 56R
RP100C 56R
RP100D 56R
RP101A 56R
RP101B 56R
RP101C 56R
RP101D 56R
C190
RP102A 56R
RP102B 56R
RP102C 56R
RP102D 56R
RP103A 56R
RP103B 56R
RP103C 56R
RP103D 56R
RP104A 56R
C192
RP104B 56R
RP104C 56R
RP104D 56R
RP105A 56R
RP105B 56R
RP105C 56R
RP105D 56R
RP106D 56R
C194
RP106C 56R
RP106B 56R
RP106A 56R
RP107D 56R
RP108C 56R
RP108A 56R
RP132C 56R
RP132D 56R
C197
RP108B 56R
RP108D 56R
RP107C 56R
RP109B 56R
RP109A 56R
RP132B 56R
RP132A 56R
RP107B 56R
RP110D 56R
RP107A 56R
R244
R246 56R
R248
R250 56R
R252 56R
R254 56R
R256
C200
R258
RP110A 56R
RP109C 56R
RP110C 56R
RP110B 56R
R734 56R
R735 56R
R736 56R
R737 56R
R738 56R
R739 56R
R740 56R
R741 56R
8
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
5 4
6 3
7 2
8 1
5 4
8 1
6 3
7 2
C207
22uF
MDC0
81
MDC1
72
MDC2
63
MDC3
54
MDC4
81
MDC5
72
MDC6
63
MDC7
54
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
81
MDC17
72
MDC18
63
MDC19
54
MDC20
81
MDC21
72
MDC22
63
MDC23
54
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
81
MDC41
72
MDC42
63
MDC43
54
MDC44
81
MDC45
72
MDC46
63
MDC47
54
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
81
MDC57
72
MDC58
63
MDC59
54
MDC60
MDC61
MDC62
MDC63
MAC0
54
MAC1
63
MAC2
81
MAC3
63
MAC4
54
MAC5
72
MAC6
54
MAC7
63
MAC8
72
MAC9
81
MAC10
72
MAC11
81
MAC12
72
MAC13
MAC14
81
56R
DQMC#0
DQMC#1
56R
DQMC#3
DQMC#4
DQMC#5
DQMC#6
56R
DQMC#7
56R
WEC#
CASC#
63
RASC#
CSC#
QSC0
R262 22R
QSC1
R264 22R
QSC2
R266 22R
QSC3
R268 22R
QSC4
QSC5
R272 22R
QSC6
R274 22R
QSC7
R276 22R
7
MDC0
RP112D 22R
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63
DQMC#[7..0] (10)
WEC# (10,12,13)
CASC# (10,12,13)
RASC# (10,12,13)
CSC# (10,12)
5 4
RP112C 22R
6 3
RP112B 22R
7 2
RP112A 22R
8 1
RP111D 22R
5 4
RP111C 22R
6 3
RP111B 22R
7 2
RP111A 22R
8 1
RP113A 22R
8 1
RP113B 22R
7 2
RP113C 22R
6 3
RP113D 22R
5 4
RP114A 22R
8 1
RP114B 22R
7 2
RP114C 22R
6 3
RP114D 22R
5 4
RP115A 22R
RP115B 22R
RP115C 22R
RP115D 22R
RP116A 22R
RP116B 22R
RP116C 22R
RP116D 22R
RP117A 22R
RP117B 22R
RP117C 22R
RP117D 22R
RP118A 22R
RP118B 22R
RP118C 22R
RP118D 22R
RP119A 22R
RP119B 22R
RP119C 22R
RP119D 22R
RP120A 22R
RP120B 22R
RP120C 22R
RP120D 22R
RP121A 22R
RP121B 22R
RP121C 22R
RP121D 22R
RP122A 22R
RP122B 22R
RP122C 22R
RP122D 22R
RP123A 22R
RP123B 22R
RP123C 22R
RP123D 22R
RP124A 22R
RP124B 22R
RP124C 22R
RP124D 22R
RP125A 22R
RP125B 22R
RP125C 22R
RP125D 22R
RP126A 22R
RP126B 22R
RP126C 22R
RP126D 22R
MAC0 M_MAC0
MAC1 M_MAC1
MAC2 M_MAC2
MAC3 M_MAC3
MAC4 M_MAC4
MAC5 M_MAC5
MAC6 M_MAC6
MAC7 M_MAC7
MAC8 M_MAC8
MAC9 M_MAC9
MAC10 M_MAC10
MAC11 M_MAC11
MAC12 M_MAC12
MAC13 M_MAC13
MAC14 M_MAC14
WEC#
RASC#
CASC#
CSC#
7
M_QSC0
M_QSC1
M_QSC2
M_QSC3
M_QSC4
M_QSC5
M_QSC6
M_QSC7
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
+VTT
81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54
R840 56R
M_MDC0
M_MDC1
M_MDC2
M_MDC3
M_MDC4
M_MDC5
M_MDC6
M_MDC7
M_MDC8
M_MDC9
M_MDC10
M_MDC11
M_MDC12
M_MDC13
M_MDC14
M_MDC15
M_MDC16
M_MDC17
M_MDC18
M_MDC19
M_MDC20
M_MDC21
M_MDC22
M_MDC23
M_MDC24
M_MDC25
M_MDC26
M_MDC27
M_MDC28
M_MDC29
M_MDC30
M_MDC31
M_MDC32
M_MDC33
M_MDC34
M_MDC35
M_MDC36
M_MDC37
M_MDC38
M_MDC39
M_MDC40
M_MDC41
M_MDC42
M_MDC43
M_MDC44
M_MDC45
M_MDC46
M_MDC47
M_MDC48
M_MDC49
M_MDC50
M_MDC51
M_MDC52
M_MDC53
M_MDC54
M_MDC55
M_MDC56
M_MDC57
M_MDC58
M_MDC59
M_MDC60
M_MDC61
M_MDC62
M_MDC63
M_WEC# (10,12,13)
M_RASC# (10,12,13)
M_CASC# (10,12,13)
M_CSC# (10,12)
M_CKEC
DNI
M_QSC[7..0] (12,13)
R841 10K
RP155D 56R
RP109D 56R
6
MDC[63..0]
MAC[14..0]
M_MDC[63..0]
MDC[63..0] (10)
MAC[14..0] (10,12,13)
M_MDC[63..0] (12,13) M_MDD[63..0] (12,13)
Vtt
TERMINATION
for DDR
M_MAC[14..0] (10,12,13)
M_CKEC (10,12,13)
QSC[7..0] (10)
QSC0
QSC1
QSC2
QSC3
QSC4
QSC5
QSC6
QSC7
54
5 4
6
+MVDDQ
100nF
C183
100nF
+MVDDQ
100nF
C187
100nF
+MVDDQ
100nF
C191
100nF
+MVDDQ
100nF
C195
100nF
+MVDDQ
100nF
C198
100nF
+MVDDQ
100nF
C202
100nF
+MVDDQ
100nF
5
C181
C185
C188
C193
C196
C201
C204
5
+VTT
RP136A 56R
RP136B 56R
RP136C 56R
RP136D 56R
RP137A 56R
RP137B 56R
RP137C 56R
RP137D 56R
RP138A 56R
RP138B 56R
RP138C 56R
RP138D 56R
RP139A 56R
RP139B 56R
RP139C 56R
RP139D 56R
RP140A 56R
RP140B 56R
RP140C 56R
RP140D 56R
RP141A 56R
RP141B 56R
RP141C 56R
RP141D 56R
RP142A 56R
RP142B 56R
RP142C 56R
RP142D 56R
RP143A 56R
RP143B 56R
RP143C 56R
RP143D 56R
RP144A 56R
RP144B 56R
RP144C 56R
RP144D 56R
RP145A 56R
RP145B 56R
RP145C 56R
RP145D 56R
RP146A 56R
RP146B 56R
RP146C 56R
RP146D 56R
RP147A 56R
RP147B 56R
RP147C 56R
RP147D 56R
RP148A 56R
RP148B 56R
RP148C 56R
RP148D 56R
RP149A 56R
RP149B 56R
RP149C 56R
RP149D 56R
RP150A 56R
RP150B 56R
RP150C 56R
RP150D 56R
RP151D 56R
RP151C 56R
RP151B 56R
RP151A 56R
RP154A 56R
RP153C 56R
RP153A 56R
RP152B 56R
RP152C 56R
RP153B 56R
RP153D 56R
RP154B 56R
RP155B 56R
RP155A 56R
RP152A 56R
RP152D 56R
RP154C 56R
RP156A 56R
RP154D 56R
R243 56R
R245 56R
R247 56R
R249 56R
R251 56R
R253 56R
R255 56R
R257 56R
RP156D 56R
RP155C 56R
RP156B 56R
RP156C 56R
R742 56R
R743 56R
R744 56R
R745 56R
R746 56R
R747 56R
R748 56R
R749 56R
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
5 4
6 3
7 2
8 1
6 3
8 1
7 2
6 3
7 2
5 4
7 2
8 1
8 1
5 4
6 3
C206
22uF
81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
54
81
72
63
81
54
54
72
63
MDD0
MDD1
MDD2
MDD3
MDD4
MDD5
MDD6
MDD7
MDD8
MDD9
MDD10
MDD11
MDD12
MDD13
MDD14
MDD15
MDD16
MDD17
MDD18
MDD19
MDD20
MDD21
MDD22
MDD23
MDD24
MDD25
MDD26
MDD27
MDD28
MDD29
MDD30
MDD31
MDD32
MDD34
MDD35
MDD36
MDD37
MDD38
MDD39
MDD40
MDD41
MDD42
MDD43
MDD44
MDD45
MDD46
MDD47
MDD48
MDD49
MDD50
MDD51
MDD52
MDD53
MDD54
MDD55
MDD56
MDD57
MDD58
MDD60
MDD61
MDD62
MDD63
MAD0
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
MAD7
MAD8
MAD9
MAD10
MAD11
MAD12
MAD13
MAD14
DQMD#0
DQMD#1
DQMD#2
DQMD#3
DQMD#4
DQMD#5
DQMD#6
DQMD#7
WED#
CASD#
RASD#
CSD#
QSD0
QSD1
QSD2
QSD3
QSD4
QSD5
QSD6
QSD7
4
+VTT
R261 22R
R263 22R
R265 22R
R267 22R
R269 22R
R271 22RR270 22R
R273 22R
R275 22R
4
MDD0
RP160A 22R
MDD1
RP160B 22R
MDD2
RP160C 22R
MDD3
RP160D 22R
MDD4
RP161A 22R
MDD5
RP161B 22R
MDD6
RP161C 22R
MDD7
RP161D 22R
MDD8
RP162A 22R
MDD9
RP162B 22R
MDD10
RP162C 22R
MDD11
RP162D 22R
MDD12
RP163A 22R
MDD13
RP163B 22R
MDD14
RP163C 22R
MDD15
RP163D 22R
MDD16
RP164A 22R
MDD17
RP164B 22R
MDD18
RP164C 22R
MDD19
RP164D 22R
MDD20
RP165A 22R
MDD21
RP165B 22R
MDD22
RP165C 22R
MDD23
RP165D 22R
MDD24
RP166A 22R
MDD25
RP166B 22R
MDD26
RP166C 22R
MDD27
RP166D 22R
MDD28
RP167A 22R
MDD29
RP167B 22R
MDD30MDD33
RP167C 22R
MDD31
RP167D 22R
MDD32
RP168A 22R
MDD33
RP168B 22R
MDD34
RP168C 22R
MDD35
RP168D 22R
MDD36
RP169A 22R
MDD37
RP169B 22R
MDD38
RP169C 22R
MDD39
RP169D 22R
MDD40
RP170A 22R
MDD41
RP170B 22R
MDD42
RP170C 22R
MDD43
RP170D 22R
MDD44
RP171A 22R
MDD45
RP171B 22R
MDD46
RP171C 22R
MDD47
RP171D 22R
MDD48
RP172A 22R
MDD49
RP172B 22R
MDD50
RP172C 22R
MDD51
RP172D 22R
MDD52
RP173A 22R
MDD53
RP173B 22R
MDD54
RP173C 22R
MDD55
RP173D 22R
MDD56MDD59
RP174A 22R
MDD57
RP174B 22R
MDD58
RP174C 22R
MDD59
RP174D 22R
MDD60
RP175A 22R
MDD61
RP175B 22R
MDD62
RP175C 22R
MDD63
RP175D 22R
WED#
RASD#
CASD#
CSD#
DNI
R838 56R
DQMD#[7..0] (10)
WED# (10,12,13)
CASD# (10,12,13)
RASD# (10,12,13)
CSD# (10,12)
M_QSD0
M_QSD1
M_QSD2
M_QSD3
M_QSD4
M_QSD5
M_QSD6
M_QSD7
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
8 1
7 2
6 3
5 4
M_MDD0
81
M_MDD1
72
M_MDD2
63
M_MDD3
54
M_MDD4
81
M_MDD5
72
M_MDD6
63
M_MDD7
54
M_MDD8
M_MDD9
M_MDD10
M_MDD11
M_MDD12
M_MDD13
M_MDD14
M_MDD15
M_MDD16
81
M_MDD17
72
M_MDD18
63
M_MDD19
54
M_MDD20
81
M_MDD21
72
M_MDD22
63
M_MDD23
54
M_MDD24
M_MDD25
M_MDD26
M_MDD27
M_MDD28
M_MDD29
M_MDD30
M_MDD31
M_MDD32
M_MDD33
M_MDD34
M_MDD35
M_MDD36
M_MDD37
M_MDD38
M_MDD39
M_MDD40
81
M_MDD41
72
M_MDD42
63
M_MDD43
54
M_MDD44
81
M_MDD45
72
M_MDD46
63
M_MDD47
54
M_MDD48
M_MDD49
M_MDD50
M_MDD51
M_MDD52
M_MDD53
M_MDD54
M_MDD55
M_MDD56
81
M_MDD57
72
M_MDD58
63
M_MDD59
54
M_MDD60
81
M_MDD61
72
M_MDD62
63
M_MDD63
54
M_WED# (10,12,13)
M_RASD# (10,12,13)
M_CASD# (10,12,13)
M_CSD# (10,12)
M_CKED
R839 10K
QSD0
QSD1
QSD2
QSD3
QSD4
QSD5
QSD6
QSD7
3
M_MDD[63..0]
M_CKED (10,12,13)
QSD[7..0] (10)
M_QSD[7..0] (12,13)
3
MDD[63..0]
MAD[14..0]
M_CLKC1
R834
56R
R224
56R
M_CLKC#1
M_CLKC0
R788
56R
R790
56R
M_CLKC#0
M_CLKD1 M_CLKD0
R836
56R
R226
56R
M_CLKD#1
M_CLKD0
R787
56R
R789
56R
M_CLKD#0
DQMC#0
DQMC#1
DQMC#2
DQMC#3
DQMC#4
DQMC#5
DQMC#6
DQMC#7
DQMD#0
DQMD#1
DQMD#2
DQMD#3
DQMD#4
DQMD#5
DQMD#6
DQMD#7
2
MDD[63..0] (10)
MAD[14..0] (10,12,13)
Differential CLOCK termination
Differential termination should be placed close to the memory.
M_CLKC0
R835
56R
C715
10nF
C838
10nF
C717
10nF
C840
10nF
R227 22R
R228 22R
R229 22R
R230 22R
R231 22R
R232 22R
R233 22R
R234 22R
R235 22R
R236 22R
R237 22R
R238 22R
R239 22R
R240 22R
R241 22R
R242 22R
MAD0 M_MAD0
MAD1 M_MAD1
MAD2 M_MAD2
MAD3 M_MAD3
MAD4 M_MAD4
MAD5 M_MAD5
MAD6 M_MAD6
MAD7 M_MAD7
MAD8 M_MAD8
MAD9 M_MAD9
MAD10 M_MAD10
MAD11 M_MAD11
MAD12 M_MAD12
MAD13 M_MAD13
MAD14 M_MAD14
Title
Size Document Number Rev
B
Date: Sheet of
R300 128M dual rank DVI VGA VO
2
R223
56R
M_CLKC#0
M_CLKC1
R784
56R
R786
56R
M_CLKC#1
R837
56R
R225
56R
M_CLKD#0
M_CLKD1
R783
56R
R785
56R
M_CLKD#1
M_DQMC#0
M_DQMC#1
M_DQMC#2
M_DQMC#3
M_DQMC#4
M_DQMC#5
M_DQMC#6
M_DQMC#7
M_DQMD#0
M_DQMD#1
M_DQMD#2
M_DQMD#3
M_DQMD#4
M_DQMD#5
M_DQMD#6DQMC#2
M_DQMD#7
GIGABYTE
GV-R9500
C716
10nF
C718
10nF
C837
10nF
C839
10nF
1
M_CLKC0 (10,12,13)
M_CLKC#0 (10,12,13)
M_CLKC1 (10,12,13)
M_CLKC#1 (10,12,13)
M_CLKD0 (10,12,13)
M_CLKD#0 (10,12,13)
M_CLKD1 (10,12,13)
M_CLKD#1 (10,12,13)
M_DQMC#[7..0] (12,13)
M_DQMD#[7..0] (12,13)
M_MAD[14..0] (10,12,13)
11 25Tuesday, March 11, 2003
1
2.1
8
M_DQMC#[7..0]
M_DQMC#0
M_DQMC#1
M_DQMC#2
M_DQMC#3
M_DQMC#4
M_DQMC#5
M_DQMC#6
M_DQMD#[7..0]
D D
M_QSC[7..0](11,13)
M_QSD[7..0](11,13)
C C
Only for BGA Elpida memory
M_MAC[14..0](10,11,13)
B B
M_MAD[14..0](10,11,13)
+MVDDQ +MVDDC
A A
C265
C264
100nF
100nF
M_DQMC#7
M_DQMD#0
M_DQMD#1
M_DQMD#2
M_DQMD#3
M_DQMD#4
M_DQMD#5
M_DQMD#6
M_DQMD#7
M_QSC0
M_QSC1
M_QSC2
M_QSC3
M_QSC4
M_QSC5
+MVDDQ
M_QSC6
M_QSC7
M_QSD0
M_QSD1
M_QSD2
M_QSD3
M_QSD4
M_QSD5
M_QSD6
M_QSD7
C266
100nF
M_CKEC
M_WEC#
M_CASC#
M_RASC#
M_CSC#
M_CLKC0
M_CLKC1
M_CLKC#0
M_CLKC#1
M_CKED
M_WED#
M_CASD#
M_RASD#
M_CSD#
M_CLKD0
M_CLKD1
M_CLKD#0
M_CLKD#1
DIMC0
DIMC1
DIMD0
DIMD1
M_MAC0
M_MAC1
M_MAC2
M_MAC3
M_MAC4
M_MAC5
M_MAC6
M_MAC7
M_MAC8
M_MAC9
M_MAC10
M_MAC11
M_MAC12
M_MAC13
M_MAC14
M_MAD0
M_MAD1
M_MAD2
M_MAD3
M_MAD4
M_MAD5
M_MAD6
M_MAD7
M_MAD8
M_MAD9
M_MAD10
M_MAD11
M_MAD12
M_MAD13
M_MAD14
C267
100nF
M_CKEC(10,11,13)
M_WEC#(10,11,13)
M_CASC#(10,11,13)
M_RASC#(10,11,13)
M_CSC#(10,11)
M_CLKC0(10,11,13)
M_CLKC1(10,11,13)
M_CLKC#0(10,11,13)
M_CLKC#1(10,11,13)
M_CKED(10,11,13)
M_WED#(10,11,13)
M_CASD#(10,11,13)
M_RASD#(10,11,13)
M_CSD#(10,11)
M_CLKD0(10,11,13)
M_CLKD1(10,11,13)
M_CLKD#0(10,11,13)
M_CLKD#1(10,11,13)
DIMC0(10,13)
DIMC1(10,13)
DIMD0(10,13)
DIMD1(10,13)
+MVDDQ +MVDDC
C284
100nF
C285
100nF
C286
C287
100nF
100nF
8
C268
100nF
C288
100nF
7
6
5
4
3
64MBytes DDR 128Mbit 1Mx32x4 uBGA Channels C and D - rank1
M_MAC12
M_MAC13
M_MAC11
M_MAC10
M_MAC9
M_MAC8
M_MAC7
M_MAC6
M_MAC5
M_MAC4
M_MAC3
M_MAC2
M_MAC1
M_MAC0
R285
4.99K
C256
R289
DIMC0 DIMC1 DIMD0 DIMD1
4.99K
100nF
M_CLKC#0
M_CSC#
M_RASC#
M_CASC#
M_WEC#
M_DQMC#1
M_DQMC#2
M_DQMC#0
M_DQMC#3
M_CKEC
M_QSC1
M_QSC2
M_QSC0
M_QSC3
U56
M3
BA0
L4
BA1
L6
A11
K5
A10
L7
A9
M10
A8/AP
M9
A7
M8
A6
L8
A5
M7
A4
M6
A3
L5
A2
M5
A1
M4
A0
B3
NC
B10
NC
G3
NC
G10
NC
K11
NC
K12
NC
L2
NC
L3
NC
M2
NC
L12
MCL
M12
VREF
L9
RFU
K8
RFU
L11
CLK
M1
CS
L1
RAS
K1
CAS
K2
WE
A11
DM3
G2
DM2
G11
DM1
A2
DM0
L10
CLK
M11
CKE
A12
DQS3
G1
DQS2
G12
DQS1
A1
DQS0
E5
TH GND
E6
TH GND
E7
TH GND
E8
TH GND
F5
TH GND
F6
TH GND
F7
TH GND
F8
TH GND
G5
TH GND
G6
TH GND
G7
TH GND
G8
TH GND
H5
TH GND
H6
TH GND
H7
TH GND
H8
TH GND
1Mx32x4
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M_MDC8
A7
M_MDC9
B8
M_MDC10
A8
M_MDC11
A9
M_MDC12
B12
M_MDC13
C11
M_MDC14
C12
M_MDC15
D12
M_MDC16
J2
M_MDC17
J1
M_MDC18
H1
M_MDC19
H2
M_MDC20
F1
M_MDC21
F2
M_MDC22
E1
M_MDC23
E2
M_MDC0
E11
M_MDC1
E12
M_MDC2
F11
M_MDC3
F12
M_MDC4
H11
M_MDC5
H12
M_MDC6
J11
M_MDC7
J12
M_MDC24
D1
M_MDC25
C1
M_MDC26
C2
M_MDC27
B1
M_MDC28
A4
M_MDC29
A5
M_MDC30
B5
M_MDC31
A6
B2
B4
+MVDDQ
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6
+MVDDC +MVDDC
C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
+MVDDQ
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
+MVDDC
H4
H9
J4
J9
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
M_MAC12
M_MAC13
M_MAC11
M_MAC10
M_MAC9
M_MAC8
M_MAC7
M_MAC6
M_MAC5
M_MAC4
M_MAC3
M_MAC2
M_MAC1
M_MAC0
+MVDDQ +MVDDQ
R286
4.99K
R290
C258
4.99K
100nF
M_CLKC#1
M_CSC#
M_RASC#
M_CASC#
M_WEC#
M_DQMC#5
M_DQMC#6
M_DQMC#4
M_DQMC#7
M_CLKC1
M_CKEC
M_QSC5
M_QSC6
C684
10uF
M_QSC4
M_QSC7
+MVDDC
C262
10uF
C688
10uF
U57
M3
BA0
L4
BA1
L6
A11
K5
A10
L7
A9
M10
A8/AP
M9
A7
M8
A6
L8
A5
M7
A4
M6
A3
L5
A2
M5
A1
M4
A0
B3
NC
B10
NC
G3
NC
G10
NC
K11
NC
K12
NC
L2
NC
L3
NC
M2
NC
L12
MCL
M12
VREF
L9
RFU
K8
RFU
L11
CLK
M1
CS
L1
RAS
K1
CAS
K2
WE
A11
DM3
G2
DM2
G11
DM1
A2
DM0
L10
CLK
M11
CKE
A12
DQS3
G1
DQS2
G12
DQS1
A1
DQS0
E5
TH GND
E6
TH GND
E7
TH GND
E8
TH GND
F5
TH GND
F6
TH GND
F7
TH GND
F8
TH GND
G5
TH GND
G6
TH GND
G7
TH GND
G8
TH GND
H5
TH GND
H6
TH GND
H7
TH GND
H8
TH GND
1Mx32x4
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M_MDC47
A7
M_MDC46
B8
M_MDC45
A8
M_MDC44
A9
M_MDC43
B12
M_MDC42
C11
M_MDC41
C12
M_MDC40
D12
M_MDC55
J2
M_MDC54
J1
M_MDC53
H1
M_MDC52
H2
M_MDC51
F1
M_MDC50
F2
M_MDC49
E1
M_MDC48
E2
M_MDC39
E11
M_MDC38
E12
M_MDC37
F11
M_MDC36
F12
M_MDC35
H11
M_MDC34
H12
M_MDC33
J11
M_MDC32
J12
M_MDC63
D1
M_MDC62
C1
M_MDC61
C2
M_MDC60
B1
M_MDC59
A4
M_MDC58
A5
M_MDC57
B5
M_MDC56
A6
B2
B4
+MVDDQ +MVDDQ
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6
C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
+MVDDQ
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
C685
10uF
M_MAD12
M_MAD13
M_MAD11
M_MAD10
M_MAD9
M_MAD8
M_MAD7
M_MAD6
M_MAD5
M_MAD4
M_MAD3
M_MAD2
M_MAD1
M_MAD0
+MVDDQ
R288
4.99K
R291
4.99K
+MVDDQ
+MVDDQ
C257
100nF
M_CLKD#0
M_CSD#
M_RASD#
M_CASD#
M_WED#
M_DQMD#1
M_DQMD#2
M_DQMD#0
M_DQMD#3
M_CLKD0M_CLKC0
M_CKED
M_QSD1
M_QSD2
M_QSD0
M_QSD3
C260
22uF 16V
C263
10uF
M_MDC[63..0](11,13)
M_MDD[63..0](11,13)
+MVDDQ
+MVDDQ
C269
100nF
C289
100nF
7
C270
100nF
C290
100nF
+MVDDC
C272
C271
100nF
100nF
+MVDDC +MVDDQ
C291
C292
100nF
100nF
C273
100nF
C293
100nF
6
+MVDDQ
+MVDDQ
C274
100nF
C294
100nF
C275
100nF
C295
100nF
C276
100nF
C296
100nF
+MVDDC
5
C277
100nF
C297
100nF
C278
100nF
C298
100nF
+MVDDQ +MVDDC
C280
100nF
C281
100nF
C279
100nF
+MVDDC+MVDDC
C299
C300
100nF
C301
100nF
4
100nF
C282
100nF
C302
100nF
U58
M3
BA0
L4
BA1
L6
A11
K5
A10
L7
A9
M10
A8/AP
M9
A7
M8
A6
L8
A5
M7
A4
M6
A3
L5
A2
M5
A1
M4
A0
B3
NC
B10
NC
G3
NC
G10
NC
K11
NC
K12
NC
L2
NC
L3
NC
M2
NC
L12
MCL
M12
VREF
L9
RFU
K8
RFU
L11
CLK
M1
CS
L1
RAS
K1
CAS
K2
WE
A11
DM3
G2
DM2
G11
DM1
A2
DM0
L10
CLK
M11
CKE
A12
DQS3
G1
DQS2
G12
DQS1
A1
DQS0
E5
TH GND
E6
TH GND
E7
TH GND
E8
TH GND
F5
TH GND
F6
TH GND
F7
TH GND
F8
TH GND
G5
TH GND
G6
TH GND
G7
TH GND
G8
TH GND
H5
TH GND
H6
TH GND
H7
TH GND
H8
TH GND
1Mx32x4
C283
100nF
C303
100nF
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
3
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M_MDD8
A7
M_MDD9
B8
M_MDD10
A8
M_MDD11
A9
M_MDD12
B12
M_MDD13
C11
M_MDD14
C12
M_MDD15
D12
M_MDD16
J2
M_MDD17
J1
M_MDD18
H1
M_MDD19
H2
M_MDD20
F1
M_MDD21
F2
M_MDD22
E1
M_MDD23
E2
M_MDD0
E11
M_MDD1
E12
M_MDD2
F11
M_MDD3
F12
M_MDD4
H11
M_MDD5
H12
M_MDD6
J11
M_MDD7
J12
M_MDD24
D1
M_MDD25
C1
M_MDD26
C2
M_MDD27
B1
M_MDD28
A4
M_MDD29
A5
M_MDD30
B5
M_MDD31
A6
B2
B4
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6
+MVDDC +MVDDC
C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
+MVDDC +MVDDQ
E9
F4
F9
G4
G9
H4
H9
J4
J9
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
2
U59
M3
BA0
L4
BA1
L6
A11
K5
A10
L7
A9
M10
A8/AP
M9
A7
M8
A6
L8
A5
M7
A4
M6
A3
L5
A2
M5
A1
M4
A0
B3
NC
B10
NC
G3
NC
G10
NC
K11
NC
K12
NC
L2
NC
L3
NC
M2
NC
L12
MCL
M12
VREF
L9
RFU
K8
RFU
L11
CLK
M1
CS
L1
RAS
K1
CAS
K2
WE
A11
DM3
G2
DM2
G11
DM1
A2
DM0
L10
CLK
M11
CKE
A12
DQS3
G1
DQS2
G12
DQS1
A1
DQS0
R292
4.99K
M_MAD12
M_MAD13
M_MAD11
M_MAD10
M_MAD9
M_MAD8
M_MAD7
M_MAD6
M_MAD5
M_MAD4
M_MAD3
M_MAD2
M_MAD1
M_MAD0
R287
4.99K
C259
100nF
M_CLKD#1
M_CSD#
M_RASD#
M_CASD#
M_WED#
M_DQMD#5
M_DQMD#6
M_DQMD#4
M_DQMD#7
M_CLKD1
M_CKED
M_QSD5
M_QSD6
M_QSD4
M_QSD7
+MVDDC
C686
10uF
C261
10uF
E5
TH GND
E6
TH GND
E7
TH GND
E8
TH GND
F5
TH GND
F6
TH GND
F7
TH GND
F8
TH GND
G5
TH GND
G6
TH GND
G7
TH GND
G8
TH GND
H5
TH GND
H6
TH GND
H7
TH GND
H8
TH GND
1Mx32x4
Title
Size Document Number Rev
B
Date: Sheet of
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
M_MDD47
A7
M_MDD46
B8
M_MDD45
A8
M_MDD44
A9
M_MDD43
B12
M_MDD42
C11
M_MDD41
C12
M_MDD40
D12
M_MDD55
J2
M_MDD54
J1
M_MDD53
H1
M_MDD52
H2
M_MDD51
F1
M_MDD50
F2
M_MDD49
E1
M_MDD48
E2
M_MDD39
E11
M_MDD38
E12
M_MDD37
F11
M_MDD36
F12
M_MDD35
H11
M_MDD34
H12
M_MDD33
J11
M_MDD32
J12
M_MDD63
D1
M_MDD62
C1
M_MDD61
C2
M_MDD60
B1
M_MDD59
A4
M_MDD58
A5
M_MDD57
B5
M_MDD56
A6
B2
B4
+MVDDQ
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6
C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
12 25Tuesday, March 11, 2003
1
C687
10uF
2.1
8
M_DQMC#[7..0]
M_DQMC#0
M_DQMC#1
M_DQMC#2
M_DQMC#3
M_DQMC#4
M_DQMC#5
M_DQMC#6
M_DQMD#[7..0]
D D
M_QSC[7..0](11,12)
M_QSD[7..0](11,12)
C C
Only for BGA Elpida memory
M_MAC[14..0](10,11,12)
B B
M_MAD[14..0](10,11,12)
+MVDDQ +MVDDC
A A
C797
C798
100nF
100nF
M_DQMC#7
M_DQMD#0
M_DQMD#1
M_DQMD#2
M_DQMD#3
M_DQMD#4
M_DQMD#5
M_DQMD#6
M_DQMD#7
M_QSC0
M_QSC1
M_QSC2
M_QSC3
M_QSC4
M_QSC5
M_QSC6
+MVDDQ
M_QSC7
M_QSD0
M_QSD1
M_QSD2
M_QSD3
M_QSD4
M_QSD5
M_QSD6
M_QSD7
C799
100nF
M_CKEC
M_WEC#
M_CASC#
M_RASC#
M_CSC#
M_CLKC0
M_CLKC1
M_CLKC#0
M_CLKC#1
M_CKED
M_WED#
M_CASD#
M_RASD#
M_CSD#
M_CLKD0
M_CLKD1
M_CLKD#0
M_CLKD#1
DIMC0
DIMC1
DIMD0
DIMD1
M_MAC0
M_MAC1
M_MAC2
M_MAC3
M_MAC4
M_MAC5
M_MAC6
M_MAC7
M_MAC8
M_MAC9
M_MAC10
M_MAC11
M_MAC12
M_MAC13
M_MAC14
M_MAD0
M_MAD1
M_MAD2
M_MAD3
M_MAD4
M_MAD5
M_MAD6
M_MAD7
M_MAD8
M_MAD9
M_MAD10
M_MAD11
M_MAD12
M_MAD13
M_MAD14
C800
100nF
M_CKEC(10,11,12)
M_WEC#(10,11,12)
M_CASC#(10,11,12)
M_RASC#(10,11,12)
M_CSC#(10,11,12)
M_CLKC0(10,11,12)
M_CLKC1(10,11,12)
M_CLKC#0(10,11,12)
M_CLKC#1(10,11,12)
M_CKED(10,11,12)
M_WED#(10,11,12)
M_CASD#(10,11,12)
M_RASD#(10,11,12)
M_CSD#(10,11,12)
M_CLKD0(10,11,12)
M_CLKD1(10,11,12)
M_CLKD#0(10,11,12)
M_CLKD#1(10,11,12)
DIMC0(10,12)
DIMC1(10,12)
DIMD0(10,12)
DIMD1(10,12)
+MVDDQ +MVDDC
C819
C817
100nF
C818
100nF
8
100nF
C820
100nF
7
6
5
4
3
64MBytes DDR 128Mbit 1Mx32x4 uBGA Channels C and D - rank2
C815
100nF
C835
100nF
U68
M3
BA0
L4
BA1
L6
A11
K5
A10
L7
A9
M10
A8/AP
M9
A7
M8
A6
L8
A5
M7
A4
M6
A3
L5
A2
M5
A1
M4
A0
B3
NC
B10
NC
G3
NC
G10
NC
K11
NC
K12
NC
L2
NC
L3
NC
M2
NC
L12
MCL
M12
VREF
L9
RFU
K8
RFU
L11
CLK
M1
CS
L1
RAS
K1
CAS
K2
WE
A11
DM3
G2
DM2
G11
DM1
A2
DM0
L10
CLK
M11
CKE
A12
DQS3
G1
DQS2
G12
DQS1
A1
DQS0
E5
TH GND
E6
TH GND
E7
TH GND
E8
TH GND
F5
TH GND
F6
TH GND
F7
TH GND
F8
TH GND
G5
TH GND
G6
TH GND
G7
TH GND
G8
TH GND
H5
TH GND
H6
TH GND
H7
TH GND
H8
TH GND
1Mx32x4
C816
100nF
C836
100nF
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
3
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M_MDD31
A7
M_MDD30
B8
M_MDD29
A8
M_MDD28
A9
M_MDD27
B12
M_MDD26
C11
M_MDD25
C12
M_MDD24
D12
M_MDD6
J2
M_MDD7
J1
M_MDD5
H1
M_MDD4
H2
M_MDD3
F1
M_MDD2
F2
M_MDD1
E1
M_MDD0
E2
M_MDD23
E11
M_MDD22
E12
M_MDD21
F11
M_MDD20
F12
M_MDD19
H11
M_MDD18
H12
M_MDD16
J11
M_MDD17
J12
M_MDD15
D1
M_MDD14
C1
M_MDD13
C2
M_MDD12
B1
M_MDD11
A4
M_MDD10
A5
M_MDD9
B5
M_MDD8
A6
B2
B4
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6
+MVDDC +MVDDC
C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
+MVDDC +MVDDQ
E9
F4
F9
G4
G9
H4
H9
J4
J9
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
M_MAC12
M_MAC13
M_MAC11
M_MAC10
M_MAC9
M_MAC8
M_MAC7
M_MAC6
M_MAC5
M_MAC4
M_MAC3
M_MAC2
M_MAC1
M_MAC0
R391
4.99K
VREF2_C0
C784
R392
100nF
4.99K
M_CLKC#0
M_MAC14 M_MAD14 M_MAD14
M_RASC#
M_CASC#
M_WEC#
M_DQMC#3
M_DQMC#0
M_DQMC#2
M_DQMC#1
M_CKEC
M_QSC3
M_QSC0
M_QSC2
M_QSC1
U66
M3
BA0
L4
BA1
L6
A11
K5
A10
L7
A9
M10
A8/AP
M9
A7
M8
A6
L8
A5
M7
A4
M6
A3
L5
A2
M5
A1
M4
A0
B3
NC
B10
NC
G3
NC
G10
NC
K11
NC
K12
NC
L2
NC
L3
NC
M2
NC
L12
MCL
M12
VREF
DIMC0 DIMC1 DIMD0 DIMD1
L9
RFU
K8
RFU
L11
CLK
M1
CS
L1
RAS
K1
CAS
K2
WE
A11
DM3
G2
DM2
G11
DM1
A2
DM0
L10
CLK
M11
CKE
A12
DQS3
G1
DQS2
G12
DQS1
A1
DQS0
E5
TH GND
E6
TH GND
E7
TH GND
E8
TH GND
F5
TH GND
F6
TH GND
F7
TH GND
F8
TH GND
G5
TH GND
G6
TH GND
G7
TH GND
G8
TH GND
H5
TH GND
H6
TH GND
H7
TH GND
H8
TH GND
1Mx32x4
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M_MDC31
A7
M_MDC30
B8
M_MDC29
A8
M_MDC28
A9
M_MDC27
B12
M_MDC26
C11
M_MDC25
C12
M_MDC24
D12
M_MDC6
J2
M_MDC7
J1
M_MDC5
H1
M_MDC4
H2
M_MDC3
F1
M_MDC2
F2
M_MDC1
E1
M_MDC0
E2
M_MDC23
E11
M_MDC22
E12
M_MDC21
F11
M_MDC20
F12
M_MDC19
H11
M_MDC18
H12
M_MDC16
J11
M_MDC17
J12
M_MDC15
D1
M_MDC14
C1
M_MDC13
C2
M_MDC12
B1
M_MDC11
A4
M_MDC10
A5
M_MDC9
B5
M_MDC8
A6
B2
B4
+MVDDQ
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6
+MVDDC +MVDDC
C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
+MVDDQ
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
+MVDDC
H4
H9
J4
J9
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
M_MAC12
M_MAC13
M_MAC11
M_MAC10
M_MAC9
M_MAC8
M_MAC7
M_MAC6
M_MAC5
M_MAC4
M_MAC3
M_MAC2
M_MAC1
M_MAC0
+MVDDQ +MVDDQ +MVDDQ
R384
4.99K
VREF2_C1 VREF2_D1
R385
C785
4.99K
100nF
M_CLKC#1
M_MAC14
M_RASC#
M_CASC#
M_WEC#
M_DQMC#7
M_DQMC#4
M_DQMC#6
M_DQMC#5
M_CLKC1
M_CKEC
M_QSC7
M_QSC4
C788
10uF
M_QSC6
M_QSC5
+MVDDC
C794
10uF
C795
10uF
U67
M3
BA0
L4
BA1
L6
A11
K5
A10
L7
A9
M10
A8/AP
M9
A7
M8
A6
L8
A5
M7
A4
M6
A3
L5
A2
M5
A1
M4
A0
B3
NC
B10
NC
G3
NC
G10
NC
K11
NC
K12
NC
L2
NC
L3
NC
M2
NC
L12
MCL
M12
VREF
L9
RFU
K8
RFU
L11
CLK
M1
CS
L1
RAS
K1
CAS
K2
WE
A11
DM3
G2
DM2
G11
DM1
A2
DM0
L10
CLK
M11
CKE
A12
DQS3
G1
DQS2
G12
DQS1
A1
DQS0
E5
TH GND
E6
TH GND
E7
TH GND
E8
TH GND
F5
TH GND
F6
TH GND
F7
TH GND
F8
TH GND
G5
TH GND
G6
TH GND
G7
TH GND
G8
TH GND
H5
TH GND
H6
TH GND
H7
TH GND
H8
TH GND
1Mx32x4
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M_MDC56
A7
M_MDC57
B8
M_MDC58
A8
M_MDC59
A9
M_MDC60
B12
M_MDC61
C11
M_MDC62
C12
M_MDC63
D12
M_MDC33
J2
M_MDC32
J1
M_MDC34
H1
M_MDC35
H2
M_MDC36
F1
M_MDC37
F2
M_MDC38
E1
M_MDC39
E2
M_MDC48
E11
M_MDC49
E12
M_MDC50
F11
M_MDC51
F12
M_MDC52
H11
M_MDC53
H12
M_MDC55
J11
M_MDC54
J12
M_MDC40
D1
M_MDC41
C1
M_MDC42
C2
M_MDC43
B1
M_MDC44
A4
M_MDC45
A5
M_MDC46
B5
M_MDC47
A6
B2
B4
+MVDDQ +MVDDQ
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6
C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
+MVDDQ
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
C789
10uF
R386
4.99K
R387
4.99K
+MVDDQ
+MVDDQ
M_MAD12
M_MAD13
M_MAD11
M_MAD10
M_MAD9
M_MAD8
M_MAD7
M_MAD6
M_MAD5
M_MAD4
M_MAD3
M_MAD2
M_MAD1
M_MAD0
VREF2_D0
C786
100nF
M_CLKD#0
M_RASD#
M_CASD#
M_WED#
M_DQMD#3
M_DQMD#0
M_DQMD#2
M_DQMD#1
M_CLKD0M_CLKC0
M_CKED
M_QSD3
M_QSD0
M_QSD2
M_QSD1
C790
22uF 16V
C796
10uF
M_MDC[63..0](11,12)
M_MDD[63..0](11,12)
C801
100nF
C821
100nF
+MVDDQ
+MVDDQ
C802
100nF
C822
100nF
7
C803
100nF
C823
100nF
+MVDDC
C805
C804
100nF
100nF
+MVDDC +MVDDQ
C825
C824
100nF
100nF
C806
100nF
C826
100nF
6
+MVDDQ
+MVDDQ
C807
100nF
C827
100nF
C808
100nF
C828
100nF
C809
100nF
C829
100nF
+MVDDC
5
C810
100nF
C700
100nF
C811
100nF
C831
100nF
+MVDDQ +MVDDC
C812
C813
100nF
C814
100nF
100nF
+MVDDC+MVDDC
C832
100nF
C833
100nF
C834
100nF
4
2
U69
M3
BA0
L4
BA1
L6
A11
K5
A10
L7
A9
M10
A8/AP
M9
A7
M8
A6
L8
A5
M7
A4
M6
A3
L5
A2
M5
A1
M4
A0
B3
NC
B10
NC
G3
NC
G10
NC
K11
NC
K12
NC
L2
NC
L3
NC
M2
NC
L12
MCL
M12
VREF
L9
RFU
K8
RFU
L11
CLK
M1
CS
L1
RAS
K1
CAS
K2
WE
A11
DM3
G2
DM2
G11
DM1
A2
DM0
L10
CLK
M11
CKE
A12
DQS3
G1
DQS2
G12
DQS1
A1
DQS0
R389
4.99K
M_MAD12
M_MAD13
M_MAD11
M_MAD10
M_MAD9
M_MAD8
M_MAD7
M_MAD6
M_MAD5
M_MAD4
M_MAD3
M_MAD2
M_MAD1
M_MAD0
R388
4.99K
C787
100nF
M_CLKD#1
M_RASD#
M_CASD#
M_WED#
M_DQMD#7
M_DQMD#4
M_DQMD#6
M_DQMD#5
M_CLKD1
M_CKED
M_QSD7
M_QSD4
M_QSD6
M_QSD5
+MVDDC
C791
10uF
C792
10uF
E5
TH GND
E6
TH GND
E7
TH GND
E8
TH GND
F5
TH GND
F6
TH GND
F7
TH GND
F8
TH GND
G5
TH GND
G6
TH GND
G7
TH GND
G8
TH GND
H5
TH GND
H6
TH GND
H7
TH GND
H8
TH GND
1Mx32x4
Title
Size Document Number Rev
B
Date: Sheet of
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
M_MDD56
A7
M_MDD57
B8
M_MDD58
A8
M_MDD59
A9
M_MDD60
B12
M_MDD61
C11
M_MDD62
C12
M_MDD63
D12
M_MDD33
J2
M_MDD32
J1
M_MDD34
H1
M_MDD35
H2
M_MDD36
F1
M_MDD37
F2
M_MDD38
E1
M_MDD39
E2
M_MDD48
E11
M_MDD49
E12
M_MDD50
F11
M_MDD51
F12
M_MDD52
H11
M_MDD53
H12
M_MDD55
J11
M_MDD54
J12
M_MDD40
D1
M_MDD41
C1
M_MDD42
C2
M_MDD43
B1
M_MDD44
A4
M_MDD45
A5
M_MDD46
B5
M_MDD47
A6
B2
B4
+MVDDQ
B6
B7
B9
B11
D2
D11
E3
E10
F3
F10
H3
H10
J3
J10
C6
C7
D3
D10
K3
K6
K7
K10
A3
A10
C3
C4
C5
C8
C9
C10
D5
D8
E4
E9
F4
F9
G4
G9
H4
H9
J4
J9
D4
D6
D7
D9
J5
J6
J7
J8
K4
K9
13 25Tuesday, March 11, 2003
1
C793
10uF
2.1
8
7
6
5
4
3
2
1
STRAPS
AGPFBSKEW -- VID(1:0)
Ra2
DNI
Ri5
R333 10K
Ri6
D D
R334 10K
Ri7
R335 10K
Ri8
R336 10K
+3.3V_BUS
Ra1
R337 10K
Ra2
R338 10K
Ra3
R339 10K
Ra4
R340 10K
Ra5
R341 10K
Ra6
R342 10K
Ra7
R343 10K
Ri1
R344 10K
Ri2
R345 10K
Ri3
R346 10K
DNI
DNI
DNI
DNI
DNI
DNI
DNI
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID[7..0]
VID[7..0] (4,22)
DNI
10K
10K
INSTALL
Rh1
Rh2
INSTALL
Rh4
C C
DVALID(4,22)
PSYNC(4)
TVO8(4)
R909 10K
VHAD0(4,22)
B B
Rh1
R347 10K
Rh2
R348 10K
Rh3
R349 10K
DNI
Rh10
R874 10K
DNI
Rh4
R350 10K
Rh5
R351 10K
+3.3V_BUS
+3.3V_BUS
EXT_PWR (6)
+3.3V_BUS
MEMORY TYPE STRAPS
Rh6
TVO6(4)
TVO7(4)
Rh7
Rh8
Rh9
R850 10K
DNI
R851 10K
DNI
R852 10K
R853 10K
+3.3V_BUS
+3.3V_BUS
Rh3
C
INSTALL
Rh5
MEMORY TYPE
TBD
TBD
TBD
TBD
ROMCS#(4,16)
ROMSO(4,16)
ROMSI(4,16)
ROMSCK(4,16)
Ri7Ra1
Ri8
refclk slightly earlier than feedback
DNI 10K
10K
DNI
10K
10K
10K
10K
DNI
DEVICE ID
NORMAL ID
Install it all the time when it is normal
device ID
Use workstation DEVICE_ID when
WSEN = 1
refclk 1 tap earlier than feedback
DNI
refclk 1 tap later than feedback
10K
refclk 2 taps earlier than feedback
DNI
(default)
DEFAULT
(00)
(01)
(10)
(11)
BUSCFG -- VID(6:4)
BUSTYPE_2
Ra7 Ri2
DNI
DNI
DNI
Rh10
Rh10
Rh10 Rh3 Rh4
VIP DEVICE
NO SLAVE VIP
Install it when internal
pull-up doesn't work
SLAVE VIP --ÂVIP device will drive low when
VIP is attached.
MEMORY TYPE STRAPS
Rh6 Rh8Rh7 Rh9
TBD TBD TBD TBD
TBD TBD TBD TBD
TBD TBD TBD TBD
TBD TBD TBD TBD
ID_DISABLE
Normal operation
CHIP SHUTS DOWN
Circuitry for external
power detection.
(DEFAULT)
(DEFAULT)
DNI
DNI
DNI DNI DNI
DNI DNI DNI10K
DNI DNI10K DNI10K
10K DNI
10K DNI
10K DNI
Rj1 Rk1
DNI
DNI
DNI DNI
DNI
10K 10K
10K
10K
10K
10K
10K
10K
10K
Rj1
R352 10K
Rk1
R353 10K
Rj2
R354 10K
Rk2
R355 10K
Rj3
R357 10K
Rk3
R358 10K
Rj4
R359 10K
Rk4
R360 10K
DNI
DNI
DNI
DNI
+3.3V_BUS
ROMIDCFG3
ROMIDCFG2
ROMIDCFG1
ROMIDCFG0
X0CLK_SKEW --VID(3:2)
BUSTYPE_1
VID6
Ra6
Ri3
DNI
10K
10K
DNI 10K
10K
10K
10K
10K
10K
10K
10K DNIDNI DNI
10K
10K
DNI10K DNIDNI
DNI
10K
Rj2 Rk2 Rj3
10K
DNI DNI
10K
DNI
10K 10K
10K
DNI
DNI DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
10K 10K
DNI
10K
10K
DNI
10K
DNI
Ra3
Ra4 Ri5
DNI
DNI
10K
DNI
10K
10K
BUSTYPE_0
VID5
Ra5
10K
DNI
10K
DNI
DNI
10K
10K
10K
10K 10K
10K
10K
DNI
DNI
DNI10K
10K DNI
10K
10K
10K
DNI DNI
DNI
10K
10K
DNI
10K
10K
10K
10K
DNI
DNI
DNI
DNI
DNI
10K 10K
10K
DNI
Ri6
x0clk to agpclk 0 tap delay
10K
DNIDNI
10K
DNI
10K10K
DNIDNI
DNI
VID4
Ri1
10K
DNI
10KDNI
DNI
DEFAULT
x0clk to agpclk 1 tap delay
x0clk to agpclk 2 taps delay
x0clk to agpclk 3 taps delay
AGP8X_DET = 0 (both GC and MB 8x capable)
DESCRIPTION
AGP 8X, 0.8V signaling PLL CLK, IDSEL = AD16
AGP 8X, 0.8V signaling PLL CLK, IDSEL = AD17
AGP 4X, 0.8V signaling PLL CLK, IDSEL = AD16
AGP 4X, 0.8V signaling PLL CLK, IDSEL = AD17
AGP8X_DET = 1 (either GC or MB not 8x capable)
AGP 4X, PLL CLK, IDSEL = AD16
10K
AGP 4X, PLL CLK, IDSEL = AD17
AGP 1X/2X, PLL CLK, IDSEL = AD16
10K
AGP 1X/2X, PLL CLK, IDSEL = AD17
PCI 66MHz, PLL CLK
DNI
PCI 33MHz, 3.3V, REF CLK
AGP 1X, REF CLK, IDSEL = AD16
10K
AGP 1X, REF CLK, IDSEL = AD17
Rk3
Rj4 Rk4
10K
DNI
DNI
DNI
10K
DNI10K
DNI
10K
DNI
10K
10K
DNI
DNI
10K
DNI
DNI
10K
10K
DNI
DNI
10K
DNI
ROMIDCFG[3:0]
10K
No ROM, CHG ID = 00
10K
No ROM, CHG ID = 01
10K
No ROM, CHG ID = 10
10K
No ROM, CHG ID = 11
10K
Parallel ROM on TVO
DNI
Serial AT25F1024, ID's from ROM
10K
Serial AT45DB011, ID's from ROM
DNI
Serial ST M25P10, ID's from ROM
10K
Serial ST M25P05, ID's from ROM
DNI
Serial SST45LF010, ID's from ROM
Parallel ROM on DVO
DNI
Serial ISSI NX25F011B, ID's from ROM
(default)
A A
8
MEMORY TYPE STRAPS
SAM
INF
HYN
TBD
7
TVO7 TVO6
0 0
1
0
1 1
0
1
6
5
4
3
Title
Size Document Number Rev
B
Date: Sheet of
R566
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
14 25Tuesday, March 11, 2003
1
2.1
8
7
6
5
4
3
2
1
SPEED CONTROLED FAN
D D
+5V_BUS+12V_BUS
R362
Install when +12V fan is used. Install when +5V fan is used.
DNI
R921 0R
VTERM2(5)
R365
10K
R368
5.11K
THERM
DNI
C489
10nF
DNI
DNI
VTERM1(5)
C C
C491
10nF
DNI
DNI
C493
10nF
DNI
R363
100K
DNI
R364
100K
Fan_VDD
VT1
DNI
U76
1
VT1
VDD
2
CF
OUT
3
VSLP
OTF
4 5
GND VT2
MC502BM
C490
10uF 16V
8
R366 270R
7
6
R768
24.3K
DNI
R361
0R
MMBT2222ALT1
1
C492
0.1uF
DNI
Fan_VDD
RT1
100K
DNI
t
0R
Rl2Rl3
DNI
3
Q11
2
DNIDNI
Place directly
underneath R300
thermal balls.
Rl2Rl3
JU1
1
2
R367
0R
H1
Rl1
0R if RT1 not used.
B B
DNI
R893 100K
R891 100K
Fan_VDD
411
U95A
3
+
2
-
LM324M
R897 100K
DNI
U95C
10
+
9
-
LM324M
R903 0R
DNI
1
8
DNI
6
DNI
R894 100K
DNI
R896
100K
R899 100K
R898 100K
DNI
Fan_VDD
DNI
R892
100K
DNI DNI
R904
100K
THERM
A A
8
7
R769
10K
DNI
DNI
DNI
U95B
5
R900
100K
+
6
-
LM324M
R901 100K
R902
100K
DNI
5
VT1
7
DNI
Title
Size Document Number Rev
B
4
3
Date: Sheet of
R566
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
15 25Tuesday, March 11, 2003
1
2.1
8
D D
7
6
5
4
3
2
1
SERIAL EEPROM 512K/1M
ROM_SO
RP192A33R
C C
B B
A A
ROMSO(4,14)
ROMSI(4,14)
ROMSCK(4,14)
ROMCS#(4,14)
ROM_CSb(23)
81
72
63
RP192D33R
54
+3.3V_BUS
SI/A16
SCK/WEb
CSb
HOLD1
+3.3V_BUS
C497
100nF
ALTERNATIVE PART :M25P05(512Kbit)
U80
5
D
6
C
1
S
7
HOLD
3
W
8
VCC
M25P05-VMN6T
Ua
ROM_SO
2
Q
4
VSS
2
GIGABYTE
GV-R9500
16 25Tuesday, March 11, 2003
2.1
1
Title
Size Document Number Rev
B
8
7
6
5
4
3
Date: Sheet of
R300 128M dual rank DVI VGA VO
8
D D
7
6
5
4
3
2
1
PRIMARY DVI-I CONNECTOR (DVI-I1)
DDCCLK_DVI_R(18)
DDCDATA_DVI_R(18)
VSYNC_DVI-I_R(18)
B38 Bead
+5V_DIN
Place close to
the connector
C558
100nF
TX2M
TX2P
TX1M
TX1P
+5V_DIN
TX0M
TX0P
TXCP
TXCM
c
DVI-I1
J4
M1
CASE
M3
CASE
1
TMDS Data2-
2
TMDS Data2+
3
TMDS Data2/4 Shield
4
TMDS Data4-
5
TMDS Data4+
6
DDC Clock
7
DDC Data
8
Analog VSYNC
9
TMDS Data1-
10
TMDS Data1+
11
TMDS Data1/3 Shield
12
TMDS Data3-
13
TMDS Data3+
14
+5V Power
15
GND (for +5V)
16
Hot Plug Detect
17
TMDS Data0-
18
TMDS Data0+
19
TMDS Data0/5 Shield
20
TMDS Data5-
21
TMDS Data5+
22
TMDS Clock Shield
23
TMDS Clock+
24
TMDS Clock-
C1
Analog Red
C2
Analog Green
C3
Analog Blue
C4
Analog HYNC
C5
Analog GND
C6
Analog GND
M4
CASE
M2
CASE
DVI A/D
R459 0R
R460 0R
R461 0R
R462 0R
c
+5V_DIN(18)
INSTALL TERMINATION RESISTORS
TX2M(4)
TX2P(4)
TX1M(4)
TX1P(4)
C C
TX0M(4)
TX0P(4)
TXCP(4)
TXCM(4)
B B
CLOSE TO ASIC
R794 330R
R795 330R
R796 330R
R797 330R
INSTALL TERMINATION RESISTORS
CLOSE TO CONNECTOR
R451 330R
DNI
R453 330R
DNI
R455 330R
DNI
R456 330R
DNI
HPD1(4)
D9
2.5V
2 1
+5VCON1(19,21)
HSYNC_DVI-I_R(18)
R457 20K
R458
100K
R_DVI-I(18)
G_DVI-I(18)
B_DVI-I(18)
A A
Title
Size Document Number Rev
B
8
7
6
5
4
3
Date: Sheet of
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
17 25Tuesday, March 11, 2003
1
2.1
8
7
6
5
4
3
2
1
D D
DDCCLK_DVI_R
DDCCLK_DAC2_5V (20)
DDCDATA_DVI_R
DDCDATA_DAC2_5V (20)
HSYNC_DAC2_B (20,21,22)
VSYNC_DAC2_B (20,22)
Place close to the
High-Density
Header
HSYNC_DVI-I_R
VSYNC_DVI-I_R
R26 0R
R27 0R
R28 0R
R_DVI-I
G_DVI-I
B_DVI-I
DDCDATA_DVI_R
DDCCLK_DVI_R
HSYNC_DVI-I_R
VSYNC_DVI-I_R
R_DVI-I
G_DVI-I
B_DVI-I
DNI DNI DNI
DNI DNI DNI
R/C_DAC2_F (20)
G/Y_DAC2_F (20)
B/COMP_DAC2_F (20)
ADDED DUE
TO LONG
TRACES
R824 33R
R825 33R
R800 0R
R803 0R
Keep length short,
or another set of
resistor may be
needed
DDCCLK_DAC1_5V(19)
DDCDATA_DAC1_5V(19)
HSYNC_DAC1_B(19)
C C
B B
VSYNC_DAC1_B(19)
R_DAC1_F1(19)
G_DAC1_F1(19)
B_DAC1_F1(19)
R822 33R
R823 33R
R799 51R
R802 51R
L57 68nH
1 2
L58 68nH
1 2
L59 68nH
1 2
Place close to the output
of the DAC1 filters
R815 0R
R816 0R
OPTIONAL ESD/HOTPLUG PROTECTION DIODES
2
2
2
D17
D18
3
1
DNI DNI DNI DNI DNI DNI DNI
C573
C574
C575
5pF
5pF
5pF
L18
L17
L16
82nH
82nH
82nH
1 2
1 2
1 2
c
Cox + Loy
D19
3
3
1
1
C749
22pF
2
3
1
C750
22pF
DNIDNI
+5V_BUS+5V_BUS +5V_BUS+5V_BUS+3.3V_BUS+3.3V_BUS +3.3V_BUS
2
2
D21
D20
3
3
1
1
PLACE CLOSE TO
CONNECTOR
2
D23
D22
3
1
+5V_DIN
DNI
MJ4
1
R
2
G
3
B
11
MS0
12
MS1
4
MS2
15
MS3
9
NC
13
HS
14
VS
5
VSS
6
VSS
7
VSS
8
VSS
10
VSS
16
CASE
17
CASE
18
CASE
19
CASE
DB15F slim RA
c
6050003000
Thin-DB15
R469 0R
R471 0R
R472 0R
R473 0R
c
DDC2_MONID0
DDC2_MONID1(SDA)
DDC2_MONID2
DDC2_MONID3(SCL)
DDCCLK_DVI_R (17)
DDCDATA_DVI_R (17)
R_DVI-I (17)
G_DVI-I (17)
B_DVI-I (17)
HSYNC_DVI-I_R (17)
VSYNC_DVI-I_R (17)
+5V_DIN (17)
A A
Title
Size Document Number Rev
C
8
7
6
5
4
3
Date: Sheet of
2
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
18 25Tuesday, March 11, 2003
1
2.1
8
7
6
5
4
3
2
1
PRIMARY CRT INTERFACE
D D
OPTIONAL ESD/HOTPLUG PROTECTION DIODES
+3.3V_BUS +5V_BUS
+3.3V_BUS
+3.3V_BUS +5V_BUS +5V_BUS
2
2
D10
BAT54SLT1
C559
3pF
L7
82nH
1 2
L8
82nH
1 2
c
C560
3pF
3
3pF
82nH
1 2
R_DAC1_F1 (18)
G_DAC1_F1 (18)
C C
R_DAC1(4)
G_DAC1(4)
B_DAC1(4)
+3.3V_BUS
CRT1DDCDATA(4)
B B
CRT1DDCCLK(4)
HSYNC_DAC1(4)
VSYNC_DAC1(4)
+3.3V_BUS
+5V_BUS
4.7K
R468
4.7K
+3.3V_BUS
1
+3.3V_BUS
BSN20
1
BSN20
Q13
32
Q12
32
+5V_BUS
10
9
13
12
74ACT08MTC
+5V_BUS
R463
6.8k
R464
6.8k
74ACT08MTC
8
U2C
11
U2D
PLACE CLOSE TO ASIC
L43
L44
L45
R51
R50
R49
75.0R
75.0R
GND_AVSSN
75.0R
1%1% 1%
C564 3pF
C567 3pF C568 1pF
C570 3pF
1 2
1 2
1 2
DNI
DNI
DNI
82nH
82nH
82nH
L46
1 2
L47 82nH
1 2
L48
1 2
C565 1pF
C571 1pF
B_DAC1_F1 (18)
82nH
82nH
R859
56R
R_DAC1_F
G_DAC1_F
B_DAC1_F
DDCDATA_DAC1_5V
DDCCLK_DAC1_5V
VSYNC_DAC1_R1
DDCDATA_DAC1_5V (18)
DDCCLK_DAC1_5V (18)
R860
56R
HSYNC_DAC1_B (18)
VSYNC_DAC1_B (18)
D11
3
3
1
1
DNI DNI DNI DNI DNI DNI DNI
R465 33R
R466 33R
R470 0R
R474 0R
C561
DNIDNIDNI
DNIDNIDNI
L9
+5V_BUS
2
2
2
D12
3
1
HSYNC_DAC1_RHSYNC_DAC1_R1
VSYNC_DAC1_R
D14
D13
3
1
1
C751
22pFR467
DNI DNI
PLACE CLOSE TO
CONNECTOR
2
2
D15
3
D16
3
1
1
C752
22pF
C562
100nF
PRIMARY VGA
CONNECTOR
F1
750mA
+5VCON1 (17,21)
B39
Bead
J5
1
R
2
G
3
B
11
MS0
12
MS1
4
MS2
15
MS3
9
NC
13
HS
14
VS
5
VSS
6
VSS
7
VSS
8
VSS
10
VSS
16
CASE
17
CASE
Connector DB15 Female VGA Blue
c
+5V_BUS
A A
Title
Size Document Number Rev
B
8
7
6
5
4
3
Date: Sheet of
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
19 25Tuesday, March 11, 2003
1
2.1
8
D D
7
6
5
4
3
2
1
PLACE CLOSE TO ASIC
C577 8pF
C579 8pF
C581 8pF
L60 56nH
1 2
L61 56nH
1 2
L62 56nH
1 2
R/C_DAC2_F (18)
G/Y_DAC2_F (18)
B/COMP_DAC2_F (18)
SECONDARY CRT LOGIC
SECONDARY CRT LOGIC
CRT2
DDCDATA_DAC2_5V (18)
DDCCLK_DAC2_5V (18)
DDCDATA_DAC2_HDH (22)
DDCCLK_DAC2_HDH (22)
HSYNC_DAC2_B (18,21,22)
VSYNC_DAC2_B (18,22)
L10 68nH
R_DAC2(21)
G_DAC2(21)
B_DAC2(21)
BSN20
Q14
32
Q15
+5V_BUS
6.8k
R480
32
+5V_BUS
6.8k
R482
U3B
6
U3C
8
R31 47R
R32 47R
R791 75.0R
R792 75.0R
R793 75.0R
R29 33R
R30 33R
DNI
GND_A2VSSN
+3.3V_BUS
R479
4.7K
C C
B B
CRT2DDCDATA(4)
+3.3V_BUS
R481
4.7K
CRT2DDCCLK(4)
HSYNC_DAC2(4)
VSYNC_DAC2(4)
1
1
BSN20
4
5
SN74ACT86PW
9
10
SN74ACT86PW
1 2
L12 68nH
1 2
L14 68nH
1 2
C576 3.3pF
C578 3.3pF
C580 3.3pF
+VDDC_CT
C590
C591
100nF
+3.3V_BUS +3.3V_BUS
A A
8
capacitors to bridge the power cut on the layer 5
7
100nF
C592
100nF
+VDDQ_BUS
6
C593
100nF
Title
Size Document Number Rev
B
5
4
3
Date: Sheet of
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
20 25Tuesday, March 11, 2003
1
2.1
5
4
3
2
1
TV-OUT
STEREOSCOPIC DISPLAY
CONNECTOR
Rm21
R763 0R
F
DNIInstall
A
E
C D
CRT2 logic (page21)
B C D E G Uv1
A CB E
A CB E
A B
A B
CRT2 logic (page21)
Uv1
D E
C
D
TVO2(4,22)
R606 0R
R608 0R
R504 0R
Connector Jm1 uses the
same footprint as Jm2
and Jm3
2
H
STEREOSYNC(4)
TBLuma
TBChroma
HSYNC_DAC2_B(18,20,22)
D D
Y_DAC2
R912
75.0R
R925 0R
G
GND_TVVSSN
C_DAC2
R913
75.0R
GND_TVVSSN
COMP_DAC2
C C
R/C_DAC2(4)
G/Y_DAC2(4)
B/COMP_DAC2(4)
GND_TVVSSN
R914
75.0R
Uv1
U96
TVO0(4,22)
B_DAC2(20)
G_DAC2(20)
B B
A A
COMP_DAC2
B_DAC2
Y_DAC2
G_DAC2
R/C_DAC2_HDH(22)
G/Y_DAC2_HDH(22)
B/COMP_DAC2_HDH(22)
5
1
2
3
5
6
11
10 14
15
R_DAC2
G_DAC2
B_DAC2
C_DAC2
Y_DAC2
COMP_DAC2
SEL
VCC
1A0
1A1
1B0
1B1
1C0
1D1
1C1 1D0
E
GND
PI5V330
R915 0R
R916 0R
R917 0R
R918 0R
R919 0R
R920 0R
R922 0R
R923 0R
R924 0R
R928 0R
R929 0R
R930 0R
R931 0R
R932 0R
R933 0R
YA
YB
YC
YD
16
4
7
9
12
13
8
C
D
E
A
B
+5V_BUS
R926 0R
ADDED TO REMOVE
STUBS WHEN VO
USED ON HDH
R927 0R
C735
100nF
R_DAC2
C_DAC2
DNI
DNI
DNI
DNI
DNI
4
R_DAC2
G_DAC2
B_DAC2
C_DAC2
Y_DAC2
COMP_DAC2
R/C_DAC2
G/Y_DAC2
B/COMP_DAC2
R/C_DAC2
G/Y_DAC2
B/COMP_DAC2
R_DAC2 (20)
TVO0 VGA2 TV out
"1"
"0"
L20
1.8uH
C583
82pF
C585
82pF
C588
82pF
L21
1.8uH
L22
1.8uH
c
c
c
TV-OUT only (main board)
VGA2 only (main board)
VGA2 & TV-OUT (main board)
VGA2 (main board)
& TV-OUT (daughter card)
TV-OUT (main board)
& VGA2 (daughter card)
VGA2 (daughter card)
& TV-OUT (daughter card)
enable
disable
disable
enable
3
C584
82pF
TBChroma
C586
82pF
C587
82pF
TBLuma
TBComp
B
CRT2 logic (page21)
A
G Uv1
Uv1
D
C
E
G
CRT2 logic (page21)
G
Uv1
12
DNI
13
Connector Jm3 uses the
same footprint as Jm1
and Jm2
COMP
Connector Jm2 uses the
same footprint as Jm1
and Jm3
D
G
G
Uv1
Rm22
Rm23
Rm24
R513 330R
DNI
Rm7
Title
Size Document Number Rev
B
Date: Sheet of
+5VCON1(17,19)
U3D
11
SN74ACT86PW
R878 0R
TBLuma_R
TBChroma_R
COMPTBComp
SYNC
Cm1
DNI
C589
470pF
R300 128M dual rank DVI VGA VO
DNI
B50 Bead
Bm4
Rm3
R517 0R
COMP
DNI
TV Out (Comp)
Jm2
J8
Jack Phono RCA
1
DNI
32
c
TV Out (SVHS)
Connector DIN Miniature Circular 7 Pin
PIN1
Rm1
R509
0R
cc c
GIGABYTE
GV-R9500
DNI
Jm3
MJ7
PIN1
1
1
2
2
7
7
8
CASE
9
CASE
10
CASE
MiniDIN 3 Pin
c
B
Jm1
J7
6
+12V
3
Y-OUT
4
C-OUT
7
Comp_out
5
SYNC
1
GND
2
GND
8
CASE
9
CASE
10
CASE
21 25Tuesday, March 11, 2003
1
2.1
8
7
6
5
4
3
2
1
HIGH-DENSITY HEADER
D D
DVO/VID Data Bus
DVO[11..0]
VID[7..0]
VPHCTL
VHAD1
SOCKET STRIP 2x35 0.05x.1
JU5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67 68
69 70
+3.3V_BUS+3.3V_BUS +5V_BUS
R818
R820
CLK_VIPCLK
VHAD0
NTSC/PAL
AGP_RESET#
DVO0
DVO2
DVO4
DVO6
DVO8
DVO10
VID7
VID5
VID3
VID1
I2C_DATA
0R
DNI
0R
C C
B B
3.3V I2C CLK
G/Y_DAC2_HDH(21)
HSYNC_DAC2_B(18,20,21)
VSYNC_DAC2_B(18,20)
DDCDATA_DAC2_HDH(20)
SCL(4)
TVO0(4,21)
TVO2(4,21)
TVO4(4)
R806 0R
+3.3V_BUS
Daughter Card Straps
R861 10K
R862 10K
R863 10K
DC_Strap5
DC_Strap3
DC_Strap1
R864 10K
R865 10K
R866 10K
Analog Display from DAC2
DDC DATA
R809 0R
R811 0R
R813 0R
DVO1
DVO3
DVO5
DVO7
DVO9
DVO11
CLK_VIDCLK
VID6
VID4
VID2
VID0
I2C_CLK
R808 0R
R810 0R
R812 0R
R814 0R
Daughter Card Straps
DC_Strap4
DC_Strap2
Use to reset Si168 External TMDS
DVALID(4,14)
R821 0R
DVO[11..0] (4)
CLK_VIDCLK (4)
VID[7..0] (4,14)
VIP Host Bus
CLK_VIPCLK (4)
VHAD0 (4,14)
VHAD1 (4)
VPHCTL (4)
SDA (4)
R867 10K
R868 10K
R869 10K
TVO3 (4)
TVO5 (4)
R870 10K
R871 10K
R872 10K
DDC CLK
DDCCLK_DAC2_HDH (20)
Analog Display from DAC2
R/C_DAC2_HDH (21)
B/COMP_DAC2_HDH (21)
AGP_RESET# (2,3,23)
HPD2 (4)
DVO Bus control lines for
External DDR TMDS
CLK_DVOCLK1 (4)
CLK_DVOCLK0 (4)
DVOCNTL2 (4)
DVOCNTL1 (4)
DVOCNTL0 (4)
3.3V I2C DATA
+3.3V_BUS
41
SW1A
DIP_SWX2
TVO1 (4)
32
SW1B
DIP_SWX2
A A
Title
Size Document Number Rev
C
8
7
6
5
4
3
Date: Sheet of
2
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
22 25Tuesday, March 11, 2003
1
2.1
8
MU106
TK11819M
IN-
1
Vin
2
OSC
IN+
3
D D
AGP_VREFGC(2,3)
AGP_DEVSEL#_R(2,3)
C C
Block_DEVSEL#
Place closest possible to AGP
connector with minimum possible
stub on AGP_DEVSEL#_R signal.
DK
USED FOR THE FOOTPRINT
DEVSEL_TTL
C761
100nF
R1550 4.99K
R1548 1.0K
U107
1
VDD
2
OUT
3
GND
4 5
LATCH VEE
MAX9203EKA-T
AGP_RESET#(2,3,22)
VCC
IN+
IN-
GND
8
7
6
Vout
T1
3
4
IN-
6
DEVSEL_TTL
5
4
+5V_BUS
+5V_BUS
U106
LMV7219M7
+
-
2 5
IN+
7
1
R1547
100K
DNI
+5V_BUS
R1551
100K
DNI
HighSpeed Comparator
8X_DET#(3)
R943 0R
C760
100nF
6
R1552
10K
DNI
1
2
ROM_CSb(16)
+5V_BUS
147
C753
100nF
U3A
SN74ACT86PW
3
U99A
SN74HCT02PWR
2
3
+5V_BUS
14
7
5
4
3
2
1
Hijack Circuit
C759
100nF
1
R952
0R
C1126
100nF
DNI
+5V_BUS
C757
100nF
14
4
2
D
3
C
5V
PR
G
CL
U103A
7
1
74VHCT74MTC
5
Q
6
Q
R951
12
11
0R
1013
D
C
9
Q
PRCL
8
Q
U103B
74VHCT74MTC
Block_DEVSEL#
R947
0R
11
12
13
U99D
SN74HCT02PWR
SWAP
Minimum possible stub on
this signal.
B B
SWAP
A A
AGP_AGPCLK(2,3)
MK1
1
SELECT
2
V+
3 4
GND NC
NLAS4599DF
+5V_BUS
C755
100nF
C756
100nF
8
K1
MAX4625EUT-T
1
3
K2
MAX4625EUT-T
1
3
MK2
1
2
3 4
NLAS4599DF
NO
COM
+
-
+
-
SELECT
V+
COM
GND NC
7
R946
270R
6
5
6
52
4
6
52
4
6
NO
5
Place closest possible to AGP connector with absolute
minimum possible trace lengths and vias.
AGP_TRDY#_R (2)
AGP_STOP#_R (2)
SIDE
6
5
6
U99B
SN74HCT02PWR
4
AGP_TRDY# (2,3)
AGP_STOP# (2,3)
R300 SIDEAGP CONNECTOR
5
8
9
10
U99C
SN74HCT02PWR
Title
Size Document Number Rev
B
4
3
Date: Sheet of
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
23 25Tuesday, March 11, 2003
1
2.1
5
4
3
2
1
DVI SCREWSCRT SCREWS
ASSY1
SCREW
JACKSCREW
D D
C C
<3rd part field>
7020000800
ASSY4
SCREW
JACKSCREW
<3rd part field>
7020000800
ASSY6
SCREW
PAN HEAD
ASSY8
BRACKET
VGA, VID OUT, DVI, 301
<3rd part field>
ASSY2
SCREW
JACKSCREW
<3rd part field>
7020000800
ASSY5
SCREW
JACKSCREW
<3rd part field>
7020000800
ASSY11
BRACKET
VGA, DVI, 308
ALT
ASSY10
DVI, 251
ALT
BRACKET
MISC. BOARD PARTS
ASSY3
BLANK
LABEL
1.50W X 0.50H
ASSY
ASSY7
ANTISTATIC
BAG
6 X 11
<3rd part field>
REF1
SCHEMATIC
105-A05600-00
<3rd part field>
REF3
ATI LOGO
LABEL
ATI LOGO LABEL
REF2
PCB
109-A05600-00
<3rd part field>
B B
A A
Title
Size Document Number Rev
B
5
4
3
2
Date: Sheet of
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
24 25Tuesday, March 11, 2003
1
2.1
8
<Variant Na
me>
Title
7
6
5
4
3
2
1
Date:Schematic No.
AGP R300 128MB dual rank BGA DVI VGA VO
REVISION HISTORY
D D
Sch
PCB
Rev
Rev
1 00 10/29/2002 MOVED RESISTOR R940 ON THE PCB
C C
Date
00A0 PROTOTYPE BASED ON 105-942XX-3009/05/2 002
REVISION DESCRIPTION
ADDED RESISTORS R103, R136 FOR POWER SEQUENCING
105-A056XX-00_1
Tuesday, March 11, 2003
Rev
2.1
B B
A A
8
7
6
5
4
3
2
1
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