Gigabyte GV-R9500 Schematic rev.2.1
5
4
3
2
1
MEMORY CHANNEL C D
D D
DDR 4M X 32 (BGA)
SHT 14
MEMORY TERMINATIONS C D
SHT 12
VGA1
MDC/D[63..0] QSC/D[7..0] CS0C/D#
MC/D[14..0]
CASC/D#
MEM A B
C C
STRAPS
SHT 15
MEM C D
DAC1
TMDS
BIOS
SHT 17
ROMCS#
ROM
TVO
External
power
B B
POWER
REGULATION
SHT 6,7,8
FAN
SHT 16
VDDC VDDC18 VDD VTT VDDQ
PVDD TPVDD MPVDD
A2VDD Vref
R300
SHEET 3, 4, 5, 09, 10
DVO
VIP
DAC2
AGP
WEA/B#RASC/D#
CKEC/D CLKC/D01
R G B HSY VSY DDC1DATA DDC1CLK
TMDS_TX[C,2..0]N TMDS_TX[C,2..0]P HPD, DDC2CLK DDC2DATA
DVO, VIP Host, VIP Data
Y/R C/G COMP/B H2SYNC
GPIO
SEL
SHT 22
DQMC/D[0..7]
CLKC/D01#
CRT2DDCDATA CRT2DDCCLK V2SYNC
D
E
M
TVOUT
LOGIC
SHT 22
U
X
SECONDARY
CRT LOGIC
SHT 19
PRIMARY CRT
LOGIC
SHEET 19
INTEG TMDS
LOGIC
HDH
SHT 23
TVout
CONN
DB15
CONN
SHT 19
DVI-I1
CONN
SHT 18
CBE3..0
GNT#
CLK
SBA[7..0]
AD_STB1#
CPUCLK
TRDY#
INTR
ST2..0
SUSPEND#
AD_STB0
DEVSEL#
SB_STB
AD_STB0#
RESET#
SERR#
SB_STB#
RBF#
Title
Size Document Number Rev
B
3
2
Date: Sheet of
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
1 25Tuesday, March 11, 2003
1
2.1
AD31..0
IRDY#
FRAME#
AGPREF
+5V
+3.3V
A A
5
+12V
AD_STB1
AGP BUS
2X/4X/8X
SHT 2
4
REQ#
PAR
STOP#
8
7
6
5
4
3
2
1
2X/4X/8X AGP BUS
GND_TPVSSGND_MPVSS
GND_PVSS GND_TXVSSR
NOTE: THIS IS A DRAWING. THESE
GROUNDS MUST BE MANUALLY
D D
CONNECTED TO THE GROUND PLANE
AGP_MB_8X_DET#(3)
C C
B B
A A
8
GND_A2VSSN
AGP_GNT#(3)
AGP_DBI_HI(3)
AGP_WBF#(3)
AGP_SBSTB#(3)
AGP_ADSTB1#(3)
AGP_FRAME#(3)
AGP_TRDY#_R(23)
AGP_TRDY#(3,23)
AGP_STOP#(3,23)
AGP_STOP#_R(23)
AGP_PAR(3)
AGP_ADSTB0#(3) AGP_ADSTB0 (3)
AGP_VREFGC(3,23)
AGP_RESET#(3,22,23)
GND_AVSSQ GND_RSET
GND_A2VSSQ
R2 0R
AGP_RST#
R4 0R
R5 0R
+VDDQ_BUS
R7 8K2
+VDDQ_BUS
R9 8K2
+VDDQ_BUS
R16 8K2
R22 100R
R854
DNI
180R C731
7
GND_R2SETGND_AVSSN
AGP_INTR#(3)
AGP_GC_8X_DET#
DNI
R13 0R
DNI
R15 0R
AGP_VREFGC
74ACT08MTC
R25
180R
GND_TVVSSN
U2A
3
+5V_BUS
147
AGP_SBSTB#_R
C5
100nF
1
2
6
+12V_BUS
+3.3V_BUS +3.3V_BUS
A1
TYDET
A2
A3
A4
GND_TY
A5
A6
A7
A8
AGP_ST1
AGP_DBI_HI_R
AGP_SBA1 AGP_SBA0
AGP_SBA3
AGP_SBA5
AGP_SBA7
AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24
AGP_ADSTB1#_R
AGP_C/BE#3
AGP_AD22
AGP_AD20
AGP_AD18
AGP_AD16
AGP_TRDY#_R
AGP_STOP#_R
AGP_PAR_R
AGP_AD15
AGP_AD13
AGP_AD11
AGP_AD9
AGP_C/BE#0
AGP_ADSTB0#_R
AGP_AD6
AGP_AD4
AGP_AD2
R19
10K
AGP_RST#
DNI
100nF
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
PWGOOD_VDDC (6)
5
R1 0R
MAGP1
12V
TYPEDET#
GC_DET#/RESEVED
USBÂGND
INTA#
RST#
GNT#
VCC3.3
ST1
MB_DET#/RESERVED
DBI_HI/PIPE#
GND
WBF#
SBA1
VCC3.3
SBA3
SB_STB#
GND
SBA5
SBA7
KEY
KEY
KEY
KEY
AD30
AD28
VCC3.3
AD26
AD24
GND
AD_STB1#
C/BE3#
VDDQ
AD22
AD20
GND
AD18
AD16
VDDQ
FRAME#
KEY
KEY
KEY
KEY
TRDY#
STOP#
PME#
GND
PAR
AD15
VDDQ
AD13
AD11
GND
AD9
C/BE0#
VDDQ
AD_STB0#
AD6
GND
AD4
AD2
VDDQ
AD0
VREFGC
UNIVERSAL AGP BUS
GND_TYTYDET
OVRCNT#
5.0V
5.0V
USB+
GND
INTB#
CLK
REQ#
VCC3.3
ST0
ST2
RBF#
GND
DBI_LO/RESERVED
SBA0
VCC3.3
SBA2
SB_STB
GND
SBA4
SBA6
KEY
KEY
KEY
KEY
AD31
AD29
VCC3.3
AD27
AD25
GND
AD_STB1
AD23
VDDQ
AD21
AD19
GND
AD17
C/BE2#
VDDQ
IRDY#
KEY
KEY
KEY
KEY
DEVSEL#
VDDQ
PERR#
GND
SERR#
C/BE1#
VDDQ
AD14
AD12
GND
AD10
AD8
VDDQ
AD_STB0
AD7
GND
AD5
AD3
VDDQ
AD1
VREFCG
+5V_BUS+VDDQ_BUS
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
SYMBOL LEGEND
DO NOT
DNI
INSTALL
ACTIVE
#
LOW
DIGITAL
GROUND
ANALOG
GROUND
4
+VDDQ_BUS
AGP_ST0
AGP_ST2
AGP_DBI_LO_R
AGP_SBA2
AGP_SBA4
AGP_SBA6
AGP_AD31
AGP_AD29
AGP_AD27
AGP_AD25
AGP_AD23
AGP_AD21
AGP_AD19
AGP_AD17
AGP_C/BE#2
AGP_C/BE#1
AGP_AD14
AGP_AD12
AGP_AD10
AGP_AD8
AGP_AD7
AGP_AD5
AGP_AD3
AGP_AD1AGP_AD0
AGP_C/BE#[3..0]
AGP_AD[31..0]
AGP_SBA[7..0]
AGP_ST[2..0]
AGP_AGPCLK_R
R6 0R
AGP_SBSTB_R
AGP_ADSTB1_R
AGP_DEVSEL#_R
AGP_ADSTB0_R
3
+12V_BUS
AGP_C/BE#[3..0] (3)
AGP_AD[31..0] (3)
AGP_SBA[7..0] (3)
AGP_ST[2..0] (3)
R3 0R
AGP_REQ# (3)
AGP_RBF# (3)
AGP_DBI_LO (3)
R8 0R
R10 0R
R17 0R
C1127
1.0uF
Title
Size Document Number Rev
B
Date: Sheet of
C1
100uF 16V
ALU
+5V_BUS
AGP_SBSTB (3)
AGP_ADSTB1 (3)
AGP_IRDY# (3)
AGP_DEVSEL#_R (3,23)
AGP_AGPREF (3)
C2
100uF 16V
+3.3V_BUS
AGP_AGPCLK (3,23)
C4
10pF
DNI
C3
100uF 16V
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
2 25Tuesday, March 11, 2003
1
2.1
8
7
6
5
4
3
2
1
D D
PLACE
CLOSE TO
THE ASIC
AGPREFCG
C C
B B
PIN
AGP_C/BE#[3..0]
AGP_ST[2..0]
AGP_SBA[7..0]
AGP_SBSTB(2)
AGP_SBSTB#(2)
AGP_ADSTB0(2)
AGP_ADSTB0#(2)
AGP_ADSTB1(2)
AGP_ADSTB1#(2)
TEST
C14
100nF
AGP_C/BE#[3..0](2)
AGP_ST[2..0](2)
AGP_SBA[7..0](2)
AGP_DEVSEL#_R(2,23)
2N7002E
AGP_AGPCLK(2,23)
AGP_GNT#(2)
AGP_REQ#(2)
AGP_RBF#(2)
AGP_INTR#(2)
AGP_RESET#(2,22,23)
AGP_WBF#(2)
AGP_FRAME#(2)
AGP_TRDY#(2,23)
AGP_IRDY#(2)
AGP_STOP#(2,23)
AGP_PAR(2)
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
+VDDQ_BUS
1
Q2
AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3
AGP_ST0
AGP_ST1
AGP_ST2
AGP_SBSTB
AGP_SBSTB#
AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
32
R39 169R
R40 71.5R
AV39
AP38
AU39
AM39
AU37
AP35
AM36
AG35
AE35
AH35
AD35
AB35
AA35
AG34
AL36
AF36
AL37
AA39
AD38
AP39
AN39
AN38
AT37
AT38
AT39
AR39
AP36
AP37
AN36
AN37
AR38
AR37
AE37
AD36
AF39
AE38
U42A
PCICLK
GNT#
REQ#
RBF#
INTA#
RST#
WBF#
FRAME#
TRDY#
IRDY#
DEVSEL#
STOP#
PAR
AGPREF
AGPTEST
CBE#0
CBE#1
CBE#2
CBE#3
ST0
ST1
ST2
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
SB_STBF
SB_STBS
AD_STBF0
AD_STBS0
AD_STBF1
AD_STBS1
R300
PART 1 OF 8
A
G
P
/
P
C
I
I
N
T
E
R
F
A
C
E
AGP 8X
TEST_AGPCLK
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
DBI_HI
DBI_LO
AGP8X_DET#
Y36
Y37
AA36
AA37
AB36
AB37
AC36
AD37
AF37
AG36
AG37
AH36
AH37
AJ36
AK37
AK36
Y39
AB39
AA38
AC39
AB38
AD39
AC38
AE39
AG39
AG38
AH39
AH38
AJ39
AJ38
AK39
AK38
AL38
AL39
AL35
AP33
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_DBI_HI
AGP_DBI_LO
AGP_MB_8X_DET#
TEST_AGPCLK
AGP_AD[31..0]
AGP_DBI_HI (2)
AGP_DBI_LO (2)
AGP_MB_8X_DET# (2)
TP1
AGP_AD[31..0] (2)
2N7002E
R23
1K
1
Q1
+VDDQ_BUS+3.3V_BUS
32
R21 1.47K
5
R20
3.32K
R24
1.02K
*
AGP_VREFGC
C6
10nF
AGP_VREFGC (2,23)
4
DNI
AGP_AGPREF(2)
AGP_RESET#(2,22,23)
Title
Size Document Number Rev
B
3
Date: Sheet of
R895 0R
32
Q19
NDS335N
1
AGPREFCG
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
3 25Tuesday, March 11, 2003
1
2.1
8X_DET#(23)
R18
47K
AGP_MB_8X_DET#(2)
AGP_MB_8X_DET#
+5V_BUS
4
5
U2B
6
74ACT08MTC
TEST
UNIVERSAL VREFGC CIRCUIT (2X, 4X, 8X)
A A
8
7
6
8
+VDDDI
1uF
C30
C29
100nF
D D
C C
B B
+VDD2DI
1uF
C36
C35
100nF
APPLICATION
TVout w/ Rage Theatre
ext 24b DDR TMDS
ext 12b DDR TMDS&TVout
24b SDR TMDS
Note1 : PVSS, and MPVSS go to ground plane directly through their own
dedicated via. No connection with other VSS..
Note2 : Separate vias for AVSSQ (A2VSSQ), and AVSSN (A2VSSN) to
ground plane.
Note3 : AVDD/AVSSN power need to use a pair of short traces (20mil at
least) and direct to link to AVDD & AVSSN balls, the ground return point
should be near the ground trace start point.
Note4: Rset resistor ground point should link to AVSSQ trace, or have via
at resistor directly to ground plane.
Note5 : Populate Ra9 and Ra10 only if they are not populated on page
24 or 25 or 31 or 32.
+VDDDI
C28
22uF 16V
+VDD2DI
C34
22uF 16V
TVOVMODE DVOVMODE
0V
VDDC18 VDDC18
0V
0V 0V
B7
Bead
B8
Bead
+VDDC_CT
X
VDDC18
DNI
DNI
+VDDC_CT
+VDDC_CT
7
R45 0R
R46 0R
R47 0R
R48 0R
DVO[11..0](22)
VID[7..0](14,22)
DVO[11..0]
6
VID[7..0]
VID0
VID1
VID2
VID3
VID4
VID5
VID6
TVO0(21,22)
TVO1(22)
TVO2(21,22)
TVO3(22)
TVO4(22)
TVO5(22)
TVO6(14)
TVO7(14)
TVO8(14)
CLK_DVOCLK0(22)
CLK_DVOCLK1(22)
VID7
R43 1K
TVO0
TVO1
TVO2
TVO3
TVO4
TVO5
TVO6
TVO7
TVO8
DVOCNTL0(22)
DVOCNTL1(22)
DVOCNTL2(22)
TEST_MCLK
TEST_YCLK
TP7
TP27
TP28
CLK_VIDCLK(22)
DVALID(14,22)
PSYNC(14)
ROMSCK(14,16)
ROMSO(14,16)
ROMSI(14,16)
ROMCS#(14,16)
TP3
TP4
TESTEN
DVO0
DVO1
DVO2
DVO3
DVO4
DVO5
DVO6
DVO7
DVO8
DVO9
DVO10
DVO11
ROMCS#
+VDDDI
+VDD2DI
Crystal Circuit
DNI
AW35
AV35
AU35
AT35
AW34
AV34
AU34
AT34
AW36
AU36
AV36
AT36
AW21
AV21
AW19
AV19
AU19
AT19
AW20
AV20
AU20
AT20
AU21
AT21
AR19
AT18
AW17
AV17
AU15
AV15
AW15
AT15
AR15
AW16
AV16
AU16
AT16
AU17
AT17
AR17
AW18
AV18
AU18
AP30
AP29
AR29
AR30
AU23
AU27
AU24
AT26
DNI
F9
G6
U42B
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VPCLK0
DVALID
PSYNC
TESTEN
TVOCLKO
TVOCLKI
TVODATA0
TVODATA1
TVODATA2
TVODATA3
TVODATA4
TVODATA5
TVODATA6
TVODATA7
TVODATA8
TVODATA9
TVOVMODE
DVOVMODE
DVOCLK0
DVOCLK1
DVOCNTL0
DVOCNTL1
DVOCNTL2
DVODATA0
DVODATA1
DVODATA2
DVODATA3
DVODATA4
DVODATA5
DVODATA6
DVODATA7
DVODATA8
DVODATA9
DVODATA10
DVODATA11
ROMSCK
ROMSO
ROMSI
ROMCS#
TEST_MCLK
TEST_YCLK
VDD1DI
VDD2DI
VSS1DI
VSS2DI
R300
C40
10pF
C41
10pF
5
PART 2 OF 8
V
Video Capture & Test
I
D
E
O
&
M
U
L
T
I
M
E
D
I
A
TVOut, DVOut & ROM
DNI
DNI
MY1
27 MHZ
DNI
2 1
TXCM
TXCP
TX0M
TX0P
TX1M
TX1P
TX2M
TX2P
TPVDD
TPVSS
TMDS / Flat PanelDAC / VGAXTAL
TXVDDR
TXVDDR
TXVSSR
TXVSSR
TXVSSR
HPD1
HPD2
DDC1DATA
DDC1CLK
AUXWIN
VSYNC
HSYNC
STEREOSYNC
AVDD
AVDD
AVSSN
AVSSN
AVSSQ
RSET
VIPCLK
VPHCTL
VHAD0
VHAD1
VIP HostI2C
SCL
SDA
XTALOUT
XTALIN
PVDD
PVSS
MPVDD
MPVSS
R2SET
C-R
Y-G
COMP_B
H2SYNC
V2SYNC
DDC2CLK
DAC2 PLL
DDC2DATA
A2VDD
A2VDD
A2VSSN
A2VSSN
A2VDDQ
A2VSSQ
R56 0R
R58 0R
4
AV29
AW29
AV30
AW30
AV31
AW31
AV32
AW32
AW28
AV28
AT29
AT28
AU28
AU29
AU30
AR31
HPD1 (17)
AR33
HPD2 (22)
AU32
CRT1DDCDATA (19)
AU31
CRT1DDCCLK (19)
TP2
AP31
AT30
VSYNC_DAC1 (19)
AT31
HSYNC_DAC1 (19)
AP32
STEREOSYNC (21)
AW24
R
AW23
G
AW22
B
AV23
AV24
AR24
AT24
AU22
R52 499R
AV22
AV33
CLK_VIPCLK (22)
AW33
VPHCTL (22)
AU33
VHAD0 (14,22)
AT33
VHAD1 (22)
AR27
AR28
R300_XOUT
AW38
R300_XIN
AV38
AW37
AV37
+MPVDD
C7
GND_MPVSS
C6
AV25
AW27
AW26
AW25
AR32
AT32
AR34
AR35
AV26
AV27
AT25
AU26
AU25
AT27
DNI
Ra1
TXCM (17)
TXCP (17)
TX0M (17)
TX0P (17)
TX1M (17)
TX1P (17)
TX2M (17)
TX2P (17)
R55 715R
R/C_DAC2 (21)
G/Y_DAC2 (21)
B/COMP_DAC2 (21)
HSYNC_DAC2 (20)
VSYNC_DAC2 (20)
CRT2DDCCLK (20)
CRT2DDCDATA (20)
R57
1M
Ra4
R59 0R
TP34
GND_RSET
C738
SCL
SDA
R300_XOUT
1uF
1uF
C15
C19
22uF 16V
R53
4.7K
GND_R2SET
3
C17
100pF
TXVDDR
+3.3V_BUS+3.3V_BUS
TP35
C20
100pF
R54
4.7K
Ra10Ra9
R300_XIN
R65
0R
Ra8
C16
C18
22uF 16V
100nF
GND_TPVSS
C21
100nF
GND_TXVSSR
GND_AVSSQ
SCL (22)
SDA (22)
1uF
C25
DNI
1uF
C37
Rk
TP33
+A2VDDQ
C38
100nF
B3
R44
0R
DNI
B4
C26
100nF
GND_A2VSSQ
Bead
Ba2
Bead
C27
22uF 16V
C39
22uF 16V
2
Ba1
Ba4
GND_PVSS
1uF
C31
DNI
Ba5
+VDDC_CT+TPVDD
DNI
+VDDC_CT
B6
200R
B9
Bead
1uF
C22
DNI
+VDDC_CT+PVDD
DNI
+A2VDD
C33
100nF
GND_A2VSSN
+VDDC_CT
C24
100nF
C32
22uF 16V
R_DAC1 (19)
G_DAC1 (19)
B_DAC1 (19)
+AVDD
C23
22uF 16V
GND_AVSSN
1
B5
Bead
Ba3
+VDDC_CT
CLOCK SOURCE SELECTION
XTAL/OSC.
CRYSTAL
R300 alone
A A
8
OSC (OPTION 1)
OSC (OPTION 2)
DEFAULT
INSTALL
Ra1,Ra4
Crystal Circuit(27M)
Ra1 = 0R
Oscillator circuit(27M)
Ra4,Ra8
Oscillator circuit(27M)
7
NOT INSTALL
Ra8
Oscillator circuit
Ra4,Ra8
Crystal Circuit
Ra1
Crystal Circuit
6
Oscillator Circuit
+3.3V_BUS
8
C47
4
100nF
Y1
VDD
GND
27.000MHz
R63 107R
5
OUT
1
E/D
+3.3V_BUS
R66
150R
5
4
3
+MPVDD
GND_MPVSS
1uF
1uF
C42
DNI DNI DNI
1uF
C43
C44
Title
Size Document Number Rev
B
Date: Sheet of
+MPVDD +VDDC_CT
C45
100nF
GIGABYTE
R300 128M dual rank DVI VGA VO
2
Ba6
C46
22uF 16V
GND_MPVSS
GV-R9500
B10
200R
DNI
4 25Tuesday, March 11, 2003
1
2.1
5
U42G
M34
VDDR1
F33
VDDR1
H33
VDDR1
R6
VDDR1
U34
VDDR1
L34
VDDR1
N34
VDDR1
T33
REGULATOR
+5V_BUS
DNI
B11 200R
D D
DNI
3 2
AS432S
MREG1
R68
47R
R69
681R
1%
1
R70
1.50K
1%
FOR
DVO/TVO(+1.8V)
DNI
+VTVO/DVO
SC431LC5SK-1
DNI
4
NC
1
NC
2
5 3
DNI DNI
REG1
USE ONLY IF TVO OR DVO MODES ARE 1.8V
C C
VTERM2(15)
B B
+VDDTVO
B12 200R
B13 200R
C709
C74
A A
1uF
100nF
+VDDDVO
B14 200R
C75
1uF
C710
100nF
B15 200R
5
+3.3V_BUS
+VDDTVO
+VDDDVO
+VDDQ_BUS
+3.3V_BUS
+VTVO/DVO
DNI
+3.3V_BUS
+VTVO/DVO
DNI
W33
W34
AP12
AN12
AP11
AN13
AP10
AN14
AR25
AN29
AP26
AN28
AN25
AR22
AR23
AP24
AP27
AP19
AN21
AP20
AN17
AN18
AP15
AR16
AP16
AN34
AM34
AN33
AK33
AJ33
AC33
AB33
AA33
AL33
AJ34
AF34
AB34
AH33
AG33
AF33
AE33
AD33
VDDR1
V33
VDDR1
VDDR1
VDDR1
F11
VDDR1
F28
VDDR1
G13
VDDR1
F14
VDDR1
F16
VDDR1
F17
VDDR1
G23
VDDR1
F25
VDDR1
F27
VDDR1
T34
VDDR1
F31
VDDR1
G8
VDDR1
G26
VDDR1
G10
VDDR1
G11
VDDR1
G17
VDDR1
G18
VDDR1
F19
VDDR1
F20
VDDR1
F21
VDDR1
F22
VDDR1
G25
VDDR1
G29
VDDR1
G30
VDDR1
R33
VDDR1
G32
VDDR1
H7
VDDR1
K6
VDDR1
J7
VDDR1
L6
VDDR1
T7
VDDR1
V6
VDDR1
V7
VDDR1
W6
VDDR1
AF7
VDDR1
D6
VDDR1
AA6
VDDR1
AA7
VDDR1
AB7
VDDR1
AB6
VDDR1
AE6
VDDR1
AD6
VDDR1
AG7
VDDR1
AJ6
VDDR1
AP8
VDDR1
AH6
VDDR1
VDDR1
AN6
VDDR1
AL6
VDDR1
AN8
VDDR1
VDDR1
VDDR1
VDDR1
AN9
VDDR1
VDDR1
G14
VDDR1
F12
VDDR1
VDDR1
F32
VDDR1
H34
VDDR1
M5
VDDR1
G33
VDDR1
U7
VDDR1
AM6
VDDR1
AP7
VDDR1
L33
VDDRH
G22
VDDRH
L7
VDDRH
AL7
VDDRH
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR3
VDDR2
VDDR2
VDDR2
VDDR4
VDDR4
VDDR4
VDDR4
VDDR4
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
Y33
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
VDDP
R300
PART 7 OF 8
P
O
W
E
R
DISPLAY I/O PWR
4
VDDC18
VDDC18
VDDC18
VDDC18
VDDC18
VDDC18
VDDC18
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
MEMORY I/O
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
CORE
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
AGP / PCI I/O
VDDCI
VDDCI
VDDCI
VDDCI
VSSRH
VSSRH
VSSRH
VSSRH
4
J33
N7
AK7
G20
AN22
AN27
AN32
AV2
AU3
AT4
AR5
AP6
AN7
N13
P13
R13
T13
U13
N14
P14
R14
T14
U14
P15
R15
T15
U15
N16
P16
R16
T16
U16
N17
P17
R17
T17
U17
AC23
AD23
AE23
AF23
AC24
AD24
AE24
AF24
AG24
AC25
AD25
AE25
AF25
AG25
AC26
AD26
AE26
AF26
AG26
AD27
AE27
AF27
AG27
N24
N25
N26
N27
P23
P24
P25
P26
P27
R23
R24
R25
R26
R27
T23
T24
T25
T26
T27
U23
U24
U25
U26
U27
AC14
AC15
AC16
AC17
AD13
AD14
AD15
AD16
AD17
AE13
AE14
AE15
AE16
AE17
AF13
AF14
AF15
AF16
AF17
AG13
AG14
AG15
AG16
AG17
N15
AC27
AG23
AC13
N23
M33
G21
M7
AM7
+VDDC_CT+MVDDQ
+VDDC
3
U42H
AM38
AF38
Y38
AM37
AJ37
AC37
AR36
AE36
AU38
AM35
AJ35
AF35
Y35
AM33
AL34
AN35
AK34
AH34
AE34
AD34
AC34
AA34
Y34
AC35
AK35
AA26
Y26
U37
U33
F29
P35
V35
V13
AU6
N37
T3
B20
AR2
K35
U6
W13
C35
C31
E32
E28
C27
Y13
AA13
E24
G7
E20
AB13
V14
C16
C37
C23
E18
E14
D4
C13
E5
C9
E10
C3
F3
N6
AU13
AR12
AA14
AB14
AA15
AB15
AA16
AB16
AA17
AB17
AA18
AB18
AA19
AB19
AA20
AB20
AA21
AB21
AA22
AG5
AD3
AP5
AH3
N3
W5
Y3
AU9
AM3
K5
AC5
W14
AL5
B2
F35
H38
Y14
F6
V15
W15
Y15
V16
W16
Y16
V17
W17
Y17
V18
W18
Y18
V19
W19
Y19
V20
W20
Y20
V21
W21
Y21
V22
W22
Y22
R300
VTERM1(15)
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSSP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AB22
Part 8 of 8
CORE GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N18
P18
VSS
R18
T18
U18
N19
P19
R19
T19
U19
N20
3
P21
VSS
R21
VSS
T21
VSS
U21
VSS
N22
VSS
P22
VSS
R22
VSS
T22
VSS
U22
VSS
V23
VSS
W23
VSS
Y23
VSS
AA23
VSS
AB23
VSS
V24
VSS
W24
VSS
Y24
VSS
AA24
VSS
AB24
VSS
V25
VSS
W25
VSS
Y25
VSS
AA25
VSS
AB25
VSS
V26
VSS
W26
VSS
AB26
VSS
V27
VSS
W27
VSS
Y27
VSS
AA27
VSS
AB27
VSS
AP28
VSS
AR26
VSS
AG22
VSS
AT22
VSS
AP34
VSS
AR20
VSS
AT23
VSS
AR21
VSS
AN31
VSS
AF22
VSS
AN23
VSS
AP25
VSS
AE22
VSS
AN30
VSS
AD22
VSS
AP22
VSS
AP17
VSS
AR18
VSS
AN19
VSS
AP21
VSS
AC22
VSS
AC21
VSS
AN24
VSS
AN16
VSS
AK6
VSS
AN10
VSS
AN15
VSS
AN20
VSS
AP13
VSS
AP14
VSS
AP18
VSS
AP9
VSS
AN11
VSS
AH7
VSS
AJ7
VSS
AP23
VSS
AF6
VSS
AG6
VSS
AD7
VSS
AE7
VSS
Y6
VSS
W7
VSS
M6
VSS
Y7
VSS
R7
VSS
P7
VSS
T6
VSS
K7
VSS
G12
VSS
F10
VSS
G9
VSS
F13
VSS
F15
VSS
G19
VSS
G15
VSS
G16
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P20
R20
T20
U20
N21
F18
F23
AN26
AC7
F26
G27
G28
F30
G31
J34
K34
K33
J6
N33
P34
V34
R34
P33
AC18
AD18
AE18
AF18
AG18
AG19
AF19
AE19
AD19
AC19
AC20
AD20
AE20
AF20
AG20
AG21
AF21
AE21
AD21
F8
H6
D7
K2
PLACE DIRECTLY
UNDERNEATH
CHANNELS A
AND B
PLACE DIRECTLY
UNDERNEATH
CHANNELS C
AND D
+VDDC_CT
C48
100nF
+VDDC
USE 47uF
TANTALUM
CAPACITOR OR
HIGHER
2
CP1A
10nF
8 1
CP2A
10nF
8 1
+VDDQ_BUS
+3.3V_BUS
+MVDDQ
2
C49
100nF
8 1
7 2
7 2
C64
47uF 16V
CP12A
10nF
CP1B
10nF
CP2B
10nF
C67
22uF 16V
C68
47uF 6.3V
1
C53
C50
C51
100nF
100nF
CP1C
10nF
6 3
CP2C
10nF
6 3
CP4A
CP4B
10nF
10nF
8 1
7 2
C60
10uf
PLACE DIRECTLY
UNDERNEATH ASIC
AT THE OPPOSITE
CORNER OF THE
VDDC FEED.
PLACE DIRECTLY UNDERNEATH
VDDP SECTION OF ASIC.
C65
10uf
8 1
C66
1uF
CP6A
10nF
8 1
C70
C71
10uf
10uf
C72
10uf
CP12B
CP12C
10nF
10nF
7 2
6 3
Title
Size Document Number Rev
Custom
Date: Sheet of
C54
5 4
5 4
CP5A
10nF
7 2
C73
10uf
CP1D
10nF
CP2D
10nF
C61
10uf
8 1
CP6B
10nF
C52
1uF
CP11A
10nF
10uf
C55
1uF
CP3A
10nF
8 1
CP4D
CP4C
10nF
10nF
5 4
6 3
C62
10uf
CP5B
CP5C
10nF
10nF
7 2
6 3
CP11B
10nF
7 2
CP6C
10nF
6 3
CP8A
10nF
8 1
7 2
CP9B
CP9A
10nF
10nF
7 2
8 1
CP12D
CP13A
10nF
10nF
5 4
8 1
7 2
5 4
CP8B
10nF
C56
1uF
CP3B
10nF
5 4
6 3
CP6D
10nF
22uF 16V
C63
10uf
CP5D
10nF
CP11C
10nF
6 3
7 2
C58
10uf
6 3
CP9C
10nF
CP13B
10nF
6 3
8 1
CP8C
10nF
C57
1uF
CP3C
10nF
5 4
CP7A
10nF
Diodes Da1
and Da2 are
needed to
protect ASIC
during power
ramping.
CP11D
10nF
5 4
6 3
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
1
C674
C59
10uf
100nF
5 4
CP9D
10nF
CP13C
10nF
5 4
7 2
CP8D
10nF
C673
1uF
CP3D
10nF
CP7B
10nF
C675
5 4
5 25Tuesday, March 11, 2003
+3.3V_BUS
+3.3V_BUS
100nF
6 3
C69
1uF
C707
100nF
CP13D
10nF
CP7C
10nF
Da1
D2
1.8V
2 1
Da2
D3
2.4V
2 1
CP7D
10nF
5 4
C708
100nF
C676
100nF
2.1
8
7
6
5
4
3
2
1
Layout Guide Lines for switching regulators
1) Feedback trace from the voltage divider resistors to the controller as short as possible.
2) Trace from VIN to Qb1 should be in the same layer, with no via, width no less than 2MM
3) VIN_SOURCE should be a 2-3" snaked trace (with at least 6 bends.) The trace width
should be 2 MM.
4) Components with " ** " should have two vias on each pad
5) Components with " *** " should have three vias on each pad.
6) Connections indicated by bold thick line are high current path. Short, thick traces (at
least 30 mil) should be used.
R77
150R
C86
2.2uF
C88
0.22uF
Cb4
+3.3V_BUS
R90
150R
C92
2.2uF
C152
0.22uF
R78
511R
1%
Rb1
R87
2.43K
1%
Rb2
***
DNI DNI DNI
C80
* * *
C10
470uF 10V
470uF
***
DUAL FOOTPRINT DUAL FOOTPRINT DUAL FOOTPRINT
*
Part
SC1175
IRU3047
SC1175
IRU3047
***
C81
C11
470uF 10V
470uF
***
C10, C11, C12, and C7 are the alternate surface
mount components for C80, C81, C82, C97
respectively.
VDDC Rb2
1.2V
1.5V
Part
INSTALL
Rb4, Rb6, Rb9, Rb10,
Cb4
Rb7, Rb8, Rb5, Cb1, Cb2
Db1, Db2
***
C82
C12
470uF
470uF 10V
*** ***
Rb1
110R 1% DNI
511R 1%
2.43k 1%
DO NOT INSTALL
Rb7, Rb8, Rb5, Cb1,
Cb2, Db2, Db1
Rb4, Rb6, Rb9, Rb10,
Cb4
+VDDC
**
***
C732
470uF
C84
22uF 16V
**
C740
1.0uF
FDS6898A
Q3B
FDS6898A
+5V_BUS
B28
60R
C741
1.0uF
FDS6898A
FDS6898A
+3.3V_BUS
***
PW
71
8
2
53
6
4
R85 100R
+5VEXT
B18
60R
71
8
2
Q4A
53
6
4
Q4B
R92 100R
B16
60R
Q3A
2 1
D25
MBRS340T3
1 2
PW1
2 1
C76
470uF 6.3V
1 2
D26
SK14
C139
10uF
1 2
R89
51.1R
D27
SK14
L1
1.5uH
R76
51.1R
1.5uH
B17
60R
L2
CORE REGULATOR VDDC
+5V_BUS
D D
R72
2.2R
R911
100KR910
10K
DNI
+12V_BUS
R73
2.2R
C87
1uF
C C
C90
1uF
B B
R81 0R
R83 0R
Rb9
Rb10
Rb7 Rb8
DNI
R74
33K
Cb1
DNI
C78
2.2nF
R940
75R
Cb2
DNI
R75
100K
C79
150pF
DNI
C77 1nf
U43
1
VREF
2
+IN2
3
-IN2
4
VCC
5
CL2-
6
CL2+
7
BST2
8
DH2
9
DL2
10 11
PGND BSTC
SC1175CSW
Alternate part IRU3047
PWRGD
SS/ENA
GND
CL1-
CL1+
BST1
R873
DNI
0R
20
C85
19
1nF
18
-IN1
17
16
15
14
13
DH1
12
DL1
PWGOOD_VDDC (2)
DNI
Rb5
R80 0R R82
R84 0R
Rb6
Rb4
0R
place close to U43
place close to U43
C93
10nF
C89
10nF
R71
5.1R
R79
5.1R
C91
470uF
Bb1
R88
5.1R
R91
5.1R
EXTERNAL POWER DETECT
+5V_BUS
Q10
MMBT3906
2
1
3
R876
680R
A A
8
R875
1K
C96
1nf
7
+5VEXT
R879
4.7K
EXT_PWR (14)
6
HEADER 1X4 RA
JUb2
JU2
22uF 16V
1
2
3
4
C101
+5VEXT +12VEXT
B30 60R
B31
60R
C124
C123
2.2uF
22uF 16V
5
C739
6.8uF 25V
C737
6.8uF 25V
4
Title
Size Document Number Rev
B
3
Date: Sheet of
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
6 25Tuesday, March 11, 2003
1
2.1
8
C763
C127
22nf
+PW_VDD
SS_VDD
C129
10nF
R122
15K
220nF
R121
3K
D D
C C
+12V_BUS
C743
220nF
+5V_BUS
DNI
R936
0R
R937
0R
C119
220nF
+12V_BUS
1
2
C734
1uF
DNI
C747
1nf
DNI
COMP_VDD
C128
33pF
7
MVDDC Switching Regulator for
Memory Core for 128M configuration
D6
BAT54SLT1
3
R112
0R C120
U48
2
DNI
Vcc
6
Vc
7
Comp
4
GND
IRU3037ACS
Alternate part IRU3037CS
Alternative 1
R118 10K
U49
2
OCSET
3
SS
4
COMP
5
FB
6
EN
7
GND
ISL6522CB
C107
10nF
BOOT1
C126
2.2nF
R116
27K
DNI
R120
51K
SS_VDD
COMP_VDD
C121 100nF
DNI
HDrv
LDrvSS
Fb
VCCRT
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
6
+PW_VDD
71
Q8A
C764
10nF
R954
10K
2
Q8B
4
53
R113
10R L5 2.2uH
5
38
1
+12V_BUS
141
13
12
11
BOOT1
10
9
8
C744
8
220nF
STS8DNF3LL
6
STS8DNF3LL
5
C745
220nF
Alternative 2
1 2
Cd1
Rd4
D24
S3AB
180uF 16V
C125
10nF
R115
1.5K
4
B29
60R
21
+12V_BUS
B21
***
+12VEXT
60R
**
R114
1%
1.33K
**
C746
10uF
DNI
**
** ***
Rd1
R117
499R
1%
Rd2
3
2
Layout Guide Lines for VDD switching regulator
The same rules apply as for VDDC regulator.
C8 is an alternate surface
*
mount component for C122.
+MVDDC
***
C8
DNI
*
470uF
DUAL FOOTPRINT
C122
470uF 10V
***
C736
470uF
***
Part
IRU3037
IRU3037A
ISL6522CB
IRU3037A
ISL6522CB
MVDDC
2.5V
2.5V
2.9V
Part
IRU3037
IRU3037A
Alternative1
ISL6522CB
Rd1
1.21K
1%
2.55K
1%
1.33K1%499R
INSTALL
1
Rd2
1.21K
1%
1.21K
1%
1%
DO NOT INSTALL
Cd1, Rd4, Alternative2
Alternative1Alternative2
Regulator for VTT Termination
+5V_BUS
+12V_BUS
+12V_BUS
B B
C103
150nF
+MVDDQ
A A
8
+PW_VTT
COMP_VTT
DNI
C105
10nF
R102
15K
C95
100nF
C762
100nF
R103 0R
R100 51K
R101 3K
DNI
C104
33pF
DNI
DNI
7
SS_VTT
C102 2.2nF
R96
27K
DNI
SS_VTT
DNI
R938
0R
BOOT
COMP_VTT
R939
0R
Alternative 1
U44
2
Vcc
6
Vc
7
Comp
4
GND
IRU3037ACS
Alternate part
IRU3037CS
DNI
R99 10K
U45
2
OCSET
3
SS
4
COMP
5
FB
6
EN
7
GND
ISL6522CB
C106
10nF
R93 10R
5
HDrv
38
LDrvSS
1
Fb
DNI
141
VCCRT
13
PVCC
12
LGATE
11
PGND
10
BOOT
9
UGATE
8
PHASE
6
C742
1.0uF
+12V_BUS
BOOT
Alternative 2
+PW_VTT
71
8
Q5A
2
STS8DNF3LL
53
6
Q5B
4
STS8DNF3LL
***
C94
470uF 6.3V
L3 3.3uH
1 2
5
Rb14
Cb5
B19
60R
+5V_BUS
Part
+VTT
** *****
DNI
DNI
C100
10nF
R95
1.5K
R94
825R
1%
Rb11
R97 1.40K
R98
1.10K
1%
DNI
Rb13
C7
470uF
***
DUAL FOOTPRINT
C97
470uF 10V
C98
22uF 16V
** **
+MPVDD
C99
22uF 16V
Rb12
4
3
IRU3037
IRU3037A
ISL6522CB
ISL6522CB
VTT
0.9V
1.25V DNI
0.9V
1.25V
1.40V 825R 1% 1.0K 1% DNI
Part
IRU3037
IRU3037A
Title
Size Document Number Rev
B
Date: Sheet of
Rb11
0R
1.07K 1%
576R 1%
INSTALL
Alternative1
Alternative2
R300 128M dual rank DVI VGA VO
2
Rb12 Rb13
DNI47.5K 1%
8.45K 1%
1.02K 1%
Cb5, Rb14,
Alternative2
Alternative1
GIGABYTE
GV-R9500
75K 1%
DNI
DNI
DNI
DO NOT INSTALL
7 25Tuesday, March 11, 2003
1
2.1
8
7
Regulator for MVDDQ (Memory I/O)
6
+5V_BUS
B22
***
60R
5
4
3
2
1
+1.8V Regulator for VDDC_CT (Core Transform)
D D
+12V_BUS
C133
100nF
C765
C142
150nF
C C
100nF
+MVDDC
+PW_VDDQ
COMP_VDDQ
C143 33pF
DNI
C144
10nF
R135 15K
Alternative 2
B B
+5V_BUS
A A
8
BOOT2
C141
2.2nF
R128
27K
R136 0R
DNI
R133 51K
R134 3K
DNI
SS_VDDQ
DNI
Part
IRU3037
IRU3037A
ISL6522CB
B26 200R
AS432S
MREG5
3 2
+12V_BUS
+5V_BUS
DNI
R9340RR935
0R
Alternative 1
U50
SS_VDDQ
COMP_VDDQ
R132 10K
C108
10nF
2
Vcc
6
Vc
7
Comp
4
GND
IRU3037ACS
Alternate part IRU3037CS
U51
2
OCSET
3
SS
4
COMP
5
FB
6
EN
7
GND
ISL6522CB
5
HDrv
38
LDrvSS
1
Fb
DNI
VCCRT
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
Alternative1 Ce1, Re8, Alternative2
REGULATOR
FOR
MVDD(+1.8V)
REG5
SC431LC5SK-1
5 3
Alternative1
Alternative2
R142
47R
+MPVDD +TPVDD
R144
681R
1%
1
R146
1.50K
1%
4
NC
1
NC
2
GND_MPVSS GND_TPVSS
7
141
13
12
11
10
9
8
DO NOT INSTALLINSTALL
R123 10R
+12V_BUS
BOOT2
+PW_VDDQ
71
8
53
6
C130
470uF 6.3V
Q9A
STS8DNF3LL
Q9B
STS8DNF3LL
L6 3.3uH
1 2
Ce1
Re8
C13 is an alternate surface
*
mount component for C136.
R124
4.99K
C140
10nF
1%
Re4
R127
1.5K
DUAL FOOTPRINT
*
C13
DNI
470uF
+MVDDQ
***
***
C136
470uF 10V
C137
C138
**
22uF 16V
**
**
22uF 16V
**
C748
1.0uF
2
4
Re5
R131
2K
1%
REGULATOR
FOR TPVDD
(+1.8V)
REG6
SC431LC5SK-1
5 3
Re4
1.21K
1%
2.55K
1%
4.99K1%2.0K
681R
1%
1.87K
1%
Part
MVDDQ
IRU3037
IRU3037A
ISL6522CB
IRU3037A
ISL6522CB
IRU3037
IRU3037A
ISL6522CB
+3.3V_BUS
B27 200R
R143
R145
681R
AS432S
1%
1
R147
MREG6
1.50K
1%
3 2
6
2.5V
2.5V
2.8V
1.8V
1.8V
18R
4
NC
1
NC
2
5
Re5
1.21K
1%
1.21K
1%
1%
1.5K
1%
1.5K
1%
4
3
C134
22uF 16V
+3.3V_BUS
B23
REG2
60R
LT1117CST
3 2
IN OUT
C135
100nF
ADJ
1
+3.3V_BUS
USE ONLY IF VDD IS +3.3V
B24
200R
1uF
C145
GND_A2VSSN GND_A2VSSN
+3.3V_BUS
B25 200R
3 2
Title
Size Document Number Rev
B
Date: Sheet of
+VDDC_CT
GND
2
R130
1.33K
1%
R126
562R
1%
+PVDD
VOUT
BYPASS
REGULATOR
FOR PVDD
(+1.8V)
4
NC
1
NC
2
GND_PVSS
C131
100nF
5 3
5
4
REGULATOR
FOR
A2VDD(+2.5V)
C147
470pF
DNI
REG4
SC431LC5SK-1
CASE
AS432S
MREG4
4
REG3
1
VIN
3
SHDN
2.5V
R139
18R
R140
681R
1%
1
R141
1.50K
1%
GIGABYTE
R300 128M dual rank DVI VGA VO
GV-R9500
2
C132
100uF 16V
+A2VDD
1uF
C146
8 25Tuesday, March 11, 2003
1
2.1
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