COVER SHEET
BOM & PCB MODIFY HISTORY
AGP BUS 8X
RV280 CORE
CC
BB
RV280 MEM INTERFACE
RV280 POWER
POWER_REG (VDDC/VDD)
POWER_REG (VDDQ/ETC)
OPTION STRAPS
SERIAL BIOS & HW STRAPS
SERIAL TERMINATION CHA
SERIAL TERMINATION CH B
TSOP 4/8Mx16 DDR
DAC RGB FILTERS
VIDEO MUX & VIVO
HEATSINK & MECHANICALS
BLOCK DIAGRAM
ATI REV HISTORY
SHEET
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3
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5
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AA
GIGABYTE THCHNOLOGIES , INC.
Title
SizeDocument NumberRev
B
星期四, 九月
8
7
6
5
4
3
Date:Sheetof
2
COVER SHEET
GV-R9200NF-NF3
25, 2003
118
1
1.0
5
4
3
2
1
Model Name: GV-R9200NF-NF3
Circuit or PCB layout change
for next version
Version:1.0
PAGEChange ItemReason
DD
167.64mm X 80.89mm, 60+/-10%
Component value change history
PAGEChange ItemReason
02.11.20NEW MODEL ,NEW BOM
02.12.17
03.02.07MODIFY BOM TO GV-R9200NF 1.0
03.02.18
03.02.18
03.03.14
03.03.14
CC
03.03.14
03.03.14
03.04.25
03.06.13TO P-BOM
03.07.04
03.07.14
03.07.25NF3 FOR 256MB (2 CHANNEL)
03.09.25
NEW MODEL ,NEW BOM, MODIFY BOM
FROM GV-R9000-8X 0.1
ADD SECOND SOURCE U1
(12SP3-040004-02)
ADD SECOND SOURCE J8
(11NR6-501002-30)
REMOVE 12KS2-010002-00
CHANGE U1 TO
M25P05-AVMN6T 512K ST
CHANGE C113 LOCATION
FROM BOTTOM TO TOP
CHANGE C57 LOCATION FROM
TOP TO BOTTOM
CHANGE MEMORY TO INFINEON
HYB25D256160BT-6,ONE CHANNEL ONLY
ADD SECOND SOURCE IR
F7413
ADD SECOND SOURCE
PCB CL,CB
REMOVE D30,D31;CHANGE U1
FROM FAB8 TO FAB12
02.11.20ATI DEMO BOARD A062
02.12.13ATI DEMO BOARD A062 REV. B
03.02.07
CHANGE MODEL NAME TO R9200NF
Rev. 1.0
BB
AA
Title
SizeDocument NumberRev
Custom
星期四, 九月
5
4
3
2
Date:Sheetof
GIGABYTE
BOM & PCB MODIFY HISTORY
GV-R9200NF-NF31.0
25, 2003
1
218
8
GND_TXVSSR
+12V_BUS
C10 place at the AGP connector
C10
DD
AGP_INTR#(4)
AGP_GNT#(4)
AGP_WBF#(4)
AGP_SB_STB#(4)
AGP_MB_8X_DET#(4)
AGP_DBI_HI(4)
AGP_RESET#(4)
CC
BB
AA
AGP_RESET#
AGP_AD_STB1#(4)
AGP_FRAME#(4)
AGP_TRDY#(4)
AGP_STOP#(4)
AGP_PAR(4)
AGP_AD_STB0#(4)
IT IS RECOMMENDED TO ALLOW SERIES RESISTOR
FOOT PRINTS ON THE INDICATED AGP CONTROL SIGNALS
TO ADDRESS ANY LAYOUT NOISE RELATED
SIGNAL DAMPING REQUIREMENTS
AGP_MB_8X_DET#
10U/12/Y/16V/S/X
4239010600
R3
100/6
U6A
R4
SN74ACT86D/SO14
180/6
COMMON
AGP_TYPEDET#
AGP_GC_8X_DET#
+3.3V_BUS+VDDQ_BUS
R830/6
+5V_BUS
147
3
R19
0/6/S
R81
0/6/S
R90
47K/6/S
13
12
7
C11
0.1U/6/Y/25V
1
2
For retail, 1K ohm
pull-down causes
AMD system detects
AGP2X only
+12V, TYPEDET#
short protection
for OEM (1KR)
U6D
SN74ACT86D/SO14
6
The following grounds should be routed back to their respective regulators and then tied directly to the ground plane with one
via: GND_PVSS, GND_MPVSS, GND_TPVSS, and GND_A2VSSN. The other ground pins (GND_AVSSN, GND_A2VSSQ,
GND_RSET, GND_R2SET) should be tied to the ground plane directly through one via as close to the pins as possible
without connecting to anything else. If space is an issue it is possible to use one via for two adjacent pins.
D SIZE
FOOTPRINT
MAGP1
A1
12V
A2
TYPEDET#
A3
GC_DET#/RESEVED
A4
USB-
A5
GND
A6
INTA#
A7
RST#
A8
GNT#
A9
VCC3.3
A10
ST1
A11
MB_DET#/RESERVED
A12
DBI_HI/PIPE#
A13
GND
A14
WBF#
A15
SBA1
A16
VCC3.3
A17
SBA3
A18
SB_STB#
A19
GND
A20
SBA5
A21
SBA7
A22
KEY
A23
KEY
A24
KEY
A25
KEY
A26
AD30
A27
AD28
A28
VCC3.3
A29
AD26
A30
AD24
A31
GND
A32
AD_STB1#
A33
C/BE3#
A34
VDDQ
A35
AD22
A36
AD20
A37
GND
A38
AD18
A39
AD16
A40
VDDQ
A41
FRAME#
A42
KEY
A43
KEY
A44
KEY
A45
KEY
A46
TRDY#
A47
STOP#
A48
PME#
A49
GND
A50
PAR
A51
AD15
A52
VDDQ
A53
AD13
A54
AD11
A55
GND
A56
AD9
A57
C/BE0#
A58
VDDQ
A59
AD_STB0#
A60
AD6
A61
GND
A62
AD4
A63
AD2
A64
VDDQ
A65
AD0
A66
VREFGC
UNIVERSAL AGP BUS/X
AGP_VREFGC
R_AGP8X must be 1%
resistor to provide
350mV +/- 5% on Vref
THE VALUES OF RSET AND R2SET SHOWN IN THE TABLE MAY BE
APPROXIMATE VALUES ONLY (SUITABLE FOR PROTOTYPING)
BEFORE GOING INTO PRODUCTION,CONTACT YOUR ATI
499R
REPRESENTATIVE FOR THE RSET/R2SET VALUES QUALIFIED FOR
(1) A2VDD regulated source
and A2VSSN return path routed
with at least 15 mil trace and
not longer than 1.5 inch.
AVSSN with single via to GND
at the regulator.
(2) Sourced from VDD thru bead
instead of the regulator
I/O
Matching
Ground
A2VSSN
(Noisy)
AC13
VDDC
AC15
VDDC
AC17
VDDC
AD13
VDDC
AD15
VDDC
M12
VDDC
M13
VDDC
M14
VDDC
M17
VDDC
M18
VDDC
M19
VDDC
N12
VDDC
N13
VDDC
N14
VDDC
N17
VDDC
N18
VDDC
N19
VDDC
P12
VDDC
P13
VDDC
P14
VDDC
P17
VDDC
A15
VDDR1
A21
VDDR1
AA7
VDDR1
AA8
VDDR1
D11
VDDR1
D14
VDDR1
D17
VDDR1
D8
VDDR1
V4
VDDR1
A28
VDDR1
A3
VDDR1
A9
VDDR1
AA1
VDDR1
AA4
VDDR1
AD4
VDDR1
B1
VDDR1
B30
POWER
VDDR1
D10
VDDR1
D19
VDDR1
D20
VDDR1
D23
VDDR1
D26
VDDR1
D6
VDDR1
V7
VDDR1
V8
VDDR1
G19
VDDRH0
N6
VDDRH1
G18
VSSRH0
M6
VSSRH1
VDDRH1 - CH B Clock PowerAGP Bus I/O Power
VDDRH0 - CH A Clock Power
(VDDR1)
A7
MPVDD
A6
MPVSS
AK27
PVDD
AK28Y23
PVSSVDDC18
PLL MPLL
AC10
VDDR4
AC9
VDDR4
AD10
VDDR4
AD9
VDDR4
AG10
VDDR4
AD22
Ext. TMDS/
DVO Power
(1.8V/3.3V)
VDDR3
AC22
VDDR3
AC21
VDDR3
AD21
VDDR3
AC19
VDDR3
AD19
VDDR3
AD7
VDDR3
AC8
VDDR3
(3.3V)
GPIO & Ext.
TMDS I/O
Power
AA23
VDDP
AA24
VDDP
AB27
VDDP
AB30
VDDP
AC23
VDDP
AD27
VDDP
AE30
VDDP
AH30
VDDP
J30
VDDP
M23
VDDP
M24
VDDP
N27
VDDP
N30
VDDP
P23
VDDP
T23
VDDP
T24
VDDP
T27
(1.5V/3.3V)(1.8V) (1.8V)
VDDP
T30
VDDP
V23
VDDP
V24
VDDP
W27
VDDP
W30
VDDP
Y27
VDDP
AH24
AVDDDI
AH23
A2VDDDI
AJ24
AVSSQ
AG23
AVSSDI
AD24
AVSSN
AE24
AVSSN
+A2VDDQ
1.8V
DAC2 Band Gap Ref.
Source from AVDD thru bead.
A2VSSQ with sigle via to GND
close to the pin.
4
+MVDDQ
+3.3V_BUS
GND_AVSSQ
GND_AVSSN
Matching
Ground
(Quiet)
C51
0.1U/6/Y/25V/S
+VDDQ_BUS
TP9
C65
0.1U/6/Y/25V/S
+AVDDDI
+A2VDDDI
1.8V
Digital Power for
DAC1 and DAC2
Source from VDDC_CT
thru bead
GND_MPVSS
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