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PCI-EXPRESS GIGABIT ETHERNET LAN CARD
GC-LC5721
C C
Revision 1.0
06/14/2004
01_CORVER
02_BROADCOM BCM5721M GIGABIT ETHERNET CONTROL L E R
B B
A A
03_PCI-EXPRESS GOLDEN FINGER & STB POWER
04_MAGNETICS & RJ45
05_GUIDELINES
06_BOM & PCB MODIFY HISTORY
BCM5721 196-Pin FBGA 15mm X 15mm
4 LAYER BOARD
GIGABYTE TECHNOLOGY CORPORATION
Title
Size Document Number Rev
Date: Sheet
5
4
3
2
星期四, 六月
17, 2004
COVER SHEET
GC-LC5721
1
16
1.0
of
Page 3
5
4
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Note: Verify that noise levels in the Design Guidelines are not exceeded.
VCC3
12
12
C2
C1
0.1U/4
4.7U/8
D D
C C
Note: Only add optional 30K resistors
to LPC bus to reduce current draw from
floating nets when left unconnected. Do
not add resistors if nets are connected in
a LPC application.
B B
C35 27P/6
C43 27P/6
12
12
C4
C3
0.1U/4
0.1U/4
PCIE_RXDP{3}
PCIE_RXDN{3}
PCIE_TXDP{3}
PCIE_TXDN{3}
PCIE_WAKE#{3}
PCIE_PERST#{3}
PCIE_REFCLKP{3}
PCIE_REFCLKN{3}
3VSB
LAN_SCL{3}
LAN_SDA{3}
12
12
R32
330K/6
12
12
C5
0.1U/4
VCC1_2SB
R25 30K/6
1 2
R26 30K/6
1 2
R29 4.7K/6/X
1 2
12
C6
10U/8
FB5
21
BLM11A601S/6
FB6
21
BLM11A601S/6
FB7
21
BLM11A601S/6
FB8
21
BLM11A601S/6
PCIE_RXDP
PCIE_RXDN
PCIE_TXDP
PCIE_TXDN
PCIE_WAKE#
PCIE_PERST#
PCIE_REFCLKP
PCIE_REFCLKN
Place 100-ohms termination
resistor close to controller
LAN_SCL
LAN_SDA
XTALO_R
12
Y1
25 MHZ
AVDDL
12
C17
4.7U/8
GPHY_PLLVDD
12
C19
4.7U/8
PCIE_PLLVDD
12
C21
4.7U/8
PCIE_SDS_VDD
12
C23
4.7U/8
C25 0.1U/4
1 2
C26 0.1U/4
1 2
CLK_SEL
1 2
LPC_FRAME#
LPC_RESET#
EXPORT#
R31 200/6
12
12
R33
1.24K/6/1
VCC3
VCC1_2SB
12
C18
0.1U/4
12
C20
0.1U/4
12
C22
0.1U/4
12
C24
0.1U/4
R20
100/6
XTALO
XTALI
RDAC
J10
F10
E10
F13
F12
G14
P10
N10
L11
M11
H11
K10
N13
J11
D10
N12
P12
A10
A7B3C5E1E4G1K3L4P2
U1
K8
VDDC
K7
VDDC
K6
VDDC
K5
K4
J5
J4
G4
F5
E9
E8
E7
E6
E5
B8
M8
M6
N6
P6
A6
C2
N8
P8
F4 H13
L5
K9
M9
L8
L9
D9
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
AVDDL
AVDDL
GPHY_PLLVDD
PCIE_PLLVDD
PCIE_SDS_VDD
PCIE_TXDP
PCIE_TXDN
PCIE_RXDP
PCIE_RXDN
WAKE#
PERST#
REFCLK+
REFCLKREFCLK_SEL GPIO1
LAD3
LAD2
LAD1
LAD0
LFRAME#
LRESET#
LCLK
SERIRQ
EXPORT#
BSAFE_GPIO1
BSAFE_GPIO0
SMB_CLK
SMB_DATA
XTALO
XTALI
RDAC
VDDIO_PCI
BROADCOM
BCM5721
VSS
VSS
VSS
VSS
VSS
VSS
B12E2F6F7F8
B7
P1G2A1
VESD1
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
15mm x 15mm
VSS
VSS
VSS
VSS
VSS
F9B4G5G6G7G8G9
VESD2
VESD3
BGA196
VSS
VSS
3VSB
D11
G11
K12
M12
VDDIO
VDDIO
VDDIO
WOL_VAUX
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G10H5H6H7H8H9H10J6J7J8J9K2N1N9P9
GPIO0_TST_CLKOUT
VSS
VSS
VSS
VSS
BIASVDD
A14
BIASVDD
XTALVDD
PCIE_TST
LINKLED#
SPD100LED#
SPD1000LED#
TRAFFICLED#
WL_LINK2.4G
WL_LINK5G
WL_ACTIVITY
PWR_IND#
ATTN_IND#
ATTN_BTTN#
REGSUP25
REGOUT25
REGSUP12
REGCTL12
REGSEN12
LOW_PWR
VAUXPRSNT
WOL_INRSH
VAUX_ON#
VMAIN_ON#
VSS
VSS
VSS
VSS
VCC2_5SB
FB1
21
BLM11A601S/6
12
VDDP
VDDP
VDDP
AVDD
AVDD
TRD3-
TRD3+
TRD2-
TRD2+
TRD1-
TRD1+
TRD0-
TRD0+
SCLK
SI
SO
CS#
GPIO2
EEDATA
EECLK
TRST#
TCK
TDI
TDO
TMS
A8
D5
P13
H14
A13
F14
E14
E13
D14
D13
C14
C13
B14
B13
D8
A11
B11
A12
B10
C10
B9
A9
H2
J2
A2
E11
E12
F11
C12
G12
G13
L10
K11
L14
M14
K14
J13
J14
L6
J12
P14
M13
N14
D12
D7
H12
D6
C11
C9
0.1U/4
VCC2_5SB
XTALVDD
AVDD_A13
AVDD_F14
TRD3N
TRD3P
TRD2N
TRD2P
TRD1N
TRD1P
TRD0N
TRD0P
PCIE_TST
LAN_LINK#
LAN_SPD100#
LAN_SPD1000#
LAN_ACT#
ATTN_BTTN
SCLK
5751_SI
5751_SO
CS#
GPI0
GPIO1
VAUX_25
REGCTL
LOW_POWER
AUX_PRES
TRST#
VCC2_5SB
12
12
C7
0.1U/4
FB2 BLM11A601S/6
C14 0.1U/4
1 2
FB3 BLM11A601S/6
C15 0.1U/4
1 2
FB4 BLM11A601S/6
C16 0.1U/4
1 2
R12 4.7K/6
1 2
TP2
TP3
R15 4.7K/6
1 2
R19 0/6/X
1 2
VCC2_5SB
12
12
C31
C32
0.1U/4
10U/8
R30 0/6
1 2
TP1
TP4
TP5
R34
4.7K/6
1 2
C8
0.1U/4
21
21
21
12
C29
0.1U/4
REGCTL_PNP
3VSB
3VSB
VCC2_5SB
12
C30
4.7U/8
3VSB
TRD3N {4}
TRD3P {4}
TRD2N {4}
TRD2P {4}
TRD1N {4}
TRD1P {4}
TRD0N {4}
TRD0P {4}
R13
1K/6
1 2
TRD3P
TRD3N
TRD2P
TRD2N
R1
49.9/4/1
R14
1K/6
1 2
U2
5
3
2
8
1
4
VCC
WP
RESET
SCK
SO
SI
GND
CS
AT45DB011B
12
12
R2
49.9/4/1
12
C10
0.1U/4
3VSB
6
7
1M Serial Flash
3VSB
12
32
Q1
1
PBSS5350Z
4
12
C33
C34
0.1U/4
4.7U/8
VCC1_2SB
12
12
C42
C41
10U/8
0.1U/4
R3
49.9/4/1
LAN_SPD1000#
LAN_SPD100#
LAN_LINK#
LAN_ACT#
12
C27
0.1U/4
SDA
SCL
12
12
C11
0.1U/4
R16
1K/6/X
1 2
12
R4
49.9/4/1
G
1
3VSB
1 2
12
2
A
R17
1K/6/X
R9
330/6
Y
3
VCC1_2SB
TRD1P
TRD1N
TRD0P
TRD0N
R5
49.9/4/1
LED1
DUAL_LED/sms
R18
4.7K/6/X
1 2
5
6
12
U3
SDA
SCL
AT24C256/X
12
R6
49.9/4/1
12
C12
0.1U/4
12
R10
330/6
LED2
LED/SMD
1 2
87
VCCWP
3
A2
2
A1
1
A0
4
GND
256K Serial EEPROM
12
12
12
C36
4.7U/8
12
C44
4.7U/8
C38
C37
0.1U/4
0.1U/4
12
12
C46
C45
0.1U/4
0.1U/4
3VSB
12
12
R7
49.9/4/1
12
C28
0.1U/4/X
C39
0.1U/4
C47
0.1U/4
3VSB
12
12
R8
49.9/4/1
12
C13
0.1U/4
12
R11
330/6
LED3
LED/SMD
1 2
12
12
C40
C78
0.1U/4
4.7U/8
12
12
C48
C79
0.1U/4
4.7U/8
BCM5721/5751M
VCC3
R36 4.7K/6
1 2
R38 4.7K/6/X
1 2
A A
CLK_SEL
AUX_PRES
R35 4.7K/6
R37 47K/6
3VSB
12
12
LED need reverse
5
4
3
2
3VSB
12
C49
4.7U/8
Title
Size Document Number Rev
Date: Sheet
12
12
C50
0.1U/4
C51
0.1U/4
12
C52
0.1U/4
GIGABYTE TECHNOLOGY CORPORATION
BCM5721 GIGABIT ETHERNET CONTR OLLER
17, 2004
GC-LC5721
星期四, 六月
12
12
C54
C53
10U/8
0.1U/4
1
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D D
LAN_SCL
R41 0/6
LAN_SCL{2}
LAN_SDA{2}
PCIE_WAKE#{2}
LAN_SDA
3VSB
PCIE_TXDP{2}
PCIE_TXDN{2}
1 2
R42 0/6
1 2
R43 10K/6
R44 0/6
R39
R40
47K/6
47K/6
1 2
1 2
LAN_SCL_R
LAN_SDA_R
12
12
PCIE_TXDP PCIE_REFCLKN
PCIE_TXDN
3VSB
4
VCC33VSB
PCIE1B
B1
12V
B2
12V
B3
RSVD
B4
GND
B5
SMCLK
B6
SMDAT
B7
GND
B8
3.3V
B9
JTAG1
B10
3.3VAUX
B11
WAKE*
B12
RVSD
B13
GND
B14
HSOP0
B15
HSON0
B16
GND
B17
PRSNT2*
B18
GND
PCIE_1X (FINGER)
KEY
PCIE1A
PRSNT1*
GND
JTAG2
JTAG3
JTAG4
JYAG5
3.3V
3.3V
PWRGD
KEY
GND
REFCLK+
REFCLK-
GND
HSIP0
HSIN0
GND
PCIE_1X (FINGER)
A1
A2
12V
A3
12V
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
VCC3
3
PCI_RST#WAKE#
PCIE_REFCLKP
PCIE_RXDP
PCIE_RXDN
PCIE_REFCLKP {2}
PCIE_REFCLKN {2}
PCIE_RXDP {2}
PCIE_RXDN {2}
2
3VSB
12
12
12
12
C57
0.001U/4
C61
0.001U/4
12
12
C58
0.001U/4
C62
0.001U/4
C55
C56
0.1U/4
0.1U/4
Place these decoupling capactors near golden fingers.
Left Side
VCC3
12
12
C59
C60
0.1U/4
0.1U/4
1
12
12
BC1
BC2
4.7U/8
4.7U/8
12
12
BC3
BC4
4.7U/8
4.7U/8
Place these decoupling capactors near golden fingers.
C C
3VSB
R51 10K/6
12
U6C
147
74LV14/TSSOP
5 6
3VSB
U6D
147
74LV14/TSSOP
9 8
U6E
147
74LV14/TSSOP
11 10
U6F
147
74LV14/TSSOP
13 12
Reserved external Power circuit
PCI_RST#
Provide a 1.2V/1.0A to LAN
Provide a 2.5V/1.0A to LAN
I1
I2
I3
I4
1
1
1
1
K1
K2
K3
K4
K5
B B
A A
1
1
MH1
923
45
1
678
K6
1
1
1
1
MH2
923
45
1
678
COUPON1
DIFF_COUPON
COUPON11
COUPON12
COUPON21
COUPON22
5
1
123
2
COUPON2
DIFF_COUPON
1
123
2
VCC2_5SB
12
C75
100U/1210/Y5V/X
3VSB
TOP Layer
Bottom Layer
3
3
3VSB
12
12
C66
0.1U/4/X
12
C67
0.1U/4/X
C63
4.7U/8/X
12
12
R45
22K/6/1/X
R47
20K/6/1/X
Layout Notice
U4
1
EN
2
VIN
3
VOUT
4 5
VADJ GND1
SC1565IS-2.5TR/SO8/X
vref = 1.2 V
Vout = 1.2 * ( 1+ 22K /20 K )
4
GND4
GND3
GND2
8
7
6
GND
Shape
VCC1_2SB
12
C76
100U/1210/Y5V/X
12
C68
0.1U/4/X
12
Vout = 1.2 * ( 1+ 0 /20 K )
3
3VSB
C69
0.1U/4/X
12
147
1 2
C64
4.7U/8/X
12
12
U6A
74LV14/TSSOP
VCC2_5SB
R46
0/6/X
R48
20K/6/1/X
2
R50 10K/6
R52 0/6
12
C65
Layout Notice
0.1U/4/X
U5
1
EN
2
VIN
3
VOUT
4 5
VADJ GND1
SC1565IS-2.5TR/SO8/X
vref = 1.2 V
12
12
GND4
GND3
GND2
3VSB3VSB
U6B
147
74LV14/TSSOP
3 4
12
C77
4.7U/8
8
7
6
GND
Shape
Title
Size Document Number Rev
Date: Sheet
PCIE_PERST# {2}
GIGABYTE TECHNOLOGY CORPORATION
PCI EXPRESS CON 1X
星期四, 六月
17, 2004
GC-LC5721
1
36
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1
Media Transmit/Receive Pairs BY CHIPSET
D D
VCC2_5SB
as short as possible
To BCM5701/BCM5703
1
TRD3N{2}
TRD3P{2}
TRD2N{2}
+
C C
-
TRD2P{2}
TRD1N{2}
+
TRD1P{2}
TRD0N{2}
TRD0P{2}
C70
0.1U/4
12
12
These CAPs for termination must be placed as close to Transformer as
possible to Minimize Common Mode Noise
C71
0.1U/4
12
C72
0.1U/4
2
3
4
5
6
7
8
9
10
11
12
12
C73
0.1U/4
Keep PAIR at least 100 mils from EACH OTHER
100 BASE 1000BASE
TX+ 1 TD1+
TX- 2 TD1-
+
-
T1
TCD_0
TRD+_0
TRD-_0
TCD_1
TRD+_1
TRD-_1
TCD_2
TRD+_2
TRD-_2
TCD_3
TRD+_3
TRD-_3
H5007/smd
MAGNETICS
12
R49
0/8/X
CMT_0
TXD+_0
TXD-_0
CMT_1
TXD+_1
TXD-_1
CMT_2
TXD+_2
TXD-_2
CMT_3
TXD+_3
TXD-_3
At Least 1" but not more than 4" and keep Close and Symmertrical and equal Length
Signal Trace between RJ45 and Magnetics should be routed with 50
Ohms controlled impedance with respect to Chassis Ground
+
75 OHM
This R pack must be placed as close to magnetics as possible.
Termination Plane: Bob Smith Termination
NOTE: RJ-45 CONNECTOR LIBRARY
LONGER PADS
J1
1
PR4PR4+
PR2PR3PR3+
PR2+
PR1PR1+
RJ45
SHOLE2
SHOLE1
2
3
4
5
6
7
8
RJ-45 CONNECTOR
DIP and SMD CO-LAY
CAPs added for EFT testing
1
10
9
24
23
22
21
20
19
18
17
16
15
14
13
RP1D
75
7 8
PC1 10U/12
1 2
BC5 1000P/8
1 2
BC6 1000P/8
1 2
PC2 4.7U/12
1 2
as short as possible
50 OHM
RP1B
RP1C
75
75
3 4
5 6
12
C74
1500P/3KV/SMD/X
Priority 1Priority 2
RP1A
75
1 2
THIS FOUR CAPS ACROSS THE GND TO AGND SPILT ARE LOCATED ABOVE THE MAGNETICS MODULE.
+
-
SMD
直行
8
RJ-45
RX+ 3 TD2+
B B
----- 4 TD3+
----- 5 TD3RX- 6 TD2-
----- 7 TD4+
----- 8 TD4-
PC3 10U/12
1 2
BC7 1000P/8
1 2
BC8 1000P/8
1 2
PC4 4.7U/12
1 2
Digital and Chassis Ground are Separated by 30 - 50 MILS
Cutting GND Plane Splited by Analog and Digital
1
THIS FOUR CAPS ACROSS THE GND TO AGND SPILT ARE LOCATED BELLOW THE MAGNETICS MODULE.
CHASSIS GND
For manufacture to test external loopback for
1000 times.
b57diag -t ABCD -T D3 -I 1000
A A
The pins connevction for external loopback
should be as following.
1-------3
2-------6
4-------7
5-------8
5
4
3
2
GIGABYTE TECHNOLOGY CORPORATION
Title
Size Document Number Rev
Date: Sheet
星期四, 六月
PHY MAGNETICS RJ45
GC-LC5721
17, 2004
46
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5
D D
C C
4
3
2
1
B B
A A
GIGABYTE TECHNOLOGY CORPORATION
Title
Size Document Number Rev
Date: Sheet
5
4
3
2
星期四, 六月
17, 2004
GUIDELINES
GC-LC5721
1
56
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Model Name: GC-LC5721
4
3
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1
Circuit or PCB layout change for next version
D D
Date
Page Page
Change Item
Circuit or PCB layout change for next version
Date Chan g e I t e m
Version: 0.20
04/16/2004 2. 1. PCIE_TXDP/N(Chipset) should connect to PCIE_RXDP/N
C C
04/16/2004 1. Add U6, R50, C77 for make a more than 12ms delay for
04/16/20043.4. 1. Reverse J1 connector for fit the TRD[0..3]N/P trace that
(Golden Finger).
2. PCIE_RXDP/N(Chipset) should connect to PCIE_TXDP/N
(Golden Finger).
3. Do not install the pull up resistor R13, R14 when
AT45DB011B not been used or the AT24C256 couldn't been
program. C27 is no need to installed.
4. Change the connection of TRD[0..3]N/P to transformer.
5. All LED of layout need to reverse. The direction of Rev 0.1
was wrong.
6. Add C78 & C79 4.7U/8 for VCC1_2SB.
PCI_RST- signal that solve chipset A0 issue.
2. Installed R52 and un-mount U6, R50 & C77 when use rev A1
chipset.
3. Add R51 for pull up the non-used pin of U6. Do not installed
it when use rev A1 chipset.
connected after transformer.
Version: 1.00
1. Change layout library of AT45DB011B.2.06/14/2004
B B
2. Mount R13, R14, U2, C27.
3. Un-mount R16, R17, R18, U3, C28.
A A
GIGABYTE TECHNOLOGY CORPORATION
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
BOM & PCB MODIFY HISTORY
17, 2004
GC-LC5721
星期四, 六月
1
66
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