Gigabyte Ga-9ivdpc_11 Schematics
第 1 頁，共 1 頁Technical Information Release Notice
Technical Information Release Notice
Doc Type Schematic Date 2005/6/17 下午 06:15:58
Project Code S93058-0 Customer
Project Name GS-SR195 Revision Old NA New 1.1
Model Name GA-9IVDPC IT Doc No DR056214
P/N RD Doc No
PCB Rev. 1.1 Check Sum
R N M
P/N Description
Description
Remark
Approved By daniel.hou 2005/6/17 下午 08:13:43 Applicant leopard.hsieh
Research
Management
Mimosa.Kao
2005/6/20 上午
10:25:30
Validation Manager Project Manager
Effected Class
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FinePrint - www.fineprint.com 用 列印 可在 訂購
2005/6/20http://10.1.1.15/ef2kweb/CHT/Forms/RTC009/RTC009_P.asp
Mimosa.Kao
5
4
3
2
1
LV-NOCONA800/ LINDENHURST
GA-9IVDPC V1.1
D D
01_TITLE
02_SYS BLOCK
03_SYS RESET
04_CLOCK BLOCK
05_SMBUS
06_POWER FLOW
07_PCI ROUTING_GPIO
08_CPU1 SYSTEM INTERFACE
C C
09_CPU1 TERMINATION
10_CPU1 POWER/GND
11_CPU2 SYSTEM INTERFACE
12_CPU1 POWER/GND
13_CPU1 TERMINATION/ITP
14_LEVEL SHIFT&CPU REDUCTION
15_MCH DDR266 CHANNEL A
16_MCH DDR266 CHANNEL B
17_MCH HI1.5&MISC
B B
18_MCH SYSTEM BUS
19_MCH PCI EXPRESS
20_MCH PWR/GND
21_MCH DECOUPLING
22_DDR266 CHANNEL A DIMMA1
23_DDR266 CHANNEL A DIMMA2
24_DDR266 CHANNEL A DIMMA3
25_DDR266 CHANNEL A DIMMA4
26_DDR266 CHANNEL A TERM/DECOUP
27_DDR266 CHANNEL A DIMMB1
A A
28_DDR266 CHANNEL A DIMMB2
29_DDR266 CHANNEL A DIMMB3
30_DDR266 CHANNEL A DIMMB4
5
31_DDR266 CHANNEL B TERM/DECOUP 61_P2V5 & P1V25_VTT
32_CK409B CLOCK GENERATOR
33_CK409B CLOCK TERMINATION
34_DB400 100NHZ BUFFER
35_PCIE X8 SLOT
36_HR PCI/HI/IDE/LPC/GPIO
37_HR SATA/GPIO/CPU/PCI-X
38_HR PWR/GND
39_HR IDE CONNECTOR
40_AIC-8130 PCIX/SATA
62_CPU1 VOLTERRA VRD
63_CPU2 VOLTERRA VRD
64_BROADCOM PCIE BCM5721
65_BROADCOM PCI BCM5705
66_IPMI & ID SWITCH
67_SMBUS MULTIPLEXER
68_COUPON
69_HISTORY
70_HISTORY
41_AIC-8130 POWER 1.2V/2.5V
42_AIC-8130 GPIO
43_AIC7901 PCIX INTERFACE
44_AIC-7901 SCSI CHANNEL
45_AIC-7901 TERMINATORS
46_AIC-7901 POWER & ZCR
47_ATI RAGE XL
48_ATI BUFFER & SDRAM
49_VGA CONNECTOR
50_SO-DIMM ZCR
51_PCIX SLOT_66MHZ
52_GLUE LOGIC CIRCUIT
53_IT8712F-IX SIO
54_FAN CONTROL
55_COM1 & KB/MOUSE
56_FRONT PANEL
57_ATX POWER CONNECTOR
3.70 mil
3.70 mil
11.1 mil
10.0 mil
11.1 mil
3.70 mil
3.70 mil
58_BIOS
59_USB
60_P1V5 & P_VTT
4
3
BOARD STACK-UP
PP 2116
CORE
PP 2116+7628
CORE
PP 2116+7628
CORE
PP 2116
2
COMPONENT SIDE
GND
INT 1
(PWR)
INT 2
SOLDER SIDE
Title
Size Document Number Rev
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
COVER SHEET
GA-9IVDPC
1
1.5 OZ
1 OZ
1 OZ
2 OZ
2 OZ(PWR)
1 OZ
1 OZGND
1.5 OZ
170Tuesday, June 14, 2005
2.0 mil
1.35 mil
1.35 mil
2.7 mil
2.7 mil
1.35 mil
1.35 mil
2.0 mil
of
1.1
5
4
3
2
1
EVRD 10.1
Intel Xeon
D D
RJ45
LAN
BROADCOM
BCM5751
PCI-E SLOT(X4)
X4
PCI EXPRESS X8 ( 16GB/S)
GbE MAC/PHY
X1
Processor
CPU 0
6.4GB/s
System Bus(800MT/S)
Intel
Lindenhurst
EVRD 10.1
Intel Xeon
Processor
CPU 1
2.1GB/s up to 2.7GB/s
Channel A
DDR266(X4)/333(X3)DIMMModuleX4
Channel B
VS
C C
ZCR SO-DIMM
PCI-X 66MHZ SLOT
RJ45
LAN
68PIN SCSI CON
SATAx4
AIC8130
AIC7901
HUB INTERFACE 1.5
266MB/s
PCI-X (64/66)
Hance
2.1GB/s up to 2.7GB/s
150MB/s
SATAx2
USB
DDR266(X4)/333(X3)DIMMModuleX4
Rear Panel USB 2.0X2
Rapids
B B
BCM5705
PCI 32 Bit BUS 133MB/s
ESB6300
IDE Connector * 1IDE BusATA-100
8MB
SDRAM
ATI Rage XL
VGA
Intel
FWH
LPC
IPMI
Front USB
SST49LF004B
VGA CON
IT8712IX
LPC Super I/O
128 PQFP
A A
COM1 LPT/GPIO
5
4
COM2 for
LCD Module
3
GIGA-BYTE TECHNOLOGY CO., LTD.
Title
Size Do c um e n t N u mb er Re v
2
Date: Sheet
BLOCK DIAGRAM
GA-9IVDPC
1
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SYS RESET & PWR SET
4
3
2
1
BTN
LEVEL
D D
LOGIC
DB400
CK409B
CK409B_PWR_GD#
VID_PWRGD
C C
B B
FP
PWRDWN#
PWRDWN#
CPU0_THRMTRIP#
VIP_PWRGD
CPU_PWR_GD
CPU_RST#
CPU0_BSEL[0/1]
CPU1_BSEL[0/1]
VIP_PWRGD
CPU_PWR_GD
CPU_RST#
CPU1_THRMTRIP#
PWB+
R
CPU_VRD_PWR_GD
VTT
LEVEL
P0
VTTEN
VTTEN
P1
FET
LINDENHUST
CPU_RST#
A A
BTN
PCI_RST#
5
MCH
FP
PWROK
RST_SW
P1_SKT0CC#
CPU_PWR_GD
PWRBTN
75
SB_VTT_PWRGD
VTTEN
P3V3
LEVEL
71
SIO
1.2V
ISL6227
VTT_PWRGD
BSEL
COMPARE
LOGIC
H-R
SYS RST#
76
72
ATX_PG
DDR DIMM DDR DIMM
DDR DIMM
DDR DIMM
AB
DDR DIMM
VTT_ENABLE
DDRA_PCIRST#
CPU_VRD_PWR_GD
DDR DIMM
DDR DIMM
DDR DIMM
DDRB_PCIRST#
2.5V
ISL6563
1.25V
6420A
PLD
PWRGD_1_5VPWRGD_2_5V
1.5V
ISL6539
LOGIC
100ms
CPU_VRD_PWR_GD
SYS_PWR_GD_3_3V
PWROK
PCI_RST#
4
PCI_RST#
RESET buffer
SYS_PWR_GD#
PLD
PCI_RST_BUFF1#
BUFF
IDE_RSTDRV#
ATI VGA
SII3114
PCI-64/66 CONN
ATP867
PCI- 32/33 CONN
3
RESET buffer
IDE_RSTDRV#
PWRBTN
SLP_S#3
PS_PWR_GD
PS_PWR_GD#
VR0_SYS_ENABLE
VR1_SYS_ENABLE
CPU1_VRD_PWR_GD
SYS_PWR_GD_BUFF
IDE CONN
IDE CONN
PCI-E 5751
PCI-X 82541PI
SIO
SE-LINK
FWH
IDE CONN
2
ATX CONN
H-R
SLP_S#3
ATX_PG
PCI-E X4 SLOT1
GIGA-BYTE TECHNOLOGY CO., LTD.
Title
Size Do c um e n t N u mb er Re v
Date: Sheet
SYS RESET
5VSB
3VSB
ISL6227
5V
ISL6227
3V
ISL6227
P0 VCORE
ISL6563CPU0_VRD_PWR_GD
P1 VCORE
ISL6563
GA-9IVDPC
1
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14.318
CRYSTAL
CPU3
D D
CPU2
3V66_1
CPU1
CPU0
SMA CONNECTOR
ITP_BCLK_P/ N ( 1 6 7MHZ)
2
MCH_BCLK_P/ N ( 1 6 7MHZ)
2
MCH_66MHZ_CLK
P1_BCLK_P/N(167MHZ)
2
P0_BCLK_P/N(167MHZ)
2
CK 409B
CLOCK SYNTHESIZER
DRIVER
C C
3V66_2
USB_48
PCIF0
REF0
DOT_48
PCI_4
ICH_HI66MHZ_CLK
ICH_USB_48MHZ_CLK
ICH_33MHZ_CLK
ICH_14MHZ_CLK
SIO_48MHZ_CLK
SIO_33MHZ_CLK
CLOCK BLOCK DIAGRAM
ITP_XDP
DDRA_CMDCLK_A0_P/N
DDRA_CMDCLK_A1_P/N
DDRA_CMDCLK_A2_P/N
BCLK(P/N-1/0)
BCLK(P/N-1/0)
32.768KHZ
CRYSTAL
Hance
Rapids
SIO
CUP1
CUP0
MCH_SRC_100MHZ_CLK_P/N
ICH_SRC_100MHZ_CLK_P/N
SUS_CLK
DDRA_CMDCLK_A3_P/N
DDRB_CMDCLK_B0_P/N
DDRB_CMDCLK_B1_P/N
LINDENHURST
DDRB_CMDCLK_B2_P/N
DDRB_CMDCLK_B3_P/N
SRC
2
DDR266 DIMM #A1
DDR266 DIMM #B1
2
DDR266 DIMM #A2
DDR266 DIMM #B2
DDR266 DIMM #A3
2
2
2
2
2
2
PCI EXPRESS SLOT1
EXP_SLOT1_100MHZ_CLK_P/N
2
DIFF0 DIFF1
2
DB400 (SRC -DIFFERENTIAL BUFFER)
2
DIFF3
DIFF2
DDR266 DIMM #B3
DDR266 DIMM #B4
DDR266 DIMM #A4
DB400_SRC_100MHZ_CLK_P/N
SRC
B B
PCIF1
PCI 0
PCI_SLOT3_33MHZ_CLK
VIDEO_33MHZ_CLK
PCI 1
PCI 2
REF 1
PLD_33MHZ_CLK
VIDEO_14MHZ_CLK
FWH_33MHZ_CLK
PCI 3
A A
2
PCI 32/33 (SLOT )
PLD
VIDEO
(RAGE XL)
FWH
25MHZ
CRYSTAL
SUS_CLK
PCIXSLOT
82541PI
ATP867B
SIL3114
25MHZ
CRYSTAL
Title
2
BCM5751
25MHZ
CRYSTAL
GIGA-BYTE TECHNOLOGY CO., LTD.
CLOCK BLOCK
Size Document Number Re v
GA-9IVDPC
5
4
3
Date: Sheet
2
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Hance
D D
Rapids
SMB Address = 44h
HR SMB PU 3.3VSB
HR/ LAN1/LAN2/SMBUS_HEADER
BUS0
ICH_SDA
C C
ICH_SCL
SMB Address = E0h
PCA9545/SO8
BUS1
BUS1
I2C_SDA
ITE-8712F-IX BACK-PLANE
SMB Address = 5Ah
DIMM B-1
SMB Address = A8h
DIMM A-1
SMB Address = A0h
HW W83792D
DIMM B-2 DIMM B-3 CK-409B
SMB Address = AAh
DIMM A-2
IPMI MODULE POWER MODULE
DIMM B-4
SMB Address = ACh
DIMM A-3
SMB Address = A4hSMB Address = A2h
SMB Address = AEh
DIMM A-3
SMB Address = A6h
P3V3
SMB Address = D2h
P3V3
I2C_SCL
BUS2
B B
PCI-X Slot1
PCI-E Slot#166MHZ
DB400
SMB Address = DCh
MCH
LINDENHURST-VS
SMB Address = 60h
P3V3
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
SMBUS
GA-9IVDPC
570Friday, June 17, 2005
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ERP12V
VT1105M,VT1105S
P12V_CPU_0
120A
VT1105M,VT1105S
P12V_CPU_1
D D
120A
P_VCCP0
P_VCCP1
CPU0
1.0/CORE
CPU1
1.0/CORE
MCH
1.2/1.5/2.5
DDR266 Hance
1.25/2.5
Rapid
1.2/1.5
3.3/P3V3_STBY/P5V_STBY
IT8712F
300mW max
P5V
P5V_STBY VBAT
ATX CONN
P12V
P12V
ISL6563
39A/8A
ISL6539
8A/15A
C C
B B
P2V5
P1V25_VTT
P_VTT
P1V5
38.8A
6.5A
6.5A
13A
4.8A
8.8A
3.2A
5.5A
30.0A
6.5A
732 mA
2.5 mA
142 mA
60 mA
30 mA
P5V_STBY
P3V3_STBYP5V_STBY
2000mA
P3V3_STBY
P5V
PCI-X CONN
P3V3
A A
P3V3_STBY
P3V3
PCI-E CONN
RC1117
320 mA
FAN1112
400 mA
26mA(3.3V) + 206mA(2.5V)
MMJT9435
563mA
P12V
5
4
3
40 mA
320mA
400mA
563mA
3.3V
1.8V
1.2V
3.3V
1.2V
BCM5705
BCM5721 1.5W
206mA
2
2.5V3.3V
GIGA-BYTE TECHNOLOGY CO., LTD.
Title
Size Do c um e n t N u mb er Re v
Date: Sheet
PWR DELIVERY
GA-9IVDPC
1
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1.1
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Hance Rapids
GPIO R PWR WELL FUNCTION
GPI 0
GPI 1
GPI 2
GPI 3
GPI 4
D D
GPI 5
GPI 6
GPI 7
GPI 8
GPI 9
GPI 10
GPI 11
GPI 12
GPI 13
GPI 14
GPI 15
GPO 16
GPO 17
GPO 18
GPO 19
GPO 20
GPO 21
GPIO 22
GPO 23
C C
GPIO 24
GPIO 25
GPIO 26
GPIO 27
GPIO 28
GPIO 29
GPIO 30
GPIO 31
GPIO 32
GPIO 33
GPIO 34
GPIO 35
GPIO 36
GPIO 37
GPIO 38
GPIO 39
GPIO 40
GPIO 41
GPIO 42
B B
GPIO 43
GPIO 44
GPIO 55
GPIO 56
GPIO 57
GPIO 58
GPIO 63
NOTE
PUPU8.2K
I
I
I
PU
I
PU
I
PU
I
I
PU 4.7K P3V3
I
PU IN P3V3_STBY
I
I
I
PU
PU
I
O
PU IN
O
PU IN
O
O
O
O
OD
O
I
PU 8.2K
I/O
PU 8.2K
O
PU 8.2K
O
PU 8.2K
O
O
O
O
PU 8.2K P3V3
/O
I
/O
PU
I
PU
/O
I
PU
/O
I
O
O
I
O
I/O
I
I
PD
PU
OD
PU
OD
P3V3
8.2K
P3V3
8.2K
P3V3
8.2K
P3V3
8.2K
P3V3
8.2K
P3V3
4.7K
P3V3PU
8.2KPU ICH_SMBALERT# ALERT EVENT FROM SMBUS
P3V3_STBY
8.2K
P3V3_STBY
8.2K
P3V3_STBY
P3V3
P3V3
P3V3
P3V3
P3V3
P3V3
P3V38.2K
P3V3
P3V3_STBY
P3V3_STBY
P3V3_STBY
P3V3_STBY
P3V3
P3V3
8.2K
P3V3
8.2K
P3V3
8.2K
P3V3
P3V3
P3V3
10K
10K ERROR SIGNAL FROM IPMIP3V3
P3V3_STBY
10K
P3V3_STBY
10K
ONLY GPIO[0:15] ALLOW AN INPUT TO BE ROUTED TO SMI# OR SCI
SIGNAL NAME
PX_REQ2PX_REQ3-
P_ IRQE-PU
P_ IRQFP_ IRQGP_ IRQH-
RESERVED
RESERVED
MCH_PME#
RESERVED
RESERVED
PX_GNT2PX_GNT3-
HW_CPU1_SMI# CPU1 SMI OUT
SATALED# HR SATALED
HW_CPU0_SMI#
PANEL_ALERT# H/L
RESERVED
RESERVED
RESERVED
RESERVED
PX_IRQ0PX_IRQ1PX_IRQ2PX_IRQ3WP#
TBL#
NMI#/SMI#
SCSI_DIS
P66DETPD
ALL_ERROR
RESERVED
RESERVED
PLL0
PLL1
RESERVED
RESERVED
PX_REQ2PX_REQ3-
NO USE
NO USE
CPU0_PROCHOT#
CPU1_PROCHOT#
CPU0 THERMALTRIP INPUT
CPU1 THERMALTRIP INPUT
SIO_SMI#
NO USE
PME EVENT FROM MCH
PX_GNT2PX_GNT3-
NO USE
NO USE
NO USE
CPU0 SMI OUT
ALERT FROM FRONT PANEL
NO USE
POWER LED CONTROL
POWER LED CONTROL
WDT_TOUTPCI-X CONN
PCI-X CONN
PCI-X CONN
PCI-X CONN
BIOS WP#
BIOS TOP BLOCK
LOCK#
NMI OR SMI INPUT
DISABLE OBBOARD SCSI
NO USE
DETECT PRIMERY IDE CABLEP3V3
PLLSEL0
PLLSEL1
NOMAL/ACT
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/L
H/H
H/L
H/L
H/L
H/L
L/H
H/L
H/L
L/H
H/L
H/L
H/L
GPIO PWR
GPIO 17
GPIO 22
GPIO 23
GPIO 42
GPIO 43 STBY
GPIO 44
GPIO 45 STBY
GPIO 46
GPIO 47
GPIO 53
GPIO 54
GP40
GP41
P5V
P5V
P5V
STBY
STBY
STBY O
STBY
STBY
STBY
STBY
STBY
I
I
O
OD
I/OD
PU_8.2K
PU_8.2K
GP30
GP31
GP32
GP33
GP34
GP35
GP37
GP52
GP24
GP25
GPIO(10/40/41/42/43/44/45/46/53/54/55) POWER BY STBY
NOTE
PLL[1:0]
133/533
167/667
200/800 1100
A Inverter between S.B and MCH , so below table difference MCH spec. table
DDR266
DDR333
01
00
SB_CPU_FORCEPR#
strap to 0.
strap to 0.
SIO_PSON# PWR ON FROM SIO(NO USE)O
PWBTIN
HR_PWRBNIN#
SLP_S#3
DIS_BCM5705
SIO_SMI
DIS_BCM5721
ICH PME
SIO_SCL
SIO_SDA
CPU1 VID0
CPU1 VID1
CPU1 VID2
CPU1 VID3
CPU1 VID4
CPU1 VID5
FAN TAC1
FAN TAC2
FAN TAC3
FAN TAC4
11
01
SIO
FUNCTION NOMAL/ACT
PWR BTIN FROM FP(NO USE)
HR_PWRBNIN#(NO USE)
H/L(PWR ON)
H/L
H/L
H/L
H/L
H/L
H/LO
H/L
H/L
H/L
H/L
PCI DEVICE
PCI-X 66 SLOT
PCI-X 64/66 AIC7902
PCI-X 64/66 ADAPTEC SATA2
SODIMM ZCR SLOT
A A
BCM5705 PCI LAN
IDSEL
PX_AD18
PX_AD20
PX_AD21
PX_AD22
AD20
REQ / GNT
PX_REQ0 / PX_GNT0
PX_REQ1 / PX_GNT1
PX_REQ2 / PX_GNT2
PX_REQ3 / PX_GNT3
REQ2/GNT2 IRQB
IRQ ROUTING
3 0 1 2
0
1
2
IRQCATI RAGE XL VGA AD30 REQ0/GNT0
GIGA-BYTE TECHNOLOGY CO., LTD.
Title
Size Do c um e n t N u mb er Re v
5
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Date: Sheet
PCI ROUTING
GA-9IVDPC
1
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END PROCESSOR 0
SB_BPRI#[11,18]
SB_CPU0_BREQ#23[9]
SB_BREQ#1[9,11,14]
SB_BREQ#0[9,11,14]
SB_CPURST#[9,11,13,14,18]
D D
C C
P_VCCP_A_CPU0
AGND_CPU0
B B
P_VTT
SB_RS#[2..0][11,18]
SB_RSP#[11,18]
SB_CPU_A20M#[9,11,37]
SB_CPU_IGNNE#[9,11,37]
SB_CPU_INIT#[9,11,37,58]
SB_CPU_NMI[9,11,14]
SB_CPU_INTR[9,11,37]
CPU_PWR_GD[9,11,13,52]
SB_CPU0_SMI#[14]
SB_CPU_SLP#[9,11,37]
SB_CPU_STPCLK#[9,11]
P0_BCLK#[32]
P0_BCLK[32]
ITP_TCK0[11,13]
ITP_TDI_MAIN[13]
ITP_TMS_MAIN[11,13]
ITP_TRST#[11,13,17]
SB_CPU0_BSEL1[9,10]
SB_CPU0_BSEL0[9,10]
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
VID_CPU0_R5[53,62]
VID_CPU0_R4[53,62]
VID_CPU0_R3[53,62]
VID_CPU0_R2[53,62]
VID_CPU0_R1[53,62]
VID_CPU0_R0[53,62]
VR0_VCCSENSE[62]
VTTEN[9,11,52]
VR0_VSSSENSE[62]
SB_BPRI#
SB_CPU0_BREQ#23
SB_BREQ#1
SB_BREQ#0
SB_CPURST#
SB_RS#2
SB_RS#1
SB_RS#0
SB_RSP#
SB_CPU_A20M#
SB_CPU_IGNNE#
SB_CPU_INIT#
SB_CPU_NMI
SB_CPU_INTR
CPU_PWR_GD
SB_CPU_SLP#
SB_CPU_STPCLK#
P0_BCLK#
P0_BCLK
ITP_TCK0
ITP_TDI_MAIN
ITP_TMS_MAIN
ITP_TRST#
SB_CPU0_BSEL1
SB_CPU0_BSEL0
VID_CPU0_R5
VID_CPU0_R4
VID_CPU0_R3
VID_CPU0_R2
VID_CPU0_R1
VID_CPU0_R0
VR0_VCCSENSE
VTTEN
VR0_VSSSENSE
D23
D10
E11
F12
D20
F21
D22
E21
F27
C26
G23
B24
AB7
C27
AE6
E24
C24
A25
F24
AB3
AA3
AE29
AE28
AE30
AD29
AD28
AC29
AB29
AB28
AA29
AA28
AE15
AC1
AE16
AD4
B27
AB4
AA5
D26
Y8
C6
D6
D4
W5
Y4
Y3
A1
B3
C3
D3
E3
F3
E1
U36A
BPRI#
NOCONA 667
BR3#
BR2#
BR1#
BR0#
RESET#
RS2#
RS1#
RS0#
RSP#
A20M#
IGNNE#
INIT#
LINT1_NMI
LINT0_INTR
PWRGOOD
SMI#
SLP#
STPCLK#
BCLK1
BCLK0
TCK
TDI
TMS
TRST#
BSEL1
BSEL0
RESERVED1
RESERVED0
RSVD16
RSVD15
RSVD14
RSVD13
RSVD12
RSVD10
RSVD9
RSVD8
RSVD7
RSVD3
RSVD2
RSVD1
VID5
VID4
VID3
VID2
VID1
VID0
VCCIOPLL
VCC_SENSE
VTTEN
VCCA
VSSA
VSS_SENSE
NOCONA 667_7
ADS#
BINIT#
BNR#
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
TRDY#
LOCK#
MCERR#
IERR#
FERR#
THERMTRIP#
PROCHOT#
TDO
GTLREF3
GTLREF2
GTLREF1
GTLREF0
ODTEN
SKTOCC#
COMP3
COMP2
COMP1
COMP0
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
SMB_PRT
VCCPLL
THERMDC
THERMDA
BOOT_SELECT
RSVD
VIDPWRGD
TEST_BUS
FORCEPR#
SLEW_CTRL
OPTIMIZED_COMPAT#
SB_ADS#
D19
SB_BINIT#
F11
SB_BNR#
F20
CPU0_BPM#5
E4
CPU0_BPM#4
E8
CPU0_BPM#3
F5
CPU0_BPM#2
E7
CPU0_BPM#1
F8
CPU0_BPM#0
F6
SB_DBSY#
F18
SB_DEFER#
C23
SB_DRDY#
E18
SB_HIT#
E22
SB_HITM#
A23
SB_TRDY#
E19
SB_LOCK#
A17
SB_MCERR#
D7
SB_CPU0_IERR#
E5
SB_CPU_FERR#
E27
CPU0_THERMALTRIP#
F26
SB_CPU0_PROCHOT#
B25
ITP_TDO_P0
E25
F9
F23
W9
W23
PD_ODTEN_CPU0
B5
SMC_CPU0_SKTOCC#
A3
PD_COMP3_CPU0
AC28
PD_COMP2_CPU0
D25
PD_COMP1_CPU0
E16
PD_COMP0_CPU0
AD16
PU_CPU0_8
Y29
PU_CPU0_7
A26
PU_CPU0_6
AE5
PU_CPU0_5
AD5
PU_CPU0_4
AA7
PU_CPU0_3
Y6
PU_CPU0_2
W8
PU_CPU0_1
W7
PU_CPU0_0
W6
AE4
AD1
CPU0_THERMDC
Y28
CPU0_THERMDA
Y27
PU_BOOT_SELECT_CPU0
G7
W3
VID_PWRGD
B1
SB_CPU0_CPU1_TESTBUS
A16
CPU_FORCEPR#
A15
SLEW_CTRL_CPU0
AC30
CPU0_OPTIM_COMPAT_CTRL
C1
COMP3 =SB_CPU0_ADDR_ERC
COMP2 =SB_CPU0_DATA_ERC
PU_CPU0_8=SB_CPU0_EDRDY
PU_CPU0_0=SB_CPU0_SNPD#
TP15
TP16
SB_ADS# [11,18]
SB_BINIT# [9,11,18]
SB_BNR# [9,11,18]
CPU0_BPM#[5..0] [13]
SB_DBSY# [11,18]
SB_DEFER# [11,18]
SB_DRDY# [11,18]
SB_HIT# [9,11,18]
SB_HITM# [9,11,18]
SB_TRDY# [11,18]
SB_LOCK# [11,18]
SB_MCERR# [ 9 ,11 ,1 8]
SB_CPU0_IERR# [9,14]
SB_CPU_FERR# [9,11,37]
CPU0_THERMALTRIP# [14]
SB_CPU0_PROCHOT# [9,14]
ITP_TDO_P0 [13]
PD_ODTEN_CPU0 [9]
SMC_CPU0_SKTOCC# [9,66]
PD_COMP3_CPU0 [9]
PD_COMP2_CPU0 [9]
PD_COMP1_CPU0 [9]
PD_COMP0_CPU0 [9]
PU_CPU0_8 [9]
PU_CPU0_7 [9]
PU_CPU0_6 [9]
PU_CPU0_5 [9]
PU_CPU0_4 [9]
PU_CPU0_3 [9]
PU_CPU0_2 [9]
PU_CPU0_1 [9]
PU_CPU0_0 [9]
CPU0_THERMDC [10]
CPU0_THERMDA [10]
PU_BOOT_SELECT_CPU0 [9]
VID_PWRGD [11,52]
SB_CPU0_CPU1_TESTBUS [9,11]
CPU_FORCEPR# [9,11,14]
SLEW_CTRL_CPU0 [9]
CPU0_OPTIM_COMPAT_CTRL [9]
SB_D#[63..0][11,18]
VREF_P_VTT_CPU0_3
VREF_P_VTT_CPU0_0
PU_VCCPLL_CPU0
SB_D#63
SB_D#62
SB_D#61
SB_D#60
SB_D#59
SB_D#58
SB_D#57
SB_D#56
SB_D#55
SB_D#54
SB_D#53
SB_D#52
SB_D#51
SB_D#50
SB_D#49
SB_D#48
SB_D#47
SB_D#46
SB_D#45
SB_D#44
SB_D#43
SB_D#42
SB_D#41
SB_D#40
SB_D#39
SB_D#38
SB_D#37
SB_D#36
SB_D#35
SB_D#34
SB_D#33
SB_D#32
SB_D#31
SB_D#30
SB_D#29
SB_D#28
SB_D#27
SB_D#26
SB_D#25
SB_D#24
SB_D#23
SB_D#22
SB_D#21
SB_D#20
SB_D#19
SB_D#18
SB_D#17
SB_D#16
SB_D#15
SB_D#14
SB_D#13
SB_D#12
SB_D#11
SB_D#10
SB_D#9
SB_D#8
SB_D#7
SB_D#6
SB_D#5
SB_D#4
SB_D#3
SB_D#2
SB_D#1
SB_D#0
AB6
AA8
AC5
AC6
AE7
AD7
AC8
AB10
AA10
AA11
AB13
AB12
AC14
AA14
AA13
AC9
AD8
AD10
AE9
AC11
AE10
AC12
AD11
AD14
AD13
AB15
AD18
AE13
AC17
AA16
AB16
AB17
AD19
AD21
AE20
AE22
AC21
AC20
AA18
AC23
AE23
AD24
AC24
AE25
AD25
AC26
AE26
AA19
AB19
AB22
AB20
AA21
AA22
AB23
AB25
AB26
AA24
Y23
AD27
AA25
Y24
AA27
Y26
Y9
U36B
D63
NOCONA 667
D62
D61
D60
D59
D58
D57
D56
D55
D54
D53
D52
D51
D50
D49
D48
D47
D46
D45
D44
D43
D42
D41
D40
D39
D38
D37
D36
D35
D34
D33
D32
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NOCONA 667_7
A35
A34
A33
A32
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
BREQ4#
BREQ3#
BREQ2#
BREQ1#
BREQ0#
DBI3#
DBI2#
DBI1#
DBI0#
DP3#
DP2#
DP1#
DP0#
AP1#
AP0#
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
SB_HA#35
C8
SB_HA#34
C9
SB_HA#33
A7
SB_HA#32
A6
SB_HA#31
B7
SB_HA#30
C11
SB_HA#29
D12
SB_HA#28
E13
SB_HA#27
B8
SB_HA#26
A9
SB_HA#25
D13
SB_HA#24
E14
SB_HA#23
C12
SB_HA#22
B11
SB_HA#21
B10
SB_HA#20
A10
SB_HA#19
F15
SB_HA#18
D15
SB_HA#17
D16
SB_HA#16
C14
SB_HA#15
C15
SB_HA#14
A12
SB_HA#13
B13
SB_HA#12
B14
SB_HA#11
B16
SB_HA#10
A13
SB_HA#9
D17
A9
A8
A7
A6
A5
A4
A3
C17
A19
C18
B18
A20
A22
B22
C20
C21
B21
B19
AB9
AE12
AD22
AC27
AE17
AC15
AE19
AC18
D9
E10
F14
F17
Y11
Y14
Y17
Y20
Y12
Y15
Y18
Y21
SB_HA#8
SB_HA#7
SB_HA#6
SB_HA#5
SB_HA#4
SB_HA#3
SB_REQ#4
SB_REQ#3
SB_REQ#2
SB_REQ#1
SB_REQ#0
SB_DBI#3
SB_DBI#2
SB_DBI#1
SB_DBI#0
SB_DP#3
SB_DP#2
SB_DP#1
SB_DP#0
SB_AP#1
SB_AP#0
SB_ADSTB#1
SB_ADSTB#0
SB_DSTBP#3
SB_DSTBP#2
SB_DSTBP#1
SB_DSTBP#0
SB_DSTBN#3
SB_DSTBN#2
SB_DSTBN#1
SB_DSTBN#0
SB_HA#[35..3] [11,18]
SB_REQ#[4..0] [11,18]
SB_DBI#[3..0] [11,18]
SB_DP#[3..0] [11,18]
SB_AP#[1..0] [11,18]
SB_ADSTB#[1..0] [11,18]
SB_DSTBP#[3..0] [11,18]
SB_DSTBN#[3..0] [11,18]
12
SC369
22U/12/Y/10V
P_VTT
12
SC473
22U/12/Y/10V
SC393
1U/6/Y/10V
SC470
0.1U/6/X/16V
2
Trace Width:12 Mils
VREF_P_VTT_CPU0_0
VREF_P_VTT_CPU0_3
VCCIOPLL_CPU0
AGND_CPU0
PU_VCCPLL_CPU0
Title
Size Document Number Rev
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
NOCONA 800 MICS P0
GA-9IVDPC
870Tuesday, June 14, 2005
1
of
1.1
P_VTT
P1V5
100mA
L14
10UH/1206
L13
10UH/1206
SR59
0/6/X
12
+
SEC2
470U/4V/7343/X
WIDE 10-12 MILS
P_VCCP_A_CPU0
12
C406
22U/12/Y/10V
AGND_CPU0
WIDE 10-12 MILS
12
SC392
4.7U/1206/X
PU_VCCPLL_CPU0
SC396
0.1U/6/X
3
SC398
0.1U/6/X
NO USE
754mV
SR86
49.9/6/1
VREF_P_VTT_CPU0_3_R
SR87
90.9/6/1
P_VTT
SC493
1U/6/Y/10V
SR82
0/6
WIDE 10-12 MILS
VREF_P_VTT_CPU0_3
SC472
SC464
220P/6
220P/6
WIDE 10-12 MILS
R637
A A
754mV
49.9/6/1
VREF_P_VTT_CPU0_0_R
R636
C395
90.9/6/1
1U/6/Y/10V
5
R673
0/6
VREF_P_VTT_CPU0_0
C414
C413
220P/6
220P/6
4
5
4
3
2
1
P_VTT
R788 220/6
D D
R789 220/6 R804 51/6/X
R799 220/6
R814 220/6
R677 220/6
R803 220/6
R808 220/6
R797 51/6
SB_CPU_A20M#
SB_CPU_IGNNE#
SB_CPU_INIT#
SB_CPU_INTR
SB_CPU_SLP#
SB_CPU_STPCLK#
SB_CPU_NMI
CPU_FORCEPR#
R554 0/6
SB_CPU_A20M# [8,11,37]
SB_CPU_IGNNE# [8,11,37]
SB_CPU_INIT# [8,11,37,58]
SB_CPU_INTR [8,11,37]
SB_CPU_SLP# [8,11,37]
SB_CPU_STPCLK# [8,11]
ICH_CPU_STPCLK# [37]
SB_CPU_NMI [8,11,14]
CPU_FORCEPR# [8,11,14]
together
To CPU
From HR
CPU1HRRouting topology CPU0 PU_R
C C
R800 51/6 R802 4.7K/6
R817 51/6
SB_CPU0_IERR#
SB_CPU0_PROCHOT#
SB_CPU0_IERR# [8 ,14]
SB_CPU0_PROCHOT# [8,14]
CPU0 HRRouting topology PU_RCPU1PU_R
P_VTT
R798 51/6/X
SR81 51/6
SR79 51/6
SR80 51/6
R638 510/6
R678 510/6
R813 100/6/1
R635 100/6/1
SR78 49.9/6/1
R672 49.9/6/1
PU_BOOT_SELECT_CPU0
CPU0_OPTIM_COMPAT_CTRL
SB_BREQ#0
SB_BREQ#1
SB_CPU0_BREQ#23
SB_CPU0_BSEL1
SB_CPU0_BSEL0
PD_COMP2_CPU0
PD_COMP3_CPU0
PD_COMP1_CPU0
PD_COMP0_CPU0
X
PU_BOOT_SELECT_CPU0 [8]
X
CPU0_OPTIM_COMPAT_CTRL [8]
SB_BREQ#0 [8,11,14]
SB_BREQ#1 [8,11,14]
SB_CPU0_BREQ#23 [8]
SB_CPU0_BSEL1 [8,10]
SB_CPU0_BSEL0 [8,10]
PD_COMP2_CPU0 [8]
PD_COMP3_CPU0 [8]
PD_COMP1_CPU0 [8]
PD_COMP0_CPU0 [8]
together
P_VTT
R676 300/6
R675 51/6
R659 51/6/X
R634 51/6/X
R665 51/6/X
R660 0/6
P3V3_STBY
P_VTT
CLOSE TO CPU0
SB_CPURST#
SLEW_CTRL_CPU0
SLEW_CTRL_CPU1
SMC_CPU0_SKTOCC#
CPU_PWR_GD
CPU_PWR_GD [8,11,13,52]
SB_CPURST# [8,11,13,14,18]
X
SLEW_CTRL_CPU0 [8]
SLEW_CTRL_CPU1 [11]
SMC_CPU0_SKTOCC# [8,66]
C397
100P/6/X
END CPU NOT USE
X
X
GA-9IVDPC
PU_CPU0_8 [8]
PU_CPU0_7 [8]
PU_CPU0_6 [8]
PU_CPU0_5 [8]
PU_CPU0_4 [8]
PU_CPU0_3 [8]
PU_CPU0_2 [8]
PU_CPU0_1 [8]
PU_CPU0_0 [8]
970Tuesday, June 14, 2005
1
of
1.1
2
R666 51/6/X
R794 51/6/X
R606 51/6
R603 51/6
R625 51/6
R622 51/6
R619 51/6
R610 51/6
R615 51/6
Title
Size Document Number Rev
Date: Sheet
Routing topology PU_RHRPU_R CPU0 CPU1
R776 51/6
B B
A A
SR74 39/6
SR85 39/6
SR83 39/6
SR84 39/6
SR73 39/6
P3V3
R805 4.7K/6
SB_CPU_FERR#
SB_BININ#_R SB_BINIT#
SB_BNR#_R
SB_HIT#_R
SB_HITM#_R
SB_MCERR#_R S B_MCERR#
VTTEN
5
SC457
47P/6/N/50V
SC465
47P/6/N/50V
SC467
47P/6/N/50V
SC466
47P/6/N/50V
SC452
47P/6/N/50V
SB_BNR#
SB_HIT#
SB_HITM#
SB_CPU_FERR# [8,11,37]
SB_BINIT# [8,11,18]
SB_BNR# [8,11,18]
SB_HIT# [8,11,18]
SB_HITM# [8,11,18]
SB_MCERR# [8,11,18]
O.D.
VTTEN [8,11,52]
4
P_VTT
R801 51/6
R778 51/6
P_VTT
R796
PD_ODTEN_CPU0
PD_ODTEN_CPU1
SB_CPU0_CPU1_TESTBUS
51/6
R795 0/6/X
End-CPU ENABLE ODT
PD_ODTEN_CPU0 [8]
PD_ODTEN_CPU1 [1 1 ]
Mid-CPU DISABLE ODT
SB_CPU0_CPU1_TESTBUS [8,11]
3
PU_CPU0_8
PU_CPU0_7
PU_CPU0_6
PU_CPU0_5
PU_CPU0_4
PU_CPU0_3
PU_CPU0_2
PU_CPU0_1
PU_CPU0_0
GIGA-BYTE TECHNOLOGY CO., LTD.
NOCONA 800 P0 TERMINATION
5
4
3
2
1
AA31
AA26
AA20
AA6
AA4
AA1
Y30
Y22
Y16
Y2
W31
W29
W27
W25
W1
V30
V28
V26
V24
V8
V6
V4
V2
U31
U29
U27
U25
U23
U9
U7
U5
U3
U1
T30
T28
T26
T24
T8
T6
T4
T2
R31
R29
R27
R25
R23
R9
R7
R5
R3
R1
P30
P28
P26
P24
P8
P6
P4
P2
N31
N29
N27
N25
N23
N9
N7
N5
N3
N1
M31
M29
M27
M25
M23
M9
M7
M5
M3
M1
P_VCCP0P_VCCP0 P_VTT
AD12
AC10
AA12
Y10
F10
E12
C10
B12
AE24
AE18
AE14
AE8
AE3
AD30
AD26
AD20
AD6
AD2
AC31
AC22
AC16
AC4
AC3
AB30
AB24
AB18
AB14
AB8
AB2
C5
L28
P3V3
B4
A4
U36E
VCC_VTT1
VCC_VTT2
VCC_VTT3
VCC_VTT4
VCC_VTT5
VCC_VTT6
VCC_VTT7
VCC_VTT8
VCC_VTT9
VCC_VTT10
VCC_VTT11
VCC_CORE160
VCC_CORE161
VCC_CORE162
VCC_CORE163
VCC_CORE164
VCC_CORE165
VCC_CORE166
VCC_CORE167
VCC_CORE168
VCC_CORE169
VCC_CORE170
VCC_CORE171
VCC_CORE172
VCC_CORE173
VCC_CORE174
VCC_CORE175
VCC_CORE176
VCC_CORE177
VCC_CORE178
VCC_CORE179
VCC_CORE180
VCC_CORE181
NOCONA 667_7
NOCONA 667
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
AE2
AD3
AE27
AE21
AE11
AD31
AD23
AD17
AD15
AD9
AC25
AC19
AC13
AC7
AC2
AB31
AB27
AB21
AB11
AB5
AB1
P3V3
U36C
L31
VSS9
L29
L27
L25
L23
D D
C C
B B
H30
H28
H26
H24
G31
G29
G27
G25
F30
F28
F25
F19
F13
E31
E29
E23
E17
E15
D30
D28
D27
D21
D11
C31
C29
C25
C19
C13
B30
B28
B23
B17
B15
A31
A29
A27
A21
A11
K30
K28
K26
K24
J31
J29
J27
J25
J23
VSS10
VSS11
VSS12
VSS13
L9
VSS14
L7
VSS15
L5
VSS16
L3
VSS17
L1
VSS18
VSS19
VSS20
VSS21
VSS22
K8
VSS23
K6
VSS24
K4
VSS25
K2
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
J9
VSS32
J7
VSS33
J5
VSS34
J3
VSS35
J1
VSS36
VSS37
VSS38
VSS39
VSS40
H8
VSS41
H6
VSS42
H4
VSS43
H2
VSS44
VSS45
VSS46
VSS47
VSS48
G9
VSS49
G5
VSS51
G3
VSS52
G1
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
F7
VSS59
F2
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
E9
VSS66
VSS68
VSS69
VSS70
VSS71
VSS72
D5
VSS73
D2
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
C7
VSS80
VSS82
VSS83
VSS84
VSS85
VSS86
B9
VSS87
B2
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
A5
VSS94
NOCONA 667_7
NOCONA 667
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
AA30
AA23
AA17
AA15
AA9
AA2
Y31
Y25
Y19
Y13
Y7
Y5
Y1
W30
W28
W26
W24
W4
W2
V31
V29
V27
V25
V23
V9
V7
V5
V3
V1
U30
U28
U26
U24
U8
U6
U4
U2
T31
T29
T27
T25
T23
T9
T7
T5
T3
T1
R30
R28
R26
R24
R8
R6
R4
R2
P31
P29
P27
P25
P23
P9
P7
P5
P3
P1
N30
N28
N26
N24
N8
N6
N4
N2
M2
M4
M6
M8
M24
M26
M28
M30
K31
K29
K27
K25
K23
H31
H29
H27
H25
H23
G30
G28
G26
G24
E30
E28
E26
E20
D31
D29
D24
D18
D14
C30
C28
C22
C16
B31
B29
B26
B20
A30
A28
A24
A18
A14
L30
L26
L24
L8
L6
L4
L2
K9
K7
K5
K3
K1
J30
J28
J26
J24
J8
J6
J4
J2
H9
H7
H5
H3
H1
G8
G6
G4
G2
F31
F29
F22
F16
F4
F1
E6
E2
D8
D1
C4
C2
B6
A8
A2
U36D
VCC_CORE1
VCC_CORE2
VCC_CORE3
VCC_CORE4
VCC_CORE5
VCC_CORE6
VCC_CORE7
VCC_CORE8
VCC_CORE9
VCC_CORE10
VCC_CORE11
VCC_CORE12
VCC_CORE13
VCC_CORE14
VCC_CORE15
VCC_CORE16
VCC_CORE17
VCC_CORE18
VCC_CORE19
VCC_CORE20
VCC_CORE21
VCC_CORE22
VCC_CORE23
VCC_CORE24
VCC_CORE25
VCC_CORE26
VCC_CORE27
VCC_CORE28
VCC_CORE29
VCC_CORE30
VCC_CORE31
VCC_CORE32
VCC_CORE33
VCC_CORE34
VCC_CORE35
VCC_CORE36
VCC_CORE37
VCC_CORE38
VCC_CORE39
VCC_CORE40
VCC_CORE41
VCC_CORE42
VCC_CORE43
VCC_CORE44
VCC_CORE45
VCC_CORE46
VCC_CORE47
VCC_CORE48
VCC_CORE49
VCC_CORE50
VCC_CORE51
VCC_CORE52
VCC_CORE53
VCC_CORE54
VCC_CORE55
VCC_CORE56
VCC_CORE57
VCC_CORE58
VCC_CORE59
VCC_CORE60
VCC_CORE61
VCC_CORE62
VCC_CORE63
VCC_CORE64
VCC_CORE65
VCC_CORE66
VCC_CORE67
VCC_CORE68
VCC_CORE69
VCC_CORE70
VCC_CORE71
VCC_CORE72
VCC_CORE73
VCC_CORE74
VCC_CORE75
VCC_CORE76
VCC_CORE77
VCC_CORE78
VCC_CORE79
VCC_CORE80
NOCONA 667_7
NOCONA 667
VCC_CORE81
VCC_CORE82
VCC_CORE83
VCC_CORE84
VCC_CORE85
VCC_CORE86
VCC_CORE87
VCC_CORE88
VCC_CORE89
VCC_CORE90
VCC_CORE91
VCC_CORE92
VCC_CORE93
VCC_CORE94
VCC_CORE95
VCC_CORE96
VCC_CORE97
VCC_CORE98
VCC_CORE99
VCC_CORE100
VCC_CORE101
VCC_CORE102
VCC_CORE103
VCC_CORE104
VCC_CORE105
VCC_CORE106
VCC_CORE107
VCC_CORE108
VCC_CORE109
VCC_CORE110
VCC_CORE111
VCC_CORE112
VCC_CORE113
VCC_CORE114
VCC_CORE115
VCC_CORE116
VCC_CORE117
VCC_CORE118
VCC_CORE119
VCC_CORE120
VCC_CORE121
VCC_CORE122
VCC_CORE123
VCC_CORE124
VCC_CORE125
VCC_CORE126
VCC_CORE127
VCC_CORE128
VCC_CORE129
VCC_CORE130
VCC_CORE131
VCC_CORE132
VCC_CORE133
VCC_CORE134
VCC_CORE135
VCC_CORE136
VCC_CORE137
VCC_CORE138
VCC_CORE139
VCC_CORE140
VCC_CORE141
VCC_CORE142
VCC_CORE143
VCC_CORE144
VCC_CORE145
VCC_CORE146
VCC_CORE147
VCC_CORE148
VCC_CORE149
VCC_CORE150
VCC_CORE151
VCC_CORE152
VCC_CORE153
VCC_CORE154
VCC_CORE155
VCC_CORE156
VCC_CORE157
VCC_CORE158
VCC_CORE159
R640
470/6
A A
CPU0_THERMDA[8]
CPU0_THERMDC[8]
CPU0_THERMDC
5
R668
0/6
R667
0/6
CPU0_THERMDA_H7
GNDSIOA
TD1PCPU0_THERMDA
C410
100P/6
GNDSIOA
TD1P [53]
GNDSIOA [12,53]
4
MMBT3904
SB_CPU0_BSEL1[8,9]
R680
470/6
Q82
SOT23
ECB
3
CPU0_BSEL1 [32,52]
Q78
MMBT3904
SOT23
ECB
R639
470/6
MMBT3904
SB_CPU0_BSEL0[8,9]
R679
470/6
Q81
SOT23
ECB
CPU0_BSEL0 [32,52]
Q77
MMBT3904
SOT23
ECB
2
Title
Size Document Number Rev
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
NOCONA 800 P0 PWR/GND
GA-9IVDPC
10 70Tuesday, June 14, 2005
1
of
1.1
5
4
3
2
1
PROCESSOR 1
SB_BPRI#[8,18]
SB_CPU1_BREQ#23[13]
SB_BREQ#0[8,9,14]
SB_BREQ#1[8,9,14]
SB_CPURST#[8,9,13,14,18]
SB_RS#[2..0][8,18]
D D
C C
AGND_CPU1
B B
P_VTT
R669
49.9/6/1
754mV
VREF_P_VCCP_CPU1_0_R
R671
84.5/6/1
P_VTT
SB_CPU_A20M#[8, 9,37]
SB_CPU_IGNNE#[8,9,37]
SB_CPU_INIT#[8,9,37,58]
SB_CPU_NMI[8,9,14]
SB_CPU_INTR[8, 9,37]
CPU_PWR_GD[8,9,13,52]
SB_CPU1_SMI#[14]
SB_CPU_SLP#[8,9,37]
SB_CPU_STPCLK#[8,9]
ITP_TMS_MAIN[8,13]
SB_CPU1_BSEL1[12,13]
SB_CPU1_BSEL0[12,13]
VID_CPU1_R5[63]
VID_CPU1_R4[63]
VID_CPU1_R3[63]
VID_CPU1_R2[63]
VID_CPU1_R1[63]
VID_CPU1_R0[63]
VR1_VCCSENSE[63]
VR1_VSSSENSE[63]
P1 VREF
SB_RSP#[8,18]
P1_BCLK#[32]
P1_BCLK[32]
ITP_TCK0[8,13]
ITP_TDI_P1[13]
ITP_TRST#[8,13,17]
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24
TP25
TP26
TP27
TP28
TP29
TP30
VTTEN[8,9,52]
C415
1U/6/Y/10V
SB_BPRI#
SB_CPU1_BREQ#23
SB_BREQ#0
SB_BREQ#1
SB_CPURST#
SB_RS#2
SB_RS#1
SB_RS#0
SB_RSP#
SB_CPU_A20M#
SB_CPU_IGNNE#
SB_CPU_INIT#
SB_CPU_NMI
SB_CPU_INTR
CPU_PWR_GD
SB_CPU_SLP#
SB_CPU_STPCLK#
P1_BCLK#
P1_BCLK
ITP_TCK0
ITP_TDI_P1
ITP_TMS_MAIN
ITP_TRST#
SB_CPU1_BSEL1
SB_CPU1_BSEL0
VID_CPU1_R5
VID_CPU1_R4
VID_CPU1_R3
VID_CPU1_R2
VID_CPU1_R1
VID_CPU1_R0
P_VCCP_A_CPU1
VR1_VCCSENSE
VTTEN
P_VCCP_A_CPU1
VR1_VSSSENSE
MCH A0 CPU B0 800 64.9ohm 0.678V
MCH B0 CPU C1 800 49.9ohm 0.756V
R670
0/6
C411
220P/6
U35A
D23
BPRI#
AE29
AE28
AE30
AD29
AD28
AC29
AB29
AB28
AA29
AA28
AE15
AE16
D10
E11
F12
D20
F21
D22
E21
F27
C26
G23
B24
AB7
C27
AE6
E24
C24
A25
F24
AB3
AA3
AC1
AD4
B27
AB4
AA5
D26
Y8
C6
D6
D4
W5
Y4
Y3
A1
B3
C3
D3
E3
F3
E1
NOCONA 667
BR3#
BR2#
BR1#
BR0#
RESET#
RS2#
RS1#
RS0#
RSP#
A20M#
IGNNE#
INIT#
LINT1_NMI
LINT0_INTR
PWRGOOD
SMI#
SLP#
STPCLK#
BCLK1
BCLK0
TCK
TDI
TMS
TRST#
BSEL1
BSEL0
RESERVED1
RESERVED0
RSVD16
RSVD15
RSVD14
RSVD13
RSVD12
RSVD10
RSVD9
RSVD8
RSVD7
RSVD3
RSVD2
RSVD1
VID5
VID4
VID3
VID2
VID1
VID0
VCCIOPLL
VCC_SENSE
VTTEN
VCCA
VSSA
VSS_SENSE
NOCONA 667_7
WIDE 10-12 MILS
VREF_P_VTT_CPU1_0
C412
220P/6
ADS#
BINIT#
BNR#
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
DBSY#
DEFER#
DRDY#
HITM#
TRDY#
LOCK#
MCERR#
IERR#
FERR#
THERMTRIP#
PROCHOT#
GTLREF3
GTLREF2
GTLREF1
GTLREF0
ODTEN
SKTOCC#
COMP3
COMP2
COMP1
COMP0
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
SMB_PRT
VCCPLL
THERMDC
THERMDA
BOOT_SELECT
RSVD
VIDPWRGD
TEST_BUS
FORCEPR#
SLEW_CTRL
OPTIMIZED_COMPAT#
HIT#
TDO
SB_ADS#
D19
SB_BINIT#
F11
SB_BNR#
F20
CPU1_BPM#5
E4
CPU1_BPM#4
E8
CPU1_BPM#3
F5
CPU1_BPM#2
E7
CPU1_BPM#1
F8
CPU1_BPM#0
F6
SB_DBSY#
F18
SB_DEFER#
C23
SB_DRDY#
E18
SB_HIT#
E22
SB_HITM#
A23
SB_TRDY#
E19
SB_LOCK#
A17
SB_MCERR#
D7
SB_CPU1_IERR#
E5
SB_CPU_FERR#
E27
CPU1_THERMALTRIP#
F26
SB_CPU1_PROCHOT#
B25
ITP_TDO_MAIN
E25
F9
F23
W9
W23
PD_ODTEN_CPU1
B5
SMC_CPU1_SKTOCC#
A3
PD_COMP3_CPU1
AC28
PD_COMP2_CPU1
D25
PD_COMP1_CPU1
E16
PD_COMP0_CPU1
AD16
PU_CPU1_8
Y29
PU_CPU1_7
A26
PU_CPU0_6
AE5
PU_CPU1_5
AD5
PU_CPU1_4
AA7
PU_CPU1_3
Y6
PU_CPU1_2
W8
PU_CPU1_1
W7
PU_CPU1_0
W6
AE4
AD1
CPU1_THERMDC
Y28
CPU1_THERMDA
Y27
PU_BOOT_SELECT_CPU1
G7
W3
VID_PWRGD
B1
SB_CPU0_CPU1_TESTBUS
A16
CPU_FORCEPR#
A15
SLEW_CTRL_CPU1
AC30
CPU1_OPTIM_COMPAT_CTRL
C1
COMP3 =SB_CPU1_ADDR_ERC
COMP2 =SB_CPU1_DATA_ERC
PU_CPU1_8=SB_CPU1_EDRDY
PU_CPU1_0=SB_CPU1_SNPD#
P_VTT
SL1
10UH/1206
SL2
10UH/1206
SB_ADS# [8,18]
SB_BINIT# [8 , 9 ,18 ]
SB_BNR# [ 8 ,9,18]
CPU1_BPM#[5..0] [13]
SB_DBSY# [8,18]
SB_DEFER# [8,18]
SB_DRDY# [8,18]
SB_HIT# [8,9,18]
SB_HITM# [8,9,18]
SB_TRDY# [8,18]
SB_LOCK# [8,18]
SB_MCERR# [8 , 9,18]
SB_CPU1_IERR# [13,14 ]
SB_CPU_FERR# [8,9,37]
CPU1_THERMALTRIP# [14]
SB_CPU1_PROCHOT# [13,14]
ITP_TDO_P1 [13]
VREF_P_VTT_CPU1_3
VREF_P_VTT_CPU1_0
PD_ODTEN_CPU1 [9]
SMC_CPU1_SKTOCC# [13,52,66]
PD_COMP3_CPU1 [13]
PD_COMP2_CPU1 [13]
PD_COMP1_CPU1 [13]
PD_COMP0_CPU1 [13]
PU_CPU1_8 [13]
PU_CPU1_7 [13]
PU_CPU1_6 [13]
PU_CPU1_5 [13]
PU_CPU1_4 [13]
PU_CPU1_3 [13]
PU_CPU1_2 [13]
PU_CPU1_1 [13]
PU_CPU1_0 [13]
TP31
PU_VCCPLL_CPU1
CPU1_THERMDC [12]
CPU1_THERMDA [12]
PU_BOOT_SELECT_CPU1 [13]
TP32
VID_PWRGD [8,52]
SB_CPU0_CPU1_TESTBUS [8,9]
CPU_FORCEPR# [8 ,9,14]
SLEW_CTRL_CPU1 [9]
CPU1_OPTIM_COMPAT_CTRL [13]
WIDE 10-12 MILS
P_VCCP_A_CPU1
12
SC399
22U/12/Y/10V
AGND_CPU1
SB_D#[63..0][8, 18]
SB_D#63
SB_D#62
SB_D#61
SB_D#60
SB_D#59
SB_D#58
SB_D#57
SB_D#56
SB_D#55
SB_D#54
SB_D#53
SB_D#52
SB_D#51
SB_D#50
SB_D#49
SB_D#48
SB_D#47
SB_D#46
SB_D#45
SB_D#44
SB_D#43
SB_D#42
SB_D#41
SB_D#40
SB_D#39
SB_D#38
SB_D#37
SB_D#36
SB_D#35
SB_D#34
SB_D#33
SB_D#32
SB_D#31
SB_D#30
SB_D#29
SB_D#28
SB_D#27
SB_D#26
SB_D#25
SB_D#24
SB_D#23
SB_D#22
SB_D#21
SB_D#20
SB_D#19
SB_D#18
SB_D#17
SB_D#16
SB_D#15
SB_D#14
SB_D#13
SB_D#12
SB_D#11
SB_D#10
SB_D#9
SB_D#8
SB_D#7
SB_D#6
SB_D#5
SB_D#4
SB_D#3
SB_D#2
SB_D#1
SB_D#0
WIDE 10-12 MILS
SR48
A A
754mV
49.9/6/1
VREF_P_VCCP_CPU1_3_R
SC368
SR49
1U/6/Y/10V
84.5/6/1
5
SR50
0/6
WIDE 10-12 MILS
VREF_P_VTT_CPU1_3
SC370
SC371
220P/6
220P/6
4
P1V5
SR60
0/6/X
12
+
SEC1
470U/4V/7343/X
NO USE
PU_VCCPLL_CPU1
12
3
SC394
4.7U/1206/X
SC379
0.1U/6/X
SC378
0.1U/6/X
AB6
Y9
AA8
AC5
AC6
AE7
AD7
AC8
AB10
AA10
AA11
AB13
AB12
AC14
AA14
AA13
AC9
AD8
AD10
AE9
AC11
AE10
AC12
AD11
AD14
AD13
AB15
AD18
AE13
AC17
AA16
AB16
AB17
AD19
AD21
AE20
AE22
AC21
AC20
AA18
AC23
AE23
AD24
AC24
AE25
AD25
AC26
AE26
AA19
AB19
AB22
AB20
AA21
AA22
AB23
AB25
AB26
AA24
Y23
AD27
AA25
Y24
AA27
Y26
12
SC383
22U/12/Y/10V
2
U35B
D63
NOCONA 667
D62
D61
D60
D59
D58
D57
D56
D55
D54
D53
D52
D51
D50
D49
D48
D47
D46
D45
D44
D43
D42
D41
D40
D39
D38
D37
D36
D35
D34
D33
D32
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NOCONA 667_7
P_VTT
12
SC480
22U/12/Y/10V
SB_HA#35
BREQ4#
BREQ3#
BREQ2#
BREQ1#
BREQ0#
DBI3#
DBI2#
DBI1#
DBI0#
DP3#
DP2#
DP1#
DP0#
AP1#
AP0#
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
SC469
1U/6/Y/10V
C8
A35
C9
A34
A7
A33
A6
A32
B7
A31
C11
A30
D12
A29
E13
A28
B8
A27
A9
A26
D13
A25
E14
A24
C12
A23
B11
A22
B10
A21
A10
A20
F15
A19
D15
A18
D16
A17
C14
A16
C15
A15
A12
A14
B13
A13
B14
A12
B16
A11
A13
A10
D17
A9
C17
A8
A19
A7
C18
A6
B18
A5
A20
A4
A22
A3
B22
C20
C21
B21
B19
AB9
AE12
AD22
AC27
AE17
AC15
AE19
AC18
D9
E10
F14
F17
Y11
Y14
Y17
Y20
Y12
Y15
Y18
Y21
SC391
0.1U/6/X/16V
SB_HA#34
SB_HA#33
SB_HA#32
SB_HA#31
SB_HA#30
SB_HA#29
SB_HA#28
SB_HA#27
SB_HA#26
SB_HA#25
SB_HA#24
SB_HA#23
SB_HA#22
SB_HA#21
SB_HA#20
SB_HA#19
SB_HA#18
SB_HA#17
SB_HA#16
SB_HA#15
SB_HA#14
SB_HA#13
SB_HA#12
SB_HA#11
SB_HA#10
SB_HA#9
SB_HA#8
SB_HA#7
SB_HA#6
SB_HA#5
SB_HA#4
SB_HA#3
SB_REQ#4
SB_REQ#3
SB_REQ#2
SB_REQ#1
SB_REQ#0
SB_DBI#3
SB_DBI#2
SB_DBI#1
SB_DBI#0
SB_DP#3
SB_DP#2
SB_DP#1
SB_DP#0
SB_AP#1
SB_AP#0
SB_ADSTB#1
SB_ADSTB#0
SB_DSTBP#3
SB_DSTBP#2
SB_DSTBP#1
SB_DSTBP#0
SB_DSTBN#3
SB_DSTBN#2
SB_DSTBN#1
SB_DSTBN#0
EC27
PSA2.5VB680MH11/8X11.5/X
Trace Width:12 Mils
VREF_P_VTT_CPU1_0
SB_HA#[35..3] [8,18]
SB_REQ#[4..0] [8,18]
SB_DBI#[3..0] [8,18]
SB_DP#[3..0] [8,18]
SB_AP#[1..0] [8,18]
SB_ADSTB#[1..0] [ 8 ,1 8 ]
SB_DSTBP#[3..0 ] [ 8,18]
SB_DSTBN#[3..0] [8,18]
VREF_P_VTT_CPU1_3
VCCIOPLL_CPU1
AGND_CPU1
PU_VCCPLL_CPU1
Title
Size Document Number Rev
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
NOCONA 800 MICS P1
GA-9IVDPC
1
11 70Tuesday, June 14, 2005
1.1
of
5
U35C
L31
VSS9
L29
L27
L25
L23
K30
H30
H28
H26
H24
G31
G29
G27
G25
F30
F28
F25
F19
F13
E31
E29
E23
E17
E15
D30
D28
D27
D21
D11
C31
C29
C25
C19
C13
B30
B28
B23
B17
B15
A31
A29
A27
A21
A11
K28
K26
K24
J31
J29
J27
J25
J23
G9
G5
G3
G1
D D
C C
B B
VSS10
VSS11
VSS12
VSS13
L9
VSS14
L7
VSS15
L5
VSS16
L3
VSS17
L1
VSS18
VSS19
VSS20
VSS21
VSS22
K8
VSS23
K6
VSS24
K4
VSS25
K2
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
J9
VSS32
J7
VSS33
J5
VSS34
J3
VSS35
J1
VSS36
VSS37
VSS38
VSS39
VSS40
H8
VSS41
H6
VSS42
H4
VSS43
H2
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
F7
VSS59
F2
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
E9
VSS66
VSS68
VSS69
VSS70
VSS71
VSS72
D5
VSS73
D2
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
C7
VSS80
VSS82
VSS83
VSS84
VSS85
VSS86
B9
VSS87
B2
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
A5
VSS94
NOCONA 667_7
NOCONA 667
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
AA30
AA23
AA17
AA15
AA9
AA2
Y31
Y25
Y19
Y13
Y7
Y5
Y1
W30
W28
W26
W24
W4
W2
V31
V29
V27
V25
V23
V9
V7
V5
V3
V1
U30
U28
U26
U24
U8
U6
U4
U2
T31
T29
T27
T25
T23
T9
T7
T5
T3
T1
R30
R28
R26
R24
R8
R6
R4
R2
P31
P29
P27
P25
P23
P9
P7
P5
P3
P1
N30
N28
N26
N24
N8
N6
N4
N2
M2
M4
M6
M8
M24
M26
M28
M30
P_VCCP1 P_VCCP1
H31
H29
H27
H25
H23
G30
G28
G26
G24
D31
D29
D24
D18
D14
C30
C28
C22
C16
L30
L26
L24
L8
L6
L4
L2
K31
K29
K27
K25
K23
K9
K7
K5
K3
K1
J30
J28
J26
J24
J8
J6
J4
J2
H9
H7
H5
H3
H1
G8
G6
G4
G2
F31
F29
F22
F16
F4
F1
E30
E28
E26
E20
E6
E2
D8
D1
C4
C2
B31
B29
B26
B20
B6
A30
A28
A24
A18
A14
A8
A2
U35D
VCC_CORE1
VCC_CORE2
VCC_CORE3
VCC_CORE4
VCC_CORE5
VCC_CORE6
VCC_CORE7
VCC_CORE8
VCC_CORE9
VCC_CORE10
VCC_CORE11
VCC_CORE12
VCC_CORE13
VCC_CORE14
VCC_CORE15
VCC_CORE16
VCC_CORE17
VCC_CORE18
VCC_CORE19
VCC_CORE20
VCC_CORE21
VCC_CORE22
VCC_CORE23
VCC_CORE24
VCC_CORE25
VCC_CORE26
VCC_CORE27
VCC_CORE28
VCC_CORE29
VCC_CORE30
VCC_CORE31
VCC_CORE32
VCC_CORE33
VCC_CORE34
VCC_CORE35
VCC_CORE36
VCC_CORE37
VCC_CORE38
VCC_CORE39
VCC_CORE40
VCC_CORE41
VCC_CORE42
VCC_CORE43
VCC_CORE44
VCC_CORE45
VCC_CORE46
VCC_CORE47
VCC_CORE48
VCC_CORE49
VCC_CORE50
VCC_CORE51
VCC_CORE52
VCC_CORE53
VCC_CORE54
VCC_CORE55
VCC_CORE56
VCC_CORE57
VCC_CORE58
VCC_CORE59
VCC_CORE60
VCC_CORE61
VCC_CORE62
VCC_CORE63
VCC_CORE64
VCC_CORE65
VCC_CORE66
VCC_CORE67
VCC_CORE68
VCC_CORE69
VCC_CORE70
VCC_CORE71
VCC_CORE72
VCC_CORE73
VCC_CORE74
VCC_CORE75
VCC_CORE76
VCC_CORE77
VCC_CORE78
VCC_CORE79
VCC_CORE80
NOCONA 667_7
4
NOCONA 667
VCC_CORE81
VCC_CORE82
VCC_CORE83
VCC_CORE84
VCC_CORE85
VCC_CORE86
VCC_CORE87
VCC_CORE88
VCC_CORE89
VCC_CORE90
VCC_CORE91
VCC_CORE92
VCC_CORE93
VCC_CORE94
VCC_CORE95
VCC_CORE96
VCC_CORE97
VCC_CORE98
VCC_CORE99
VCC_CORE100
VCC_CORE101
VCC_CORE102
VCC_CORE103
VCC_CORE104
VCC_CORE105
VCC_CORE106
VCC_CORE107
VCC_CORE108
VCC_CORE109
VCC_CORE110
VCC_CORE111
VCC_CORE112
VCC_CORE113
VCC_CORE114
VCC_CORE115
VCC_CORE116
VCC_CORE117
VCC_CORE118
VCC_CORE119
VCC_CORE120
VCC_CORE121
VCC_CORE122
VCC_CORE123
VCC_CORE124
VCC_CORE125
VCC_CORE126
VCC_CORE127
VCC_CORE128
VCC_CORE129
VCC_CORE130
VCC_CORE131
VCC_CORE132
VCC_CORE133
VCC_CORE134
VCC_CORE135
VCC_CORE136
VCC_CORE137
VCC_CORE138
VCC_CORE139
VCC_CORE140
VCC_CORE141
VCC_CORE142
VCC_CORE143
VCC_CORE144
VCC_CORE145
VCC_CORE146
VCC_CORE147
VCC_CORE148
VCC_CORE149
VCC_CORE150
VCC_CORE151
VCC_CORE152
VCC_CORE153
VCC_CORE154
VCC_CORE155
VCC_CORE156
VCC_CORE157
VCC_CORE158
VCC_CORE159
AA31
AA26
AA20
AA6
AA4
AA1
Y30
Y22
Y16
Y2
W31
W29
W27
W25
W1
V30
V28
V26
V24
V8
V6
V4
V2
U31
U29
U27
U25
U23
U9
U7
U5
U3
U1
T30
T28
T26
T24
T8
T6
T4
T2
R31
R29
R27
R25
R23
R9
R7
R5
R3
R1
P30
P28
P26
P24
P8
P6
P4
P2
N31
N29
N27
N25
N23
N9
N7
N5
N3
N1
M31
M29
M27
M25
M23
M9
M7
M5
M3
M1
P_VCCP1
P_VTT
AD12
AC10
AA12
AE24
AE18
AE14
AD30
AD26
AD20
AD6
AD2
AC31
AC22
AC16
AC4
AC3
AB30
AB24
AB18
AB14
AB8
AB2
Y10
F10
E12
C10
B12
AE8
AE3
L28
B4
C5
A4
3
U35E
VCC_VTT1
VCC_VTT2
VCC_VTT3
VCC_VTT4
VCC_VTT5
VCC_VTT6
VCC_VTT7
VCC_VTT8
VCC_VTT9
VCC_VTT10
VCC_VTT11
VCC_CORE160
VCC_CORE161
VCC_CORE162
VCC_CORE163
VCC_CORE164
VCC_CORE165
VCC_CORE166
VCC_CORE167
VCC_CORE168
VCC_CORE169
VCC_CORE170
VCC_CORE171
VCC_CORE172
VCC_CORE173
VCC_CORE174
VCC_CORE175
VCC_CORE176
VCC_CORE177
VCC_CORE178
VCC_CORE179
VCC_CORE180
VCC_CORE181
NOCONA 667_7
NOCONA 667
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
AE2
AD3
AE27
AE21
AE11
AD31
AD23
AD17
AD15
AD9
AC25
AC19
AC13
AC7
AC2
AB31
AB27
AB21
AB11
AB5
AB1
2
1
P3V3 P3V3
ECB
SQ2
MMBT3904
SOT23
CPU1_BSEL1 [5 2 ]
SB_CPU1_BSEL0[11,13]
MMBT3904
SR68
470/6
SR52
470/6
SQ3
SOT23
ECB
CPU1_THERMDA[11]
A A
CPU1_THERMDC[11]
CPU1_THERMDA
CPU1_THERMDC
5
R663
0/6
R662
0/6
CPU1_THERMDA_H7
GNDSIOA
TD2P
C409
100P/6
GNDSIOA
TD2P [53]
GNDSIOA [10,53]
4
MMBT3904
SB_CPU1_BSEL1[11,13]
SR66
470/6
SR51
470/6
SQ1
SOT23
ECB
3
2
ECB
SQ4
MMBT3904
SOT23
CPU1_BSEL0 [5 2]
Title
Size Document Number Rev
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
NOCONA 800 P1 PWR/GND
GA-9IVDPC
12 70Tuesday, June 14, 2005
1
of
1.1
P_VTT
5
4
P_VTT
3
2
1
R661 51/6
R780 51/6
R787 51/6
D D
R811 51/6
R786 51/6/X
R784 51/6/X
R785 51/6
C C
SR65 510/6
SR67 510/6
R664 100/6/1
R810 100/6/1
SR77 49.9/6/1
B B
R681 49.9/6/1
A A
SB_CPU1_IERR#
SB_CPU1_PROCHOT#
PU_BOOT_SELECT_CPU1
CPU1_OPTIM_COMPAT_CTRL
R783 51/6/X
SB_CPU1_BREQ#23
SB_CPU1_BSEL1
SB_CPU1_BSEL0
PD_COMP3_CPU1
PD_COMP2_CPU1
PD_COMP1_CPU1
PD_COMP0_CPU1
CPU_PWR_GD[8,9,11,52]
ITP_TCK1[17]
ITP_TCK0[8,11]
5
CPU_PWR_GD
SB_CPU1_IERR# [11,14]
SB_CPU1_PROCHOT# [11,14]
X
PU_BOOT_SELECT_CPU1 [11]
X
CPU1_OPTIM_COMPAT_CTRL [11]
SB_CPU1_BREQ#23 [11]
SB_CPU1_BSEL1 [11,12]
SB_CPU1_BSEL0 [11,12]
PD_COMP3_CPU1 [11]
PD_COMP2_CPU1 [11]
PD_COMP1_CPU1 [11]
PD_COMP0_CPU1 [11]
P_VTT
R792 0/6
MCH_PME#[18,37]
R835 51/6
R828 51/6
ITP_CPU_PWRGOOD
R657 51/6
R658 51/6
R653 51/6
R655 51/6
R652 51/6
R654 51/6
R656 51/6
P3V3_STBY
R779 4.7K/6
CPU_PWR_GD
C396
100P/6/X
CPU0_BPM#5
CPU0_BPM#4
CPU0_BPM#3
CPU0_BPM#2
CPU0_BPM#1
CPU0_BPM#0
CPU1_BPM#5
CPU1_BPM#4
CPU1_BPM#3
CPU1_BPM#2
CPU1_BPM#1
CPU1_BPM#0
MCH_PME# SB_CPURST#_R
ITP_TCK1
ITP_TCK0
4
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
PU_CPU1_8
PU_CPU1_7
PU_CPU1_6
PU_CPU1_5
PU_CPU1_4
PU_CPU1_3
PU_CPU1_2
PU_CPU1_1
PU_CPU1_0
SMC_CPU1_SKTOCC#
CPU_PWR_GD [8,9,11,52]
ITP
1
3
5
7
9
ITP/X
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
P1V5
PU_CPU1_8 [ 11]
PU_CPU1_7 [ 11]
PU_CPU1_6 [ 11]
PU_CPU1_5 [ 11]
PU_CPU1_4 [ 11]
PU_CPU1_3 [ 11]
PU_CPU1_2 [ 11]
PU_CPU1_1 [ 11]
PU_CPU1_0 [ 11]
SMC_CPU1_SKTOCC# [11,52,66]
MODE TEST PROCESSOR CONFIGURATION
UP 2-3 P0 INSTALLED;P1 REMOVED
DP 1-2 & 3-4 P0 & P1 INSTALLED
ITP_MCH_DEBUG0
ITP_MCH_DEBUG1
ITP_MCH_DEBUG2
ITP_MCH_DEBUG3
ITP_MCH_DEBUG4
ITP_MCH_DEBUG5
ITP_MCH_DEBUG6
ITP_MCH_DEBUG7
ITP_BCLK
ITP_BCLK#
DBR_RESET#
ITP_TDO_MAIN
ITP_TRST#
ITP_TDI_MAIN
ITP_TMS_MAIN
R895
3
ITP_MCH_DEBUG[7..0]
ITP_BCLK [32]
ITP_BCLK# [32]
ITP_TRST# [8,11,17]
ITP_TMS_MAIN [8,11]
1K/6
TP133
TP250
TP251
TP296
ITP_TMS_MAIN[8,11] ITP_TMS_MCH [17]
ITP_TDI_MAIN[8]
ITP_MCH_DEBUG[7..0] [17]
PLACE WITHIN 1" OF CPU
P_VTT
R882
51/6
ITP_TDI_P1
ITP_TDO_P0
ITP_TDO_P1
R762
51/6
R897 0/6
ITP_TDI_MAIN [8]
ITP_TDI_P1 [11]
ITP_TDO_P0 [8]
ITP_TDO_P1 [11]
R896
51/6/X
SB_CPURST#_R
ITP_TMS_MAIN
DBR_RESET#
ITP_TDI_MAIN
P_VTT
R870
0/6
RN93 51/8P4R
1 2
3 4
5 6
7 8
RN94 51/8P4R
1 2
3 4
5 6
7 8
RN95 51/8P4R
1 2
3 4
5 6
7 8
R841 51/6
R850 51/6
P_VTT
R903
51/6
PLACE WITHIN 1" OF MCH
ITP_TDO_MCH
Title
Size Document Number Rev
2
Date: Sheet
R674 0/6
R847 0/6
R898 0/6
P_VTT
R861
51/6
CPU1_BPM#5
CPU1_BPM#4
CPU1_BPM#3
CPU1_BPM#2
CPU0_BPM#4
CPU1_BPM#1
CPU1_BPM#0
CPU0_BPM#5
CPU0_BPM#0
CPU0_BPM#1
CPU0_BPM#2
CPU0_BPM#3
ITP_TDO_MCH [17]
SB_CPURST#
ITP_TMS_MCH
ITP_RESET#
SB_CPURST# [8,9,11,14,18]
SYS_RESET# [37,53,56]
PLACE WITHIN 1" OF MCH
ITP_TDI_MCH
ITP_TMS_MCH
ITP_TMS_MAIN
ITP_TDI_MCH [17]
CPU1_BPM#[5..0] [11]
CPU0_BPM#[5..0] [8]
ITP_TMS_MCH [17]
ITP_TMS_MAIN [8,11]
GIGA-BYTE TECHNOLOGY CO., LTD.
NOCONA 800 P1 TERMINATION/ITP
GA-9IVDPC
13 70Tuesday, June 14, 2005
1
of
1.1
5
4
3
2
1
check
P_VTT
12
R1864
200/6
package
U184
1
GND
GREF
2
SREF
DREF
3
S1
S24D2
GTL2002/TSSOP8/X
ECB
D1
Q232
MMBT3904
SOT23
8
7
6
5
C1259
0.1U/6/X/16V
1 2
C1474
0.1U/6/Y/10V/X
P_VTT
P_VTT
12
R1872
12
C908
200/6
D D
ICH_CPU_SMI#[37]
0.01U/6/X/50V
ICH_CPU_SMI# GTL_SMI#
Trace Length Limitation
V1.0
ECB
ECB
R856
470/6
R868
470/6
SOT23
SOT23
P3V3
P3V3P5V
R887
300/6
CPU0_PROCHOT#
Q99
MMBT3904
SOT23
ECB
R869
300/6
CPU1_PROCHOT#
Q96
MMBT3904
SOT23
ECB
CPU0_PROCHOT# [36]
CPU1_PROCHOT# [36]
R825
51/6
R867
51/6
P5V
Q93
MMBT3904
Q95
MMBT3904
C C
P_VTT
SB_CPU0_PROCHOT#[8,9]
B B
SB_CPU1_PROCHOT#[11, 13]
SB_CPU0_PROCHOT#
SB_CPU1_PROCHOT#
R833 470/6
P_VTT
R866 470/6
P3V3
P3V3
12
12
R1627
10K/6
1 2
R1632
1K/6
SB_CPURST#[8 , 9 , 1 1, 13,18]
Trace Length Limitation
SB_CPU0_IERR#[8,9]
SB_CPU0_IERR#
Trace Length Limitation
SB_CPU1_IERR#[11,13]
SB_CPU1_IERR#
P_VTT
P_VTT
R826
51/6
R881
51/6
Q194
MMBT2222A/SOT23
R1643 10K/ 6
1 2
Q92
MMBT3904
R832 470/6
Q101
MMBT3904
R880 470/6
53
2 4
P3V3 P_VTT
C1262
53
2 4
R528 0/6
R530 0/6
P5V
Q91
MMBT3904
P_VTTP3V3
12
12
U181
74LVC07/SOT23-5
12
12
U183
74LVC07/SOT23-5
SB_BREQ#0MCH_BREQ#0
SB_BREQ#1
R854
470/6
SOT23
ECB
R1636
51/6/1
SB_CPU0_SMI#
R1642
51/6/1
SB_CPU1_SMI#
SB_BREQ#0 [8,9,11]
SB_BREQ#1 [8,9,11]
P_VTT
R886
51/6/X
ECB
SB_CPU0_SMI# [8]
SB_CPU1_SMI# [11]
CPU_FORCEPR# [8,9,11]
Q97
MMBT3904
SOT23
CPU0/1MCH
P3V3
12
12
R1638
R1637
1K/6
1K/6
BMC_BSP_TRI#[66]
BMC_AP_TRI#[ 66]
P3V3
12
R1641
1K/6
12
C1263
SOT23
0.1U/6/Y/25V
ECB
P5V
R855
470/6
ECB
R879
470/6
ECB
SOT23
SOT23
P3V3
P3V3P5V
R846
4.7K/6
-PROC_IERR0
Q98
MMBT3904
SOT23
ECB
R860
4.7K/6
-PROC_IERR1
Q100
MMBT3904
SOT23
ECB
GTL_SMI#
P3V3
12
R1640
1K/6
D
D
Q193
2N7002
GS
S
G
CPU0_IERR# [66]
CPU1_IERR# [66]
P3V3
16
11
10
14
13
15
SB_CPU_FORCEPR#[53]
12
U182
VCC
2
1A
1Y
3
1B
5
2A
2Y
6
2B
3A
3Y
3B
4A
4Y
4B
1
A/B
G
8
GND
74LCX157/TSSOP16
MCH_BREQ#0[18]
MCH_BREQ#1[18]
C1261
0.1U/6/Y/25V
4
7
9
12
MCH_BREQ#1
P5V
C1260
0.1U/6/Y/25V
0.1U/6/Y/25V
R824
4.7K/6
R831
4.7K/6
R1865
470/6
ECB
R1869
470/6
ECB
SOT23
SOT23
P3V3
R1866
4.7K/6
CPU0_THERMTRIP#
Q229
MMBT3904
SOT23
ECB
R1870
4.7K/6
CPU1_THERMTRIP#
Q231
MMBT3904
SOT23
ECB
PS_PWR_GD#[52]
CPU0_THERMTRIP#
CPU1_THERMTRIP#
CPU1_THERMTRIP#
CPU0_THERMTRIP#
4
1
2
3
SN74LVC2G32DCTR/SSOP8
1A
VCC
1B
1Y
2Y
2B
GND42A
U186
D62 RB751V -40/SMD
D63 RB751V -40/SMD
3
P3V3_STBY
8
7
6
5
12
12
IPMI_CPU1_THRMTRIP# [ 66 ]
V1.0
IPMI_CPU0_THRMTRIP# [ 66 ]
SB_CPU_THERMTRIP# [37]
2
R1867
0/6
SB_CPU_NMI [8, 9, 11]SB_ICH_NMI[37]
GIGA-BYTE TECHNOLOGY CO., LTD.
Title
Size Do c um e n t N u mb er Re v
Date: Sheet
LEVEL/THERMAL/BREQ
GA-9IVDPC
1
14 70Tuesday, Ju ne 14, 2005
1.1
of
P5V
P_VTT
Q228
MMBT3904
R1647
P_VTT
200/6
R1868 470/6
Q230
MMBT3904
R1646
200/6
R1871 470/6
P5V P3V3
Trace Length Limitation
CPU0_THERMALTRIP#[8]
A A
Trace Length Limitation
CPU1_THERMALTRIP#[11]
V1.0
5
5
DDRA_MA[13..0][22,23,24,25,26]
D D
DDRA_CB[7..0][22,23,24,25,26]
C C
MOW 40
4 DIMM 2/4 CHANGE
DDRA_CMDCLK_A0_P[22,26]
DDRA_CMDCLK_A0_N[22,26]
DDRA_CMDCLK_A3_P[25,26]
DDRA_CMDCLK_A3_N[25,26]
DDRA_CMDCLK_A2_P[24,26]
PLACE DDR VREF VOLTAGE
DIVIDER NEAR CHANNEL A
DIMMS
P2V5
R372
75/6/1
B B
R365
75/6/1
PLACE CLOSE TO DIMM < 0.5
A A
C248
1U/6/Y/10V
5
PLACE CLOSE TO MCH < 0.5
C258
0.1U/6/X/16V
DDRA_DQS[8..0][22,23,24,25,26]
DDRA_CMDCLK_A2_N[24,26]
DDRA_CMDCLK_A1_P[23,26]
DDRA_CMDCLK_A1_N[23,26]
DDRA_CS#[7..0][22,23,24,25,26]
DDRA_MCH_VREF_R
4
U23A
DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
DDRA_CB0
DDRA_CB1
DDRA_CB2
DDRA_CB3
DDRA_CB4
DDRA_CB5
DDRA_CB6
DDRA_CB7
MEM_CKE0[22,26]
MEM_CKE1[26,27]
MEM_CKE2[23,26]
MEM_CKE3[26,28]
DDRA_CAS#[22,23,24,25,26]
DDRA_RAS#[22,23,24,25,26]
DDRA_WE#[22,23,24,25,26]
DDRA_BA0[22,23,24,25,26]
DDRA_BA1[22,23,24,25,26]
4
MEM_CKE0
MEM_CKE1
MEM_CKE2
MEM_CKE3
DDRA_CMDCLK_A0_P
DDRA_CMDCLK_A0_N
DDRA_CMDCLK_A3_P
DDRA_CMDCLK_A3_N
DDRA_CMDCLK_A2_P
DDRA_CMDCLK_A2_N
DDRA_CMDCLK_A1_P
DDRA_CMDCLK_A1_N
DDRA_CS#0
DDRA_CS#1
DDRA_CS#2
DDRA_CS#3
DDRA_CS#4
DDRA_CS#5
DDRA_CS#6
DDRA_CS#7
DDRA_CAS#
DDRA_RAS#
DDRA_WE#
DDRA_BA0
DDRA_BA1
DDRA_DQS0
DDRA_DQS1
DDRA_DQS2
DDRA_DQS3
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS7
DDRA_DQS8
AH5
DDR_A_MA0
AD14
DDR_A_MA1
AL14
DDR_A_MA2
AK15
DDR_A_MA3
AJ16
DDR_A_MA4
AH17
DDR_A_MA5
AF18
DDR_A_MA6
AN20
DDR_A_MA7
AK20
DDR_A_MA8
AJ22
DDR_A_MA9
AE4
DDR_A_MA10
AF22
DDR_A_MA11
AG23
DDR_A_MA12
U6
DDR_A_MA13
AJ9
DDR_A_CB0
AG11
DDR_A_CB1
AE11
DDR_A_CB2
AD11
DDR_A_CB3
AJ10
DDR_A_CB4
AH10
DDR_A_CB5
AF10
DDR_A_CB6
AE10
DDR_A_CB7
AE26
DDR_CKE0
AN26
DDR_CKE1
AL26
DDR_CKE2
AK26
DDR_CKE3
AF13
DDR_A_CMDCLK_P0
AF12
DDR_A_CMDCLK_N0
AH11
DDR_A_CMDCLK_P1
AJ12
DDR_A_CMDCLK_N1
AH13
DDR_A_CMDCLK_P2
AG12
DDR_A_CMDCLK_N2
AC10
DDR_A_CMDCLK_P3
AD9
DDR_A_CMDCLK_N3
W2
DDR_A_#CS0
V3
DDR_A_#CS1
T8
DDR_A_#CS2
T10
DDR_A_#CS3
N5
DDR_A_#CS4
M5
DDR_A_#CS5
M3
DDR_A_#CS6
L4
DDR_A_#CS7
AM3
DDR_A_VREF
W8
DDR_A_CAS#
AA6
DDR_A_RAS#
Y10
DDE_A_WE#
AB5
DDR_A_BA0
AF6
DDR_A_BA1
AE25
DDR_A_BA2
AJ30
DDR_A_DQS_P0
AJ31
DDR_A_DQS_N0
AJ24
DDR_A_DQS_P1
AJ25
DDR_A_DQS_N1
AH19
DDR_A_DQS_P2
AH20
DDR_A_DQS_N2
AG14
DDR_A_DQS_P3
AG15
DDR_A_DQS_N3
AC6
DDR_A_DQS_P4
AD6
DDR_A_DQS_N4
W7
DDR_A_DQS_P5
V8
DDR_A_DQS_N5
N7
DDR_A_DQS_P6
P7
DDR_A_DQS_N6
G4
DDR_A_DQS_P7
H4
DDR_A_DQS_N7
AF9
DDR_A_DQS_P8
AG9
DDR_A_DQS_N8
3
DDR_A_DQ0
DDR_A_DQ1
DDR_A_DQ2
DDR_A_DQ3
DDR_A_DQ4
DDR_A_DQ5
DDR_A_DQ6
DDR_A_DQ7
DDR_A_DQ8
DDR_A_DQ9
DDR_A_DQ10
DDR_A_DQ11
DDR_A_DQ12
DDR_A_DQ13
DDR_A_DQ14
DDR_A_DQ15
DDR_A_DQ16
DDR_A_DQ17
DDR_A_DQ18
DDR_A_DQ19
DDR_A_DQ20
DDR_A_DQ21
DDR_A_DQ22
DDR_A_DQ23
DDR_A_DQ24
DDR_A_DQ25
DDR_A_DQ26
DDR_A_DQ27
DDR GROUP A
Lindenhurst-VS
3
DDR_A_DQ28
DDR_A_DQ29
DDR_A_DQ30
DDR_A_DQ31
DDR_A_DQ32
DDR_A_DQ33
DDR_A_DQ34
DDR_A_DQ35
DDR_A_DQ36
DDR_A_DQ37
DDR_A_DQ38
DDR_A_DQ39
DDR_A_DQ40
DDR_A_DQ41
DDR_A_DQ42
DDR_A_DQ43
DDR_A_DQ44
DDR_A_DQ45
DDR_A_DQ46
DDR_A_DQ47
DDR_A_DQ48
DDR_A_DQ49
DDR_A_DQ50
DDR_A_DQ51
DDR_A_DQ52
DDR_A_DQ53
DDR_A_DQ54
DDR_A_DQ55
DDR_A_DQ56
DDR_A_DQ57
DDR_A_DQ58
DDR_A_DQ59
DDR_A_DQ60
DDR_A_DQ61
DDR_A_DQ62
DDR_A_DQ63
DDR_A_DQS_P9
DDR_A_DQS_N9
DDR_A_DQS_P10
DDR_A_DQS_N10
DDR_A_DQS_P11
DDR_A_DQS_N11
DDR_A_DQS_P12
DDR_A_DQS_N12
DDR_A_DQS_P13
DDR_A_DQS_N13
DDR_A_DQS_P14
DDR_A_DQS_N14
DDR_A_DQS_P15
DDR_A_DQS_N15
DDR_A_DQS_P16
DDR_A_DQS_N16
DDR_A_DQS_P17
DDR_A_DQS_N17
AK32
AH31
AH29
AF28
AJ33
AK33
AG30
AG29
AG27
AG26
AD24
AD23
AE28
AF27
AH25
AG24
AF21
AG21
AF19
AG18
AE22
AD21
AJ18
AG20
AF16
AF15
AE13
AD12
AE17
AJ15
AE16
AD17
AH4
AG5
AB8
AB7
AB10
AA9
AE5
AD5
U9
AA5
V6
U7
W10
U10
W5
V5
R6
R5
L7
L6
P9
T5
N8
M9
K5
J5
K8
K10
L9
L10
K7
H7
AL32
AL31
AF25
AF24
AE20
AE19
AH14
AJ13
AD8
AC7
Y7
Y6
P10
N10
J6
H6
AH8
AJ7
DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15
DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31
DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63
DDRA_DQS9
DDRA_DQS10
DDRA_DQS11
DDRA_DQS12
DDRA_DQS13
DDRA_DQS14
DDRA_DQS15
DDRA_DQS16
DDRA_DQS17
2
DDRA_DQ[63..0] [22,23,24,25,26]
1
A1 A2 A3 A4
MCH
B1 B2 B3
A1
A2
A3
A4
DDRA_DQS[17..9] [22,23,24,25,26]
Title
Size Document Number Rev
2
Date: Sheet
A2A1A0 A2A1A0
0XA0(000)
0XA2(001)
0XA4(010)
0XA6(011)
B1
B2
B3
B4
GIGA-BYTE TECHNOLOGY CO., LTD.
MCH_MR DDR 266 CHA
GA-9IVDPC
B4
0XA8(100)
0XAA(101)
0XAC(110)
0XAE(111)
15 70Tuesday, June 14, 2005
1
of
1.1
5
D D
DDRB_CB[7..0][27,28,29,30,31]
C C
PLACE DDR VREF VOLTAGE
DIVIDER NEAR CHANNEL B
DIMMS
P2V5
R364
75/6/1
B B
A A
R371
75/6/1
PLACE CLOSE TO DIMM< 0.5
C247
1U/6/Y/10V
5
MOW 40
4 DIMM 1/4 CHANGE
DDRB_CS#[7..0][27,28,29,30,31]
DDRB_MCH_VREF_R
C257
0.1U/6/X/16V
DDRB_DQS[8..0][27,28,29,30,31]
DDRB_CMDCLK_B3_P[30,31]
DDRB_CMDCLK_B3_N[30,31]
DDRB_CMDCLK_B1_P[28,31]
DDRB_CMDCLK_B1_N[28,31]
DDRB_CMDCLK_B2_P[29,31]
DDRB_CMDCLK_B2_N[29,31]
DDRB_CMDCLK_B0_P[27,31]
DDRB_CMDCLK_B0_N[27,31]
4
U23B
DDRB_MA[13..0][27,28,29,30,31]
MEM_CKE4[24,26]
MEM_CKE5[26,29]
MEM_CKE6[25,26]
MEM_CKE7[26,30]
DDRB_CAS#[27,28,29,30,31]
DDRB_RAS#[27,28,29,30,31]
DDRB_WE#[27,28,29,30,31]
DDRB_BA0[27,28,29,30,31]
DDRB_BA1[27,28,29,30,31]
DDRB_DQS0
DDRB_DQS1
DDRB_DQS2
DDRB_DQS3
DDRB_DQS4
DDRB_DQS5
DDRB_DQS6
DDRB_DQS7
DDRB_DQS8
4
DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13
DDRB_CB0
DDRB_CB1
DDRB_CB2
DDRB_CB3
DDRB_CB4
DDRB_CB5
DDRB_CB6
DDRB_CB7
MEM_CKE4
MEM_CKE5
MEM_CKE6
MEM_CKE7
DDRB_CMDCLK_B3_P
DDRB_CMDCLK_B3_N
DDRB_CMDCLK_B1_P
DDRB_CMDCLK_B1_N
DDRB_CMDCLK_B2_P
DDRB_CMDCLK_B2_N
DDRB_CMDCLK_B0_P
DDRB_CMDCLK_B0_N
DDRB_CS#0
DDRB_CS#1
DDRB_CS#2
DDRB_CS#3
DDRB_CS#4
DDRB_CS#5
DDRB_CS#6
DDRB_CS#7
DDRB_CAS#
DDRB_RAS#
DDRB_WE#
DDRB_BA0DDRB_BA0
DDRB_BA1DDRB_BA1
AF7
DDR_B_MA0
AE14
DDR_B_MA1
AN14
DDR_B_MA2
AK14
DDR_B_MA3
AD15
DDR_B_MA4
AH16
DDR_B_MA5
AG17
DDR_B_MA6
AD18
DDR_B_MA7
AL20
DDR_B_MA8
AJ21
DDR_B_MA9
AC4
DDR_B_MA10
AH22
DDR_B_MA11
AH23
DDR_B_MA12
U4
DDR_B_MA13
AM7
DDR_B_CB0
AL7
DDR_B_CB1
AM4
DDR_B_CB2
AL4
DDR_B_CB3
AN8
DDR_B_CB4
AK8
DDR_B_CB5
AN5
DDR_B_CB6
AL5
DDR_B_CB7
AH26
DDR_CKE4
AJ27
DDR_CKE5
AJ28
DDR_CKE6
AH28
DDR_CKE7
AH7
DDR_B_CMDCLK_P0
AJ6
DDR_B_CMDCLK_N0
AH6
DDR_B_CMDCLK_P1
AG6
DDR_B_CMDCLK_N1
AG8
DDR_B_CMDCLK_P2
AE8
DDR_B_CMDCLK_N2
AK9
DDR_B_CMDCLK_P3
AL8
DDR_B_CMDCLK_N3
V9
DDR_B_#CS0
V2
DDR_B_#CS1
T7
DDR_B_#CS2
P6
DDR_B_#CS3
N4
DDR_B_#CS4
M2
DDR_B_#CS5
M6
DDR_B_#CS6
L3
DDR_B_#CS7
AN4
DDR_B_VREF
W1
DDR_B_CAS#
Y9
DDR_B_RAS#
W4
DDE_B_WE#
AA8
DDR_B_BA0
AE7
DDR_B_BA1
AM25
DDR_B_BA2
AM28
DDR_B_DQS_P0
AN29
DDR_B_DQS_N0
AM22
DDR_B_DQS_P1
AN23
DDR_B_DQS_N1
AK17
DDR_B_DQS_P2
AL17
DDR_B_DQS_N2
AK11
DDR_B_DQS_P3
AL11
DDR_B_DQS_N3
AG2
DDR_B_DQS_P4
AH2
DDR_B_DQS_N4
AA3
DDR_B_DQS_P5
AB4
DDR_B_DQS_N5
P1
DDR_B_DQS_P6
R2
DDR_B_DQS_N6
H3
DDR_B_DQS_P7
H1
DDR_B_DQS_N7
AK5
DDR_B_DQS_P8
AK6
DDR_B_DQS_N8
Lindenhurst-VS
3
DDR GROUP B
DDR_B_DQS_P9
DDR_B_DQS_N9
DDR_B_DQS_P10
DDR_B_DQS_N10
DDR_B_DQS_P11
DDR_B_DQS_N11
DDR_B_DQS_P12
DDR_B_DQS_N12
DDR_B_DQS_P13
DDR_B_DQS_N13
DDR_B_DQS_P14
DDR_B_DQS_N14
DDR_B_DQS_P15
DDR_B_DQS_N15
DDR_B_DQS_P16
DDR_B_DQS_N16
DDR_B_DQS_P17
DDR_B_DQS_N17
3
DDR_B_DQ0
DDR_B_DQ1
DDR_B_DQ2
DDR_B_DQ3
DDR_B_DQ4
DDR_B_DQ5
DDR_B_DQ6
DDR_B_DQ7
DDR_B_DQ8
DDR_B_DQ9
DDR_B_DQ10
DDR_B_DQ11
DDR_B_DQ12
DDR_B_DQ13
DDR_B_DQ14
DDR_B_DQ15
DDR_B_DQ16
DDR_B_DQ17
DDR_B_DQ18
DDR_B_DQ19
DDR_B_DQ20
DDR_B_DQ21
DDR_B_DQ22
DDR_B_DQ23
DDR_B_DQ24
DDR_B_DQ25
DDR_B_DQ26
DDR_B_DQ27
DDR_B_DQ28
DDR_B_DQ29
DDR_B_DQ30
DDR_B_DQ31
DDR_B_DQ32
DDR_B_DQ33
DDR_B_DQ34
DDR_B_DQ35
DDR_B_DQ36
DDR_B_DQ37
DDR_B_DQ38
DDR_B_DQ39
DDR_B_DQ40
DDR_B_DQ41
DDR_B_DQ42
DDR_B_DQ43
DDR_B_DQ44
DDR_B_DQ45
DDR_B_DQ46
DDR_B_DQ47
DDR_B_DQ48
DDR_B_DQ49
DDR_B_DQ50
DDR_B_DQ51
DDR_B_DQ52
DDR_B_DQ53
DDR_B_DQ54
DDR_B_DQ55
DDR_B_DQ56
DDR_B_DQ57
DDR_B_DQ58
DDR_B_DQ59
DDR_B_DQ60
DDR_B_DQ61
DDR_B_DQ62
DDR_B_DQ63
AM30
AN30
AN27
AM27
AK30
AM31
AL28
AK27
AM24
AN24
AN21
AM21
AL25
AK24
AL22
AK21
AK18
AM18
AN15
AM15
AL19
AM19
AM16
AL16
AK12
AM12
AN9
AM9
AL13
AM13
AM10
AL10
AJ3
AJ4
AF1
AF4
AK3
AK2
AG3
AF3
AC3
AC1
Y3
Y4
AD2
AD3
AA2
Y1
T4
T1
N1
N2
U3
U1
P3
P4
K2
K1
F2
E1
L1
K4
G1
G2
AK29
AL29
AK23
AL23
AN18
AN17
AN12
AN11
AJ1
AH1
AB2
AB1
T2
R3
J3
J2
AM6
AN6
DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15
DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23
DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31
DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39
DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47
DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55
DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63
DDRB_DQS9
DDRB_DQS10
DDRB_DQS11
DDRB_DQS12
DDRB_DQS13
DDRB_DQS14
DDRB_DQS15
DDRB_DQS16
DDRB_DQS17
2
DDRB_DQ[63..0] [27,28,29,30,31]
DDRB_DQS[17..9] [27,28,29,30,31]
Title
Size Document Number Rev
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
MCH_MR DDR 266 CHB
GA-9IVDPC
1
1.1
16 70Tuesday, June 14, 2005
1
of
5
4
3
2
1
P3V3
D12
D D
MCH_HI_VSWING
MCH_HI_VREF
C C
B B
P1V5
C339
100P/6/X
R427 40.2/6/1
P2V5
R428 40.2/6/1
R542
43.2/6/1
SYS_PWR_GD_3_3V[33,37,52]
W>12mil/ L<500mil
C276
0.1U/6/X/16V
0.1U/6/X/16V
C319
PCI_SLOT_SCL[34,35,51,67]
PCI_SLOT_SDA[34,35,51,67]
HIA_STRBS[36]
HIA_STRBF[36]
MCH_66MHZ_CLK[33]
PCI_SLOT_SCL[34,35,51,67]
PCI_SLOT_SDA[34,35,51,67]
ITP_TMS_MCH[13]
ITP_TDI_MCH[13]
ITP_TDO_MCH[13]
ITP_TCK1[13]
ITP_TRST#[8,11,13]
TP81
TP82
C269
TP83
TP84
TP85
TP86
TP87
TP88
TP89
TP90
TP91
HIA_STRBS
HIA_STRBF
MCH_66MHZ_CLK
MCH_HI_RCOMP
SYS_PWR_GD_3_3V
I2C_BUS2_SCL
I2C_BUS2_SDA
ITP_TMS_MCH
ITP_TDI_MCH
ITP_TDO_MCH
ITP_TCK1
ITP_TRST#
PD_DDRRES1
PD_DDRRES2
TP_RESERVED2
TP_RESERVED3
TP_RESERVED4
TP_RESERVED5
TP_RESERVED6
TP_RESERVED7
TP_RESERVED8
TP_RESERVED9
TP_RESERVED10
TP_RESERVED11
TP_RESERVED12
E31
D32
H31
L24
K25
F32
AE2
AE1
AF30
AE23
AD20
AJ19
R10
AA24
R32
L33
G5
G6
M8
E3
C3
D4
F3
D2
J9
R9
R8
U23E
HI_STBS
HI_STBF
HISWING
HICLK
HIRCOMP
HIVREF
PWRGOOD
SMBCLK
SMBDATA
TMS
TDI
TDO
TCK
TRST#
DDR_RES1
DDR_RES2
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
RESERVED10
RESERVED11
RESERVED12
Lindenhurst-VS
HI 1.5 & Miscellaneous
0.1U/6/X/16V
V3REF
DDRSLWCRES
DDR_CRES0
DDR_IMPCRES
PLLSEL1#
PLLSEL0#
HI10
HI11
DEBUG0
DEBUG1
DEBUG2
DEBUG3
DEBUG4
DEBUG5
DEBUG6
DEBUG7
TDIOCATHODE
TDIOANODE
HI0
HI1
HI2
HI3
HI4
HI5
HI6
HI7
HI8
HI9
H33
MCH_DDRSLWCRE S
AK1
AC9
AL2
A29
C31
J30
H30
C32
G31
G29
H28
K26
J27
F30
E33
J29
G32
ITP_MCH_DEBUG0
J8
ITP_MCH_DEBUG1
G7
ITP_MCH_DEBUG2
G8
ITP_MCH_DEBUG3
H9
ITP_MCH_DEBUG4
B2
ITP_MCH_DEBUG5
D3
ITP_MCH_DEBUG6
L11
ITP_MCH_DEBUG7
D1
F33
D33
1N5820/SMD
MCH_DDRCRES0
MCH_DDRIMPCRES
MCH_PLLSEL1#
MCH_PLLSEL0#
HI_A0
HI_A1
HI_A2
HI_A3
HI_A4
HI_A5
HI_A6
HI_A7
HI_A8
HI_A9
HI_A10
HI_A11
MCH_TDC
MCH_TDA
12
R392 1.13K/6/1
R388 374/6/1
TP220
TP222
P1V5
Internal PU
ICH_PLLSEL1 [37]
HI_A[11..0] [36]
ICH_PLLSEL0 [37]
Below table is MCH spec table, but because a Inverter between S.B and MCH ,
so below t able difference page 37 and page 7 table.
DDR333
00
10
ITP_MCH_DEBUG[7..0] [13]
ICH_PLLSEL[1:0]
133/533
167/667
DDR266
10
11
200/800 0011
P1V5 P1V5
R481
78.7/6/1
354mV 804mV
A A
R489
24.3/6/1
5
W>20mil W>20mil
MCH_HI_VREF MCH_HI_VSWING
C328
0.01U/6/X/50V
4
R469
43.2/6/1
R472
49.9/6/1
C321
0.01U/6/X/50V
Title
Size Document Number Rev
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
MCH HI 1.5/MISC
GA-9IVDPC
17 70Tuesday, June 14, 2005
1
of
1.1
5
4
3
2
1
SB_ADS#[8,11]
SB_AP#0[8,11]
SB_AP#1[8,11]
SB_MCERR#[8,9,11]
SB_BNR#[8,9,11]
SB_BPRI#[8,11]
MCH_BREQ#0[14]
D D
C C
B B
A A
MCH_BREQ#1[14]
SB_CPURST#[8,9,11,13,14]
SB_DBSY#[8,11]
SB_DEFER#[8,11]
SB_DRDY#[8,11]
SB_DP#[3..0][8,11]
SB_DBI#[3..0][8,11]
SB_D#[63..0][8,11]
SB_ADS#
SB_AP#0
SB_AP#1
SB_MCERR#
SB_BNR#
SB_BPRI#
MCH_BREQ#0
MCH_BREQ#1
SB_CPURST#
SB_DBSY#
SB_DEFER#
SB_DRDY#
SB_DP#0
SB_DP#1
SB_DP#2
SB_DP#3
SB_DBI#0
SB_DBI#1
SB_DBI#2
SB_DBI#3
SB_D#0
SB_D#1
SB_D#2
SB_D#3
SB_D#4
SB_D#5
SB_D#6
SB_D#7
SB_D#8
SB_D#9
SB_D#10
SB_D#11
SB_D#12
SB_D#13
SB_D#14
SB_D#15
SB_D#16
SB_D#17
SB_D#18
SB_D#19
SB_D#20
SB_D#21
SB_D#22
SB_D#23
SB_D#24
SB_D#25
SB_D#26
SB_D#27
SB_D#28
SB_D#29
SB_D#30
SB_D#31
SB_D#32
SB_D#33
SB_D#34
SB_D#35
SB_D#36
SB_D#37
SB_D#38
SB_D#39
SB_D#40
SB_D#41
SB_D#42
SB_D#43
SB_D#44
SB_D#45
SB_D#46
SB_D#47
SB_D#48
SB_D#49
SB_D#50
SB_D#51
SB_D#52
SB_D#53
SB_D#54
SB_D#55
SB_D#56
SB_D#57
SB_D#58
SB_D#59
SB_D#60
SB_D#61
SB_D#62
SB_D#63
5
B27
G25
H25
H24
B31
A28
F24
D29
H27
B28
B30
C29
E28
E25
F27
D16
E15
C18
B19
C14
A17
A19
B16
C17
B18
D17
A16
B13
A14
A13
D14
C12
B12
E18
H18
F17
G17
K17
E16
F14
F15
G16
K16
H16
G14
K14
E12
C11
H13
F11
G13
D11
F12
G10
H10
G11
K13
H12
B10
A10
A11
J24
J18
J17
J14
J12
F9
A5
E9
D8
F8
C9
B9
C8
B6
B7
E7
B4
A4
B3
D5
C6
D7
C5
U23C
ADS#
AP#0
AP#1
MCERR#
BNR#
BPRI#
BREQ#0
BREQ#1
CPURST#
DBSY#
DEFER#
DRDY#
DP#0
DP#1
DP#2
DP#3
DBI#0
DBI#1
DBI#2
DBI#3
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
Lindenhurst-VS
SB_DSTBP#0
HIT#
HITM#
HLOCK#
HTRDY#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
TESTIN#
RSTIN#
HCRES0
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HA#32
HA#33
HA#34
HA#35
HCLKINN
HCLKINP
RS#0
RS#1
RS#2
RSP#
BINIT#
PME#
GPE#
C15
B15
J15
H15
E10
D10
A7
A8
E30
D28
C30
A30
K20
J21
J23
H22
K23
L12
C2
C27
E27
F26
D13
E13
F23
K22
J20
G23
G22
H21
K19
H19
G19
E22
E21
F18
E19
F21
F20
D26
C26
A26
D22
B22
A25
B25
D25
C24
A22
B21
D23
A23
B24
A20
D19
C20
C21
D20
J11
K11
G20
C23
F29
D31
G28
J26
G26
M24
L25
SB_DSTBN#0
SB_DSTBP#1
SB_DSTBN#1
SB_DSTBP#2
SB_DSTBN#2
SB_DSTBP#3
SB_DSTBN#3
SB_HIT#
SB_HITM#
SB_LOCK#
SB_TRDY#
SB_REQ#0
SB_REQ#1
SB_REQ#2
SB_REQ#3
SB_REQ#4
MCH_TESTIN#
-PCIRST_MCH
HCRES0
SB_ODTCRES_MCH
SB_SLWCRES_MCH
SB_HA#3
SB_HA#4
SB_HA#5
SB_HA#6
SB_HA#7
SB_HA#8
SB_HA#9
SB_HA#10
SB_HA#11
SB_HA#12
SB_HA#13
SB_HA#14
SB_HA#15
SB_HA#16
SB_HA#17
SB_HA#18
SB_HA#19
SB_HA#20
SB_HA#21
SB_HA#22
SB_HA#23
SB_HA#24
SB_HA#25
SB_HA#26
SB_HA#27
SB_HA#28
SB_HA#29
SB_HA#30
SB_HA#31
SB_HA#32
SB_HA#33
SB_HA#34
SB_HA#35
MCH_BCLK#
MCH_BCLK
SB_ADSTB#0
SB_ADSTB#1
SB_RS#0
SB_RS#1
SB_RS#2
SB_RSP#
SB_BINIT#
MCH_PME#
SB_HIT# [8,9,11]
SB_HITM# [8,9,11]
SB_LOCK# [8,11]
SB_TRDY# [8,11]
-PCIRST_MCH [37]
MCH_BCLK# [32]
MCH_BCLK [32]
SB_BINIT# [8,9,11 ]
MCH_PME# [13,37]
HDSTBP#0
HDSTBN#0
HDSTBP#1
HDSTBN#1
HDSTBP#2
HDSTBN#2
HDSTBP#3
HDSTBN#3
HODTCRES
HSLWCRES
HDVREF0
HDVREF1
System Bus Interface
HACVREF
HADSTB#0
HADSTB#1
4
SB_REQ#[4..0] [8 ,11]
TP92
SB_HA#[35..3] [ 8,11]
V1.0
SB_ADSTB#[1..0] [8,1 1]
SB_RS#[2..0] [8,11]
SB_RSP# [8,11]
3
SB_DSTBP#[3..0] [8,11 ]
SB_DSTBN#[3..0] [ 8,11]
MCH_BREQ#0
MCH_BREQ#1
R452
8.2K/6
R526
48.7/6/1
R527
442/6/1
Add Caps/ Layout
R529 51/6/X
R524 51/6/X
P3V3
MCH_SB_VREF
P_VTT
P_VTT
R544
R533 0/6
C349
220P/6
Title
Size Document Number Rev
2
Date: Sheet
754mV
C367
1U/6/Y/10V
1
MCH_HSINK
GIGA-BYTE TECHNOLOGY CO., LTD.
MCH SYS BUS
49.9/6/1
R548
90.9/6/1
MCH_HSINK1
GA-9IVDPC
2
1.1
of
18 70Tuesday, June 14, 2005
1
5
4
3
2
1
U23D
D D
C C
MCH_SRC_100MHZ_CLK_N[34]
MCH_SRC_100MHZ_CLK_P[34]
B B
EXP_A_RXP0[64]
EXP_A_RXP4[35]
EXP_A_RXP5[35]
EXP_A_RXP6[35]
EXP_A_RXP7[35]
EXP_A_RXN0[64]
EXP_A_RXN4[35]
EXP_A_RXN5[35]
EXP_A_RXN6[35]
EXP_A_RXN7[35]
MCH_SRC_100MHZ_CLK_N
MCH_SRC_100MHZ_CLK_P
EXP_A_RXP0
EXP_A_RXP4
EXP_A_RXP5
EXP_A_RXP6
EXP_A_RXP7
EXP_A_RXN0
EXP_A_RXN4
EXP_A_RXN5
EXP_A_RXN6
EXP_A_RXN7
M27
M26
AG33
AE32
AC30
AC31
AD29
AC25
AB26
AF33
AD32
AD30
AB31
AE29
AC24
AB25
AA30
AA29
R33
N28
L31
J33
R26
N25
K29
P33
N29
L30
J32
R27
N26
K28
Y25
Y24
Y28
Y30
V33
T32
R30
V27
V24
Y27
Y31
V32
T31
R29
V26
U24
R24
T23
EXP_A_RXP0
EXP_A_RXP1
EXP_A_RXP2
EXP_A_RXP3
EXP_A_RXP4
EXP_A_RXP5
EXP_A_RXP6
EXP_A_RXP7
EXP_A_RXN0
EXP_A_RXN1
EXP_A_RXN2
EXP_A_RXN3
EXP_A_RXN4
EXP_A_RXN5
EXP_A_RXN6
EXP_A_RXN7
EXP_B_RXP0
EXP_B_RXP1
EXP_B_RXP2
EXP_B_RXP3
EXP_B_RXP4
EXP_B_RXP5
EXP_B_RXP6
EXP_B_RXP7
EXP_B_RXN0
EXP_B_RXN1
EXP_B_RXN2
EXP_B_RXN3
EXP_B_RXN4
EXP_B_RXN5
EXP_B_RXN6
EXP_B_RXN7
EXP_C_RXP0
EXP_C_RXP1
EXP_C_RXP2
EXP_C_RXP3
EXP_C_RXP4
EXP_C_RXP5
EXP_C_RXP6
EXP_C_RXP7
EXP_C_RXN0
EXP_C_RXN1
EXP_C_RXN2
EXP_C_RXN3
EXP_C_RXN4
EXP_C_RXN5
EXP_C_RXN6
EXP_C_RXN7
EXP_CLKN
EXP_CLKP
Lindenhurst-VS
EXP_A_TXP0
EXP_A_TXP1
EXP_A_TXP2
EXP_A_TXP3
EXP_A_TXP4
EXP_A_TXP5
EXP_A_TXP6
EXP_A_TXP7
EXP_A_TXN0
EXP_A_TXN1
EXP_A_TXN2
EXP_A_TXN3
EXP_A_TXN4
EXP_A_TXN5
EXP_A_TXN6
EXP_A_TXN7
EXP_B_TXP0
EXP_B_TXP1
EXP_B_TXP2
EXP_B_TXP3
EXP_B_TXP4
PCI Express
EXP_B_TXP5
EXP_B_TXP6
EXP_B_TXP7
EXP_B_TXN0
EXP_B_TXN1
EXP_B_TXN2
EXP_B_TXN3
EXP_B_TXN4
EXP_B_TXN5
EXP_B_TXN6
EXP_B_TXN7
EXP_C_TXP0
EXP_C_TXP1
EXP_C_TXP2
EXP_C_TXP3
EXP_C_TXP4
EXP_C_TXP5
EXP_C_TXP6
EXP_C_TXP7
EXP_C_TXN0
EXP_C_TXN1
EXP_C_TXN2
EXP_C_TXN3
EXP_C_TXN4
EXP_C_TXN5
EXP_C_TXN6
EXP_C_TXN7
EXP_COMP0
EXP_COMP1
EXPHPINTR#
VCCBGEXP
VSSBGEXP
CAP CLOSE TO MCH
P30
N31
M33
K32
P24
P27
M30
L28
P31
N32
M32
K31
P25
P28
M29
L27
AG32
AF31
AC33
AB32
AD27
AC27
AB29
AA27
AH32
AE31
AD33
AA32
AD26
AC28
AB28
AA26
W26
W28
Y33
W32
U31
V30
T29
T26
W25
W29
AA33
W31
U30
V29
T28
T25
U33
U25
E6
U27
U28
EXP_A_TXP_C0
EXP_A_TXP_C1
EXP_A_TXP_C2
EXP_A_TXP_C3
EXP_A_TXP_C4
EXP_A_TXP_C5
EXP_A_TXP_C6
EXP_A_TXP_C7
EXP_A_TXN_C0
EXP_A_TXN_C1
EXP_A_TXN_C2
EXP_A_TXN_C3
EXP_A_TXN_C4
EXP_A_TXN_C5
EXP_A_TXN_C6
EXP_A_TXN_C7
EXP_COMP0
EXP_COMP1
PU_EXPHPINTR#
SC273 0.1U /4/Y/16V
SC304 0.1U/4/Y/16V/X
SC311 0.1U/4/Y/16V/X
SC316 0.1U/4/Y/16V/X
SC274 0.1U /4/Y/16V
SC296 0.1U /4/Y/16V
SC298 0.1U /4/Y/16V
SC315 0.1U /4/Y/16V
SC272 0.1U /4/Y/16V
SC300 0.1U/4/Y/16V/X
SC314 0.1U/4/Y/16V/X
SC319 0.1U/4/Y/16V/X
SC275 0.1U /4/Y/16V
SC297 0.1U /4/Y/16V
SC299 0.1U /4/Y/16V
SC317 0.1U /4/Y/16V
P1V5
R441
24.9/6/1
P3V3
EXP_A_TXP0
EXP_A_TXP4
EXP_A_TXP5
EXP_A_TXP6
EXP_A_TXP7
EXP_A_TXN0
EXP_A_TXN4
EXP_A_TXN5
EXP_A_TXN6
EXP_A_TXN7
R515
1K/6/X
EXP_A_TXP0 [64 ]
EXP_A_TXP4 [35 ]
EXP_A_TXP5 [35 ]
EXP_A_TXP6 [35 ]
EXP_A_TXP7 [35 ]
EXP_A_TXN0 [6 4]
EXP_A_TXN4 [3 5]
EXP_A_TXN5 [3 5]
EXP_A_TXN6 [3 5]
EXP_A_TXN7 [3 5]
Do Not Sup p ort PCI E xpress Hot-Plug
MCH_VCCBGEXP
MCH_VSSBGEXP
DIFFERENTIAL PAIRS
12
C301
10U/8/Y/10V
MCH_VSSBGEXP
L6
4.7UH/60mA/8
C300
0.1U/6/X/16V
R438 0/6
P3V3_U24MCH_VCCBGEXP
P3V3
R436
100/6
2.5V 3% 600uA
U24
LM431/SOT23
R
A C
R445
0/6
NO USE
NO USE
LAN/SLOT
PORT B
PORT C
PORT A
DDR
FSB
HI
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
MCH PCI EXPRESS
GA-9IVDPC
1
of
19 70Tuesday, June 14, 2005
1.1
5
P2V5
D D
C C
P1V5
B B
A A
AN28
AN22
AN16
AN10
AN3
AL30
AL24
AL18
AL12
AL6
AJ26
AJ20
AJ14
AJ8
AH3
AG28
AG22
AG16
AG10
AF5
AE24
AE18
AE12
AD7
AD1
AC23
AC21
AC19
AC17
AC15
AC13
AC11
AB22
AB20
AB18
AB16
AB14
AB12
AB9
AB3
AA11
Y12
W11
V12
U11
T12
R11
P12
N11
AL1
AH33
AE33
AE30
AC29
AB33
AB27
AB24
AA23
Y29
Y22
W33
W27
W23
V22
U29
T33
T27
T24
T22
R23
P29
N33
M28
K33
K30
Y5
V7
V1
T9
T3
P5
M1
K3
H5
F1
M7
5
U23F
VCC_DDR0
VCC_DDR1
VCC_DDR2
VCC_DDR3
VCC_DDR4
VCC_DDR5
VCC_DDR6
VCC_DDR7
VCC_DDR8
VCC_DDR9
VCC_DDR10
VCC_DDR11
VCC_DDR12
VCC_DDR13
VCC_DDR14
VCC_DDR15
VCC_DDR16
VCC_DDR17
VCC_DDR18
VCC_DDR19
VCC_DDR20
VCC_DDR21
VCC_DDR22
VCC_DDR23
VCC_DDR24
VCC_DDR25
VCC_DDR26
VCC_DDR27
VCC_DDR28
VCC_DDR29
VCC_DDR30
VCC_DDR31
VCC_DDR32
VCC_DDR33
VCC_DDR34
VCC_DDR35
VCC_DDR36
VCC_DDR37
VCC_DDR38
VCC_DDR39
VCC_DDR40
VCC_DDR41
VCC_DDR42
VCC_DDR43
VCC_DDR44
VCC_DDR45
VCC_DDR46
VCC_DDR47
VCC_DDR48
VCC_DDR49
VCC_DDR50
VCC_DDR51
VCC_DDR52
VCC_DDR53
VCC_DDR54
VCC_DDR55
VCC_DDR56
VCC_DDR57
VCC_DDR58
VCC_DDR59
VCC_DDR60
VCC_EXP0
VCC_EXP1
VCC_EXP2
VCC_EXP3
VCC_EXP4
VCC_EXP5
VCC_EXP6
VCC_EXP7
VCC_EXP8
VCC_EXP9
VCC_EXP10
VCC_EXP11
VCC_EXP12
VCC_EXP13
VCC_EXP14
VCC_EXP15
VCC_EXP16
VCC_EXP17
VCC_EXP18
VCC_EXP19
VCC_EXP20
VCC_EXP21
VCC_EXP22
VCC_EXP23
VCC_EXP24
Lindenhurst-VS
VCC_CORE0
VCC_CORE1
VCC_CORE2
VCC_CORE3
VCC_CORE4
VCC_CORE5
VCC_CORE6
VCC_CORE7
VCC_CORE8
VCC_CORE9
VCC_CORE10
VCC_CORE11
VCC_CORE12
VCC_CORE13
VCC_CORE14
VCC_CORE15
VCC_CORE16
VCC_CORE17
VCC_CORE18
VCC_CORE19
VCC_CORE20
VCC_CORE21
VCC_CORE22
VCC_CORE23
VCC_CORE24
POWER
VCC_CORE25
VCC_CORE26
VCC_CORE27
VCC_CORE28
VCC_CORE29
VCC_CORE30
VCC_CORE31
VCC_CORE32
VCC_CORE33
VCC_CORE34
VCC_CORE35
VCC_CORE36
VCC_CORE37
VCC_CORE38
VCC_CORE39
VCC_CORE40
VCC_CORE41
VCC_CORE42
VCC_CORE43
VCC_CORE44
VCC_CORE45
VCC_CORE46
VCC_CORE47
VCC_CORE48
VCC_CORE49
VCC_VTT0
VCC_VTT1
VCC_VTT2
VCC_VTT3
VCC_VTT4
VCC_VTT5
VCC_VTT6
VCC_VTT7
VCC_VTT8
VCC_VTT9
VCC_VTT10
VCC_VTT11
VCC_VTT12
VCC_VTT13
VCC_VTT14
VCC_VTT15
VCC_VTT16
VCC_VTT17
VCC_VTT18
VCC_VTT19
VCC_VTT20
VCC_VTT21
VCC_VTT22
VCC_VTT23
VCC_VTT24
VCC_VTT25
VCC_VTT26
VCC_VTT27
VCC_VTT28
VCCA_CORE0
VSSA_CORE1
VCCA_EXP0
VSSA_EXP1
VCCA_HI0
VSSA_HI1
VCCA_DDR
AA21
AA19
AA17
AA15
AA13
Y20
Y18
Y16
Y14
W21
W19
W17
W15
W13
V20
V18
V16
V14
U21
U19
U17
U15
T20
T18
T16
T14
R21
R19
R17
R15
R13
P18
P16
P14
N21
N19
N17
N15
N13
U13
C33
K9
M12
G33
H29
K27
L23
N23
P22
M22
A31
M20
M18
M16
M14
L21
L19
L17
L15
L13
J19
J16
J13
H26
H23
E23
E20
E17
E14
E11
E8
D30
D27
A18
A15
A12
A9
A6
A3
F6
F5
U23
V23
P20
P21
E4
P1V5
VCCA_SB
VSSA_SB
VCCA_EXP
VSSA_EXP
VCCA_HI
VSSA_HI
VCCA_DDR
P_VTT
4
Y13
Y11
Y8
Y2
W30
W24
W22
W20
W18
W16
W14
W12
W9
W6
W3
V31
V28
V25
V21
V19
V17
V15
V13
V11
V10
V4
U32
AB6
AA31
AA28
AA25
AA22
AA20
AA18
AA16
AA14
AA12
AA10
AA7
AB23
AB21
AB19
AB17
AB15
AB13
AN31
AN25
AN19
AN13
AN7
AM32
AM29
AM26
AM23
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL33
AL27
AL21
AL15
AL9
AL3
AK31
AK28
AK25
AK22
AK19
AK16
AG13
E24
VCCA_SB [2 1]
VSSA_SB [21]
VCCA_EXP [21]
VSSA_EXP [21]
VCCA_HI [21]
VSSA_HI [21]
VCCA_DDR [21]
4
U23G
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
Lindenhurst-VS
3
3
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
GND
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
AF29
AF26
AF23
AF20
AF17
AF14
AF11
AF8
AF2
AE27
AE21
AE15
AE9
AE6
AE3
AD31
AD28
AD25
AD22
AD19
AD16
AD13
AD10
AD4
AC32
AC26
AC22
AC20
AC18
AC16
AC14
AC12
AC8
AC5
AC2
AB30
AK7
AK4
AJ32
AJ29
AJ17
AJ11
AJ5
AJ23
AJ2
AH30
AH27
AH24
AH21
AH18
AH15
AH12
AH9
AG31
AG25
AG19
AG1
AF32
AA4
AA1
Y32
Y26
Y23
Y21
Y19
Y17
Y15
AB11
AK10
AK13
U26
U22
U20
2
U23H
M13
VSS148
M11
VSS149
M10
VSS150
M4
VSS151
L32
VSS152
L29
VSS153
L26
VSS154
L22
VSS155
L20
VSS156
L18
VSS157
L16
VSS158
L14
VSS159
L8
VSS160
L5
VSS161
L2
VSS162
K24
VSS163
K21
VSS164
K18
VSS165
K15
VSS166
K12
VSS167
K6
VSS168
J31
VSS169
J28
VSS170
J25
VSS171
J22
VSS172
J10
VSS173
J7
VSS174
J4
VSS175
J1
VSS176
H32
VSS177
H20
VSS178
H17
VSS179
H14
VSS180
H11
VSS181
AG4
VSS182
AG7
VSS183
U18
VSS184
U16
VSS185
U14
VSS186
U12
VSS187
U8
VSS188
U5
VSS189
U2
VSS190
T30
VSS191
T21
VSS192
T19
VSS193
T17
VSS194
T15
VSS195
T11
VSS196
T13
VSS197
T6
VSS198
R31
VSS199
R28
VSS200
R25
VSS201
R22
VSS202
R20
VSS203
R18
VSS204
R16
VSS205
R14
VSS206
R12
VSS207
R7
VSS208
R4
VSS209
R1
VSS210
P32
VSS211
P26
VSS212
P23
VSS213
P19
VSS214
P17
VSS215
P15
VSS216
N22
VSS217
N20
VSS218
N18
VSS219
N16
VSS220
N14
VSS221
Lindenhurst-VS
Title
Size Document Number Rev
2
Date: Sheet
GND
F16
VSS222
F13
VSS223
F10
VSS224
F7
VSS225
F4
VSS226
H8
VSS227
H2
VSS228
G30
VSS229
G27
VSS230
G21
VSS231
G18
VSS232
G15
VSS233
G12
VSS234
G9
VSS235
G3
VSS236
F31
VSS237
F28
VSS238
G24
VSS239
F25
VSS240
F22
VSS241
F19
VSS242
N3
VSS243
M31
VSS244
M25
VSS245
M23
VSS246
M21
VSS247
M19
VSS248
M17
VSS249
M15
VSS250
N6
VSS251
E32
VSS252
E29
VSS253
E26
VSS254
E5
VSS255
E2
VSS256
D24
VSS257
D21
VSS258
D18
VSS259
D15
VSS260
D12
VSS261
D9
VSS262
D6
VSS263
B32
VSS264
C28
VSS265
C25
VSS266
C22
VSS267
C19
VSS268
C16
VSS269
C13
VSS270
C10
VSS271
C7
VSS272
C4
VSS273
C1
VSS274
B29
VSS275
B26
VSS276
B23
VSS277
B20
VSS278
B14
VSS279
B11
VSS280
B8
VSS281
B5
VSS282
A27
VSS283
A24
VSS284
A21
VSS285
P13
VSS286
P11
VSS287
P8
VSS288
P2
VSS289
N30
VSS290
N27
VSS291
N24
VSS292
N12
VSS293
N9
VSS294
B17
VSS295
GIGA-BYTE TECHNOLOGY CO., LTD.
MCH PWR/GND
GA-9IVDPC
1
1.1
of
20 70Tuesday, June 14, 2005
1
5
P1V5
SC361
SC237
0.1U/6/X/16V
SC268
0.1U/6/X/16V
SC286
0.01U/6/X/50V
SC250
0.1U/6/X/16V
C336
0.1U/6/X/16V
SC290
0.1U/6/X/16V
SC267
0.1U/6/X/16V
SC327
0.1U/6/X/16V
SC276
0.1U/6/X/16V
C333
0.1U/6/X/16V
0.1U/6/X/16V
D D
SC269
0.1U/6/X/16V
SC302
0.01U/6/X/50V
SC318
P1V5
0.1U/6/X/16V
SC242
0.1U/6/X/16V
C C
SC224
0.1U/6/X/16V
SC266
0.1U/6/X/16V
SC303
0.01U/6/X/50V
SC265
0.1U/6/X/16V
C452
0.1U/6/X/16V
SC235
0.1U/6/X/16V
SC240
0.1U/6/X/16V
SC236
0.01U/6/X/50V
C351
0.1U/6/X/16V
SC222
0.1U/6/X/16V
SC259
0.1U/6/X/16V
SC251
0.01U/6/X/50V
C318
0.01U/6/X/50V
SC249
0.1U/6/X/16V
SC271
0.1U/6/X/16V
SC295
0.01U/6/X/50V
C343
0.01U/6/X/50V
4
SC260
0.1U/6/X/16V
SC270
0.1U/6/X/16V
SC258
0.01U/6/X/50V
C353
0.1U/6/X/16V
SC257
0.1U/6/X/16V
SC281
0.01U/6/X/50V
SC243
0.01U/6/X/50V
C265
0.01U/6/X/50V
SC293
0.1U/6/X/16V
SC360
0.1U/6/X/16V
SC336
0.1U/6/X/16V
C354
0.01U/6/X/50V
SC252
0.1U/6/X/16V
SC359
0.1U/6/X/16V
SC366
0.01U/6/X/50V
3
VCCA_HI
VCCA_EXP
VCCA_DDR
VCCA_SB
PLACE COMPONENTS:
GROUP ASSOCIATE COMPONENTS
TOGHTER AND AS PHYSICALLY
PIN AS POSSIBLE
MIN TRACE WIDTH:
AS WIDE AS POSSIBLE
>= 25 MILS
MIN TRACE SPACING:
>= 10 MILS
MAX LENGTH
>=1.2(BOARD+BREAKOUT)
ROUTE
DIFFERENTIAL PAIRS
MCH VCCA
P1V5
P1V5
P1V5
P1V5
2
R444
VCCA_HI_R_N VCCA_HI
1/6/1
3% 31.8mA
R433
1/6/1
3% 30.9mA
R550
1/6/1
3% 28.9mA
R549
VCCA_SB_R_N VCCA_SB
1/6/1
3% 28.9mA
L8 4.7UH/60mA/8
L5 4.7UH/60mA/8
12
C289
10U/8/Y/10V
L10 4.7UH/60mA/8
L9 4.7UH/60mA/8
12
C305
10U/8/Y/10V
12
C280
10U/8/Y/10V
12
C356
10U/8/Y/10V
12
C355
10U/8/Y/10V
C307
0.1U/6/X/16V
VSSA_HI
VCCA_EXPVCCA_EXP_R_N
C290
0.1U/6/X/16V
VSSA_EXP
VCCA_DDRVCCA_DDR_R_N
C364
0.1U/6/X/16V
VSSA_SB
C363
0.1U/6/X/16V
VSSA_SB
1
VCCA_HI [20]
VSSA_HI [20]
VCCA_EXP [20]
VSSA_EXP [20]
VCCA_DDR [20]
VSSA_SB [20]
VCCA_SB [2 0]
VSSA_SB [20]
C316
C308
P2V5
SC207
0.1U/6/X/16V
C233
0.1U/6/X/16V
0.1U/6/X/16V
SC206
0.1U/6/X/16V
C234
0.1U/6/X/16V
0.1U/6/X/16V
SC217
0.1U/6/X/16V
SC223
0.1U/6/X/16V
5
B B
A A
C347
0.1U/6/X/16V
C279
0.1U/6/X/16V
C278
0.1U/6/X/16V
SC241
0.01U/6/X/50V
C250
0.1U/6/X/16V
C249
0.1U/6/X/16V
C352
0.01U/6/X/50V
C251
0.1U/6/X/16V
C292
0.1U/6/X/16V
C330
0.1U/6/X/16V
C252
0.1U/6/X/16V
C295
0.1U/6/X/16V
C253
0.1U/6/X/16V
C302
0.1U/6/X/16V
4
C254
0.1U/6/X/16V
C304
0.1U/6/X/16V
C255
0.1U/6/X/16V
C306
0.1U/6/X/16V
12
+
EC18
100U/1210/Y5U/6.3V
12
+
EC16
100U/12/X5R/6.3V/X
12
+
EC19
100U/1210/Y5U/6.3V
P_VTT
12
12
3
C366
22U/12/Y/10V
C358
22U/12/Y/10V
C345
0.1U/6/X/16V
C348
1U/6/X/16V
Title
Size Document Number Rev
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
MCH DECOUPING
GA-9IVDPC
21 70Tuesday, June 14, 2005
1
of
1.1
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