Gigabyte GA-9ITDW-FJ rev.1.3 Schematic
第1頁，共1頁
Technical Information Release Notice
Technical Information Release Notice
Doc Type Schematic Date 2004/11/2 下午 02:56:37
Project Code S93011-0 Customer FJ JPN
Project Name GS-ST591-FJ Revision Old 1.2 New 1.3
Model Name GA-9ITDW IT Doc No DR04B021
P/N 9M9ITDW00-FJ-13B RD Doc No
PCB Rev. 1.3 Check Sum
M/B GA-9ITDW 1.3B
P/N Description
FINISHED GOOD FUJITSU
Description
Remark
Approved By daniel.hou 2004/11/2 下午 08:55:27 Applicant Vincent.Weng
Research
Management
emily.chin
2004/11/3 下午
03:57:27
R
R
IT
IT
Validation Manager Project Manager
h
h
c
c
r
r
ea
ea
s
e
e
s
2
2
00
00
Effected Class
a
a
M
M
/1
/1
4
4
n
n
1/
1/
a
a
g
g
3
3
e
e
R N M
A B C D E F
A B
t
t
n
n
e
e
m
m
2004/11/3http://gwfap/ef2kweb/CHT/Forms/RTC009/RTC009_P.asp
emily.chin
5
4
3
2
1
GA - 9ITDW-FJ REV 1.3
D D
1 TITLE
2 PCB STACK UP
3 SYSTEM BLOCK DIAGRAM
4 GPIO LIST
5 SYSTEM RESET / POWER GOOD DIAGRAM
6 CLOCK BLOCK DIAGRAM
7 SMBUS DIAGRAM
8 POWER DELIVERY DIAGRAM
C C
9-12 NOCONA P0
11-14 NOCONA P1
15 THERMAL SENSORS
16 ITP - EXTENDED DEBUG PORT
17-23 MCH-TUMWATER
24-26 DDRII CHANNEL A
27-29 DDRII CHANNEL B
30 DDRII TERMINATION / DECOUPLING
31-32 CK409B CLOCK GENERATOR
33 DB800 - CLOCK SRC BUFFER
B B
34 X16 PCI EXPRESS SLOT 6
35 PCI EXPRESS SERIES CAPS
36-40 PXH-D/PXH
41-44 U320 SCSI - ADAPTEC AIC7902W
TABLE OF CONTENTS
56 1394a - TSB43AB23
57 SATA / IDE CONNECTOR
58 LPC SUPER I/O - IT8712F
59 FWH
60-61 AUDIO - ALC655 / AUDIO CONNECTOR
62 USB2.0 / USB+RJ-45 CONNECTOR
63 SSI 3.5 POWER / USB+1394 CONNECTOR
64 COM / PS2 / FLOPPY / LPT
65 FRONT PANEL
66 FAN CONTROL
67 VTT / AUX / PCI-X VIO VOLTAGE REGULATORS
68 1.5V / 1.8V / LAN VOLTAGE REGULATOR
69 EVRD 10.1 - PROCESSOR 0 VOLTAGE REGULATORS
70 EVRD 10.1 - PROCESSOR 1 VOLTAGE REGULATORS
71 VID CIRCUITS
72 SMBUS REPEATER / SYSTEM MOUNTING HOLS
73 H/W MONITOR - LM93
74-77 BLANK
78 PCI ROUTING TABLE
79 REVISION HISTORY 0.2
80 REVISION HISTORY 1.0 & 1.1
81 REVISION HISTORY 1.2 & 1.3
45-46 PCI-X 1.0 (100MHz) SLOT 3-4
47 PCI-X 1.0 (133MHz) SLOT 5
48 GbE -Broadcom BCM5751
49 S3/S4 POWER CONTROL & OVP CIRCUIT
50-53 ICH5
54 PCI 32-BIT/33MHz SLOT 1-2
A A
55 GLUE LOGIC (PLD)
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
TITLE / TABLE OF CONTENTS
GA-9ITDW-FJ
1
of
181Wednesday, October 13, 2004
1.3
5
D D
4
3
2
1
PCB STACK UP
SIGNAL
(3.7-mil)
PREPREG
GND
(3.7-mil)
CORE
SIGNAL
(11.10-mil)
PREPREG
POWER
C C
(10-mil)
CORE
POWER
(11.10-mil)
PREPREG
SIGNAL
(3.7-mil)
CORE
GND
(3.7-mil)
PREPREG
SIGNAL
(2.0-mil/1.5oz Cu Plating)
(1.35-mil / 1.0oz Cu)
(1.35-mil / 1.0oz Cu)
(2.7-mil / 2.0oz Cu)
(2.7-mil / 2.0oz Cu)
(1.35-mil / 1.0oz Cu)
(1.35-mil / 1.0oz Cu)
(2.0-mil/1.5oz Cu Plating)
B B
A A
Title
GIGA-BYTE TECHNOLOGY CO., LTD.
PCB STACK UP
Size Document Number Rev
GA-9ITDW-FJ
5
4
3
Date: Sheet
2
of
281Wednesday, October 13, 2004
1
1.3
5
4
3
2
1
GA - 9ITDW SYSTEM BLOCK DIAGRAM
SCSI 68-pin
CONNECTOR
SCSI 68-pin
CONNECTOR
D D
SLOT #5
PCI-X 133MHz
C C
SLOT #4
PCI-X 100MHz
SLOT #3
SUPPORT ZCR
PCI-X 100MHz
SCSI 0
Dual U320
SCSI
(AIC7902W)
PCI-X (100MT/S - 800MB/S)
PCI-X (133MT/S - 1GB/S)
PCI-X (266MT/S - 2GB/S) if PXH-D
SCSI 1
PXH /
PXH-D
PCI EXPRESS X4 (2 GB/S)
PCI EXPRESS X16 ( 8 GB/S)
BCM5721
PCI EXPRESS X16 SLOT #6
RJ-45
or 5751
PCI EXPRESS X1 (0.5 GB/S)
For TPM interface( BCM 5751 only)
LPC
NOCONA /
JAYHAWK
NOCONA /
JAYHAWK
CPU0 CPU1
System Bus(800MT/S - 6.4GB/S)
Tumwater
MCH
HUB INTERFACE 1.5
DDR II (400MT/S - 3.2GB/S)
DDR II (400MT/S - 3.2GB/S)
USB 2.0 (480 Mb/S)
Channel A
DDRII 400 DIMM Module X 3
Channel B
DDRII 400 DIMM Module X 3
ITP
DEBUG PORT
FRONT PANEL
USB 2.0 X 4
REAR PANEL USB
2.0 X 4
EVRD
10.1
CK409B
CLOCK
DB800
SRC buffer
PCI 32-Bit 33MT/S - 133MB/S
PCI 33MHz
SLOT #1
PCI 33MHz
SLOT #2
B B
400 Mb/s
REAR PANEL
1394 X 1
A A
5
IEEE 1394
TSB43AB23
400 Mb/s
FRONT PANEL
1394 X 2
400 Mb/s
SATA 0
SATA 1
SYSTEM BIOS
COM 1
COM 2
4
Intel
FWH
COM 2
KB / MS
150 MB/s
150 MB/s
LPC
Floppy Connector
ICH5 /
ICH5R
IT 8712F
LPC Super I/O
AC LINK
AC-97 2.3 COMPATIBLE
LPT PORT
3
ATA-100
ATA-100
ALC 658
6CH AC97
CODEC
SYS
FAN1
SYS
FAN2
SYS
FAN3
IDE
Connector X2
AUDIO PHONE
JACK
2
CPU0
FAN
CPU1
FAN
LM93
H/W
MONITOR
GIGA-BYTE TECHNOLOGY CO., LTD.
Title
Size Document Number Rev
Date: Sheet
BLOCK DIAGRAM
GA-9ITDW-FJ
1
381Wednesday, October 13, 2004
of
1.3
5
ICH5/R GPIO LIST
ITEM FUNCTION DEFAULT POWER
GPI 0
GPI 1
ICH_SL E E P _BTN# Front Panel sleep button P3V3
GPI [5..2] PCI_PIRQ#H / G / F / E
D D
GPI 6
GPI 7 MCHPME#
GPI 8
GPI 9
MCHGPE# P3V3
WAKE# P3V3_DUAL
CISW_PRESENT#
USB_ICH_OC#5 Not UsedGPI 10 P3V3_DUAL
GPI 11 ICH_SMBALERT#
GPI 12
GPI 13
FP_NMI#
SIO_PME#
GPI [15..14] USB_ICH_OC#7 / 6
TER_SCSIA_EN#
GPO 17
GPO 18
TER_SCSIB_EN#
ICH_GPO18
GPO 19 P3V3SLEEP_S1-5#
CPU0_FORCEPR#GPO 20 P3V3High
C C
GPIO 24
GPIO 25
GPIO 27
GPIO 28
FWH_TBL#GPO 23 P3V3
ICH_PWRLED_G
ICH_PWRLED_O
ICH_MESSAGE
ICH_SCSIDIS#
SKIP_PWD#GPIO 32 P3V3
SATA_LED# P3V3GPIO 33
IDE_PRI_CBLSNS P3V3GPIO 34 Primary IDE cable sense
GPI 40 FREQ_SEL0 P3V3
FREQ_SEL1GPI 41 FSB frequency select 1 P3V3
Low
Secondary IDE cable sense LAN_DISABLE# (OD)P U L L-UPGPIO 10
High
PCI slot interrupts
High
Not Used
High
MCH PME
High
PCI Express Devices Wake Event
High
Chasis Instrusion Switch present detect
High
High
SMBus Alert
High
Front Panel NMI
High
Super I/O PME
High
Not Used
High
SCSI Channel A terminator disable
High
SCSI Channel B terminator disable
High
Not Used
High
Low
F_USB2 S1 ~ S5 wake up enable
FWH write protect
High
High
Front Panel Power-On L ED
LOW
Front Panel Standby LED
High
Front Panel Message LED
High
Onboard SCSI disable
High
Skip Password
High
High
SATA access LED
Low
FSB frequency select 0
High
High
4
DESCRIPTION
P3V3IDE_SEC_CBLSNS
P5V
P3V3
P3V3_DUAL
P3V3_DUAL
P3V3_DUAL
P3V3_DUAL
P3V3_DUAL
P3V3GPO 16
P3V3
P3V3
P3V3GPO 2 1 CPU1_ F O R C E P R # High
P3V3GPO 22(OD) FWH_WP#
P3V3_DUAL
P3V3_DUAL
P3V3_DUAL
P3V3_DUAL
3
5V TOLERANT
GPIO
2
1
IT8712F GPIO LIST
POWER RAILITEM DEFAULT CONDITIONFUNCTION
GPIO 11
GPIO 12
GPIO 13
GPIO 14
GPIO 15
GPIO[16..17]
GPIO 20
GPIO 21
GPIO 22
SCRCLK
SCRIO
SCRFETSCRRST
CIRTX
N.C
SIO_BEEP
N.C
SIO_S1LED#
(OD)PULL-UP
(OD)PULL-UP
(OD)PULL-UP
(OD)PULL-UP
N.C
GPIO 2 5 SIO_SYS_FAN_TACH4 (OD)PULL - UP MAIN(5V)
GPIO [27..23]
GPIO [35..30]
GPIO 36
GPIO 37
GPIO 40
GPIO 41
GPIO 42
GPIO 43
GPIO 44
GPIO 45
GPIO 46
GPIO 47
N.C
N.C
SIO_SYS_FAN_PWM3
SIO_SYS_FAN_TACH3
S5_FUSB_DIS#
S5_RUSB_DIS#
PS_ON#
SIO_PWRBTN#
SIO_PWRON#
SIO_PSIN
IRRX
IRTX
GPIO 50
GPIO 51
GPIO 52
GPIO 53
GPIO 54 RESUME(3V3)
GPIO 55
SIO_SYS_FAN_PWM2
SIO_SYS_FAN_TACH2
SIO_RING#
SIO_PME#
CIRRX
N.C
N.C
(OD)PULL-UP
(OD)PULL-UP
(OD)PULL-UP
(OD)PULL-UP
(OD)ICH5 INTERNAL PULL-UP
(OD)NO PULL-UP, CONTROL BY SLP_S#3
N.C
N.C
(OD)PULL-UP
(OD)PULL-UP
(OD)PULL-UP
N.C
RESUME(3V3)
MAIN(5V)
MAIN(5V)
MAIN(5V)
MAIN(5V)
MAIN(3V3)
MAIN(3V3)(OD)PULL-UP
MAIN(3V3)
MAIN(3V3)
RESUME(3V3)
RESUME(3V3)
RESUME(5V)
RESUME(5V)
RESUME(3V3)
RESUME(3V3)
RESUME
MAIN(5V)
MAIN(3V3)
MAIN(3V3)
RESUME(5V)
RESUME
P3V3GPO 48 TP_OEM_GPIO1 NOT USED,TEST POINT
GPO 4 9 CPU_PWR _GD P_VTT
High
CPU Power Good
IT8712F GPIOs HAVE INTEGRATED OPEN DRAIN INPUT/OUTPUT BUFFER
B B
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
POWER TABLE / GPIO LIST
GA-9ITDW-FJ
1
of
481Wednesday, October 13, 2004
1.3
5
4
3
2
1
(P5V)
PS_PWR_GD
D D
VR 1.5V soft-start control signal
(P3V3)
PS_PWR_GD#
VR_P1V5PSU
PWRGD_1_5V
SYS_PWR_GD#
VR_P1V8
CPLD
CPU_VRD_PWR_GD
delay 110 ms
(P3V3)
PWRGD_1_8V
CPLD
P3V3_DUAL/P5VDUAL control signal
SYS_PWR_GD_3_3V
CPLD
delay 1 ms
(P3V3) (P3V3)
VTTEN
C C
CPLD
(P3V3)
VTT_ENABLE
VR_VTT
(P3V3)
VTT_PWRGD SB_VTT_PWRGD
CPLD
delay 1 ms
(P3V3)
CK409B_PWR_GD#
CK409B will latch FS[1..0] input after
CK409B_PWR_GD# signal asserted.
CK 409B
CPU
(P3V3)
0/X
(P_VTT)
VID_PWRGD
(P_VTT)
VID[5..0]
(P_VTT)
CPU_PWR_GD
VOLTAGE
TRANSLATOR
(P3V3 to P_VTT)
VR_SYS_ENABLE
VR_CPU
0
CPU_VRD_PWR_GD
ITP
B B
CPU_VRD_PWR_GD
0
SYS_PWR_GD_3_3V
0/X
A A
5
(P3V3)
CK409B_PWRDWN#
4
VRMPWRGD
ICH5
PWROK
CK 409B
DB800
Title
Size Document Number Rev
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
SYSTEM PWRGD DIAGRAM
GA-9ITDW-FJ
1
of
581Wednesday, October 13, 2004
1.3
5
4
3
2
1
14.318MHz
CRYSTAL
P0_BCLK/P0_BCLK# (200MHZ)
CPU0
D D
3V66_0
3V66_3
3V66_4
P1_BCLK/P1_BCLK# (200MHZ)
CPU1
ITP_BCLK/ITP_BCLK# (200MHZ)
CPU3
MCH_BCLK/MCH_BCLK# (200MHZ)
CPU2
MCH_66MHZ_CLK
3V66_1
2
2
2
2
CK 409B
CLOCK
SYNTHESIZER
ICH5_HI66MHZ_CLK
C C
B B
PCIF2
PCI6
PCI 5
A A
3V66_2
USB_48
PCIF0
REF0
PCI 3
SRC
DOT_48
PCI_F1
PCI 0
PCI 1
PCI 2
PCI 4
REF 1
ICH5_USB_48MHZ_CLK
ICH5_33MHZ_CLK
PLD_33MHZ_CLK
DB800_SRC_100MHZ_CLK_P/DB800_SRC_100MHZ_CLK_N
SIO_48MHZ_CLK
SIO_33MHZ_CLK
PCI_SLOT1_33MHZ_CLK
PCI_SLOT2_33MHZ_CLK
FWH_33MHZ_CLK
1394_33MHZ_CLK
AUDIO_14MHZ_CLK
32.768KHZ
CRYSTAL
ICH5
SUS_CLK
SIO
PCI 33MHz SLOT #1
PCI 33MHz SLOT #2
FWH
24.576MHZ
CRYSTAL
TSB43AB23 IEEE-1394
24.576MHZ
CRYSTAL
ALC655 AUDIO CODEC
CLOCK BLOCK DIAGRAM
CPU0
CUP1
ITP PORT
TUMWATER
2
ICH_SRC_100MHZ_CLK_P/ICH_SRC_100MHZ_CLK_N
2
SUS_CLKICH5_14MHZ_CLK
CPLD
2
PXH_PAPCLK_FB PXH_PBPCLK_FB
DDRA_CMDCLK0_P/DDRA_CMDCLK0_N
DDRA_CMDCLK1_P/DDRA_CMDCLK1_N
DDRA_CMDCLK2_P/DDRA_CMDCLK2_N
DDRB_CMDCLK0_P/DDRB_CMDCLK0_N
DDRB_CMDCLK1_P/DDRB_CMDCLK1_N
DDRB_CMDCLK2_P/DDRB_CMDCLK2_N
MCH_SRC_100MHZ_CLK_P/MCH_SRC_100MHZ_CLK_N
DIFF3
DB800 (SRC -DIFFERENTIAL BUFFER)
SRC
PAPCLKI
PAPCLK0(6)
PXH/PXH-D
PAPCLK0(2)
PXH_PAPCLKO2
PXH_PAPCLKO1
PCI-X 100MHz SLOT #4
PCI-X 100MHz SLOT #3V(ZCR) PCI-X 133/266MHz SLOT #5
U320 SCSI
2
2
2
2
DDR II DIMM #A1
2
DDR II DIMM #B1
2
LAN_SRC_100MHZ_CLK_P/LAN_SRC_100MHZ_CLK_N
DIFF6
DIFF2
PXH_SRC_100MHZ_CLK_P/PXH_SRC_100MHZ_CLK_N
PXH_PAPCLKO0
80MHZ
OSC
DIFF7
DIFF0DIFF1 DIFF4 DIFF5
PBPCLKI
PBPCLK0(6)
PBPCLK0(0)PAPCLK0(1) PAPCLK0(0)
DDR II DIMM #A2
2
PXH_PBPCLKO0
DDR II DIMM #B2
DDR II DIMM #B3
DDR II DIMM #A3
25MHZ
CRYSTAL
BCM5751
EXP_SLOT6_100MHZ_CLK_P/EXP_SLOT6_100MHZ_CLK_N
2
PCI EXPRESS X16 SLOT #6
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
CLOCK BLOCK DIAGRAM
GA-9ITDW-FJ
1
of
681Wednesday, October 13, 2004
1.3
5
4
3
2
1
GA-9ITDW SMBUS BLOCK DIAGRAM
0/X
0/X
0/X
0/X
0/X
P3V_STBY
P3V_STBY
P3V_STBY
P3V_STBY
P3V_STBY
P3V_STBY
5.1K
5.1K
5.1K
5.1K
5.1K
PCI-EXPRESS X16 Slot
Slot # 1
PCI-X 133MHz Slot
Slot # 2
PCI 33MHz Slot
Slot # 3
PCI 33MHz Slot
Slot # 4
PCI-X 100MHz Slot
Slot # 5
DYNAMIC BUS ADDRESSING FOR I/O SLOTS
P3V_STBY
P3V3_DUAL
D D
1K/X 8.2K
0
LM75
Addr 0X90
CPU0 socket
LM75_SMBALERT#
LM75
Addr 0X92
P3V_STBY
8.2K
ICH_SMB
NIC_SMBALERT# LM93_SMBALERT#
NORTHWAY
82570EI
Addr TBD
0
P3V_STBY
NIC_SMB
8.2K/X
0
DDRII slots
LM75
C C
Addr 0X94
PCI slots
LM75
P3V3_DUAL
1K/X
LM75_SMB
0
ICH5/R
SLAVE ADDR 0X44
( SMBUS DEFAULT )
SLAVE ADDR 0X80
( SMLINK )
LM93
Addr 0X5C
P3V_STBY
8.2K/X
0
P3V_STBY
10K/X
Addr 0X96
SCSI controller
P3V3
0/X
0
0/X
PCI_SMB
P3V3
DIMM A1
MCH TUMWATER
B B
Addr 0X60
5.1K
PCA9515PCA9515
DIMM_SMB
5.1K
Addr 0XA2
DIMM A2
Addr 0XA4
PXH/PXH-D
Addr 0XC0
MCH_SMB
0/X
DIMM A3
Addr 0XA6
5.1K
0/X
PCI-X 100MHz Slot
Slot # 6
DIMM B1
Addr 0XAA
DIMM B2
Addr 0XAC
DIMM B3
Addr 0XAE
2
DDR II CH B
Title
Size Document Number Rev
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
SMBUS DIAGRAM
GA-9ITDW-FJ
1
of
781Wednesday, October 13, 2004
1.3
CK409B
DDR II CH A
Addr 0XD2
A A
DB800
Addr 0XDC
0/X
0/X
ITP PORT
MASTER ONLY
5
1394_SMB
4
P3V3
2.7K
IEEE1394 TI
TSB43AB23
DYNAMIC BUS ADDRESSING
3
5
ATX CONN 2X2
4
3
2
1
D D
P12V_CPU_0
EVRD 10.1 PWM
4 PHASE
ISL6556B
+
HIP6601B
MOSFET DRIVER
X4
ATX CONN 2X4
P_VCCP0
105A Typical
120A Maximun
CPU0
0.8375V ~ 1.6V/ CORE
P_VTT
P_VTT
Voltage
Regulator
P12V_CPU_0
4 PHASE
P12V_CPU_1
C C
ATX CONN 2X12
EVRD 10.1 PWM
2 PHASE
ISL6556B
+
HIP6601B
MOSFET DRIVER
HIP6302 HIP6602
P12V
P5V
B B
1.8V PWM MOSFET DRIVER
ISL6525
1.5V PWM
APL1084
APL1084
P3V3
APL1084
P5V_STBY
A A
P5V
P-MOSFET +
N-MOSFET
+
P3V3_DUAL
P2V5_SCSIA
P2V5_SCSIB
P1V8_SCSI
P5V_DUAL P3V3_DUAL
X4
APL1084
P_VCCP1
105A Typical
120A Maximun
P1V8
40A Maximun
APL1084
P1V5
18A Maximun
U320 SCSI
3.3V : 0.36A Typical
2.5V_B : 0.35A Typical
2.5V_A : 0.35A Typical
1.8V : 0.78A Typical
P1V8_STBY
CPU1
0.8375V ~ 1.6V/ CORE
S3/S4
Control
Circuit
PXH
1.5V (Core+PCI-X
MODE2+PCI EXPRESS):
3.1A Max
3.3V (PCI/PCI-X MODE1):
1.8A Max
P3V3
P1V8_AUX
NPN
BJT
P3V3
P1V2_AUX
DDRII
400
MODULE
1.8V : 27.5A Max
TUMWATER
1.5V (Core+HI+PCI
EXPRESS): 5.11A Max
1.8V (DDRII 400): 6.7A Max
1.25V (VTT, FSB): TBD
ICH5/R
1.5V : 1A Max
1.2V (VTT) : 2.5mA Max
3.3V : 0.48A Max
3.3V STBY : 0.58A Max
BCM5751
3.3V : 230mA Typ
2.5V : 210mA Typ
1.2V : 570mA Typ
3.5A Typical
6A Maximun
P0V9_DDR
1.98A Typical
2.1A Maximun
P2V5_AUX
RT9173A
DDR2
TERMINATOR
N12V
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
PWR DELIVERY
GA-9ITDW-FJ
1
of
881Wednesday, October 13, 2004
1.3
5
4
3
2
1
PROCESSOR 0
AB10
AA10
AA11
AB13
AB12
AC14
AA14
AA13
AD10
AC11
AE10
AC12
AD11
AD14
AD13
AB15
AD18
AE13
AC17
AA16
AB16
AB17
AD19
AD21
AE20
AE22
AC21
AC20
AA18
AC23
AE23
AD24
AC24
AE25
AD25
AC26
AE26
AA19
AB19
AB22
AB20
AA21
AA22
AB23
AB25
AB26
AA24
AD27
AA25
AA27
AB6
AA8
AC5
AC6
AE7
AD7
AC8
AC9
AD8
AE9
Y23
Y24
Y26
Y9
U1B
D63#
NOCONA 800
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
D39#
D38#
D37#
D36#
D35#
D34#
D33#
D32#
D31#
D30#
D29#
D28#
D27#
D26#
D25#
D24#
D23#
D22#
D21#
D20#
D19#
D18#
D17#
D16#
D15#
D14#
D13#
D12#
D11#
D10#
D9#
D8#
D7#
D6#
D5#
D4#
D3#
D2#
D1#
D0#
NOCONA 667
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
DBI3#
DBI2#
DBI1#
DBI0#
DP3#
DP2#
DP1#
DP0#
AP1#
AP0#
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
SB_HA#35
C8
SB_HA#34
C9
SB_HA#33
A7
SB_HA#32
A6
SB_HA#31
B7
SB_HA#30
C11
SB_HA#29
D12
SB_HA#28
E13
SB_HA#27
B8
SB_HA#26
A9
SB_HA#25
D13
SB_HA#24
E14
SB_HA#23
C12
SB_HA#22
B11
SB_HA#21
B10
SB_HA#20
A10
SB_HA#19
F15
SB_HA#18
D15
SB_HA#17
D16
SB_HA#16
C14
SB_HA#15
C15
SB_HA#14
A12
SB_HA#13
B13
SB_HA#12
B14
SB_HA#11
B16
SB_HA#10
A13
SB_HA#9
D17
A9#
A8#
A7#
A6#
A5#
A4#
A3#
C17
A19
C18
B18
A20
A22
B22
C20
C21
B21
B19
AB9
AE12
AD22
AC27
AE17
AC15
AE19
AC18
D9
E10
F14
F17
Y11
Y14
Y17
Y20
Y12
Y15
Y18
Y21
SB_HA#8
SB_HA#7
SB_HA#6
SB_HA#5
SB_HA#4
SB_HA#3
SB_REQ#4
SB_REQ#3
SB_REQ#2
SB_REQ#1
SB_REQ#0
SB_DBI#3
SB_DBI#2
SB_DBI#1
SB_DBI#0
SB_DP#3
SB_DP#2
SB_DP#1
SB_DP#0
SB_AP#1
SB_AP#0
SB_ADSTB#1
SB_ADSTB#0
SB_DSTBP#3
SB_DSTBP#2
SB_DSTBP#1
SB_DSTBP#0
SB_DSTBN#3
SB_DSTBN#2
SB_DSTBN#1
SB_DSTBN#0
SB_BPRI#13,19
SB_CPU0_BREQ#2311
SB_BREQ#111,12,13
SB_BREQ#011,12,13
D D
C C
B B
SB_RS#[0..2]13,19
VID_CPU0_R[5..0]71
P_VCCP_A_CPU0
AGND_CPU0
P_VTT
754mV
P_VTT
SB_CPURST#11,13,16,19
SB_RSP#13,19
SB_CPU_A20M#11,13,51
SB_CPU_IGNNE#11,13,51
SB_CPU_INIT#11,13,51,59
SB_CPU_NMI11,12,13
SB_CPU_INTR11,13,51
CPU_PWR_GD11,13,16,51
SB_CPU0_SMI#11,12
SB_CPU_SLP#11,13,51
SB_CPU_STPCLK#11,13
P0_BCLK#31
P0_BCLK31
ITP_TCK013,16
ITP_TDI_MAIN16
ITP_TMS_MAIN13,16
ITP_TRST#13,16,21
SB_CPU0_BSEL111,12
SB_CPU0_BSEL011,12
VR0_VCCSENSE69
VTTEN11,13,55
VR0_VSSSENSE69
PLACE COMPONENTS: GROUP ASSOCIATE COMPONENTS
TOGETHER AND AS PHYISCALLY CLOSE TO ASSOCIATED PIN AS
POSSIBBLE WITH THE 220PF CAP CL OSEST TO THE PIN
MIN TRACE WIDTH >=10 - 12 MILS
SR164
49.9/1%
VREF_P_VTT_CPU0_0_R
SC767
SR165
1U/6/X/10V
90.9/1%
SB_BPRI#
SB_CPU0_BREQ#23
SB_BREQ#1
SB_BREQ#0
SB_CPURST#
SB_RS#2
SB_RS#1
SB_RS#0
SB_RSP#
SB_CPU_A20M#
SB_CPU_IGNNE#
SB_CPU_INIT#
SB_CPU_NMI
SB_CPU_INTR
CPU_PWR_GD
SB_CPU0_SMI#
SB_CPU_SLP#
SB_CPU_STPCLK#
P0_BCLK#
P0_BCLK
ITP_TCK0
ITP_TDI_MAIN
ITP_TMS_MAIN
ITP_TRST#
SB_CPU0_BSEL1
SB_CPU0_BSEL0
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
P0_RSVD13
P0_RSVD12
P0_RSVD11
P0_RSVD10
P0_RSVD9
P0_RSVD8
P0_RSVD7
P0_RSVD6
P0_RSVD5
P0_RSVD4
P0_RSVD3
P0_RSVD2
P0_RSVD1
P0_RSVD0
VID_CPU0_R5
VID_CPU0_R4
VID_CPU0_R3
VID_CPU0_R2
VID_CPU0_R1
VID_CPU0_R0
VR0_VCCSENSE
VTTEN
VR0_VSSSENSE
PLACE 0 OHM RESISTOR ON BACK SIDE
SR160
0
VREF_P_VTT_CPU0_0
SC763
220P/6/X/50V
U1A
D23
BPRI#
D10
E11
F12
D20
F21
D22
E21
F27
C26
G23
B24
AB7
C27
AE6
E24
C24
A25
F24
AB3
AA3
AE29
AE28
AE30
AD29
AD28
AC29
AB29
AB28
AA29
AA28
AE15
AC1
AE16
AD4
B27
AB4
AA5
D26 C1
NOCONA 800
BR3#
BR2#
BR1#
BR0#
Y8
RESET#
RS2#
RS1#
RS0#
C6
RSP#
A20M#
IGNNE#
D6
INIT#
LINT1_NMI
LINT0_INTR
PWRGOOD
SMI#
SLP#
D4
STPCLK#
W5
BCLK1
Y4
BCLK0
TCK
TDI
TMS
TRST#
BSEL1
BSEL0
RESERVED1
RESERVED0
NC
Y3
RSVD15
RSVD14
RSVD13
RSVD12
RSVD10
RSVD9
RSVD8
RSVD7
RSVD3
RSVD2
RSVD1
A1
VID5
B3
VID4
C3
VID3
D3
VID2
E3
VID1
F3
VID0
VCCIOPLL
VCC_SENSE
E1
VTTEN
VCCA
VSSA
VSSSENSE OPTIMIZED_COMPAT#
NOCONA 667
SC764
220P/6/X/50V
ADS#
BINIT#
BNR#
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
TRDY#
LOCK#
MCERR#
IERR#
FERR#
THERMTRIP#
PROCHOT#
TDO
GTLREF3
GTLREF2
GTLREF1
GTLREF0
ODTEN
SKTOCC#
RSVD11/COMP3
RSVD5/COMP2
COMP1
COMP0
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
SMB_PRT
VCCPLL
THERMDC
THERMDA
BOOT_SELECT
RSVD
VIDPWRGD
TEST_BUS
FORCEPR#
SLEW_CTRL
P_VTT
PLACE COMP ONENTS: ROUTE TRACE FROM L1 TO P IN AD4 , ROUTE
TRACE FROM L2 TO PIN AB4 .PLACE CAP BETWEEN AB4 AND
AGND_CPU0 . MI N TR AC E WI DTH >=10 - 12 MILS
SB_ADS#
D19
SB_BINIT#
F11
SB_BNR#
F20
CPU0_BPM#5
E4
CPU0_BPM#4
E8
CPU0_BPM#3
F5
CPU0_BPM#2
E7
CPU0_BPM#1
F8
CPU0_BPM#0
F6
SB_DBSY#
F18
SB_DEFER#
C23
SB_DRDY#
E18
SB_HIT#
E22
SB_HITM#
A23
SB_TRDY#
E19
SB_LOCK#
A17
SB_MCERR#
D7
SB_CPU0_IERR#
E5
SB_CPU_FERR#
E27
SB_CPU_THERMTRIP#
F26
SB_CPU0_PROCHOT#
B25
ITP_TDO_P0
E25
F9
F23
W9
W23
PU_ODTEN_CPU0
B5
SMC_CPU0_SKTOCC#
A3
PU_COMP3_CPU0
D25
PU_COMP2_CPU0
AC28
PD_COMP1_CPU0
E16
PD_COMP0_CPU0
AD16
PU_CPU0_8
Y29
PU_CPU0_0
A26
PU_CPU0_5
AE5
PU_CPU0_6
AD5
PU_CPU0_1
AA7
PU_CPU0_7
Y6
PU_CPU0_3
W8
PU_CPU0_2
W7
PU_CPU0_4
W6
P0_RSVD16
AE4
AD1
CPU0_THERMDC
Y28
CPU0_THERMDA
Y27
PU_BOOT_SELECT_CPU0
G7
P0_RSVD15
W3
VID_PWRGD
B1
SB_CPU0_CPU1_TESTBUS
A16
SB_CPU0_FORCEPR#
A15
SLEW_CTRL_CPU0
AC30
CPU0_OPTIM_COMPAT_CTRL
SB_ADS# 13,19
SB_BINIT# 11,13,19
SB_BNR# 11,13,19
SB_DBSY# 13,19
SB_DEFER# 13,19
SB_DRDY# 13,19
SB_HIT# 11,13,19
SB_HITM# 11,13,19
SB_TRDY# 13,19
SB_LOCK# 13,19
SB_MCERR# 11,13,19
SB_CPU0_IERR# 11,12
SB_CPU_FERR# 11,13,51,53
SB_CPU_THERMTRIP# 11,12,13,51,53
SB_CPU0_PROCHOT# 11,12
ITP_TDO_P0 16
PU_ODTEN_CPU0 11
SMC_CPU0_SKTOCC# 11,15
PU_COMP3_CPU0 11
PU_COMP2_CPU0 11
PD_COMP1_CPU0 11
PD_COMP0_CPU0 11
PU_CPU0_8 11
PU_CPU0_0 11
PU_CPU0_5 11
PU_CPU0_6 11
PU_CPU0_1 11
PU_CPU0_7 11
PU_CPU0_3 11
PU_CPU0_2 11
PU_CPU0_4 11
TP15
CPU0_THERMDC 15
CPU0_THERMDA 15
PU_BOOT_SELECT_CPU0 11
TP16
VID_PWRGD 13,55
SB_CPU0_CPU1_TESTBUS 11,13
SB_CPU0_FORCEPR# 11,12
CPU0_SLEW_CTRL 11
CPU0_OPTIM_COMPAT_CTRL 11
WW35 eMOW: Icc of VCCIOPLL pins : 100 mA
WW35 eMOW: Icc for VCCA pins : 120mA
L1
10UH/8
L2
10UH/8
P_VCCP_A_CPU0
12
C1
22U/1210/X/6.3V
AGND_CPU0
CPU0_BPM#[5..0] 16
SB_D#[63..0]13,19
VREF_P_VTT_CPU0_3
VREF_P_VTT_CPU0_0
PU_VCCPLL_CPU0
SB_D#63
SB_D#62
SB_D#61
SB_D#60
SB_D#59
SB_D#58
SB_D#57
SB_D#56
SB_D#55
SB_D#54
SB_D#53
SB_D#52
SB_D#51
SB_D#50
SB_D#49
SB_D#48
SB_D#47
SB_D#46
SB_D#45
SB_D#44
SB_D#43
SB_D#42
SB_D#41
SB_D#40
SB_D#39
SB_D#38
SB_D#37
SB_D#36
SB_D#35
SB_D#34
SB_D#33
SB_D#32
SB_D#31
SB_D#30
SB_D#29
SB_D#28
SB_D#27
SB_D#26
SB_D#25
SB_D#24
SB_D#23
SB_D#22
SB_D#21
SB_D#20
SB_D#19
SB_D#18
SB_D#17
SB_D#16
SB_D#15
SB_D#14
SB_D#13
SB_D#12
SB_D#11
SB_D#10
SB_D#9
SB_D#8
SB_D#7
SB_D#6
SB_D#5
SB_D#4
SB_D#3
SB_D#2
SB_D#1
SB_D#0
COMP3 =SB_CPU0_ADDR_ERC
COMP2 =SB_CPU0_DATA_ERC
PU_CPU0_8=SB_CPU0_EDRDY
PU_CPU0_0=SB_CPU0_SNPD#
SB_HA#[35..3] 13,19
SB_REQ#[4..0] 13,19
SB_DBI#[3..0] 13,19
SB_DP#[3..0] 13,19
SB_AP#[1..0] 13,19
SB_ADSTB#[1..0] 13,19
SB_DSTBP#[3..0] 13,19
SB_DSTBN#[3..0] 13,19
C1105
P_VTT
12
SC192
22U/1206/X/6.3V
SC2
1U/6/X/10V
2
C1103
0.1U/6/X/16V
Title
Size Document Number Rev
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
P0 SYSTEM BUS INTERFACE
GA-9ITDW-FJ
1
1.3
of
981Wednesday, October 13, 2004
SR166
A A
754mV
49.9/1%
SR167
SC768
90.9/1%
1U/6/X/10V
R3, R7: change from 84.5 to 90.9
ohm/ 1% (2004 WW12 eMOW)
PLACE 0 OHM RESISTOR ON BACK SIDE
SR161
0
5
SC766
220P/6/X/50V
VREF_P_VTT_CPU0_3VREF_P_VTT_CPU0_3_R
SC765
220P/6/X/50V
P1V5
R6
0/X
PLACE COMPONENTS: GROUP ASSOCIATE COMPONENTS
TOGETHER AND AS PHYISCALLY CLOSE TO ASSOCIATED PIN AS
POSSIBBLE M IN TRACE W IDTH >=10 - 12 MILS
4
WW35 eMOW: Icc for VCCPLL pin is 220 mA
12
TC1
+
470U/4V/7343/X
12
C4
4.7U/1206/X/10V/X
PU_VCCPLL_CPU0
C5
0.1U/6/X/16V/X
3
C6
0.1U/6/X/16V/X
12
22U/1206/X/6.3V
5
4
3
2
1
U1C
L31
GND
H30
H28
H26
H24
G31
G29
G27
G25
F30
F28
F25
F19
F13
E31
E29
E23
E17
E15
D30
D28
D27
D21
D11
C31
C29
C25
C19
C13
B30
B28
B23
B17
B15
A31
A29
A27
A21
A11
L29
L27
L25
L23
L9
L7
L5
L3
L1
K30
K28
K26
K24
K8
K6
K4
K2
J31
J29
J27
J25
J23
J9
J7
J5
J3
J1
H8
H6
H4
H2
G9
G5
G3
G1
F7
F2
E9
D5
D2
C7
B9
B2
A5
D D
C C
B B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NOCONA 800
NOCONA 667
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AA30
AA23
AA17
AA15
AA9
AA2
Y31
Y25
Y19
Y13
Y7
Y5
Y1
W30
W28
W26
W24
W4
W2
V31
V29
V27
V25
V23
V9
V7
V5
V3
V1
U30
U28
U26
U24
U8
U6
U4
U2
T31
T29
T27
T25
T23
T9
T7
T5
T3
T1
R30
R28
R26
R24
R8
R6
R4
R2
P31
P29
P27
P25
P23
P9
P7
P5
P3
P1
N30
N28
N26
N24
N8
N6
N4
N2
M2
M4
M6
M8
M24
M26
M28
M30
P_VCCP0 P_VCCP0
H31
H29
H27
H25
H23
G30
G28
G26
G24
F31
F29
F22
F16
E30
E28
E26
E20
D31
D29
D24
D18
D14
C30
C28
C22
C16
B31
B29
B26
B20
A30
A28
A24
A18
A14
U1D
L30
L26
L24
L8
L6
L4
L2
K31
K29
K27
K25
K23
K9
K7
K5
K3
K1
J30
J28
J26
J24
J8
J6
J4
J2
H9
H7
H5
H3
H1
G8
G6
G4
G2
F4
F1
E6
E2
D8
D1
C4
C2
B6
A8
A2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NOCONA 800
NOCONA 667
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
L28
AA31
AA26
AA20
AA6
AA4
AA1
Y30
Y22
Y16
Y2
W31
W29
W27
W25
W1
V30
V28
V26
V24
V8
V6
V4
V2
U31
U29
U27
U25
U23
U9
U7
U5
U3
U1
T30
T28
T26
T24
T8
T6
T4
T2
R31
R29
R27
R25
R23
R9
R7
R5
R3
R1
P30
P28
P26
P24
P8
P6
P4
P2
N31
N29
N27
N25
N23
N9
N7
N5
N3
N1
M31
M29
M27
M25
M23
M9
M7
M5
M3
M1
PLACE IN ACCESSIBLE LOCATION
SECONDARY SIDE IS
PREFERABLE
P_VTT
SR1
SR2
0
0
CPU0_TEST0
CPU0_TEST1
P_VCCP0
P_VTT
U1E
B4
C5
A4
NOCONA 800
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
CPU0_TEST0
NOCONA 667
AD12
AC10
AA12
Y10
F10
E12
C10
B12
AE24
AE18
AE14
AE8
AE3
AD30
AD26
AD20
AD6
AD2
AC31
AC22
AC16
AC4
AC3
AB30
AB24
AB18
AB14
AB8
AB2
PIN SIGNAL C-SPEC SIGNAL
C5B4CPU0_TEST1
VCCVIDPRG
VCCFUSEPRG
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AE2
AD3
AE27
AE21
AE11
AD31
AD23
AD17
AD15
AD9
AC25
AC19
AC13
AC7
AC2
AB31
AB27
AB21
AB11
AB5
AB1
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
P0 POWER/GROUND
GA-9ITDW-FJ
1
of
10 81Wednesday, October 13, 2004
1.3
5
4
3
2
1
P_VTT
ROUTE PD_COMP0_CPU0,PD_COMP1_CPU0 AS SHORT AS POSSIBLE, 10-mil WIDE
R10 220
R13 220
D D
C C
B B
A A
SR3 220
R18 220
R20 220
SR5 220
R25 220
R27 220
R30 51/X
SR6 51
R34 51
R36 51
R39 51
SR7 51/X
SR8 51/X
SR10 51
SR11 51
SR12 51
R55 510
R59 510
R62 100/1%
R67 100/1%
P3V3
R74 4.7K
P_VTT
SR13 39
SR14 39
SR15 39
SR16 39
SR17 39
SB_CPU_IGNNE#
SB_CPU_INIT#
SB_CPU_INTR
SB_CPU_SLP#
SB_CPU_STPCLK#
SB_CPU_NMI
SB_CPU0_SMI#
SB_CPU0_FORCEPR#
SB_CPU0_IERR#
SB_CPU0_PROCHOT#
SB_CPU_THERMTRIP#
SB_CPU_FERR#
PU_BOOT_SELECT_CPU0
CPU0_OPTIM_COMPAT_CTRL
SR9 51/X
SB_BREQ#0
SB_BREQ#1
SB_CPU0_BREQ#23
SB_CPU0_BSEL1
SB_CPU0_BSEL0
PU_COMP2_CPU0
PU_COMP3_CPU0
VTTEN
SC6
SB_BINIT#_R
SB_BNR#_R
SB_HIT#_R
SB_HITM#_R SB_HITM#
SB_MCERR#_R
5
47P/6/N/50V
SC7
47P/6/N/50V
SC9
47P/6/N/50V
SC10
47P/6/N/50V
SC11
47P/6/N/50V
SB_BINIT#
SB_BNR#
SB_HIT#
SB_MCERR#
SB_CPU_A20M# 9,13,51
SB_CPU_IGNNE# 9,13,51
SB_CPU_INIT# 9,13,51,59
SB_CPU_INTR 9,13,51
SB_CPU_SLP# 9,13,51
SB_CPU_STPCLK# 9,13
SB_CPU_NMI 9,12,13
SB_CPU0_SMI# 9,12
SB_CPU0_FORCEPR# 9,12
SB_CPU0_IERR# 9,12
SB_CPU0_PROCHOT# 9,12
SB_CPU_THERMTRIP# 9,12,13,51,53
SB_CPU_FERR# 9,13,51,53
PU_BOOT_SELECT_CPU0 9
CPU0_OPTIM_COMPAT_CTRL 9
SB_BREQ#0 9,12,13
SB_BREQ#1 9,12,13
SB_CPU0_BREQ#23 9
SB_CPU0_BSEL1 9,12
SB_CPU0_BSEL0 9,12
PU_COMP2_CPU0 9
PU_COMP3_CPU0 9
VTTEN 9,13,55
SB_BINIT# 9,13,19
SB_BNR# 9,13,19
SB_HIT# 9,13,19
SB_HITM# 9,13,19
SB_MCERR# 9,13,19
4
R11 49.9/1%
SR22 49.9/1%
P_VTT
SR4 51
P_VTT
R29 300
R37 51
R41 51/X
P3V3_DUAL
R49 4.7K
P_VTT
P_VTT
R54 51/X
RN81
1 2
3 4
5 6
7 8
51/8P4R
RN82
1 2
3 4
5 6
7 8
51/8P4R
R72 51/X
Place near CPU1(Middle Agent)
R77 51
PD_COMP1_CPU0SB_CPU_A20M#
PD_COMP0_CPU0
PU_ODTEN_CPU0
CPU_PWR_GD
SC5
100P/6/N/50V/X
PLACE CLOSE TO CPU0
SB_CPURST#
CPU0_SLEW_CTRL
R44 0/X
SMC_CPU0_SKTOCC#
PU_CPU0_8
PU_CPU0_7
PU_CPU0_6
PU_CPU0_5
PU_CPU0_4
PU_CPU0_3
PU_CPU0_2
PU_CPU0_1
PU_CPU0_0
SB_CPU0_CPU1_TESTBUS
R80 100/X
R84 0
PD_COMP1_CPU0 9
PD_COMP0_CPU0 9
PU_ODTEN_CPU0 9
CPU_PWR_GD 9,13,16,51
SB_CPURST# 9,13,16,19
CPU0_SLEW_CTRL 9
SMC_CPU0_SKTOCC# 9,15
PU_CPU0_8 9
PU_CPU0_7 9
PU_CPU0_6 9
PU_CPU0_5 9
PU_CPU0_4 9
PU_CPU0_3 9
PU_CPU0_2 9
PU_CPU0_1 9
PU_CPU0_0 9
SB_CPU0_CPU1_TESTBUS 9,13
ICH_CPU_STPCLK# 51SB_CPU_STPCLK#9,13
3
P_VTT
R12 220
R15 51
R17 51
R19 51
R21 51/X
R24 51/X
R28 51
R31 51/X
R35 510
R38 510
R40 100/1%
R43 100/1%
ROUTE PD_COMP0_CPU1,PD_COMP1_CPU1 AS SHORT AS POSSIBLE, 10-mil WIDE
R46 49.9/1%
R48 49.9/1%
R51 51
P_VTT
R57 51
RN83
1 2
3 4
5 6
7 8
51/8P4R
RN84
1 2
3 4
5 6
7 8
51/8P4R
R76 51
P3V3_DUAL
R79 4.7K
PLACE CLOSE TO CPU1 PIN
2
SB_CPU1_SMI#
SB_CPU1_FORCEPR#
SB_CPU1_IERR#
SB_CPU1_PROCHOT#
PU_BOOT_SELECT_CPU1
CPU1_OPTIM_COMPAT_CTRL
R26 51/X
SB_CPU1_BREQ#23
CPU1_SLEW_CTRL
R33 0
SB_CPU1_BSEL1
SB_CPU1_BSEL0
PU_COMP3_CPU1
PU_COMP2_CPU1
PD_COMP1_CPU1
PD_COMP0_CPU1
PD_ODTEN_CPU1
PU_CPU1_8
PU_CPU1_7
PU_CPU1_6
PU_CPU1_5
PU_CPU1_4
PU_CPU1_3
PU_CPU1_2
PU_CPU1_1
PU_CPU1_0
SMC_CPU1_SKTOCC#
SC8
CPU_PWR_GD
100P/6/N/50V/X
Title
Size Document Number Rev
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
NOCONA P0 TERMINATION
SB_CPU1_SMI# 12,13
SB_CPU1_FORCEPR# 12,13
SB_CPU1_IERR# 12,13
SB_CPU1_PROCHOT# 12,13
PU_BOOT_SELECT_CPU1 13
CPU1_OPTIM_COMPAT_CTRL 13
SB_CPU1_BREQ#23 13
CPU1_SLEW_CTRL 13
SB_CPU1_BSEL1 12,13
SB_CPU1_BSEL0 12,13
PU_COMP3_CPU1 13
PU_COMP2_CPU1 13
PD_COMP1_CPU1 13
PD_COMP0_CPU1 13
PD_ODTEN_CPU1 13
PU_CPU1_8 13
PU_CPU1_7 13
PU_CPU1_6 13
PU_CPU1_5 13
PU_CPU1_4 13
PU_CPU1_3 13
PU_CPU1_2 13
PU_CPU1_1 13
PU_CPU1_0 13
SMC_CPU1_SKTOCC# 13,55
CPU_PWR_GD 9,13,16,51
GA-9ITDW-FJ
1
1.3
of
11 81Wednesday, October 13, 2004
PROCESSOR 0 TERMINATION PROCESSOR 1 TERMINATION
5
D D
SB_CPU1_BSEL011,13
SB_CPU1_BSEL111,13
C C
R88
SB_CPU1_BSEL0_R SB_CPU0_BSEL0_R
100
R92
SB_CPU1_BSEL1_R
100
P3V3
ECB
R86
3.3K
CPU1_BSEL0_N
Q3
MMBT2222A
SOT23
R90
3.3K
CPU1_BSEL1_N
Q7
MMBT2222A
SOT23
ECB
4
ECB
ECB
Q1
MMBT2222A
SOT23
Q5
MMBT2222A
SOT23
3
CPU1_BSEL0 55 CPU0_BSEL0 31,55
SB_CPU0_BSEL09,11
CPU1_BSEL1 55
SB_CPU0_BSEL19,11
R89
100
R93
100
2
SB_CPU0_BSEL1_R
P3V3
CPU0_BSEL0_N
ECB
P3V3P3V3
R91
3.3K
CPU0_BSEL1_N
ECB
R87
3.3K
Q4
MMBT2222A
SOT23
Q8
MMBT2222A
SOT23
ECB
ECB
Q2
MMBT2222A
SOT23
Q6
MMBT2222A
SOT23
1
CPU0_BSEL1 31,55
SC14
0.01U/6/X/50V
R116 4.7K
R117 4.7K
5
R94 0/X
R98 0
R99 0/X
R100 0
R94, R99 UNSTUFF ED
R98, R100 UNSTUFFED
R107
200
R108
200
R109
220
GTL_B01
CPU1_FORCEPR#51,53
VR1_FORCEPR#70,73
CPU0_FORCEPR#51,53
VR0_FORCEPR#69,73
(* DEFAULT)
STUFFING OPTIONS FOR FORCEPR:
* THERMAL CIRCUIT SUPPORT: R98, R100 STUFFED
GPIO SUPPORT: R94, R99 STUFF ED
B B
P_VTT
SC13
1U/6/X/10V
SB_CPU1_IERR#11,13
SB_CPU0_IERR#9,11
SB_CPU0_PROCHOT#9,11
SB_CPU1_PROCHOT#11,13
A A
SB_CPU_THERMTRIP#9,11,13,51,53
SB_CPU0_FORCEPR#9,11
SB_CPU1_FORCEPR#11,13
ICH_CPU_SMI#51
SB_ICH_NMI51
P3V3
CPU1_FORCEPR#_R
CPU0_FORCEPR#_R
R110
51
PU_DIS_CPU0#
PU_DIS_CPU1#
R111
51
R112
51/X
R113
51
BSP SEL
MCH_BREQ#0
MCH_BREQ#119
P_VTT
R103
P_VTT
R114
R115
51
220
4
49.9/1%
GTL2006_VREF
R106
100/1%
U8
1
VREF
27
1BI
26
2BI
19
3BI
18
4BI
21
5BI
25
7BO1
20
6BI
24
7BO2
23
8BO
9
9BI
12
10AI1
13
10AI2
7
11BI
SC15
1U/6/X/10V
VCC
1AO
2AO
3AO
4AO
8AI
9AO
10BO1
10BO2
11BO
11AGND
GTL2006/TSSOP28
5A
6A
P3V3
28
2
3
10
11
4
5
6
15
17
16
22
814
TP_SMC_SMI#_R
PU_SMC_CPU_NMI
SC16
1U/6/X/10V
P3V3
3
R104
220
R105
1K
CPU0_FORCEPR#_RGTL_BI
CPU1_FORCEPR#_R
R1134
TP17
1K/X
R1135
1K/X
CPU1_IERR# 73
CPU0_IERR# 73
CPU0_PROCHOT# 73
CPU1_PROCHOT# 73
CPU_THERMTRIP# 73
SB_CPU0_SMI# 9,11
SB_CPU1_SMI# 11,13
SB_CPU_NMI 9,11,13
MCH_BREQ#1
2
R95 0
R96 0
Title
Size Document Number Rev
Date: Sheet
SB_BREQ#0
SB_BREQ#1
SB_BREQ#0 9,11,13MCH_BREQ#019
SB_BREQ#1 9,11,13
GIGA-BYTE TECHNOLOGY CO., LTD.
NOCONA FREQ. SELECT LOGIC
GA-9ITDW-FJ
1
of
12 81Wednesday, October 13, 2004
1.3
5
4
3
2
1
PROCESSOR 1
SB_BPRI#9,19
SB_CPU1_BREQ#2311
SB_BREQ#09,11,12
SB_BREQ#19,11,12
D D
SB_RS#[0..2]9,19
C C
VID_CPU1_R[5..0]71
B B
P_VTT
754mV
P_VTT
SB_CPURST#9,11,16,19
SB_RSP#9,19
SB_CPU_A20M#9,11,51
SB_CPU_IGNNE#9,11,51
SB_CPU_INIT#9,11,51,59
SB_CPU_NMI9,11,12
SB_CPU_INTR9,11,51
CPU_PWR_GD9,11,16,51
SB_CPU1_SMI#11,12
SB_CPU_SLP#9,11,51
SB_CPU_STPCLK#9,11
P1_BCLK#31
P1_BCLK31
ITP_TCK09,16
ITP_TDI_P116
ITP_TMS_MAIN9,16
ITP_TRST#9,16,21
SB_CPU1_BSEL111,12
SB_CPU1_BSEL011,12
P_VCCP_A_CPU1
VR1_VCCSENSE70
VTTEN9,11,55
AGND_CPU1
VR1_VSSSENSE70
PLACE COMPONENTS: GROUP ASSOCIATE COMPONENTS
TOGETHER AND AS PHYISCALLY CLOSE TO ASSOCIATED PIN AS
POSSIBBLE WITH THE 220PF CAP CL OSEST TO THE PIN
MIN TRACE WIDTH >=10 - 12 MILS
R118
49.9/1%
VREF_P_VTT_CPU1_0_R
C8
R120
1U/6/X/10V
84.5/1%
SB_BPRI#
SB_CPU1_BREQ#23
SB_BREQ#0
SB_BREQ#1
SB_CPURST#
SB_RS#2
SB_RS#1
SB_RS#0
SB_RSP#
SB_CPU_A20M#
SB_CPU_IGNNE#
SB_CPU_INIT#
SB_CPU_NMI
SB_CPU_INTR
CPU_PWR_GD
SB_CPU1_SMI#
SB_CPU_SLP#
SB_CPU_STPCLK#
P1_BCLK#
P1_BCLK
ITP_TCK0
ITP_TDI_P1
ITP_TMS_MAIN
ITP_TRST#
SB_CPU1_BSEL1
SB_CPU1_BSEL0
TP18
TP19
TP20
TP21
TP22
TP23
TP24
TP25
TP26
TP27
TP28
TP29
TP30
TP31
P1_RSVD13
P1_RSVD12
P1_RSVD11
P1_RSVD10
P1_RSVD9
P1_RSVD8
P1_RSVD7
P1_RSVD6
P1_RSVD5
P1_RSVD4
P1_RSVD3
P1_RSVD2
P1_RSVD1
P1_RSVD0
VID_CPU1_R5
VID_CPU1_R4
VID_CPU1_R3
VID_CPU1_R2
VID_CPU1_R1
VID_CPU1_R0
VR1_VCCSENSE
VTTEN
VR1_VSSSENSE
PLACE 0 OHM RESISTOR ON BACK SIDE
SR162
0
VREF_P_VTT_CPU1_0
C12
220P/6/X/50V
U2A
D23
BPRI#
D10
E11
F12
D20
F21
D22
E21
F27
C26
G23
B24
AB7
C27
AE6
E24
C24
A25
F24
AB3
AA3
AE29
AE28
AE30
AD29
AD28
AC29
AB29
AB28
AA29
AA28
AE15
AC1
AE16
AD4
B27
AB4
AA5
D26 C1
C13
220P/6/X/50V
NOCONA 800
BR3#
BR2#
BR1#
BR0#
Y8
RESET#
RS2#
RS1#
RS0#
C6
RSP#
A20M#
IGNNE#
D6
INIT#
LINT1_NMI
LINT0_INTR
PWRGOOD
SMI#
SLP#
D4
STPCLK#
W5
BCLK1
Y4
BCLK0
TCK
TDI
TMS
TRST#
BSEL1
BSEL0
RESERVED1
RESERVED0
NC
Y3
RSVD15
RSVD14
RSVD13
RSVD12
RSVD10
RSVD9
RSVD8
RSVD7
RSVD3
RSVD2
RSVD1
A1
VID5
B3
VID4
C3
VID3
D3
VID2
E3
VID1
F3
VID0
VCCIOPLL
VCC_SENSE
E1
VTTEN
VCCA
VSSA
VSSSENSE OPTIMIZED_COMPAT#
NOCONA 667
ADS#
BINIT#
BNR#
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
DBSY#
DEFER#
DRDY#
HIT#
HITM#
TRDY#
LOCK#
MCERR#
IERR#
FERR#
THERMTRIP#
PROCHOT#
TDO
GTLREF3
GTLREF2
GTLREF1
GTLREF0
ODTEN
SKTOCC#
RSVD11/COMP3
RSVD5/COMP2
COMP1
COMP0
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
SMB_PRT
VCCPLL
THERMDC
THERMDA
BOOT_SELECT
RSVD
VIDPWRGD
TEST_BUS
FORCEPR#
SLEW_CTRL
P_VTT
10UH/8
10UH/8
PLACE COMP ONENTS: ROUTE TRACE FROM L1 TO P IN AD4 , ROUTE
TRACE FROM L2 TO PIN AB4 .PLACE CAP BETWEEN AB4 AND
AGND_CPU0 . MI N TR AC E WI DTH >=10 - 12 MILS
D19
F11
F20
E4
E8
F5
E7
F8
F6
F18
C23
E18
E22
A23
E19
A17
D7
E5
E27
F26
B25
E25
F9
F23
W9
W23
B5
SMC_CPU1_SKTOCC#
A3
PU_COMP3_CPU1
D25
PU_COMP2_CPU1
AC28
PD_COMP1_CPU1
E16
PD_COMP0_CPU1
AD16
PU_CPU1_8
Y29
PU_CPU1_0
A26
PU_CPU0_5
AE5
PU_CPU1_6
AD5
PU_CPU1_1
AA7
PU_CPU1_7
Y6
PU_CPU1_3
W8
PU_CPU1_2
W7
PU_CPU1_4
W6
P1_RSVD16
AE4
AD1
CPU1_THERMDC
Y28
CPU1_THERMDA
Y27
PU_BOOT_SELECT_CPU1
G7
P1_RSVD15
W3
VID_PWRGD
B1
SB_CPU0_CPU1_TESTBUS
A16
SB_CPU1_FORCEPR#
A15
CPU1_SLEW_CTRL
AC30
CPU1_OPTIM_COMPAT_CTRL
L3
L4
SB_ADS#
SB_BINIT#
SB_BNR#
CPU1_BPM#5
CPU1_BPM#4
CPU1_BPM#3
CPU1_BPM#2
CPU1_BPM#1
CPU1_BPM#0
SB_DBSY#
SB_DEFER#
SB_DRDY#
SB_HIT#
SB_HITM#
SB_TRDY#
SB_LOCK#
SB_MCERR#
SB_CPU1_IERR#
SB_CPU_FERR#
SB_CPU_THERMTRIP#
SB_CPU1_PROCHOT#
ITP_TDO_P1
PD_ODTEN_CPU1
12
C11
22U/1210/X/6.3V
SB_ADS# 9,19
SB_BINIT# 9,11,19
SB_BNR# 9,11,19
SB_DBSY# 9,19
SB_DEFER# 9,19
SB_DRDY# 9,19
SB_HIT# 9,11,19
SB_HITM# 9,11,19
SB_TRDY# 9,19
SB_LOCK# 9,19
SB_MCERR# 9,11,19
SB_CPU1_IERR# 11,12
SB_CPU_FERR# 9,11,51,53
SB_CPU_THERMTRIP# 9,11,12,51,53
SB_CPU1_PROCHOT# 11,12
ITP_TDO_P1 16
PD_ODTEN_CPU1 11
SMC_CPU1_SKTOCC# 11,55
PU_COMP3_CPU1 11
PU_COMP2_CPU1 11
PD_COMP1_CPU1 11
PD_COMP0_CPU1 11
PU_CPU1_8 11
PU_CPU1_0 11
PU_CPU1_5 11
PU_CPU1_6 11
PU_CPU1_1 11
PU_CPU1_7 11
PU_CPU1_3 11
PU_CPU1_2 11
PU_CPU1_4 11
TP32
CPU1_THERMDC 15
CPU1_THERMDA 15
PU_BOOT_SELECT_CPU1 11
TP33
VID_PWRGD 9,55
SB_CPU0_CPU1_TESTBUS 9,11
SB_CPU1_FORCEPR# 11,12
CPU1_SLEW_CTRL 11
CPU1_OPTIM_COMPAT_CTRL 11
P_VCCP_A_CPU1
AGND_CPU1
CPU1_BPM#[5..0] 16
SB_D#[63..0]9,19
VREF_P_VTT_CPU1_3
VREF_P_VTT_CPU1_0
PU_VCCPLL_CPU1
SB_D#63
SB_D#62
SB_D#61
SB_D#60
SB_D#59
SB_D#58
SB_D#57
SB_D#56
SB_D#55
SB_D#54
SB_D#53
SB_D#52
SB_D#51
SB_D#50
SB_D#49
SB_D#48
SB_D#47
SB_D#46
SB_D#45
SB_D#44
SB_D#43
SB_D#42
SB_D#41
SB_D#40
SB_D#39
SB_D#38
SB_D#37
SB_D#36
SB_D#35
SB_D#34
SB_D#33
SB_D#32
SB_D#31
SB_D#30
SB_D#29
SB_D#28
SB_D#27
SB_D#26
SB_D#25
SB_D#24
SB_D#23
SB_D#22
SB_D#21
SB_D#20
SB_D#19
SB_D#18
SB_D#17
SB_D#16
SB_D#15
SB_D#14
SB_D#13
SB_D#12
SB_D#11
SB_D#10
SB_D#9
SB_D#8
SB_D#7
SB_D#6
SB_D#5
SB_D#4
SB_D#3
SB_D#2
SB_D#1
SB_D#0
COMP3 =SB_CPU1_ADDR_ERC
COMP2 =SB_CPU1_DATA_ERC
PU_CPU1_8=SB_CPU1_EDRDY
PU_CPU1_0=SB_CPU1_SNPD#
AB6
AA8
AC5
AC6
AE7
AD7
AC8
AB10
AA10
AA11
AB13
AB12
AC14
AA14
AA13
AC9
AD8
AD10
AE9
AC11
AE10
AC12
AD11
AD14
AD13
AB15
AD18
AE13
AC17
AA16
AB16
AB17
AD19
AD21
AE20
AE22
AC21
AC20
AA18
AC23
AE23
AD24
AC24
AE25
AD25
AC26
AE26
AA19
AB19
AB22
AB20
AA21
AA22
AB23
AB25
AB26
AA24
Y23
AD27
AA25
Y24
AA27
Y26
Y9
U2B
D63#
NOCONA 800
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
D39#
D38#
D37#
D36#
D35#
D34#
D33#
D32#
D31#
D30#
D29#
D28#
D27#
D26#
D25#
D24#
D23#
D22#
D21#
D20#
D19#
D18#
D17#
D16#
D15#
D14#
D13#
D12#
D11#
D10#
D9#
D8#
D7#
D6#
D5#
D4#
D3#
D2#
D1#
D0#
NOCONA 667
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
A9#
A8#
A7#
A6#
A5#
A4#
A3#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
DBI3#
DBI2#
DBI1#
DBI0#
DP3#
DP2#
DP1#
DP0#
AP1#
AP0#
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
SB_HA#35
C8
SB_HA#34
C9
SB_HA#33
A7
SB_HA#32
A6
SB_HA#31
B7
SB_HA#30
C11
SB_HA#29
D12
SB_HA#28
E13
SB_HA#27
B8
SB_HA#26
A9
SB_HA#25
D13
SB_HA#24
E14
SB_HA#23
C12
SB_HA#22
B11
SB_HA#21
B10
SB_HA#20
A10
SB_HA#19
F15
SB_HA#18
D15
SB_HA#17
D16
SB_HA#16
C14
SB_HA#15
C15
SB_HA#14
A12
SB_HA#13
B13
SB_HA#12
B14
SB_HA#11
B16
SB_HA#10
A13
SB_HA#9
D17
SB_HA#8
C17
SB_HA#7
A19
SB_HA#6
C18
SB_HA#5
B18
SB_HA#4
A20
SB_HA#3
A22
SB_REQ#4
B22
SB_REQ#3
C20
SB_REQ#2
C21
SB_REQ#1
B21
SB_REQ#0
B19
SB_DBI#3
AB9
SB_DBI#2
AE12
SB_DBI#1
AD22
SB_DBI#0
AC27
SB_DP#3
AE17
SB_DP#2
AC15
SB_DP#1
AE19
SB_DP#0
AC18
SB_AP#1
D9
SB_AP#0
E10
SB_ADSTB#1
F14
SB_ADSTB#0
F17
SB_DSTBP#3
Y11
SB_DSTBP#2
Y14
SB_DSTBP#1
Y17
SB_DSTBP#0
Y20
SB_DSTBN#3
Y12
SB_DSTBN#2
Y15
SB_DSTBN#1
Y18
SB_DSTBN#0
Y21
Trace Width:12 Mils
VREF_P_VTT_CPU1_0
VREF_P_VTT_CPU1_3
VCCIOPLL_CPU1
AGND_CPU1
PU_VCCPLL_CPU1
SB_HA#[35..3] 9,19
SB_REQ#[4..0] 9,19
SB_DBI#[3..0] 9,19
SB_DP#[3..0] 9,19
SB_AP#[1..0] 9,19
SB_ADSTB#[1..0] 9,19
SB_DSTBP#[3..0] 9,19
SB_DSTBN#[3..0] 9,19
12
C1106
22U/1206/X/6.3V
P_VTT
12
SC193
22U/1206/X/6.3V
SC18
1U/6/X/10V
2
SC19
0.1U/6/X/16V
Title
Size Document Number Rev
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
NOCONA 667 MICS P1
GA-9ITDW-FJ
1
of
13 81Wednesday, October 13, 2004
1.3
R121
A A
754mV
49.9/1%
R124
84.5/1%
C18
1U/6/X/10V
PLACE 0 OHM RESISTOR ON BACK SIDE
SR163
0
5
C20
220P/6/X/50V
VREF_P_VTT_CPU1_3VREF_P_VTT_CPU1_3_R
C19
220P/6/X/50V
P1V5
R123
12
0/X
PLACE COMPONENTS: GROUP ASSOCIATE COMPONENTS
TOGETHER AND AS PHYISCALLY CLOSE TO ASSOCIATED PIN AS
POSSIBBLE M IN TRACE W IDTH >=10 - 12 MILS
4
TC2
+
470U/4V/7343/X
12
C14
4.7U/1206/X/10V/X
PU_VCCPLL_CPU1
C15
0.1U/6/X/16V/X
3
C16
0.1U/6/X/16V/X
5
4
3
2
1
P_VCCP1 P_VCCP1
H31
H29
H27
H25
H23
G30
G28
G26
G24
F31
F29
F22
F16
E30
E28
E26
E20
D31
D29
D24
D18
D14
C30
C28
C22
C16
B31
B29
B26
B20
A30
A28
A24
A18
A14
U2D
L30
L26
L24
L8
L6
L4
L2
K31
K29
K27
K25
K23
K9
K7
K5
K3
K1
J30
J28
J26
J24
J8
J6
J4
J2
H9
H7
H5
H3
H1
G8
G6
G4
G2
F4
F1
E6
E2
D8
D1
C4
C2
B6
A8
A2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NOCONA 800
NOCONA 667
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
L28
AA31
AA26
AA20
AA6
AA4
AA1
Y30
Y22
Y16
Y2
W31
W29
W27
W25
W1
V30
V28
V26
V24
V8
V6
V4
V2
U31
U29
U27
U25
U23
U9
U7
U5
U3
U1
T30
T28
T26
T24
T8
T6
T4
T2
R31
R29
R27
R25
R23
R9
R7
R5
R3
R1
P30
P28
P26
P24
P8
P6
P4
P2
N31
N29
N27
N25
N23
N9
N7
N5
N3
N1
M31
M29
M27
M25
M23
M9
M7
M5
M3
M1
P_VCCP1
P_VTT
AD12
AC10
AA12
AE24
AE18
AE14
AE8
AE3
AD30
AD26
AD20
AD6
AD2
AC31
AC22
AC16
AC4
AC3
AB30
AB24
AB18
AB14
AB8
AB2
U2E
NOCONA 800
VTT
VTT
VTT
Y10
VTT
F10
VTT
E12
VTT
C10
VTT
B12
VTT
B4
VTT
C5
VTT
A4
VTT
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NOCONA 667
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AE2
AD3
AE27
AE21
AE11
AD31
AD23
AD17
AD15
AD9
AC25
AC19
AC13
AC7
AC2
AB31
AB27
AB21
AB11
AB5
AB1
H30
H28
H26
H24
G31
G29
G27
G25
F30
F28
F25
F19
F13
E31
E29
E23
E17
E15
D30
D28
D27
D21
D11
C31
C29
C25
C19
C13
B30
B28
B23
B17
B15
A31
A29
A27
A21
A11
U2C
L31
GND
L29
L27
L25
L23
L9
L7
L5
L3
L1
K30
K28
K26
K24
K8
K6
K4
K2
J31
J29
J27
J25
J23
J9
J7
J5
J3
J1
H8
H6
H4
H2
G9
G5
G3
G1
F7
F2
E9
D5
D2
C7
B9
B2
A5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NOCONA 800
NOCONA 667
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AA30
AA23
AA17
AA15
AA9
AA2
Y31
Y25
Y19
Y13
Y7
Y5
Y1
W30
W28
W26
W24
W4
W2
V31
V29
V27
V25
V23
V9
V7
V5
V3
V1
U30
U28
U26
U24
U8
U6
U4
U2
T31
T29
T27
T25
T23
T9
T7
T5
T3
T1
R30
R28
R26
R24
R8
R6
R4
R2
P31
P29
P27
P25
P23
P9
P7
P5
P3
P1
N30
N28
N26
N24
N8
N6
N4
N2
M2
M4
M6
M8
M24
M26
M28
M30
D D
C C
B B
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
NOCONA 667 P1 PWR/GND
GA-9ITDW-FJ
1
of
14 81Wednesday, October 13, 2004
1.3
5
D D
SLP_S#449,51
P3V3_DUAL
4.7K
D
D
GS
NEAR CPU0
R125
0
R127
0
NEAR MCH
R129
0/X
R131
0/X
NEAR CPU1
R126
0
R128
0
NEAR PXH
R130
0/X
R132
0/X
SMC_CPU0_SKTOCC#
CPU0_THERMDC_H7
MCH_TDA_H7
MEM_TDA
MEM_TDC
CPU1_THERMDA_H7
CPU1_THERMDC_H7
PXH_TDA_H7
PXH_TDC_H7
CPU0_SKT_TDA
CPU0_SKT_TDC
SMC_CPU0_SKTOCC#9,11 SLP_S#349,51,58,63
C C
CPU0_THERMDA9 TD1P 73
MCH_TDA21
MCH_TDC21
B B
CPU1_THERMDA13 TD2P 73
CPU1_THERMDC13
PXH_TDA36
PXH_TDC36
A A
CPU0_THERMDA CPU0_THERMDA_H7
CPU0_THERMDC
MCH_TDA
MCH_TDC MCH_TDC_H7
Q9
B
C
E
MMBT2222A/X
MMBT2222A/X
CPU1_THERMDA
CPU1_THERMDC
PXH_TDA
PXH_TDC
Q10
B
C
E
5
SOT23
SOT23
G
S
R260
R261
R263
R264
R266
R267
4
R1184
SMC_CPU0_SKTOCC
Q115
2N7002
0
0
0/X
0/X
0/X
0/X
R269
R270
R272
R273
R275
R276
0
0
0/X
0/X
0/X
0/X
TD1P
C21
100P/6/N/50V
TD1N
PLACE CLOSE TOGETHER AND NEAR LM93
PLACE CLOSE TOGETHER AND NEAR LM93
TD2P
C22
100P/6/N/50V
TD2N
4
P3V3_DUAL
53
1
2
SN74LVC1G08
TD1N 73CPU0_THERMDC9
TD2N 73
3
Q113
2N7002
S
R1364
10K/1%
RT2
10K/8/1%/TR
R1182 0
t
D
D
GS
G
P5V_STBY
R1183
10K
CPU_S3_PS_ON#
Q114
U74
4
CPU0_SKTOCC_S3
VREF58
TEMPIN158
TEMPIN258
TEMPIN358
10RH1-001002-20
R1185
1K
R1366
10K/1%
RT1
t
10K/8/1%/TR
3
ECB
MMBT2222A
SOT23
t
2
P5V_STBY
R1181
4.7K
PS_ON#_R 49,63
1
SMC_CPU0_SKTOCC# SLP_S#3 SLP_S#4 PS_ON#
1
11 1
110
0
1
TOUT
VDD
TOUT
VDD
TOUT
VDD
TOUT
VDD
3
8
3
8
3
8
3
8
P3V3_DUAL
R1111
1K/X
UNDER
CPU
SOCKET
NEAR DDRII
SLOT
NEAR PCI
SLOT
NEAR SCSI
CONTROLLER
LM75_SMBALERT#
U66
SDA
SCL
A2
A1
A0 GND
LM75/3.3V/X
U67
SDA
SCL
A2
A1
A0 GND
LM75/3.3V/X
U68
SDA
SCL
A2
A1
A0 GND
LM75/3.3V/X
U69
SDA
SCL
A2
A1
A0 GND
LM75/3.3V/X
GIGA-BYTE TECHNOLOGY CO., LTD.
THERMAL SENSER
GA-9ITDW-FJ
1
LM93_SMBALERT#72,73
removable, duplicated.
LM75_SMBDAT72
LM75_SMBCLK72
R1365
10K/1%
RT3
10K/8/1%/TR
0
0
00
R1110
P3V3_DUAL
R1109
R1108
1K/X
1K/X
2
R1112 47/X
R1113
47/X
R1122
47/X
R1123
47/X
0/X
1
2
5
6
7 4
1
P3V3_DUAL
2
5
6
7 4
1
2
5
6
7 4
1
2
5
6
7 4
Title
Size Document Number Rev
Date: Sheet
0
1
1
1.3
of
15 81Wednesday, October 13, 2004
5
2
2
4
3
2
1
ITP1
CPU0_BPM#5
CPU0_BPM#4
CPU0_BPM#3
CPU0_BPM#2
D D
CPU_PWR_GD9,11,13,51
MCHPME#19,53
MCH_SMBDAT
,56,7
MCH_SMBCLK
,56,7
C C
B B
ITP_TCK121
ITP_TCK09,13
CPU_PWR_GD
MCHPME#
MCH_SMBDAT
MCH_SMBCLK MCH_SMBCLK_R
P_VTT
SR23 51
SR24 51
SR25 51
SR26 51
SR27 51
SR28 51
SR29 51
SR30 51
SR31 51
SR32 51
SR33 51
SR34 51
PLACE RESISTORS AT END OF NET
R160 51
R162 51
R136 0/X
R137 0/X
R138 0/X
R139 51
R140 51
PLACE RESISTORS AT END OF NET
CPU1_BPM#5
CPU1_BPM#4
CPU1_BPM#3
CPU1_BPM#2
CPU1_BPM#1
CPU1_BPM#0
CPU0_BPM#5
CPU0_BPM#4
CPU0_BPM#3
CPU0_BPM#2
CPU0_BPM#1
CPU0_BPM#0
P_VTT
ITP_TMS_MCH
ITP_TMS_MAIN
TP34
TP35
CPU0_BPM#1
CPU0_BPM#0
CPU1_BPM#5
CPU1_BPM#4
CPU1_BPM#3
CPU1_BPM#2
CPU1_BPM#1
CPU1_BPM#0
ITP_CPU_PWRGOOD
ITP_TP_41
ITP_TP_47
MCH_SMBDAT_R
ITP_TCK1
ITP_TCK0
CPU1_BPM#[5..0] 13
CPU0_BPM#[5..0] 9
ITP_TMS_MCH 21
ITP_TMS_MAIN 9,13
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
ITP CONN/X
P1V5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
ITP_TP_4
ITP_MCH_DEBUG0
ITP_TP_10
ITP_MCH_DEBUG1
ITP_MCH_DEBUG2
ITP_MCH_DEBUG3
ITP_TP_22
ITP_TP_24
ITP_MCH_DEBUG4
ITP_MCH_DEBUG5
ITP_MCH_DEBUG6
ITP_MCH_DEBUG7
ITP_BCLK
ITP_BCLK#
SB_CPURST#_R
DBR_RESET#
ITP_TDO_MAIN
ITP_TRST#
ITP_TDI_MAIN
ITP_TMS_MAIN
ITP_TMS_MAIN9,13 ITP_TMS_MCH 21
ITP_MCH_DEBUG[7..0]
PLACE WITHIN
1" OF CPU(0)
ITP_BCLK 31
ITP_BCLK# 31
ITP_TRST# 9,13,21
ITP_TMS_MAIN 9,13
R141
51
PIN1X4/X
SB_CPURST#_R
DBR_RESET# FP_RESET#
ITP_TMS_MAIN
ITP_TDI_MAIN
ITP_TDO_MAIN
R143 1K/X
R146 0/X
R149 0
R156
0/X
R161
0/X
JP1
1
2
3
4
P_VTT
R153
51
P_VTT
R159
51
ITP_MCH_DEBUG[7..0] 21
P_VTT
PLACE WITHIN
1" OF CPU(ITP)
R133
51
ITP_TDI_P1
ITP_TDO_P0
ITP_TDO_P1
SB_CPURST#
ITP_TMS_MCH
PLACE WITHIN 1" OF MCH
ITP_TDI_MCH
PLACE WITHIN 1" OF MCH
ITP_TDO_MCH
SR168
51
SR18
PLACE WITHIN
1" OF CPU(1)
51
ITP_TDI_MAIN 9
ITP_TDI_P1 13
ITP_TDO_P0 9
ITP_TDO_P1 13
SB_CPURST# 9,11,13,19
FP_RESET# 51,53,65
ITP_TDI_MCH 21ITP_TDI_MAIN9
ITP_TDO_MCH 21
MODE JUMP JP1 PROCESSOR CONNFIGURATION
UP 2-3 P0 INSTALLED ; P1 REMOVED
DP 1-2 & 3-4 P0 & P1 INSTALLED
ITP_TP_4
ITP_TP_10
ITP_TP_22
ITP_TP_24
TP36
TP37
TP38
TP39
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
ITP_EXETENDED DEBUG PORT
GA-9ITDW-FJ
1
of
16 81Wednesday, October 13, 2004
1.3
5
DDRA_MA[13..0]24,25,26,30
D D
DDRA_CB[7..0]24,25,26
PLACE DDRA_MCH_VREF VOLTAGE
DIVIDER NEAR MCH
P1V8_AUX
C C
B B
A A
R163
75/1%
R164
75/1%
20-MIL TRACE WIDTH,
12-MIL SPACING
DDRA_MCH_VREF
SC21
1U/6/X/10V
DDRA_MCH_VREF
R165 0
SC22
0.1U/6/X/16V
DDRA_DQS[17..0]24,25,26
DDRA_DQS#[17..0]24,25,26
MEM_CKE[7..0]18,24,25,26,27,28,29,30
DDRA_CMDCLK3_P30
DDRA_CMDCLK3_N30
DDRA_CMDCLK2_P25,30
DDRA_CMDCLK2_N25,30
DDRA_CMDCLK1_P26,30
DDRA_CMDCLK1_N26,30
DDRA_CMDCLK0_P24,30
DDRA_CMDCLK0_N24,30
DDRA_CS#[7..0]24,25,26,30
DDRA_CAS#24,25,26,30
DDRA_RAS#24,25,26,30
DDRA_WE#24,25,26,30
DDRA_BA[2..0]24,25,26,30
4
DDRA_MA13
DDRA_MA12
DDRA_MA11
DDRA_MA10
DDRA_MA9
DDRA_MA8
DDRA_MA7
DDRA_MA6
DDRA_MA5
DDRA_MA4
DDRA_MA3
DDRA_MA2
DDRA_MA1
DDRA_MA0
DDRA_CB7
DDRA_CB6
DDRA_CB5
DDRA_CB4
DDRA_CB3
DDRA_CB2
DDRA_CB1
DDRA_CB0
MEM_CKE3
MEM_CKE2
MEM_CKE1
MEM_CKE0
DDRA_CMDCLK3_P
DDRA_CMDCLK3_N
DDRA_CMDCLK2_P
DDRA_CMDCLK2_N
DDRA_CMDCLK1_P
DDRA_CMDCLK1_N
DDRA_CMDCLK0_P
DDRA_CMDCLK0_N
DDRA_CS#7
DDRA_CS#6
DDRA_CS#5
DDRA_CS#4
DDRA_CS#3
DDRA_CS#2
DDRA_CS#1
DDRA_CS#0
DDRA_MCH_VREF_R
DDRA_CAS#
DDRA_RAS#
DDRA_WE#
DDRA_BA0
DDRA_BA1
DDRA_BA2
DDRA_DQS8
DDRA_DQS#8
DDRA_DQS7
DDRA_DQS#7
DDRA_DQS6
DDRA_DQS#6
DDRA_DQS5
DDRA_DQS#5
DDRA_DQS4
DDRA_DQS#4
DDRA_DQS3
DDRA_DQS#3
DDRA_DQS2
DDRA_DQS#2
DDRA_DQS1
DDRA_DQS#1
DDRA_DQS0
DDRA_DQS#0
U3A
U6
DDR_A_MA<13>
AG23
DDR_A_MA<12>
AF22
DDR_A_MA<11>
AE4
DDR_A_MA<10>
AJ22
DDR_A_MA<9>
AK20
DDR_A_MA<8>
AN20
DDR_A_MA<7>
AF18
DDR_A_MA<6>
AH17
DDR_A_MA<5>
AJ16
DDR_A_MA<4>
AK15
DDR_A_MA<3>
AL14
DDR_A_MA<2>
AD14
DDR_A_MA<1>
AH5
DDR_A_MA<0>
AE10
DDR_A_CB<7>
AF10
DDR_A_CB<6>
AH10
DDR_A_CB<5>
AJ10
DDR_A_CB<4>
AD11
DDR_A_CB<3>
AE11
DDR_A_CB<2>
AG11
DDR_A_CB<1>
AJ9
DDR_A_CB<0>
AK26
DDR_CKE<3>
AL26
DDR_CKE<2>
AN26
DDR_CKE<1>
AE26
DDR_CKE<0>
AC10
DDR_A_CMDCLK_P<3>
AD9
DDR_A_CMDCLK_N<3>
AH13
DDR_A_CMDCLK_P<2>
AG12
DDR_A_CMDCLK_N<2>
AH11
DDR_A_CMDCLK_P<1>
AJ12
DDR_A_CMDCLK_N<1>
AF13
DDR_A_CMDCLK_P<0>
AF12
DDR_A_CMDCLK_N<0>
L4
DDR_A_CS_N<7>
M3
DDR_A_CS_N<6>
M5
DDR_A_CS_N<5>
N5
DDR_A_CS_N<4>
T10
DDR_A_CS_N<3>
T8
DDR_A_CS_N<2>
V3
DDR_A_CS_N<1>
W2
DDR_A_CS_N<0>
AM3
DDR_A_VREF
W8
DDR_A_CAS_N
AA6
DDR_A_RAS_N
Y10
DDR_A_WE_N
AB5
DDR_A_BA<0>
AF6
DDR_A_BA<1>
AE25
DDR_A_BA<2>
AF9
DDR_A_DQS_P<8>
AG9
DDR_A_DQS_N<8>
G4
DDR_A_DQS_P<7>
H4
DDR_A_DQS_N<7>
N7
DDR_A_DQS_P<6>
P7
DDR_A_DQS_N<6>
W7
DDR_A_DQS_P<5>
V8
DDR_A_DQS_N<5>
AC6
DDR_A_DQS_P<4>
AD6
DDR_A_DQS_N<4>
AG14
DDR_A_DQS_P<3>
AG15
DDR_A_DQS_N<3>
AH19
DDR_A_DQS_P<2>
AH20
DDR_A_DQS_N<2>
AJ24
DDR_A_DQS_P<1>
AJ25
DDR_A_DQS_N<1>
AJ30
DDR_A_DQS_P<0>
AJ31
DDR_A_DQS_N<0>
MCH 1/8
DDR GROUP A
TUMWATER
3
DDR_A_DQ<63>
DDR_A_DQ<62>
DDR_A_DQ<61>
DDR_A_DQ<60>
DDR_A_DQ<59>
DDR_A_DQ<58>
DDR_A_DQ<57>
DDR_A_DQ<56>
DDR_A_DQ<55>
DDR_A_DQ<54>
DDR_A_DQ<53>
DDR_A_DQ<52>
DDR_A_DQ<51>
DDR_A_DQ<50>
DDR_A_DQ<49>
DDR_A_DQ<48>
DDR_A_DQ<47>
DDR_A_DQ<46>
DDR_A_DQ<45>
DDR_A_DQ<44>
DDR_A_DQ<43>
DDR_A_DQ<42>
DDR_A_DQ<41>
DDR_A_DQ<40>
DDR_A_DQ<39>
DDR_A_DQ<38>
DDR_A_DQ<37>
DDR_A_DQ<36>
DDR_A_DQ<35>
DDR_A_DQ<34>
DDR_A_DQ<33>
DDR_A_DQ<32>
DDR_A_DQ<31>
DDR_A_DQ<30>
DDR_A_DQ<29>
DDR_A_DQ<28>
DDR_A_DQ<27>
DDR_A_DQ<26>
DDR_A_DQ<25>
DDR_A_DQ<24>
DDR_A_DQ<23>
DDR_A_DQ<22>
DDR_A_DQ<21>
DDR_A_DQ<20>
DDR_A_DQ<19>
DDR_A_DQ<18>
DDR_A_DQ<17>
DDR_A_DQ<16>
DDR_A_DQ<15>
DDR_A_DQ<14>
DDR_A_DQ<13>
DDR_A_DQ<12>
DDR_A_DQ<11>
DDR_A_DQ<10>
DDR_A_DQ<9>
DDR_A_DQ<8>
DDR_A_DQ<7>
DDR_A_DQ<6>
DDR_A_DQ<5>
DDR_A_DQ<4>
DDR_A_DQ<3>
DDR_A_DQ<2>
DDR_A_DQ<1>
DDR_A_DQ<0>
DDR_A_DQS_P<17>
DDR_A_DQS_N<17>
DDR_A_DQS_P<16>
DDR_A_DQS_N<16>
DDR_A_DQS_P<15>
DDR_A_DQS_N<15>
DDR_A_DQS_P<14>
DDR_A_DQS_N<14>
DDR_A_DQS_P<13>
DDR_A_DQS_N<13>
DDR_A_DQS_P<12>
DDR_A_DQS_N<12>
DDR_A_DQS_P<11>
DDR_A_DQS_N<11>
DDR_A_DQS_P<10>
DDR_A_DQS_N<10>
DDR_A_DQS_P<9>
DDR_A_DQS_N<9>
H7
K7
L10
L9
K10
K8
J5
K5
M9
N8
T5
P9
L6
L7
R5
R6
V5
W5
U10
W10
U7
V6
AA5
U9
AD5
AE5
AA9
AB10
AB7
AB8
AG5
AH4
AD17
AE16
AJ15
AE17
AD12
AE13
AF15
AF16
AG20
AJ18
AD21
AE22
AG18
AF19
AG21
AF21
AG24
AH25
AF27
AE28
AD23
AD24
AG26
AG27
AG29
AG30
AK33
AJ33
AF28
AH29
AH31
AK32
AH8
AJ7
J6
H6
P10
N10
Y7
Y6
AD8
AC7
AH14
AJ13
AE20
AE19
AF25
AF24
AL32
AL31
DDRA_DQ63
DDRA_DQ62
DDRA_DQ61
DDRA_DQ60
DDRA_DQ59
DDRA_DQ58
DDRA_DQ57
DDRA_DQ56
DDRA_DQ55
DDRA_DQ54
DDRA_DQ53
DDRA_DQ52
DDRA_DQ51
DDRA_DQ50
DDRA_DQ49
DDRA_DQ48
DDRA_DQ47
DDRA_DQ46
DDRA_DQ45
DDRA_DQ44
DDRA_DQ43
DDRA_DQ42
DDRA_DQ41
DDRA_DQ40
DDRA_DQ39
DDRA_DQ38
DDRA_DQ37
DDRA_DQ36
DDRA_DQ35
DDRA_DQ34
DDRA_DQ33
DDRA_DQ32
DDRA_DQ31
DDRA_DQ30
DDRA_DQ29
DDRA_DQ28
DDRA_DQ27
DDRA_DQ26
DDRA_DQ25
DDRA_DQ24
DDRA_DQ23
DDRA_DQ22
DDRA_DQ21
DDRA_DQ20
DDRA_DQ19
DDRA_DQ18
DDRA_DQ17
DDRA_DQ16
DDRA_DQ15
DDRA_DQ14
DDRA_DQ13
DDRA_DQ12
DDRA_DQ11
DDRA_DQ10
DDRA_DQ9
DDRA_DQ8
DDRA_DQ7
DDRA_DQ6
DDRA_DQ5
DDRA_DQ4
DDRA_DQ3
DDRA_DQ2
DDRA_DQ1
DDRA_DQ0
DDRA_DQS17
DDRA_DQS#17
DDRA_DQS16
DDRA_DQS#16
DDRA_DQS15
DDRA_DQS#15
DDRA_DQS14
DDRA_DQS#14
DDRA_DQS13
DDRA_DQS#13
DDRA_DQS12
DDRA_DQS#12
DDRA_DQS11
DDRA_DQS#11
DDRA_DQS10
DDRA_DQS#10
DDRA_DQS9
DDRA_DQS#9
2
DDRA_DQ[63..0] 24,25,26
DDRA_DQS[17..0] 24,25,26
DDRA_DQS#[17..0] 24,25,26
1
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
MCH DDR II CHANNEL A
GA-9ITDW-FJ
1
of
17 81Wednesday, October 13, 2004
1.3
5
DDRB_MA[13..0]27,28,29,30
D D
DDRB_CB[7..0]27,28,29
PLACE DDRB_MCH_VREF VOLTAGE
DIVIDER NEAR MCH
P1V8_AUX
C C
B B
A A
R166
20-MIL TRACE WIDTH,
75/1%
R167
75/1%
DDRB_MCH_VREF DDRB_MCH_VREF_R
12-MIL SPACING
DDRB_MCH_VREF
SC23
1U/6/X/10V
R168 0
SC24
0.1U/6/X/16V
MEM_CKE[7..0]17,24,25,26,27,28,29,30
DDRB_CMDCLK3_N30
DDRB_CMDCLK3_P30
DDRB_CMDCLK2_N27,30
DDRB_CMDCLK2_P27,30
DDRB_CMDCLK1_N28,30
DDRB_CMDCLK1_P28,30
DDRB_CMDCLK0_N29,30
DDRB_CMDCLK0_P29,30
DDRB_CS#[7..0]27,28,29,30
DDRB_WE#27,28,29,30
DDRB_RAS#27,28,29,30
DDRB_CAS#27,28,29,30
DDRB_BA[2..0]27,28,29,30
DDRB_DQS[17..0]27,28,29
DDRB_DQS#[17..0]27,28,29
4
DDRB_MA13
DDRB_MA12
DDRB_MA11
DDRB_MA10
DDRB_MA9
DDRB_MA8
DDRB_MA7
DDRB_MA6
DDRB_MA5
DDRB_MA4
DDRB_MA3
DDRB_MA2
DDRB_MA1
DDRB_MA0
DDRB_CB7
DDRB_CB6
DDRB_CB5
DDRB_CB4
DDRB_CB3
DDRB_CB2
DDRB_CB1
DDRB_CB0
MEM_CKE7
MEM_CKE6
MEM_CKE5
MEM_CKE4
DDRB_CMDCLK3_N
DDRB_CMDCLK3_P
DDRB_CMDCLK2_N
DDRB_CMDCLK2_P
DDRB_CMDCLK1_N
DDRB_CMDCLK1_P
DDRB_CMDCLK0_N
DDRB_CMDCLK0_P
DDRB_CS#7
DDRB_CS#6
DDRB_CS#5
DDRB_CS#4
DDRB_CS#3
DDRB_CS#2
DDRB_CS#1
DDRB_CS#0
DDRB_WE#
DDRB_RAS#
DDRB_CAS#
DDRB_BA2
DDRB_BA1
DDRB_BA0
DDRB_DQS8
DDRB_DQS#8
DDRB_DQS7
DDRB_DQS#7
DDRB_DQS6
DDRB_DQS#6
DDRB_DQS5
DDRB_DQS#5
DDRB_DQS4
DDRB_DQS#4
DDRB_DQS3
DDRB_DQS#3
DDRB_DQS2
DDRB_DQS#2
DDRB_DQS1
DDRB_DQS#1
DDRB_DQS0
DDRB_DQS#0
U3B
U4
DDR_B_MA<13>
AH23
DDR_B_MA<12>
AH22
DDR_B_MA<11>
AC4
DDR_B_MA<10>
AJ21
DDR_B_MA<9>
AL20
DDR_B_MA<8>
AD18
DDR_B_MA<7>
AG17
DDR_B_MA<6>
AH16
DDR_B_MA<5>
AD15
DDR_B_MA<4>
AK14
DDR_B_MA<3>
AN14
DDR_B_MA<2>
AE14
DDR_B_MA<1>
AF7
DDR_B_MA<0>
AL5
DDR_B_CB<7>
AN5
DDR_B_CB<6>
AK8
DDR_B_CB<5>
AN8
DDR_B_CB<4>
AL4
DDR_B_CB<3>
AM4
DDR_B_CB<2>
AL7
DDR_B_CB<1>
AM7
DDR_B_CB<0>
AH28
DDR_CKE<7>
AJ28
DDR_CKE<6>
AJ27
DDR_CKE<5>
AH26
DDR_CKE<4>
AL8
DDR_B_CMDCLK_N<3>
AK9
DDR_B_CMDCLK_P<3>
AE8
DDR_B_CMDCLK_N<2>
AG8
DDR_B_CMDCLK_P<2>
AG6
DDR_B_CMDCLK_N<1>
AH6
DDR_B_CMDCLK_P<1>
AJ6
DDR_B_CMDCLK_N<0>
AH7
DDR_B_CMDCLK_P<0>
L3
DDR_B_CS_N<7>
M6
DDR_B_CS_N<6>
M2
DDR_B_CS_N<5>
N4
DDR_B_CS_N<4>
P6
DDR_B_CS_N<3>
T7
DDR_B_CS_N<2>
V2
DDR_B_CS_N<1>
V9
DDR_B_CS_N<0>
W4
DDR_B_WE_N
Y9
DDR_B_RAS_N
W1
DDR_B_CAS_N
AN4
DDR_B_VREF
AM25
DDR_B_BA<2>
AE7
DDR_B_BA<1>
AA8
DDR_B_BA<0>
AK5
DDR_B_DQS_P<8>
AK6
DDR_B_DQS_N<8>
H3
DDR_B_DQS_P<7>
H1
DDR_B_DQS_N<7>
P1
DDR_B_DQS_P<6>
R2
DDR_B_DQS_N<6>
AA3
DDR_B_DQS_P<5>
AB4
DDR_B_DQS_N<5>
AG2
DDR_B_DQS_P<4>
AH2
DDR_B_DQS_N<4>
AK11
DDR_B_DQS_P<3>
AL11
DDR_B_DQS_N<3>
AK17
DDR_B_DQS_P<2>
AL17
DDR_B_DQS_N<2>
AM22
DDR_B_DQS_P<1>
AN23
DDR_B_DQS_N<1>
AM28
DDR_B_DQS_P<0>
AN29
DDR_B_DQS_N<0>
MCH 2/8
DDR GROUP B
TUMWATER
3
DDR_B_DQ<63>
DDR_B_DQ<62>
DDR_B_DQ<61>
DDR_B_DQ<60>
DDR_B_DQ<59>
DDR_B_DQ<58>
DDR_B_DQ<57>
DDR_B_DQ<56>
DDR_B_DQ<55>
DDR_B_DQ<54>
DDR_B_DQ<53>
DDR_B_DQ<52>
DDR_B_DQ<51>
DDR_B_DQ<50>
DDR_B_DQ<49>
DDR_B_DQ<48>
DDR_B_DQ<47>
DDR_B_DQ<46>
DDR_B_DQ<45>
DDR_B_DQ<44>
DDR_B_DQ<43>
DDR_B_DQ<42>
DDR_B_DQ<41>
DDR_B_DQ<40>
DDR_B_DQ<39>
DDR_B_DQ<38>
DDR_B_DQ<37>
DDR_B_DQ<36>
DDR_B_DQ<35>
DDR_B_DQ<34>
DDR_B_DQ<33>
DDR_B_DQ<32>
DDR_B_DQ<31>
DDR_B_DQ<30>
DDR_B_DQ<29>
DDR_B_DQ<28>
DDR_B_DQ<27>
DDR_B_DQ<26>
DDR_B_DQ<25>
DDR_B_DQ<24>
DDR_B_DQ<23>
DDR_B_DQ<22>
DDR_B_DQ<21>
DDR_B_DQ<20>
DDR_B_DQ<19>
DDR_B_DQ<18>
DDR_B_DQ<17>
DDR_B_DQ<16>
DDR_B_DQ<15>
DDR_B_DQ<14>
DDR_B_DQ<13>
DDR_B_DQ<12>
DDR_B_DQ<11>
DDR_B_DQ<10>
DDR_B_DQ<9>
DDR_B_DQ<8>
DDR_B_DQ<7>
DDR_B_DQ<6>
DDR_B_DQ<5>
DDR_B_DQ<4>
DDR_B_DQ<3>
DDR_B_DQ<2>
DDR_B_DQ<1>
DDR_B_DQ<0>
DDR_B_DQS_P<17>
DDR_B_DQS_N<17>
DDR_B_DQS_P<16>
DDR_B_DQS_N<16>
DDR_B_DQS_P<15>
DDR_B_DQS_N<15>
DDR_B_DQS_P<14>
DDR_B_DQS_N<14>
DDR_B_DQS_P<13>
DDR_B_DQS_N<13>
DDR_B_DQS_P<12>
DDR_B_DQS_N<12>
DDR_B_DQS_P<11>
DDR_B_DQS_N<11>
DDR_B_DQS_P<10>
DDR_B_DQS_N<10>
DDR_B_DQS_P<9>
DDR_B_DQS_N<9>
G2
G1
K4
L1
E1
F2
K1
K2
P4
P3
U1
U3
N2
N1
T1
T4
Y1
AA2
AD3
AD2
Y4
Y3
AC1
AC3
AF3
AG3
AK2
AK3
AF4
AF1
AJ4
AJ3
AL10
AM10
AM13
AL13
AM9
AN9
AM12
AK12
AL16
AM16
AM19
AL19
AM15
AN15
AM18
AK18
AK21
AL22
AK24
AL25
AM21
AN21
AN24
AM24
AK27
AL28
AM31
AK30
AM27
AN27
AN30
AM30
AM6
AN6
J3
J2
T2
R3
AB2
AB1
AJ1
AH1
AN12
AN11
AN18
AN17
AK23
AL23
AK29
AL29
DDRB_DQ63
DDRB_DQ62
DDRB_DQ61
DDRB_DQ60
DDRB_DQ59
DDRB_DQ58
DDRB_DQ57
DDRB_DQ56
DDRB_DQ55
DDRB_DQ54
DDRB_DQ53
DDRB_DQ52
DDRB_DQ51
DDRB_DQ50
DDRB_DQ49
DDRB_DQ48
DDRB_DQ47
DDRB_DQ46
DDRB_DQ45
DDRB_DQ44
DDRB_DQ43
DDRB_DQ42
DDRB_DQ41
DDRB_DQ40
DDRB_DQ39
DDRB_DQ38
DDRB_DQ37
DDRB_DQ36
DDRB_DQ35
DDRB_DQ34
DDRB_DQ33
DDRB_DQ32
DDRB_DQ31
DDRB_DQ30
DDRB_DQ29
DDRB_DQ28
DDRB_DQ27
DDRB_DQ26
DDRB_DQ25
DDRB_DQ24
DDRB_DQ23
DDRB_DQ22
DDRB_DQ21
DDRB_DQ20
DDRB_DQ19
DDRB_DQ18
DDRB_DQ17
DDRB_DQ16
DDRB_DQ15
DDRB_DQ14
DDRB_DQ13
DDRB_DQ12
DDRB_DQ11
DDRB_DQ10
DDRB_DQ9
DDRB_DQ8
DDRB_DQ7
DDRB_DQ6
DDRB_DQ5
DDRB_DQ4
DDRB_DQ3
DDRB_DQ2
DDRB_DQ1
DDRB_DQ0
DDRB_DQS17
DDRB_DQS#17
DDRB_DQS16
DDRB_DQS#16
DDRB_DQS15
DDRB_DQS#15
DDRB_DQS14
DDRB_DQS#14
DDRB_DQS13
DDRB_DQS#13
DDRB_DQS12
DDRB_DQS#12
DDRB_DQS11
DDRB_DQS#11
DDRB_DQS10
DDRB_DQS#10
DDRB_DQS9
DDRB_DQS#9
2
DDRB_DQ[63..0] 27,28,29
DDRB_DQS[17..0] 27,28,29
DDRB_DQS#[17..0] 27,28,29
1
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
MCH DDR II CHANNEL B
GA-9ITDW-FJ
1
of
18 81Wednesday, October 13, 2004
1.3
5
SB_ADS#9,13
SB_AP#19,13
SB_AP#09,13
SB_MCERR#9,11,13
SB_BNR#9,11,13
SB_BPRI#9,13
MCH_BREQ#112
MCH_BREQ#012
D D
SB_DP#[3..0]9,13
SB_DBI#[3..0]9,13
SB_D#[63..0]9,13
C C
B B
SB_CPURST#9,11,13,16
SB_DBSY#9,13
SB_DEFER#9,13
SB_DRDY#9,13
SB_ADS#
SB_AP#1
SB_AP#0
SB_MCERR#
SB_BNR#
SB_BPRI#
MCH_BREQ#1
MCH_BREQ#0
SB_CPURST#
SB_DBSY#
SB_DEFER#
SB_DRDY#
SB_DP#3
SB_DP#2
SB_DP#1
SB_DP#0
SB_DBI#3
SB_DBI#2
SB_DBI#1
SB_DBI#0
SB_D#63
SB_D#62
SB_D#61
SB_D#60
SB_D#59
SB_D#58
SB_D#57
SB_D#56
SB_D#55
SB_D#54
SB_D#53
SB_D#52
SB_D#51
SB_D#50
SB_D#49
SB_D#48
SB_D#47
SB_D#46
SB_D#45
SB_D#44
SB_D#43
SB_D#42
SB_D#41
SB_D#40
SB_D#39
SB_D#38
SB_D#37
SB_D#36
SB_D#35
SB_D#34
SB_D#33
SB_D#32
SB_D#31
SB_D#30
SB_D#29
SB_D#28
SB_D#27
SB_D#26
SB_D#25
SB_D#24
SB_D#23
SB_D#22
SB_D#21
SB_D#20
SB_D#19
SB_D#18
SB_D#17
SB_D#16
SB_D#15
SB_D#14
SB_D#13
SB_D#12
SB_D#11
SB_D#10
SB_D#9
SB_D#8
SB_D#7
SB_D#6
SB_D#5
SB_D#4
SB_D#3
SB_D#2
SB_D#1
SB_D#0
G25
G11
G10
G13
G14
G16
G17
B27
H25
H24
B31
A28
D29
F24
J24
H27
B28
B30
F27
E25
E28
C29
A5
F9
E15
D16
C5
D7
C6
D5
B3
A4
B4
E7
B7
B6
C8
B9
C9
A11
A10
B10
H12
K13
J12
F8
H10
D8
F12
E9
D11
F11
H13
C11
E12
K14
H16
K16
F15
F14
J14
J17
E16
K17
F17
H18
J18
E18
B12
C12
D14
A13
A14
B13
A16
D17
B18
C17
B16
A19
A17
C14
B19
C18
U3C
ADS_N
AP_N<1>
AP_N<0>
MCERR_N
BNR_N
BPRI_N
BREQ_N<1>
BREQ_N<0>
CPURST_N
DBSY_N
DEFER_N
DRDY_N
DP_N<3>
DP_N<2>
DP_N<1>
DP_N<0>
DBI_N<3>
DBI_N<2>
DBI_N<1>
DBI_N<0>
HD_N<63>
HD_N<62>
HD_N<61>
HD_N<60>
HD_N<59>
HD_N<58>
HD_N<57>
HD_N<56>
HD_N<55>
HD_N<54>
HD_N<53>
HD_N<52>
HD_N<51>
HD_N<50>
HD_N<49>
HD_N<48>
HD_N<47>
HD_N<46>
HD_N<45>
HD_N<44>
HD_N<43>
HD_N<42>
HD_N<41>
HD_N<40>
HD_N<39>
HD_N<38>
HD_N<37>
HD_N<36>
HD_N<35>
HD_N<34>
HD_N<33>
HD_N<32>
HD_N<31>
HD_N<30>
HD_N<29>
HD_N<28>
HD_N<27>
HD_N<26>
HD_N<25>
HD_N<24>
HD_N<23>
HD_N<22>
HD_N<21>
HD_N<20>
HD_N<19>
HD_N<18>
HD_N<17>
HD_N<16>
HD_N<15>
HD_N<14>
HD_N<13>
HD_N<12>
HD_N<11>
HD_N<10>
HD_N<9>
HD_N<8>
HD_N<7>
HD_N<6>
HD_N<5>
HD_N<4>
HD_N<3>
HD_N<2>
HD_N<1>
HD_N<0>
4
MCH 3/8
SYSTEM BUS
HDSTBN<3>
HDSTBP<3>
HDSTBN<2>
HDSTBP<2>
HDSTBN<1>
HDSTBP<1>
HDSTBN<0>
HDSTBP<0>
HIT_N
HITM_N
HLOCK_N
HTRDY_N
HREQ_N<4>
HREQ_N<3>
HREQ_N<2>
HREQ_N<1>
HREQ_N<0>
TESTIN_N
RSTIN_N
HCRES0
HODTCRES
HSLWCRES
HDVREF<1>
HDVREF<0>
HACVREF
HA_N<35>
HA_N<34>
HA_N<33>
HA_N<32>
HA_N<31>
HA_N<30>
HA_N<29>
HA_N<28>
HA_N<27>
HA_N<26>
HA_N<25>
HA_N<24>
HA_N<23>
HA_N<22>
HA_N<21>
HA_N<20>
HA_N<19>
HA_N<18>
HA_N<17>
HA_N<16>
HA_N<15>
HA_N<14>
HA_N<13>
HA_N<12>
HA_N<11>
HA_N<10>
HA_N<9>
HA_N<8>
HA_N<7>
HA_N<6>
HA_N<5>
HA_N<4>
HA_N<3>
HCLKINN
HCLKINP
HADSTB_N<1>
HADSTB_N<0>
RS_N<2>
RS_N<1>
RS_N<0>
RSP_N
BINIT_N
PME_N
GPE_N
A8
A7
D10
E10
H15
J15
B15
C15
E30
D28
C30
A30
K23
H22
J23
J21
K20
L12
C2
SB_CRES0_MCH
C27
SB_ODTCRES0_MCH
E27
SB_SLWCRES0_MCH
F26
E13
D13
F23
D20
C21
C20
D19
A20
B24
A23
D23
B21
A22
C24
D25
B25
A25
B22
D22
A26
C26
D26
F20
F21
E19
F18
E21
E22
G19
H19
K19
H21
G22
G23
J20
K22
MCH_BCLK#
J11
MCH_BCLK
K11
C23
G20
G28
D31
F29
J26
G26
M24
L25
SB_DSTBN#3
SB_DSTBP#3
SB_DSTBN#2
SB_DSTBP#2
SB_DSTBN#1
SB_DSTBP#1
SB_DSTBN#0
SB_DSTBP#0
SB_HIT#
SB_HITM#
SB_LOCK#
SB_TRDY#
SB_REQ#4
SB_REQ#3
SB_REQ#2
SB_REQ#1
SB_REQ#0
MCH_TESTIN#
PCIRST#
MCH_SB_VREF
SB_HA#35
SB_HA#34
SB_HA#33
SB_HA#32
SB_HA#31
SB_HA#30
SB_HA#29
SB_HA#28
SB_HA#27
SB_HA#26
SB_HA#25
SB_HA#24
SB_HA#23
SB_HA#22
SB_HA#21
SB_HA#20
SB_HA#19
SB_HA#18
SB_HA#17
SB_HA#16
SB_HA#15
SB_HA#14
SB_HA#13
SB_HA#12
SB_HA#11
SB_HA#10
SB_HA#9
SB_HA#8
SB_HA#7
SB_HA#6
SB_HA#5
SB_HA#4
SB_HA#3
SB_ADSTB#1
SB_ADSTB#0
SB_RS#2
SB_RS#1
SB_RS#0
SB_RSP#
SB_BINIT#
MCHPME#
MCHGPE#
3
SB_HIT# 9,11,13
SB_HITM# 9,11,13
SB_LOCK# 9,13
SB_TRDY# 9,13
SB_REQ#[4..0] 9,13
TP40
PCIRST# 34,36,48,50,53,54,55,56
SB_HA#[35..3] 9,13
MCH_BCLK# 31
MCH_BCLK 31
SB_RSP# 9,13
SB_BINIT# 9,11,13
MCHPME# 16,53
MCHGPE# 51,53
SB_ADSTB#[1..0] 9,13
SB_RS#[2..0] 9,13
SB_DSTBN#[3..0] 9,13
SB_DSTBP#[3..0] 9,13
2
R169:change from 49.9 to 48.7
ohm/ 1% (2004 WW12 eMOW)
SB_CRES0_MCH
R169
SB_ODTCRES0_MCH
SB_SLWCRES0_MCH
MCH_SB_VREF
PLACE NEAR
PIN E13
WW37 eMOW: The MCH_BREQ[1:0] signals should only be
terminated at processor 0, the MCH provides internal termination.
MCH_BREQ#1
MCH_BREQ#0
MCHGPE#
R172
0
SC25
220P/6/X/50V
R174
51/X
R175
51/X
R176
8.2K
48.7/1%
MCH_SB_VREF_R
C23
1U/6/X/10V
R170
442/1%
A0 silicon: 374 ohm/ 1%
B0 silicon: 549 ohm/ 1%
442 ohm/ 1% (2004 WW12 eMOW)
P_VTT
R171
49.9/1%
754mV
R173
90.9/1%
R173: change from 84.5 to 90.9
ohm/ 1% (2004 WW12 eMOW)
P_VTT
P3V3
1
TUMWATER
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
MCH SYS BUS
GA-9ITDW-FJ
1
of
19 81Wednesday, October 13, 2004
1.3
5
U3D
D D
C C
B B
EXP_A_RXP[7..4]35
EXP_A_RXP[3..0]35
EXP_A_RXN[7..4]35
EXP_A_RXN[3..0]35
EXP_B_RXP[7..4]34
EXP_B_RXP[3..0]34
EXP_B_RXN[7..4]34
EXP_B_RXN[3..0]34
EXP_B_RXP[15..12]34
EXP_B_RXP[11..8]34
EXP_B_RXN[15..12]34
EXP_B_RXN[11..8]34
MCH_SRC_100MHZ_CLK_N33
MCH_SRC_100MHZ_CLK_P33
EXP_A_RXP7
EXP_A_RXP6
EXP_A_RXP5
EXP_A_RXP4
EXP_A_RXP3
EXP_A_RXP2
EXP_A_RXP1
EXP_A_RXP0
EXP_A_RXN7
EXP_A_RXN6
EXP_A_RXN5
EXP_A_RXN4
EXP_A_RXN3
EXP_A_RXN2
EXP_A_RXN1
EXP_A_RXN0
EXP_B_RXP7
EXP_B_RXP6
EXP_B_RXP5
EXP_B_RXP4
EXP_B_RXP3
EXP_B_RXP2
EXP_B_RXP1
EXP_B_RXP0
EXP_B_RXN7
EXP_B_RXN6
EXP_B_RXN5
EXP_B_RXN4
EXP_B_RXN3
EXP_B_RXN2
EXP_B_RXN1
EXP_B_RXN0
EXP_B_RXP15
EXP_B_RXP14
EXP_B_RXP13
EXP_B_RXP12
EXP_B_RXP11
EXP_B_RXP10
EXP_B_RXP9
EXP_B_RXP8
EXP_B_RXN15
EXP_B_RXN14
EXP_B_RXN13
EXP_B_RXN12
EXP_B_RXN11
EXP_B_RXN10
EXP_B_RXN9
EXP_B_RXN8
MCH_SRC_100MHZ_CLK_N
MCH_SRC_100MHZ_CLK_P
AB26
AC25
AD29
AC31
AC30
AE32
AG33
AB25
AC24
AE29
AB31
AD30
AD32
AF33
AA30
AA29
K29
M27
N25
R26
N28
R33
K28
M26
N26
R27
N29
P33
Y25
Y24
V24
V27
R30
T32
V33
Y30
Y28
U24
V26
R29
T31
V32
Y31
Y27
R24
T23
J33
L31
J32
L30
EXP_A_RXP<7>
EXP_A_RXP<6>
EXP_A_RXP<5>
EXP_A_RXP<4>
EXP_A_RXP<3>
EXP_A_RXP<2>
EXP_A_RXP<1>
EXP_A_RXP<0>
EXP_A_RXN<7>
EXP_A_RXN<6>
EXP_A_RXN<5>
EXP_A_RXN<4>
EXP_A_RXN<3>
EXP_A_RXN<2>
EXP_A_RXN<1>
EXP_A_RXN<0>
EXP_B_RXP<7>
EXP_B_RXP<6>
EXP_B_RXP<5>
EXP_B_RXP<4>
EXP_B_RXP<3>
EXP_B_RXP<2>
EXP_B_RXP<1>
EXP_B_RXP<0>
EXP_B_RXN<7>
EXP_B_RXN<6>
EXP_B_RXN<5>
EXP_B_RXN<4>
EXP_B_RXN<3>
EXP_B_RXN<2>
EXP_B_RXN<1>
EXP_B_RXN<0>
EXP_B_RXP<15>
EXP_B_RXP<14>
EXP_B_RXP<13>
EXP_B_RXP<12>
EXP_B_RXP<11>
EXP_B_RXP<10>
EXP_B_RXP<9>
EXP_B_RXP<8>
EXP_B_RXN<15>
EXP_B_RXN<14>
EXP_B_RXN<13>
EXP_B_RXN<12>
EXP_B_RXN<11>
EXP_B_RXN<10>
EXP_B_RXN<9>
EXP_B_RXN<8>
EXP_CLK_N
EXP_CLK_P
4
MCH 4/8
PCI EXPRESS
EXP_A_TXP<7>
EXP_A_TXP<6>
EXP_A_TXP<5>
EXP_A_TXP<4>
EXP_A_TXP<3>
EXP_A_TXP<2>
EXP_A_TXP<1>
EXP_A_TXP<0>
EXP_A_TXN<7>
EXP_A_TXN<6>
EXP_A_TXN<5>
EXP_A_TXN<4>
EXP_A_TXN<3>
EXP_A_TXN<2>
EXP_A_TXN<1>
EXP_A_TXN<0>
EXP_B_TXP<7>
EXP_B_TXP<6>
EXP_B_TXP<5>
EXP_B_TXP<4>
EXP_B_TXP<3>
EXP_B_TXP<2>
EXP_B_TXP<1>
EXP_B_TXP<0>
EXP_B_TXN<7>
EXP_B_TXN<6>
EXP_B_TXN<5>
EXP_B_TXN<4>
EXP_B_TXN<3>
EXP_B_TXN<2>
EXP_B_TXN<1>
EXP_B_TXN<0>
EXP_B_TXP<15>
EXP_B_TXP<14>
EXP_B_TXP<13>
EXP_B_TXP<12>
EXP_B_TXP<11>
EXP_B_TXP<10>
EXP_B_TXP<9>
EXP_B_TXP<8>
EXP_B_TXN<15>
EXP_B_TXN<14>
EXP_B_TXN<13>
EXP_B_TXN<12>
EXP_B_TXN<11>
EXP_B_TXN<10>
EXP_B_TXN<9>
EXP_B_TXN<8>
EXPCOMP<1>
EXPCOMP<0>
EXPHPINTR_N
TUMWATER
P3V3
VCCBGEXP
VSSBGEXP
L28
M30
P27
P24
K32
M33
N31
P30
L27
M29
P28
P25
K31
M32
N32
P31
AA27
AB29
AC27
AD27
AB32
AC33
AF31
AG32
AA26
AB28
AC28
AD26
AA32
AD33
AE31
AH32
T26
T29
V30
U31
W32
Y33
W28
W26
T25
T28
V29
U30
W31
AA33
W29
W25
U25
U33
E6
U27
U28
EXP_A_TXP_C7
EXP_A_TXP_C6
EXP_A_TXP_C5
EXP_A_TXP_C4
EXP_A_TXP_C3
EXP_A_TXP_C2
EXP_A_TXP_C1
EXP_A_TXP_C0
EXP_A_TXN_C7
EXP_A_TXN_C6
EXP_A_TXN_C5
EXP_A_TXN_C4
EXP_A_TXN_C3
EXP_A_TXN_C2
EXP_A_TXN_C1
EXP_A_TXN_C0
EXP_B_TXP_C7
EXP_B_TXP_C6
EXP_B_TXP_C5
EXP_B_TXP_C4
EXP_B_TXP_C3
EXP_B_TXP_C2
EXP_B_TXP_C1
EXP_B_TXP_C0
EXP_B_TXN_C7
EXP_B_TXN_C6
EXP_B_TXN_C5
EXP_B_TXN_C4
EXP_B_TXN_C3
EXP_B_TXN_C2
EXP_B_TXN_C1
EXP_B_TXN_C0
EXP_B_TXP_C15
EXP_B_TXP_C14
EXP_B_TXP_C13
EXP_B_TXP_C12
EXP_B_TXP_C11
EXP_B_TXP_C10
EXP_B_TXP_C9
EXP_B_TXP_C8
EXP_B_TXN_C15
EXP_B_TXN_C14
EXP_B_TXN_C13
EXP_B_TXN_C12
EXP_B_TXN_C11
EXP_B_TXN_C10
EXP_B_TXN_C9
EXP_B_TXN_C8
MCH_EXPCOMP
TP_MCH_E6
MCH_VCCBGEXP
3
EXP_A_TXP_C[7..4] 35
EXP_A_TXP_C[3..0] 35
EXP_A_TXN_C[7..4] 35
EXP_A_TXN_C[3..0] 35
EXP_B_TXP_C[7..4] 35
EXP_B_TXP_C[3..0] 35
EXP_B_TXN_C[7..4] 35
EXP_B_TXN_C[3..0] 35
EXP_B_TXP_C[15..12] 35
EXP_B_TXP_C[11..8] 35
EXP_B_TXN_C[15..12] 35
EXP_B_TXN_C[11..8] 35
P1V5 P3V3
R177
24.9/1%
R178
FOR PCI EXPRESS HOT
SWAP FUNCTION ENABLE
P.U: ENABLE
1K/X
N.C: DISABLE
2
1
R179
NEEDS TO BE REPLACED WITH 160 OHMS 5% 0603 RESISTOR
162/1%
2.5V
+/-3%
14.3K/1% if 431
Vref = 1.24
A A
5
U9
LM431BCM3
A C
R
MCH _BG_REF
603mV
R180
0
R181
14K/1%/X
4
C24
12
10U/8/X/6.3V
MCH_VCCBGEXP
SC26
0.1U/6/X/16V
VIA @ SC26 FOR GROUND. THEN ROUTE THE GROUND TO MCH(U3)
PIN-U28 WITH MCH_VCCBGEXP DIFFERENTIALLY. ROUTE GND
TRACE WITH MINIMUM 10-MIL WIDTH TO MCH PIN-U28
3
Title
Size Document Number Rev
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
MCH PCI EXPRESS
GA-9ITDW-FJ
1
of
20 81Wednesday, October 13, 2004
1.3
5
MCH_66MHZ_CLK
SC762
27P/4/N/50V/X
P1V5 P3V3
Place near SC27
D D
C C
P1V8_AUX
D25
1 2
1N5817
SYS_PWR_GD_3_3V
SC28
100P/6/N/50V/X
R186
40.2/1%
R188
40.2/1%
DDRRES1
SC29
0.1U/6/X/16V
DDRRES2
SC30
0.1U/6/X/16V
SYS_PWR_GD_3_3V32,36,51,55
MCH_SMBCLK16,31,33,36,56,72
MCH_SMBDAT16,31,33,36,56,72
Place very close to ball L24
HIA_STRBS50
HIA_STRBF50
MCH_66MHZ_CLK32
ITP_TMS_MCH16
ITP_TDI_MCH16
ITP_TDO_MCH16
ITP_TCK116
ITP_TRST#9,13,16
20-MIL WIDE,
12-MIL SPACING
TP41
TP42
TP43
TP44
TP45
TP46
TP47
TP48
4
HIA_STRBS
HIA_STRBF
MCH_HI_VSWING
MCH_66MHZ_CLK
MCH_HI_VREF
SYS_PWR_GD_3_3V
MCH_SMBCLK
MCH_SMBDAT
ITP_TMS_MCH
ITP_TDI_MCH
ITP_TDO_MCH
ITP_TCK1
ITP_TRST#
DDRRES1
DDRRES2
TP_RESERVED2
TP_RESERVED3
TP_RESERVED4
TP_RESERVED5
TP_RESERVED6
TP_RESERVED7
TP_RESERVED8
TP_RESERVED9
D32
H31
AE2
AE1
AF30
AE23
AD20
AJ19
R10
E31
L24
K25
F32
E3
C3
D4
F3
G5
G6
D2
R9
R8
M8
J9
U3E
HI_STBS
HI_STBF
HISWING
HICLK
HIRCOMP
HIVREF
PWRGD
SMBCLK
SMBDATA
TMS
TDI
TDO
TCK
TRST
DDRRES1
DDRRES2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MCH 5/8
SYSTEM BUS
TUMWATER
V3REF
DDRSLWCRES
DDRCRES0
DDRIMPCRES
PLLSEL1_N
PLLSEL0_N
HI<11>
HI<10>
HI<9>
HI<8>
HI<7>
HI<6>
HI<5>
HI<4>
HI<3>
HI<2>
HI<1>
HI<0>
DEBUG<7>
DEBUG<6>
DEBUG<5>
DEBUG<4>
DEBUG<3>
DEBUG<2>
DEBUG<1>
DEBUG<0>
TDIOCATHODE
TDIOANODE
RESERVED
RESERVED
RESERVED
P3V3
H33
MCH_DDRSLWCRES
AK1
MCH_DDRCRES0
AC9
MCH_DDRIMPCRES
AL2
A29
C31
G32
J29
E33
F30
J27
K26
H28
G29
G31
C32
H30
J30
ITP_MCH_DEBUG7
D1
ITP_MCH_DEBUG6
L11
ITP_MCH_DEBUG5
D3
ITP_MCH_DEBUG4
B2
ITP_MCH_DEBUG3
H9
ITP_MCH_DEBUG2
G8
ITP_MCH_DEBUG1
G7
ITP_MCH_DEBUG0
J8
F33
D33
AA24
R32
L33
3
SC27
0.1U/6/X/16V
MCH_PLLSEL1#
MCH_PLLSEL0#MCH_HI_RCOMP
HI_A11
HI_A10
HI_A9
HI_A8
HI_A7
HI_A6
HI_A5
HI_A4
HI_A3
HI_A2
HI_A1
HI_A0
MCH_TDC
MCH_TDA
TP_RESERVED10
TP_RESERVED11
TP_RESERVED12
R183 change value from 825 ohm to 1050 ohm
+/-1%, for MCH drives excessive s l e w r a t e
problem( sighting report item 59)
R183 change value to 976 ohm +/-1% (04
WW14 MOW)
R183 976/1%
R184 287/8/1%
MCH_TDC 15
MCH_TDA 15
TP49
TP50
TP51
20-MIL WIDE,
12-MIL SPACING
HI_A[11..0] 50
ITP_MCH_DEBUG[7..0] 16
2
WW31 MOW: PLLSEL[1:0] input pins have integrated on-die pull-ups
and should not be actively driven or pull high by the platform.Rather
,they should be left floating when electrical high is desired.
P1V5
R187
1K/X
R189
0
FSB Speed Memory
533 MHz
667 MHz
800 MHz
DDR266
DDR333
DDRII 400
DDR266
DDR333
DDRII 400
DDR266
DDR333
DDRII 400
1
MCH_PLLSEL1#MCH_PLLSEL0#
PLLSEL0# PLLSEL1#
LO
LO
LO
HI
LO
LO
HI
LO
LO
HI
LO
HI
HI
HI
HI
HI
LO
LO
P1V5
R182
1K/X
R185
0
HUB INTERFACE VREF CIRCUITS MCH HEATSINK RETENTION CLIP
P1V5
B B
354mV
+/- 2%
20MILS
A A
R190
43.2/1%
MCH_HI_RCOMP
P1V5 P1V5
R191
78.7/1%
MCH_VREF_DIV
R194
24/1%
Intel recommands
of 24.3 OHM/1%
5
R193
0
MCH_HI_VREF
SC31
0.01U/6/X/50V
804mV
+/-2%
20MILS
R192
43.2/1%
R195
49.9/1%
4
HS1
1
2
MCH HEATSINK
PLACE CAP WITHIN 0.25" OF MCHPLACE CAP WITHIN 0.25" OF MCH
MCH_HI_VSWING
SC32
0.01U/6/X/50V
3
2
J5
1
2
MRN H1X2/X
J6
1
2
MRN H1X2/X
Title
Size Document Number Rev
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
MCH HI 1.5 AND MISC.
GA-9ITDW-FJ
1
of
21 81Wednesday, October 13, 2004
1.3
5
P1V8_AUX
D D
C C
P1V5
B B
AN28
AN22
AN16
AN10
AL30
AL24
AL18
AL12
AN3
AJ26
AJ20
AJ14
AH3
AG28
AG22
AG16
AG10
AF5
AE24
AE18
AE12
AD7
AD1
AC23
AC21
AC19
AC17
AC15
AC13
AC11
AB22
AB20
AB18
AB16
AB14
AB12
AB9
AB3
AA11
W11
U11
R11
N11
AH33
AE33
AE30
AC29
AB33
AB27
AB24
AA23
W33
W27
W23
U29
R23
N33
M28
U3F
VCCDDR
VCCDDR
VCCDDR
VCCDDR
AL1
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
AL6
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
AJ8
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
VCCDDR
Y12
VCCDDR
Y5
VCCDDR
VCCDDR
V12
VCCDDR
V7
VCCDDR
V1
VCCDDR
VCCDDR
T12
VCCDDR
T9
VCCDDR
T3
VCCDDR
VCCDDR
P12
VCCDDR
P5
VCCDDR
VCCDDR
M1
VCCDDR
K3
VCCDDR
H5
VCCDDR
F1
VCCDDR
M7
VCCDDR
VCCEXP
VCCEXP
VCCEXP
VCCEXP
VCCEXP
VCCEXP
VCCEXP
VCCEXP
Y29
VCCEXP
Y22
VCCEXP
VCCEXP
VCCEXP
VCCEXP
V22
VCCEXP
VCCEXP
T33
VCCEXP
T27
VCCEXP
T24
VCCEXP
T22
VCCEXP
VCCEXP
P29
VCCEXP
VCCEXP
VCCEXP
K33
VCCEXP
K30
VCCEXP
MCH 6/8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA_CORE
VCCA_DDR
VCCA_EXP
VCCA_HI
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
AA21
AA19
AA17
AA15
AA13
Y20
Y18
Y16
Y14
W21
W19
W17
W15
W13
V20
V18
V16
V14
U21
U19
U17
U15
T20
T18
T16
T14
R21
R19
R17
R15
R13
P18
P16
P14
N21
N19
N17
N15
N13
U13
C33
P22
N23
L23
K27
H29
G33
K9
M12
M22
M20
M18
M16
M14
L21
L19
L17
L15
L13
J19
J16
J13
H26
H23
E23
E20
E17
E14
E11
E8
D30
D27
A31
A18
A15
A12
A9
A6
A3
F6
E4
U23
P20
P1V5
VCCA_SB
VCCA_DDR
VCCA_EXP
VCCA_HI
P_VTT
4
VCCA_SB 23
VCCA_DDR 23
VCCA_EXP 23
VCCA_HI 23
Y13
Y11
W30
W24
W22
W20
W18
W16
W14
W12
V31
V28
V25
V21
V19
V17
V15
V13
V11
V10
U32
AB6
AA31
AA28
AA25
AA22
AA20
AA18
AA16
AA14
AA12
AA10
AA7
AB23
AB21
AB19
AB17
AB15
AB13
AN31
AN25
AN19
AN13
AN7
AM32
AM29
AM26
AM23
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL33
AL27
AL21
AL15
AL9
AL3
AK31
AK28
AK25
AK22
AK19
AK16
AG13
E24
3
U3G
MCH 7/8
AF29
VSS
VSS
Y8
VSS
Y2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
W9
VSS
W6
VSS
W3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TUMWATER
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA_CORE
VSSAHI
VSSA_EXP
AF26
AF23
AF20
AF17
AF14
AF11
AF8
AF2
AE27
AE21
AE15
AE9
AE6
AE3
AD31
AD28
AD25
AD22
AD19
AD16
AD13
AD10
AD4
AC32
AC26
AC22
AC20
AC18
AC16
AC14
AC12
AC8
AC5
AC2
AB30
AK7
AK4
AJ32
AJ29
AJ17
AJ11
AJ5
AJ23
AJ2
AH30
AH27
AH24
AH21
AH18
AH15
AH12
AH9
AG31
AG25
AG19
AG1
AF32
AA4
AA1
Y32
Y26
Y23
Y21
Y19
Y17
Y15
AB11
AK10
AK13
U26
U22
U20
F5
P21
V23
VSSA_SB
VSSA_HI
VSSA_EXP
VSSA_SB 23
VSSA_HI 23
VSSA_EXP 23
2
U3H
1
MCH 8/8
M13
M11
M10
AG4
AG7
VSS
VSS
VSS
M4
VSS
L32
VSS
L29
VSS
L26
VSS
L22
VSS
L20
VSS
L18
VSS
L16
VSS
L14
VSS
L8
VSS
L5
VSS
L2
VSS
K24
VSS
K21
VSS
K18
VSS
K15
VSS
K12
VSS
K6
VSS
J31
VSS
J28
VSS
J25
VSS
J22
VSS
J10
VSS
J7
VSS
J4
VSS
J1
VSS
H32
VSS
H20
VSS
H17
VSS
H14
VSS
H11
VSS
VSS
VSS
U18
VSS
U16
VSS
U14
VSS
U12
VSS
U8
VSS
U5
VSS
U2
VSS
T30
VSS
T21
VSS
T19
VSS
T17
VSS
T15
VSS
T11
VSS
T13
VSS
T6
VSS
R31
VSS
R28
VSS
R25
VSS
R22
VSS
R20
VSS
R18
VSS
R16
VSS
R14
VSS
R12
VSS
R7
VSS
R4
VSS
R1
VSS
P32
VSS
P26
VSS
P23
VSS
P19
VSS
P17
VSS
P15
VSS
N22
VSS
N20
VSS
N18
VSS
N16
VSS
N14
VSS
TUMWATER
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F16
F13
F10
F7
F4
H8
H2
G30
G27
G21
G18
G15
G12
G9
G3
F31
F28
G24
F25
F22
F19
N3
M31
M25
M23
M21
M19
M17
M15
N6
E32
E29
E26
E5
E2
D24
D21
D18
D15
D12
D9
D6
B32
C28
C25
C22
C19
C16
C13
C10
C7
C4
C1
B29
B26
B23
B20
B17
B14
B11
B8
B5
A27
A24
A21
P13
P11
P8
P2
N30
N27
N24
N12
N9
TUMWATER
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
MCH POWER / GROUND
GA-9ITDW-FJ
1
of
22 81Wednesday, October 13, 2004
1.3
SC201
1U/6/X/10V
SC206
1U/6/X/10V
SC212
1U/6/X/10V
5
SC203
0.1U/6/X/16V
SC209
1U/6/X/10V
SC215
1U/6/X/10V
SC220
1U/6/X/10V
SC207
1U/6/X/10V
SC213
1U/6/X/10V
SC218
1U/6/X/10V
SC202
1U/6/X/10V
SC208
1U/6/X/10V
SC214
1U/6/X/10V
SC219
1U/6/X/10V
P1V5
D D
1.5V DECOUPLING
C C
P1V5
SC33
0.1U/6/X/16V
SC41
0.1U/6/X/16V
SC42
1000P/6/X/50V
SC44
0.1U/6/X/16V
TOPSIDE CAPS
SC48
0.1U/6/X/16V
SC204
1U/6/X/10V
SC210
1U/6/X/10V
SC216
1U/6/X/10V
SC221
1U/6/X/10V
SC51
0.1U/6/X/16V
4
SC205
1U/6/X/10V
SC211
1U/6/X/10V
SC217
1U/6/X/10V
SC55
0.1U/6/X/16V
3
VCCA_HI
VCCA_EXP
VCCA_DDR
VCCA_SB
VCCVGHS
PLACE COMPONENTS:
GROUP ASSOCIATE COMPONENTS
TOGHTER AND AS PHYSICALLY
CLOSE TO ASSOCIATED PIN AS
POSSIBLE WITH 1ST
AND 2ND CAPS <=1"
AND 1ST CAPS <=1" FROM PIN
MIN TRACE WIDTH:
AS WIDE AS POSSIBLE
>= 10-12 MILS
MIN TRACE SPACING:
>= 10 MILS
2
P1V5
R196
VCCAHI_R_N VCCA_HI
1/1%
P1V5
R197
1/1%
P1V5
R198
VCCA_SB_R_N VCCA_SB
1/1%
P1V5
R199
1/1%
Intel recommands of 0.5 OHM/1%
L5 4.7UH/8
L6 4.7UH/8
L7 4.7UH/8
L8 4.7UH/8
12
C31
10U/8/X/6.3V
12
C25
10U/8/X/6.3V
12
C27
10U/8/X/6.3V
12
C29
10U/8/X/6.3V
12
C32
10U/8/X/6.3V
C26
0.1U/6/X/16V
C28
0.1U/6/X/16V
C30
0.1U/6/X/16V
1
VSSA_HI
VCCA_DDRVCCADDR_R_N
VSSA_SB
VSSA_SB
VCCA_EXPVCCA_EXP_R_N
C33
0.1U/6/X/16V
VSSA_EXP
VCCA_HI 22
VSSA_HI 22
VCCA_DDR 22
VSSA_SB 22
VCCA_SB 22
VSSA_SB 22
VCCA_EXP 22
VSSA_EXP 22
1.5V DECOUPLING
BACKSIDE CAPS
P_VTT
C39
B B
P1V8_AUX
A A
22U/1206/X/6.3V
C926
0.1U/6/X/16V
C938
0.1U/6/X/16V
SC77
0.1U/6/X/16V
C40
22U/1206/X/6.3V
C927
0.1U/6/X/16V
C939
0.1U/6/X/16V
SC78
0.1U/6/X/16V
5
SC56
1U/6/X/10V
C928
0.1U/6/X/16V
C940
0.1U/6/X/16V
SC79
0.1U/6/X/16V
SC57
0.1U/6/X/16V
C929
0.1U/6/X/16V
C941
0.1U/6/X/16V
SC80
0.1U/6/X/16V
SC58
0.1U/6/X/16V
C930
0.1U/6/X/16V
C942
0.1U/6/X/16V
SC81
0.1U/6/X/16V
C931
0.1U/6/X/16V
C943
0.1U/6/X/16V
SC82
0.1U/6/X/16V
4
C932
0.1U/6/X/16V
C972
0.1U/6/X/16V
C933
0.1U/6/X/16V
C973
0.1U/6/X/16V
C934
0.1U/6/X/16V
C974
0.1U/6/X/16V
12
C935
+
100U/1210/Y/6.3V
3
12
C936
+
100U/1210/Y/6.3V
12
C937
+
100U/1210/Y/6.3V
2
MCH VCCA
Title
Size Document Number Rev
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
MCH DECOUPING
GA-9ITDW-FJ
1
1.3
of
23 81Wednesday, October 13, 2004
5
4
3
2
1
DDR6A
DDRA_CMDCLK0_P
DDRA_CMDCLK0_N
R203 0
DDRA_PCIRST#
DDRA_WE#
DDRA_RAS#
DDRA_CAS#
DDRA_BA2
DDRA_MA13
DDRA_MA12
DDRA_MA11
DDRA_MA10
DDRA_MA9
DDRA_MA8
DDRA_MA7
DDRA_MA6
DDRA_MA5
DDRA_MA4
DDRA_MA3
DDRA_MA2
DDRA_MA1
DDRA_MA0
DIMMA1_CS#1
DDRA_CS#2
DDRA_CS#3
DIMMA1_CKE1
MEM_CKE2
DDRA_BA1
DDRA_BA0
DDRA_DIMMA1_SA2
DDRA_DIMMA1_SA1
DDRA_DIMMA1_SA0
DIMM_SMBDAT
DIMM_SMBCLK
DDRA1_VREFDDRA_DIMM_VREF
DDRA_PCIRST#
DDRA_CB7
DDRA_CB6
DDRA_CB5
DDRA_CB4
DDRA_CB3
DDRA_CB2
DDRA_CB1
DDRA_CB0
DDRA_DQS#17
DDRA_DQS17
DDRA_DQS#16
DDRA_DQS16
DDRA_DQS#15
DDRA_DQS15
DDRA_DQS#14
DDRA_DQS14
DDRA_DQS#13
DDRA_DQS13
DDRA_DQS#12
DDRA_DQS12
DDRA_DQS#11
DDRA_DQS11
DDRA_DQS#10
DDRA_DQS10
DDRA_DQS#9
DDRA_DQS9
DDRA_WE#17,25,26,30
DDRA_RAS#17,25,26,30
DDRA_CAS#17,25,26,30
DDRA_BA217,25,26,30
D D
C C
DDRA_DIMM_VREF25,26
B B
A A
DDRA1_VREF
C47
0.1U/6/X/16V
DDRA_MA[13..0]17,25,26,30
DDRA_CMDCLK0_P17,30
DDRA_CMDCLK0_N17,30
DDRA_CS#[7..0]17,25,26,30
MEM_CKE[7..0]17,18,25,26,27,28,29,30
DDRA_BA117,25,26,30
DDRA_BA017,25,26,30
DIMM_SMBDAT25,26,27,28,29,72
DIMM_SMBCLK25,26,27,28,29,72
P3V3
DDRA_PCIRST#25,26,55
DDRA_CB[7..0]17,25,26
DDRA_DQS#[17..0]17,25,26
DDRA_DQS[17..0]17,25,26
P1V8_AUX
R207 1K
5
73
192
74
54
173
174
196
176
57
70
177
179
58
180
60
61
182
63
183
188
220
221
137
138
185
186
76
193
171
52
190
71
101
240
239
119
120
1
238
55
18
168
167
162
161
49
48
43
42
165
164
233
232
224
223
212
211
203
202
156
155
147
146
135
134
126
125
WE_N
RAS_N
CAS_N
A16/BA2
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CK2P
CK2N
CK1P
CK1N
CK0P
CK0N
CS1_N
CS0_N
CKE1
CKE0
BA1
BA0
SA2
SA1
SA0
SDA
SCL
VREF
VDDSPD
RC0
RFU/RC1
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
NC/DQS17N
DM8/DQS17P
NC/DQS16N
DM7/DQS16P
NC/DQS15N
DM6/DQS15P
NC/DQS14N
DM5/DQS14P
NC/DQS13N
DM4/DQS13P
NC/DQS12N
DM3/DQS12P
NC/DQS11N
DM2/DQS11P
NC/DQS10N
DM1/DQS10P
NC/DQS9N
DM0/DQS9P
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
ODT1
ODT0
DQS8N
DQS8P
DQS7N
DQS7P
DQS6N
DQS6P
DQS5N
DQS5P
DQS4N
DQS4P
DQS3N
DQS3P
DQS2N
DQS2P
DQS1N
DQS1P
DQS0N
DQS0P
DDR II
4
236
235
230
229
117
116
111
110
227
226
218
217
108
107
99
98
215
214
209
208
96
95
90
89
206
205
200
199
87
86
81
80
159
158
153
152
40
39
34
33
150
149
144
143
31
30
25
24
141
140
132
131
22
21
13
12
129
128
123
122
10
9
4
3
77
195
45
46
113
114
104
105
92
93
83
84
36
37
27
28
15
16
6
7
DDRA_DQ63
DDRA_DQ62
DDRA_DQ61
DDRA_DQ60
DDRA_DQ59
DDRA_DQ58
DDRA_DQ57
DDRA_DQ56
DDRA_DQ55
DDRA_DQ54
DDRA_DQ53
DDRA_DQ52
DDRA_DQ51
DDRA_DQ50
DDRA_DQ49
DDRA_DQ48
DDRA_DQ47
DDRA_DQ46
DDRA_DQ45
DDRA_DQ44
DDRA_DQ43
DDRA_DQ42
DDRA_DQ41
DDRA_DQ40
DDRA_DQ39
DDRA_DQ38
DDRA_DQ37
DDRA_DQ36
DDRA_DQ35
DDRA_DQ34
DDRA_DQ33
DDRA_DQ32
DDRA_DQ31
DDRA_DQ30
DDRA_DQ29
DDRA_DQ28
DDRA_DQ27
DDRA_DQ26
DDRA_DQ25
DDRA_DQ24
DDRA_DQ23
DDRA_DQ22
DDRA_DQ21
DDRA_DQ20
DDRA_DQ19
DDRA_DQ18
DDRA_DQ17
DDRA_DQ16
DDRA_DQ15
DDRA_DQ14
DDRA_DQ13
DDRA_DQ12
DDRA_DQ11
DDRA_DQ10
DDRA_DQ9
DDRA_DQ8
DDRA_DQ7
DDRA_DQ6
DDRA_DQ5
DDRA_DQ4
DDRA_DQ3
DDRA_DQ2
DDRA_DQ1
DDRA_DQ0
DIMMA1_ODT1
DDRA_CS#3
DDRA_DQS#8
DDRA_DQS8
DDRA_DQS#7
DDRA_DQS7
DDRA_DQS#6
DDRA_DQS6
DDRA_DQS#5
DDRA_DQS5
DDRA_DQS#4
DDRA_DQS4
DDRA_DQS#3
DDRA_DQS3
DDRA_DQS#2
DDRA_DQS2
DDRA_DQS#1
DDRA_DQS1
DDRA_DQS#0
DDRA_DQS0
P1V8_AUX
DDRA_DQ[63..0]
PLACE NEAR THE CENTER OF DIMM A1
C41
10U/8/X/6.3V
THESE DECOUPLING CAPS ARE PLACE HOLDERS
3
DDRA_DQ[63..0] 17,25,26
DDRA_DQS#[17..0] 17,25,26
DDRA_DQS[17..0] 17,25,26
C42
10U/8/X/6.3V
C43
10U/8/X/6.3V
P1V8_AUX P1V8_AUX
DDR6B
197
VDD
189
VDD
187
VDD
184
VDD
178
VDD
172
VDD
69
VDD
67
VDD
64
VDD
59
VDD
53
VDD
102
NC
68
NC
19
NC
115
GND
112
GND
109
GND
106
GND
103
GND
100
GND
97
GND
94
GND
91
GND
88
GND
85
GND
82
GND
79
GND
66
GND
65
GND
50
GND
47
GND
44
GND
41
GND
38
GND
35
GND
32
GND
29
GND
26
GND
23
GND
20
GND
17
GND
14
GND
11
GND
8
GND
5
GND
2
GND
DDR II
C44
0.1U/6/X/16V
C45
1U/6/X/10V
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
191
181
175
170
78
75
72
62
56
51
194
237
234
231
228
225
222
219
216
213
210
207
204
201
198
169
166
163
160
157
154
151
148
145
142
139
136
133
130
127
124
121
118
C46
1U/6/X/10V
P1V8_AUX
SR120
1K/X
SR121
1K
DIMMA1_CS#1
DIMMA1_CKE1
DIMMA1_ODT1
P3V3
SR118
1K
SR119
1K/X
DDRA_DIMMA1_SA2
DDRA_DIMMA1_SA1
DDRA_DIMMA1_SA0
R200 4.7K
R201 1K
R202 1K
R204
1K
SMBUS ADDR: 0XA2
SINGLE RANK
193
195
MEM_CKE2
Title
Size Document Number Rev
Date: Sheet
GIGA-BYTE TECHNOLOGY CO., LTD.
DDR II DIMM A1
GA-9ITDW-FJ
1
DUAL RANK
76DDRA_CS#2
77
17152
PULL UP
PULL LOWDDRA_CS#3
PULL LOW
24 81Wednesday, October 13, 2004
of
1.3
Loading...