GHI ALFAT SoC User Manual
GHI Electronics 2012 www.ghielectronics.com
ALFAT SoC Processor
Rev. 1.09 Date: June 22, 2012 User Manual
A high performance FAT file system SoC processor with dual USB Host
interfaces and 4-bit SD interface. Controlled through UART, SPI or I2C.
Document
Information Description
Abstract ALFAT SoC processor concept, pin-out, specifications,
commands, hardware integration guide and full
information needed to implement a solution using this
processor.
Firmware V1.07
GHI Electronics ALFAT SoC Processor
Document Revision History
Rev No. Date Modification
Rev 1.09 06/21/12 Some SD cards do not work with high clock frequency SD-bus. "I
Initialize command" is modified to set different clock frequencies.
ALFAT command's terminator can be LF('\n') or CR ('\r').
Fixed "? Find File or Folder command" date format.
Clarified I2C addressing
Rev 1.08 06/05/12 Clarified card detect and write protection signals in the pin-out
and Initialize command sections.
Added Card Detect and Write Protect signals section.
Rev 1.07 06/01/12 Minor spelling errors.
Rev 1.06 05/29/12 Edited SPI Bus configuration section.
Added L command (Fast Write), SPI DMA receive channel.
Added new features to Z command.
Added new features to J command.
Added CD and WP pin description to pin-out table.
Fixed #WAKEUP pin description
Rev 1.05 05/11/12 Added integration guide and updated performance section.
Rev 1.04 04/16/12 Major changes to ALFAT access interface section (UART, SPI
and I2C) to match firmware version1.03. Busy pin is required to
be monitored.
Fixing B and K command description.
Rev 1.03 03/19/12 Fixes to multiple typos.
Clarifying some ambiguous points.
Rev 1.02 03/15/12 Adding 6.4.Updating the firmware using a terminal console
Fixes to 8.2.ALFAT SD board pin-mount tables
Rev 1.01 03/08/12 Updates to 4.3.SPI interface mode section
Updates to 6.2.Firmware Updater App
Rev 1.00 02/15/12 Preliminary document
Rev. 1.09 Page 2 of 48 www.ghielectronics.com
GHI Electronics ALFAT SoC Processor
Table of Contents
Table of Contents
1.Introduction.......................................................................4
1.1.ALFAT SoC processor Concept...............................4
1.2.Example applications...............................................5
1.3.Key features.............................................................5
2.Architecture......................................................................6
2.1.Commander.............................................................7
2.2.FAT File System Engine...........................................7
2.3.Memory Card Access (SDHC, SD or MMC)............7
2.4.USB Mass Storage Access......................................8
2.5.Boot Loader.............................................................8
3.Package and Pin-Out ......................................................9
4.ALFAT access interface..................................................12
4.1.Selecting the access interface...............................12
4.2.UART Interface......................................................12
UART configurations..............................................13
4.3.SPI Interface Mode................................................13
Write Transaction...................................................13
Read Transaction...................................................14
SPI DMA receive channel......................................15
SPI Bus Configurations..........................................15
4.4.I2C Interface Mode................................................15
I2C Bus Configuration............................................16
5.ALFAT Command Set.....................................................17
V - Get Version Number.........................................18
# - Enable Echo......................................................18
Z - Set Low Power Mode........................................18
T - Initialize Real Time Clock..................................19
S - Set Current Time and Date...............................20
G - Get Current Time and Date..............................20
B - Set UART Baud Rate.......................................20
I - Initialize and Mount MMC/SD or USB................20
J - Read Status Register........................................21
K- Get Free Size....................................................22
@ - Initialize Files and Folders List........................23
N - Get Next Directory Entry..................................24
O - Open File for Read, Write or Append...............25
R - Read from File..................................................26
W - Write to File.....................................................27
L- Fast Write to File (SPI mode only).....................27
F - Flush File Data..................................................29
C - Close File.........................................................29
P - File Seek...........................................................29
Y - File Tell.............................................................30
D - Delete File or Folder.........................................30
? - Find File or Folder.............................................31
M - Copy From File to Another ..............................31
A - Rename file ......................................................32
E - Test Media Speed.............................................32
Q – Format.............................................................33
6.Boot Loader and firmware update..................................34
6.1.General Description...............................................34
6.2.Firmware Updater App...........................................34
6.3.Boot Loader Commands........................................36
6.4.Updating the firmware using a terminal console....36
7.Hardware integration guide............................................39
7.1.Power Source........................................................39
7.2.Crystals..................................................................39
7.3.Card Detect and Write Protect signals...................39
7.4.Full Speed / High Speed with ULPI PHY...............40
7.5.Real Time Clock.....................................................41
7.6.Bootloader Access.................................................41
7.7.Electrical characteristics........................................41
8.ALFAT Off-the-shelf Circuit Boards................................42
8.1.ALFAT OEM Board................................................42
ALFAT OEM Pinout................................................42
8.2.ALFAT SD Board....................................................43
ALFAT SD Pin-out..................................................43
9.Conditions of Use and Performance..............................45
9.1.Selecting the Right Storage Media........................45
9.2.File Access Speed.................................................45
9.3.Serial Interface Speed Overhead..........................46
10.Error Codes..................................................................47
DISCLAIMER.................................................................... 48
Rev. 1.09 Page 3 of 48 www.ghielectronics.com
GHI Electronics ALFAT SoC Processor
Introduction
1. Introduction
1.1. ALFAT SoC processor Concept
Adding FAT file system to products requires a lot of resources from the system and needs
intensive development efforts. This also requires USB Host drivers and SD memory drivers
to be able o access storage medias such as SD cards or USB Mass Storage devices.
Additionally, licensing patented technologies, such as LFN is a lengthy and expensive
process. Thanks to ALFAT SoC Processor, any simple system can now access files on SD
cards and USB memory drives in a very short time, with minimal resources through simple
UART, SPI or I2C interface. ALFAT SoC processor is capable of accessing two USB mass
storage devices and one memory card simultaneously. This gives the user unique features
such as copying data from one media to another.
The Host MCU controls ALFAT through simple commands sent through UART (serial), SPI
or I2C. The commands give the host MCU the ability to access files on the storage media.
With ALFAT, file access rate can reach 4000 KBytes/sec.
An important advantage of ALFAT is that supports Long File Name LFN and it is licensed
by Microsoft for commercial use. Solutions that depends on ALFAT can use LFN
commercially without the need for any additional licensing.
Rev. 1.09 Page 4 of 48 www.ghielectronics.com
GHI Electronics ALFAT SoC Processor
Introduction
1.2. Example applications
● High speed Data loggers.
● Automated Machinery.
● Digital picture viewer.
● Consumer products.
1.3. Key features
● Built-in 2-port USB Host controller.
● FAT16 and FAT32 File system.
● No limits on media size, file size or file/folder count.
● LFN (Long File Name), licensed by Microsoft.
● Friendly user interface through UART,SPI or I2C.
● Programmable UART baud-rate.
● Up to 8 simultaneous file access.
● SD/SDHC card support, no 2GB limit. GHI electronics is an SD
association member.
● MMC card support.
● Built-in 2x USB 2.0 FS PHY USB, 12mbps.
● One USB ports is capable of HS 480mbps through external ULPI PHY.
● High speed 4-bit SD card interface.
● Up to 4000 KBytes/sec file access speed on SD cards.
● Up to 4000 KBytes/sec file access speed on USB (with ULPI HS PHY).
● Up to 1000 KBytes/sec file access speed on USB Full Speed (no ULPI HS PHY).
● RTC (Real Clock Time) with separate power domain.
● All I/O pins are 5 volt tolerant EXCEPT RESET PIN.
● Small surface mount package, LQFP 64 pin.
● Single 3.3V power source.
● Low power consumption, 38mA fully operational and 5mA in hibernate.
● -40˚C to +85˚C operational temperature.
● RoHS Compliant/Lead free.
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GHI Electronics ALFAT SoC Processor
Architecture
2. Architecture
ALFAT SoC processor is an ARM Cortex-M3 processor that runs a robust file system
engine with SD and USB host (mass storage) drivers. The processor access storage
media though its 4-bit SD interface and two USB host 2.0 interface. One of the USB host
ports is capable running at high speed 480mbps with external ULPI HS PHY chip.
ALFAT SoC processor provides 3 different standard access interfaces for the host system,
UART, SPI or I2C.
Rev. 1.09 Page 6 of 48 www.ghielectronics.com
ULPI HS PHY
(P/N FUSB2805)
optional
USB Host
Connector 1
USB Host
Connector 0
SD/μSD
MMC socket
User/machine friendly
Commander
SDHC/SD/MMC
Driver
Host System
AVR, PIC ...etc
USB MS
Device
ALFAT SoC
Processor
ARM Cortex-M3 Core
UART,SPI
or I2C
4-Bit SD Bus
USB0 FS
SD/miniSD/μSD
SDHC
MMC card
USB Host driver with
Mass Storage class driver
USB1 HS
8bit bus
FAT File System Engine
can handle 3 different storage medias
and 8 file handles simultaneously
USB MS
Device
USB1 HS
USB1 FS
Boot Loader
UART
GHI Electronics ALFAT SoC Processor
Architecture
2.1. Commander
The function of the commander is to provide the user with a protocol and a set of
commands to control the processor and access the files on the storage devices.
The physical interface that the user (the host system) can use to access the commander is
UART, SPI or I2C serial port.
Commands are human-readable ASCII format. This allows for easier development and
troubleshooting. But at the same time, the commands are designed to be easy to parse by
the the host software.
2.2. FAT File System Engine
The function of the file system engine is to handle accessing the file system according to
FAT standards. It has been optimized for high speed access and with high performance.
Here are some of the capabilities of this engine:
● FAT16, FAT32.
● Licensed Long File Names support. Licensed to be used on ALFAT by Microsoft.
● Access up to 16 opened files simultaneously.
● Complete directories (folders) support.
● File access functions include read, write, append, seek, tell, find, delete, remove
folder ...etc.
● High speed read or write access, up to 4000KBytes/sec.
● No limits on media size, file size or file/folder count.
It is important to note here that the 16 file handle limit is only on how many simultaneous
files are open. ALFAT SoC processor Has no limits on how many files can be opened and
closed.
2.3. Memory Card Access (SDHC, SD or MMC)
ALFAT SoC processor includes memory card driver
internally that supports SD, SDHC and MMC cards. This
gives ALFAT the ability to access a wide range of
memory cards such as standard or high capacity
SD/μSD cards or multimedia cards. There is no limit on
the card capacity.
Unlike typical solutions that access the card through
SPI-based interface, ALFAT's hardware provides a 4-bit
SD bus interface for higher performance.
GHI Electronics is a member of SD association.
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GHI Electronics ALFAT SoC Processor
Architecture
2.4. USB Mass Storage Access
ALFAT SoC processor is capable of accessing FAT file system files on
USB mass storage devices. The hardware provides two standard Full
Speed* USB 2.0 compatible host interfaces (USB0 and USB1) that
use the internal USB PHY. Only 22ohm resistors and USB host
connector is needed.
USB1 interface is also capable of running in USB 2.0 High Speed mode by
adding ULPI High Speed+ PHY chips like FUSB2805. This options quadruples
the file system access speed.
*Full-Speed USB 2.0 is 12mbps.
+
High-Speed USB 2.0 is 480mbps.
2.5. Boot Loader
The boot loader is a piece of software that boots the system up. It verifies and runs ALFAT
firmware. Also It gives the hosting system an interface for firmware maintenance.
GHI Electronics regularly maintains ALFAT firmware with improvements and bug fixes.
ALFAT boot loader allows the hosting system to update the firmware.
The boot loader can only be accessed through the UART port and it uses XMODEM 1K to
transfer the firmware file to ALFAT. Boot Loader and firmware update section explain this in
more details.
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GHI Electronics ALFAT SoC Processor
Package and Pin-Out
3. Package and Pin-Out
ALFAT SoC package is standard 10x10mm LQFP64. The following Table illustrates a brief
description of ALFAT SoC processor pins.
Pin Name Description
1 VBAT
Power source for the internal RTC. Connect to 3V battery or
VCC. Always use 2 diodes to connect a battery and VCC in case
the battery runs out of power. VBAT works 1.65V to 3.6V.
If RTC is not needed, connect to VCC
2 NC Should not be connected
3 OSC32_IN Pin 1 for the 32.768KHz crystal, for the real time clock. Optional
4 OSC32_OUT Pin 2 for the 32.768KHz crystal, for the real time clock. Optional
5 OSC_IN
Pin 1 for parallel-cut 12MHz system crystal. 10pF to 20pF is
recommended
6 OSC_OUT Pin 2 for 12MHz system crystal
7 RESET
Reset signal, the pin pulled up internally. Active Low.
THIS PIN IS NOT 5VOLT TOLERANT
8 USB1_ULPI_STP USB High Speed PHY signal. Do not connect if PHY is not used
9 NC Should not be connected
10 USB1_ULPI_DIR USB High Speed PHY signal. Do not connect if PHY is not used
11 USB1_ULPI_NXT USB High Speed PHY signal. Do not connect if PHY is not used
12 VSSA Ground
13 VDDA 3.3V Power source
14 WAKEUP Wake up ALFAT, check power mode command Z for more details
15 NC Should not be connected
16 NC Should not be connected
17 USB1_ULPI_D0 USB High Speed PHY signal. Do not connect if PHY is not used
18 VSS1 Ground
19 VDD1 Power, 3.3V
20 ACTIVE Active signal indicates the current status of command
processing. Useful for a system-activity-LED, max 8mA.
On UART: Active pin is high when a command is received and
Rev. 1.09 Page 9 of 48 www.ghielectronics.com
GHI Electronics ALFAT SoC Processor
Package and Pin-Out
Pin Name Description
being processed. Low when command is complete.
Note: The command is considered complete when ALFAT is done
sending the response to the command. This is automatically
completed in UART but SPI and I2C are slaves so ACTIVE pin
will go low after the master reads the response.
It is completely safe to ignore this signal and keep it not
connected.
21 USB1_ULPI_CK USB High Speed PHY signal. Not connected if PHY is not used
22
SPI_MISO
UART_BUSY
MISO SPI interface and UART BUSY pin, 5V tolerant
23 SPI_MOSI MOSI SPI interface, 5V tolerant
24 WP
SD Write protection signal input. Low = card not protected.
Note: WP MUST be connected to ground if Write protection
signal is not used in the hardware design.
25 CD
Memory Card Detect signal input. Low = card detected.
Note: CD MUST be connected to ground if Card Detect signal
is not used in the hardware design.
26 USB1_ULPI_D1 USB High Speed PHY signal. Do not connect if PHY is not used
27 USB1_ULPI_D2 USB High Speed PHY signal. Do not connect if PHY is not used
28 BOOT1 Add a 10K resistor to ground.
29 USB1_ULPI_D3 USB High Speed PHY signal. Do not connect if PHY is not used
30 USB1_ULPI_D4 USB High Speed PHY signal. Do not connect if PHY is not used
31 VCAP_1 Connect to a 22uF to ground
32 VDD1 Power, 3.3V
33 USB1_ULPI_D5 USB High Speed PHY signal. Do not connect if PHY is not used
34 USB1_ULPI_D6 USB High Speed PHY signal. Do not connect if PHY is not used
35 USB1_DM
Data Minus, USB Port 1. This is only used if no HS PHY is
installed.
NC if PHY is used. Add 22ohm resistor in series if used
36 USB1_DP
Data Plus, USB Port 1. This is only used if no HS PHY is
installed.
NC if PHY is used. Add 22ohm resistor in series if used
37 NC Should not be connected
38 NC Should not be connected
39 SD_D0 D0, 4-bit SD Bus. Add a 47K resistor between this pin and VDD
40 SD_D1 D1, 4-bit SD Bus. Add a 47K resistor between this pin and VDD
Rev. 1.09 Page 10 of 48 www.ghielectronics.com
GHI Electronics ALFAT SoC Processor
Package and Pin-Out
Pin Name Description
41 ULPI_19_2MHZ
This pin generates 19.2MHz clock. It is usually used to clock the
USB High Speed PHY
42 UART_TX TX UART interface, 5V tolerant
43 UART_RX
SPI_BUSY
I2C_BUSY
RX UART interface BUSY pin for SPI and I2C, 5V tolerant
Add a 10K resistor between this pin and VDD
44 USB0_DM Data Minus, USB Port 0. Add 22ohm resistor in series
45 USB0_DP Data Plus, USB Port 0. Add a 22ohm resistor in series
46 NC Should not be connected
47 VCAP_2 Connect to a 22uF to ground
48 VDD3 Power, 3.3V
49 NC Should not be connected
50 SPI_SSEL SSEL SPI interface, 5V tolerant
51 SD_D2 D0, 4-bit SD Bus. Add a 47K resistor between this pin and VDD
52 SD_D3 D1, 4-bit SD Bus. Add a 47K resistor between this pin and VDD
53 SD_CLK CLK, 4-bit SD Bus
54 SD_CMD
CMD, 4-bit SD Bus. Add a 47K resistor between this pin and
VDD
55 SPI_SCK SCK SPI interface, 5V tolerant
56 NC Should not be connected
57 USB1_ULPI_D7
USB High Speed PHY signal. Add a 10K resistor to VDD.
Only add10K resistor if HS PHY is not used
58 I2C_SCL SCL I2C Interface
59 I2C_SDA SDA I2C Interface
60 BOOT0
Should not be connected. It is safe to have pull up or down
resistor on this pin.
61 NC Should not be connected
62 NC Should not be connected
63 VSS2 Ground
64 VDD4 Power, 3.3V
Note: All pins have internal weak pull ups, leaving them unconnected is safe.
Rev. 1.09 Page 11 of 48 www.ghielectronics.com
GHI Electronics ALFAT SoC Processor
ALFAT access interface
4. ALFAT access interface
ALFAT is controlled through UART, SPI or I2C serial interfaces. 2 pins are sampled on
power up to determine the interface. The pins are SPI_SSEL and SPI_MOSI.
4.1. Selecting the access interface
On power up, the system should hold ALFAT in reset state until the power is stable. This is
done by holding reset pin low. Then, pins SPI_SSEL and SPI_MOSI must be set to the
desired serial interface, UART, SPI, I2C or even to force the boot loader. The boot loader is
needed for firmware updates. Those pins have internal pull-down resistor so an
unconnected pin is considered low. After pins are set, the reset pin must be set to high
state to allow ALFAT to boot up. Note that the reset pin is NOT 5V tolerant.
ALFAT needs about 30 milliseconds to sample these pins from the time reset pin goes high
then it needs a bit more to initialize the system. We recommend a 50 milliseconds delay
before sending any commands to ALFAT. If the selected interface is SPI, these pins can
be change to their appropriate SPI functions; otherwise, it is safe to leave the pins in the
same state used on power-up.
SPI_SSEL SPI_MOSI Interface
low low UART
low high Boot loader
high low I2C
high high SPI
4.2. UART Interface
UART interface uses three hardware signals:
• UART_TX signal to send data out from ALFAT.
• UART_RX signal to receive data to ALFAT.
• UART_BUSY signal. This should be monitored while sending data to ALFAT. When
it is high, no more data should be transmitted to ALFAT till it gets low.
Note: ALFAT access reference code library, available with ALFAT's downloads, provides an
example how to use UART interface.
Rev. 1.09 Page 12 of 48 www.ghielectronics.com
GHI Electronics ALFAT SoC Processor
ALFAT access interface
UART configurations
• The default baud rate is 115200. The maximum tested baud rate is 3M. To
change the baud rate use B command.
• Data bits: 8
• Parity: None
• Stop bit: 1
4.3. SPI Interface Mode
SPI interface uses four hardware signals:
• SPI_SSEL: ALFAT Chip Select.
• SPI_MOSI: ALFAT Data in.
• SPI_MISO: ALFAT Data out.
• SPI_BUSY: This should be monitored while sending data to ALFAT. When it is high,
no more data should be exchanged with ALFAT till it gets low.
Note: ALFAT access reference code library, available with ALFAT's downloads, provides an
example how to use SPI interface.
Sending and receiving data to and from ALFAT over SPI is performed through frame
transactions which is a layer that resides between the actual SPI data bus and the
communication stream (commands, responses, data). It is important to know that SPI
frame transaction layer is independent from how ALFAT commands work.
Communication Stream @ M:\TEST\TMP<LF>
Frame Transaction
SPI Bus
01 08 00 '@' ' ' 'M' ' : ' '\' 'T' 'E' 'S' 01 06 00 'T' '\' 'T' 'M' 'P' 0x0A
Write Transaction
Request Frame
The frame consists of two parts, a header and payload.
• The header consists of three bytes. The first byte is the frame type, the second
and the third bytes are 16-bit transaction length (Not including the header).
• Payload: This is actual transaction payload needed to be sent to ALFAT. The
payload section size MUST match the declared in the transaction size field.
Rev. 1.09 Page 13 of 48 www.ghielectronics.com
Write Frame: @ M:\TES
Write Frame: T\TMP<LF>
GHI Electronics ALFAT SoC Processor
ALFAT access interface
Frame
Type
16-bit Transaction
Size N
Payload
0x01 Size LSB Size MSB Byte 1 Byte 2 ... Byte N
Response Frame
0x00 RFB RFB RFB RFB ... RFB
RFB is Ready Flag Byte.
When a write transaction request is being sent, ALFAT returns zero with the first
received byte (Frame Type) and then it returns a ready flag with the received second
byte (Size LSB).
If the ready flag is 0x00, this means that ALFAT is not ready to receive any data over
SPI. The current transaction gets terminated and the user must not send more bytes for
this frame.
If the ready flag is 0x01, this means that ALFAT is ready to receive and the user can
proceed and send Size MSB and the payload bytes.
Read Transaction
Processing read transaction is preformed by sending read request frames and receiving
response frames that carry the useful payload.
Request Frame
The frame consists of two parts, a header and stuffing bytes.
• The header consists of three bytes. The first byte is the frame type, the second
and the third bytes are the requested 16-bit transaction length.
• Stuffing bytes: the bytes should always be 0x00. This section size should equal
P, where P is the actual payload size that ALFAT will send back.
Frame
Type
Requested
Transaction
16-bit Size N
Stuffing Bytea, the size is P.
0x02 N LSB N MSB 0x00 0x00 0x00 0x00
Response Frame
The frame consists of two parts, a header and payload.
• The header consists of three bytes. The first byte is the frame type response
which is always 0x00, the second and the third bytes are 16-bit value ACT that
indicates the actual data size available in the send buffer of ALFAT. ACT value
could be more or less that N (the requested transaction size)
• Payload: This is the actual transaction payload that is being send out from ALFAT
to the host. This section size is P.
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GHI Electronics ALFAT SoC Processor
ALFAT access interface
That actual Payload size is calculated as the following: If the requested transaction size
N is larger than ACT then P should equal ACT otherwise P should equal N.
Response
Type
Internal buffer filled
portion
16-bit Size ACT
Payload Bytes, the size is P
if N > ACT then P = ACT else P =N
0x00 ACT LSB ACT MSB Byte 1 Byte 2 ... Byte P
Important: ACT size should be used only for data size estimating purposes because
the send buffer might get filled with more data while processing the read command.
SPI DMA receive channel
This internal DMA channel that is used for high speed data receiving through SPI bus.
ALFAT opens this DMA channel only when it accepts to receive data with Fast Write to
File command (L Command).
ALFAT reserves 8192 Bytes in RAM for this DMA channel. So the user can send
8192(or less)-Byte blocks of data without any delays in between the bytes and the DMA
forwards the data to the reserved RAM region. Then ALFAT will save the data into the
file. But the user needs to check SPI_BUSY pin before sending each block.
Check Fast Write to File command (L Command) for more details about how to utilize
SPI DMA channel. Also ALFAT access reference code library provides an example how
to use L command and access SPI DMA.
SPI Bus Configurations
• The maximum SPI clock is 24MHz.
• SPI clock Idle state is Low.
• Sampling is at the rising edge.
• SPI_BUSY active state is High.
• Data is sent MSB first.
• SPI_SSEL active state is Low. SPI_SSEL can be toggled with with every byte or
with every chunk of bytes.
• A minimum of 4uS delay is required between each byte. This requirement is not
needed with Fast Write to File command (L Command) that uses SPI DMA receive
channel.
4.4. I2C Interface Mode
I2C interface uses three hardware signals:
• I2C_SCL: I2C clock signal.
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