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TRF7970A

SLOS743K –AUGUST 2011–REVISED APRIL 2014

TRF7970A Multiprotocol Fully Integrated 13.56-MHz RFID and Near Field Communication

(NFC) Transceiver IC

1 Device Overview

1.1 Features

• Supports Near Field Communication (NFC) • Programmable Output Power: +20 dBm (100 mW), Standards NFCIP-1 (ISO/IEC 18092) and NFCIP‑2 +23 dBm (200 mW) (ISO/IEC 21481)

• Completely Integrated Protocol Handling for to 5.5 VDC ISO15693, ISO18000-3, ISO14443A/B, and FeliCa™

• Integrated Encoders, Decoders, and Data Framing Crystal or Oscillator for NFC Initiator, Active and Passive Target Operation for All Three Bit Rates (106 kbps, 212 kbps, 424 kbps) and Card Emulation

• RF Field Detector With Programmable Wake-Up Levels for NFC Passive Transponder Emulation Operation

• RF Field Detector for NFC Physical Collision Avoidance.

• Integrated State Machine for ISO14443A Anticollision (Broken Bytes) Operation (Transponder Emulation or NFC Passive Target)

• Input Voltage Range: 2.7 VDC to 5.5 VDC

• Programmable I/O Voltage Levels From 1.8 VDC

• Programmable System Clock Frequency Output (RF, RF/2, RF/4) from 13.56-MHz or 27.12-MHz

• Integrated Voltage Regulator Output for Other System Components (MCU, Peripherals, Indicators), 20 mA (Max)

• Programmable Modulation Depth

• Dual Receiver Architecture With RSSI for Elimination of "Read Holes" and Adjacent Reader System or Ambient In-Band Noise Detection

• Programmable Power Modes for Ultra Low-Power System Design (Power Down <1 µA)

• Parallel or SPI Interface (With 127-Byte FIFO)

• Temperature Range: –40°C to 110°C

• 32-Pin QFN Package (5 mm x 5 mm)

1.2 Applications

• Mobile Devices (Tablets, Handsets) • Short-Range Wireless Communication Tasks

• Secure Pairing ( Bluetooth®, Wi-Fi®, Other Paired

(Firmware Updates)

Wireless Networks) • Product Identification or Authentication

• Public Transport or Event Ticketing • Medical Equipment or Consumables

• Passport or Payment (POS) Reader Systems • Access Control, Digital Door Locks

• Sharing of Electronic Business Cards

1.3 Description

The TRF7970A device is an integrated analog front end and data-framing device for a 13.56-MHz RFID and Near Field Communication (NFC) system. Built-in programming options make the device suitable for a wide range of applications for proximity and vicinity identification systems.

The device can perform in one of three modes: RFID and NFC reader, NFC peer, or in card emulation mode. Built-in user-configurable programming options make the device suitable for a wide range of applications. The TRF7970A device is configured by selecting the desired protocol in the control registers. Direct access to all control registers allows fine tuning of various reader parameters as needed.

Documentation, reference designs, EVM, and source code TI MSP430™ MCUs or ARM®MCUs are available.

Device Information

PART NUMBER PACKAGE BODY SIZE

TRF7970ARHB VQFN (32) 5 mm x 5 mm

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

MUX

RX_IN1

RX_IN2

PHASE&

AMPLITUDE

DETECTOR

GAIN

RSSI

(AUX)

LOGIC

LEVEL SHIFTER

STATE

CONTROL

LOGIC

[CONTROL

REGISTERS &

COMMAND

LOGIC]

127-BYTE

FIFO

MCU

INTERFACE

VDD_I/O

I/O_0

I/O_1

I/O_2

I/O_3

I/O_4

I/O_5

I/O_6

I/O_7

IRQ

SYS_CLK

DATA_CLK

ISO PROTOCOL HANDLING

DECODER

RSSI

(EXTERNAL)

PHASE&

AMPLITUDE

DETECTOR

GAIN

RSSI

(MAIN)

FILTER & AGC

DIGITIZER

BIT

FRAMING

SERIAL

CONVERSION

CRC &PARITY

TRANSMITTER ANALOG

FRONT END

TX_OUT

VDD_PA

VSS_PA

DIGITAL CONTROL

STATE MACHINE

CRYSTAL OR OSCILLATOR

TIMING SYSTEM

EN2

ASK/OOK

MOD

OSC_IN

OSC_OUT

VOLTAGE SUPPLY REGULATOR SYSTEMS

(SUPPLY REGULATORS AND REFERENCE VOLTAGES)

VSS_A

VSS_RF

VDD_RF

VDD_X

VSS_D

VSS

VIN

VDD_A

BAND_GAP

RF LEVEL

DETECTOR

TRF7970A

SLOS743K –AUGUST 2011–REVISED APRIL 2014

1.4 Functional Block Diagram

Figure 1-1 shows the block diagram.

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Figure 1-1. Block Diagram

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1 Device Overview ......................................... 1 6.8 Transmitter – Digital Section........................ 28

1.1 Features .............................................. 1

1.2 Applications........................................... 1

1.3 Description............................................ 1

1.4 Functional Block Diagram ............................ 2

2 Revision History ......................................... 4

3 Device Characteristics.................................. 5

4 Terminal Configuration and Functions.............. 6

4.1 Pin Assignments...................................... 6

4.2 Terminal Functions ................................... 7

5 Specifications ............................................ 9

5.1 Absolute Maximum Ratings .......................... 9

5.2 Recommended Operating Conditions................ 9

5.3 Electrical Characteristics............................ 10

5.4 Handling Ratings.................................... 11

5.5 Thermal Characteristics............................. 11

5.6 Switching Characteristics ........................... 11

6 Detailed Description ................................... 12

6.1 Overview ............................................ 12

6.2 System Block Diagram.............................. 15

6.3 Power Supplies...................................... 15

6.4 Receiver – Analog Section .......................... 21

6.5 Receiver – Digital Section........................... 22

6.6 Oscillator Section ................................... 27

6.7 Transmitter – Analog Section ....................... 28

6.9 Transmitter – External Power Amplifier and

Subcarrier Detector ................................. 29

6.10 TRF7970A IC Communication Interface ............ 30

6.11 Special Direct Mode for Improved MIFARE™

Compatibility......................................... 48

6.12 NFC Modes.......................................... 48

6.13 Direct Commands from MCU to Reader ............ 51

6.14 Register Description................................. 55

7 Application Schematic and Layout

Considerations.......................................... 75

7.1 TRF7970A Reader System Using Parallel

Microcontroller Interface............................. 75

7.2 TRF7970A Reader System Using SPI With SS

Mode ................................................ 76

7.3 Layout Considerations .............................. 77

7.4 Impedance Matching TX_Out (Pin 5) to 50 Ω ...... 77

7.5 Reader Antenna Design Guidelines ................ 79

8 Device and Documentation Support ............... 80

8.1 Documentation Support ............................. 80

8.2 Community Resources.............................. 80

8.3 Trademarks.......................................... 80

8.4 Electrostatic Discharge Caution..................... 80

8.5 Glossary............................................. 80

9 Mechanical Packaging and Orderable

Information .............................................. 80

9.1 Packaging Information .............................. 80

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SLOS743K –AUGUST 2011–REVISED APRIL 2014

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision J (February 2014) to Revision K Page

• Changed Figure 1-1 to show 127-byte FIFO...................................................................................... 2

• Moved Section 3...................................................................................................................... 5

• Changed title of Section 4 .......................................................................................................... 6

• Changed title of Section 5 ........................................................................................................... 9

• Added ASK/OOK and MOD to VILand V

• Moved Section 5.3 .................................................................................................................. 10

• Changed V

TYP value from 3.5 V to 3.4 V ................................................................................. 10

DD_A

• Moved Section 5.4 .................................................................................................................. 11

• Added V

MIN values, test specifications, and notes....................................................................... 11

(ESD)

• Changed title of Section 5.5 from Dissipation Ratings to Thermal Characteristics......................................... 11

• Moved Section 5.6 .................................................................................................................. 11

• Changed title of Section 6.......................................................................................................... 12

• Moved previous Section 3, Device Overview, to Section 6.1.................................................................. 12

• Changed from "By default, the AGC is frozen after..." to "By default, the AGC window comparator is set after..." ... 21

• Changed from "TX Pulse Length Control register (0x05)" to "TX Pulse Length Control register (0x06)" ............... 28

• Changed from "18.8 s" to "18.8 µs" in the sentence that starts with "If the register contains all zeros..."............... 28

• Changed Table 6-18 to match Table 6-43 ....................................................................................... 50

• Changed command 0x18 to "Test internal RF" ................................................................................. 51

• Changed command 0x19 to "Test external RF" ................................................................................ 51

• Moved Section 6.14................................................................................................................. 55

• Changed the sentence that starts "The AGC action is fast..." from "finishes after four subcarrier pulses" to

"finishes within eight subcarrier pulses" ......................................................................................... 64

• Moved Section 7..................................................................................................................... 75

• Deleted previous Section 10, System Design, and moved contents to Section 7.3 through Section 7.5 ............... 77

• Removed references to figure numbers in Figure 7-3.......................................................................... 78

........................................................................................ 9

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3 Device Characteristics

Table 3-1 shows the supported modes of operation for the TRF7970A device.

Table 3-1. Supported Modes of Operation

P2P Initiator or Reader/Writer Card Emulation P2P Target

Technology Technology Technology

NFC-A/B (ISO14443A/B) NFC-A/B 106 NFC-A 106

NFC-F (JIS: X6319-4) 212, 424 N/A N/A NFC-F 212, 424

NFC-V (ISO15693) 6.7, 26.7 N/A N/A N/A N/A

(1) 848 kbps only applies to reader/writer mode.

Bit rate Bit rate Bit rate

(kbps) (kbps) (kbps)

106, 212, 424,

(1)

848

TRF7970A

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VDD_A

VIN

VDD_RF

VDD_PA

TX_OUT

VSS_PA

VSS_RX

RX_IN1

I/0_7

RX_IN2

VSS

ASK/OOK

IRQ

MOD

VSS_A

VDD_I/O

Pad

VDD_X

OSC_IN

OSC_OUT

VSS_D

SYS_CLK

DATA_CLK

EN2

9 10

11 12

15 16

32 31 30

29 28

26 25

I/0_6

I/0_5

I/0_4

I/0_3

I/0_2

I/0_1

I/0_0

TRF7970A

SLOS743K –AUGUST 2011–REVISED APRIL 2014

4 Terminal Configuration and Functions

4.1 Pin Assignments

Figure 4-1 shows the pin assignments for the 32-pin RHB package.

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Figure 4-1. 32-Pin RHB Package (Top View)

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4.2 Terminal Functions

Table 4-1 describes the signals.

Table 4-1. Terminal Functions

TERMINAL

NAME NO.

DD_A

DD_RF

DD_PA

1 OUT Internal regulated supply (2.7 V to 3.4 V) for analog circuitry 2 SUP External supply input to chip (2.7 V to 5.5 V) 3 OUT Internal regulated supply (2.7 V to 5 V), normally connected to V

4 INP Supply for PA; normally connected externally to V TX_OUT 5 OUT RF output (selectable output power, 100 mW or 200 mW, with VDD= 5 V) V

SS_PA

SS_RX

6 SUP Negative supply for PA; normally connected to circuit ground

7 SUP Negative supply for RX inputs; normally connected to circuit ground RX_IN1 8 INP Main RX input RX_IN2 9 INP Auxiliary RX input V

10 SUP Chip substrate ground

BAND_GAP 11 OUT Bandgap voltage (VBG= 1.6 V); internal analog voltage reference

ASK/OOK 12 BID

IRQ 13 OUT Interrupt request

MOD 14

SS_A

DD_I/O

15 SUP Negative supply for internal analog circuits; connected to GND

16 INP Supply for I/O communications (1.8 V to VIN) level shifter. VINshould be never exceeded. I/O_0 17 BID I/O pin for parallel communication I/O_1 18 BID I/O pin for parallel communication

I/O_2 19 BID

I/O_3 20 BID

I/O_4 21 BID

I/O_5 22 BID

I/O_6 23 BID MISO for serial communication (SPI)

I/O_7 24 BID

EN2 25 INP DATA_CLK 26 INP Data Clock input for MCU communication (parallel and serial)

(1)

TYPE

DESCRIPTION

DD_RF

Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for Direct Mode 0 or 1. Can be configured as an output to provide the received analog signal output.

INP External data modulation input for Direct Mode 0 or 1

OUT Subcarrier digital data output (see registers 0x1A and 0x1B)

I/O pin for parallel communication TX Enable (in Special Direct Mode) I/O pin for parallel communication TX Data (in Special Direct Mode) I/O pin for parallel communication Slave Select signal in SPI mode I/O pin for parallel communication Data clock output in Direct Mode 1 and Special Direct Mode I/O pin for parallel communication

Serial bit data output in Direct Mode 1 or subcarrier signal in Direct Mode 0 I/O pin for parallel communication. MOSI for serial communication (SPI) Selection of power down mode. If EN2 is connected to VIN, then V

down mode 2 (for example, to supply the MCU).

DD_PA

(pin 3)

DD_X

TRF7970A

(pin 4)

is active during power

If EN = 1 (EN2 = don't care) the system clock for MCU is configured. Depending on the crystal that is used, options are as follows (see register 0x09):

SYS_CLK 27 OUT

13.56-MHz crystal: Off, 3.39 MHz, 6.78 MHz, or 13.56 MHz

27.12-MHz crystal: Off, 6.78 MHz, 13.56 MHz, or 27.12 MHz

If EN = 0 and EN2 = 1, then system clock is set to 60 kHz EN 28 INP Chip enable input (If EN = 0, then chip is in sleep or power-down mode). V

SS_D

29 SUP Negative supply for internal digital circuits

(1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output

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Table 4-1. Terminal Functions (continued)

TERMINAL

NAME NO.

OSC_OUT 30 OUT Crystal or oscillator output

OSC_IN 31

DD_X

32 OUT

Thermal Pad PAD SUP Chip substrate ground

(1)

TYPE

INP Crystal or oscillator input

OUT Crystal oscillator output

Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example,

MCU)

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DESCRIPTION

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5 Specifications

TRF7970A

SLOS743K –AUGUST 2011–REVISED APRIL 2014

5.1 Absolute Maximum Ratings

(1) (2)

over operating free-air temperature range (unless otherwise noted)

Input voltage range -0.3 V to 6 V

Maximum current V

Maximum operating virtual junction temperature

Any condition 140°C Continuous operation, long-term reliability

(3)

150 mA

125°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Operating Conditions are not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to substrate ground terminal VSS. (3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may

result in reduced reliability or lifetime of the device.

5.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

Operating input voltage 2.7 5 5.5 V Operating ambient temperature -40 25 110 °C Operating virtual junction temperature -40 25 125 °C

Input voltage - logic low V

Input voltage threshold, logic high V

I/O lines, IRQ, SYS_CLK, DATA_CLK, 0.2 x EN, EN2, ASK/OOK, MOD V

DD_I/O

I/O lines, IRQ, SYS_CLK, DATA_CLK, 0.8 x EN, EN2, ASK/OOK, MOD V

DD_I/O

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5.3 Electrical Characteristics

TYP operating conditions are TA= 25°C, VIN = 5 V, full-power mode (unless otherwise noted) MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PD1

PD2

STBY

ON1

ON2

ON3

POR

DD_A

DD_X

VDD_Xmax

RFOUT

RFIN

RF_INmax

RF_INmin

SYS_CLK

CRYSTAL

D_CLKmax

OUT

SYS_CLK

Supply current in Power Down Mode 1 voltage regulators; measured after 500-ms 0.5 5 µA

Supply current in Power Down Mode 2 (Sleep Mode)

Supply current in stand-by mode 1.9 3.5 mA Supply current without antenna driver Oscillator, regulators, RX and AGC active, TX

current is off Supply current – TX (half power) 70 78 mA

Supply current – TX (full power) 130 150 mA Power-on reset voltage Input voltage at V

Bandgap voltage (pin 11) Internal analog reference voltage 1.5 1.6 1.7 V Regulated output voltage for analog

circuitry (pin 1) Regulated supply for external circuitry Output voltage pin 32, VIN= 5 V 3.1 3.4 3.8 V Maximum output current of V

Antenna driver output resistance

DD_X

(1)

RX_IN1 and RX_IN2 input resistance 4 10 20 kΩ Maximum RF input voltage at RX_IN1 and

RX_IN2 Minimum RF input voltage at RX_IN1 and

RX_IN2 (input sensitivity)

(2)

SYS_CLK frequency In power mode 2, EN = 0, EN2 = 1 25 60 120 kHz Carrier frequency Defined by external crystal 13.56 MHz

Crystal run-in time 3 ms

Maximum DATA_CLK frequency

(4)

Output resistance I/O_0 to I/O_7 500 800 Ω Output resistance R

SYS_CLK

(1) Antenna driver output resistance (2) Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1. (3) Depends on the crystal parameters and components (4) Recommended DATA_CLK speed is 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not

exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output

resistance of 400 Ω (12-ns time constant when 30-pF load used).

All building blocks disabled, including supplysettling time (EN = 0, EN2 = 0)

The SYS_CLK generator and V active to support external circuitry; measured 120 200 µA

DD_X

remain

after 100-ms settling time (EN = 0, EN2 = 1) Oscillator running, supply-voltage regulators in

low-consumption mode (EN = 1, EN2 = x)

10.5 14 mA

Oscillator, regulators, RX and AGC and TX active, P

OUT

= 100 mW

Oscillator, regulators, RX and AGC and TX active, P

OUT

= 200 mW

1.4 2 2.6 V

VIN= 5 V 3.1 3.4 3.8 V

Output current pin 32, VIN= 5 V 20 mA Half-power mode, VIN= 2.7 V to 5.5 V 8 12 Full-power mode, VIN= 2.7 V to 5.5 V 4 6

RF_INmax

SUBCARRIER

Time until oscillator stable bit is set (register 0x0F)

Depends on capacitive load on the I/O lines, recommendation is 2 MHz

should not exceed V

= 424 kHz 1.4 2.5

= 848 kHz 2.1 3

(3)

(4)

2 8 10 MHz

3.5 V

200 400 Ω

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5.4 Handling Ratings

MIN MAX UNIT

T V

STG (ESD)

Storage temperature range -55 150 °C Electrostatic discharge Human-Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

Charged-Device Model (CDM), per JEDEC specification JESD22-C101, -500 500 V

(2)

all pins

(1)

-2 2 kV

Machine Model (MM) -200 200 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 2 kV

may actually have higher performance. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 500 V

may actually have higher performance.

5.5 Thermal Characteristics

PACKAGE θ

(1)

TA≤ 25°C TA≤ 85°C

POWER RATING

RHB (32 pin) 31°C/W 36.4°C/W 2.7 W 1.1 W

(1) This data was taken using the JEDEC standard high-K test PCB. (2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to increase substantially.

Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-

term reliability.

(2)

5.6 Switching Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LO/HI

STE,LEAD

STE,LAG

STE,DIS

SU,SI

HD,SI

SU,SO

HD,SO

VALID,SO

DATA_CLK time high or low, one half of DATA_CLK at 50% duty cycle

Depends on capacitive load on the I/O lines

Slave select lead time, slave select low to clock

Slave select lag time, last clock to slave select high

Slave select disable time, slave select rising edge to next slave select falling 300 ns edge

MOSI input data setup time 15 ns MOSI input data hold time 15 ns MISO input data setup time 15 ns MISO input data hold time 15 ns MISO output data valid time DATA_CLK edge to MISO valid, CL≤ 30 pF 30 50 75 ns

(1)

250 62.5 50 ns

200 ns

(1) Recommended DATA_CLK speed is 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not

exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output

resistance of 400 Ω (12-ns time constant when 30-pF load used).

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TRF7970A

MCU

(MSP430/ARM)

Matching

DD_X

DD_I/O

TX_OUT

RX_IN 1

RX_IN2

VSSV

Parallel

or SPI

Supply: 2.7 V – 5.5 V

Crystal

13.56 MHz

XIN

TRF7970A

SLOS743K –AUGUST 2011–REVISED APRIL 2014

6 Detailed Description

6.1 Overview

6.1.1 RFID and NFC Operation – Reader and Writer

The TRF7970A is a high performance 13.56-MHz HF RFID and NFC Transceiver IC composed of an integrated analog front end (AFE) and a built-in data framing engine for ISO15693, ISO14443A/B, and FeliCa. This includes data rates up to 848 kbps for ISO14443 with all framing and synchronization tasks on board (in default mode). The TRF7970A also supports NFC Tag Type 1, 2, 3, and 4 operations. This architecture enables the customer to build a complete cost-effective yet high-performance multi-protocol

13.56-MHz RFID and NFC system together with a low-cost microcontroller. Other standards and even custom protocols can be implemented by using either of the Direct Modes that

the device offers. These Direct Modes (0 and 1) allow the user to fully control the analog front end (AFE) and also gain access to the raw subcarrier data or the unframed but already ISO formatted data and the associated (extracted) clock signal.

The receiver system has a dual input receiver architecture. The receivers also include various automatic and manual gain control options. The received input bandwidth can be selected to cover a broad range of input subcarrier signal options.

The received signal strength from transponders, ambient sources, or internal levels is available through the RSSI register. The receiver output is selectable among a digitized subcarrier signal and any of the integrated subcarrier decoders. The selected subcarrier decoder delivers the data bit stream and the data clock as outputs.

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The TRF7970A also includes a receiver framing engine. This receiver framing engine performs the CRC or parity check, removes the EOF and SOF settings, and organizes the data in bytes for ISO14443A/B, ISO15693, and FeliCa protocols. Framed data is then accessible to the microcontroller (MCU) through a 127-byte FIFO register.

A parallel or serial interface (SPI) can be used for the communication between the MCU and the TRF7970A reader. When the built-in hardware encoders and decoders are used, transmit and receive functions use a 127-byte FIFO register. For direct transmit or receive functions, the encoders and decoders can be bypassed so that the MCU can process the data in real time. The TRF7970A supports data communication voltage levels from 1.8 V to 5.5 V for the MCU I/O interface. The transmitter has

Figure 6-1. Application Block Diagram

selectable output-power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ω load when using a 5-V supply.

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The transmitter supports OOK and ASK modulation with selectable modulation depth. The TRF7970A also includes a data transmission engine that comprises low-level encoding for ISO15693, ISO14443A/B and FeliCa. Included with the transmit data coding is the automatic generation of Start Of Frame (SOF), End Of Frame (EOF), Cyclic Redundancy Check (CRC), or parity bits.

Several integrated voltage regulators ensure a proper power-supply noise rejection for the complete reader system. The built-in programmable auxiliary voltage regulator V 20 mA to supply a microcontroller and additional external circuits within the reader system.

6.1.2 NFC Device Operation – Initiator

The desired system of operation (bit rate) is achieved by selecting the option bits in control registers in the same way as for RFID reader operation. Also the communication to external MCU and data exchange is identical.

The transmitting system comprises an RF level detector (programmable level) which is used for initial (or response) RF collision avoidance. The RF collision avoidance sequence is started by sending a direct command. If successful, the NFC initiator can send the data or commands, the MCU has loaded in the FIFO register. The coding of this data is done by hardware coders either in ISO14443A/B format or in FeliCa format. The coders also provide CRC and parity bits (if required) and automatically add preambles, SOF, EOF, and synchronization bytes as defined by selected protocol.

The receiver system offers same analog features (AGC, AM/PM, bandwidth selection, etc.) as described previously in RFID and NFC reader and writer description. The system comprises integrated decoders for passive targets (ISO14443A/B tag or FeliCa) or active targets (ISO14443A/B reader or FeliCa). For all this options, the system also supports framing including CRC and parity check and removal of SOF, EOF, and synchronization bytes as specified by the selected protocol.

TRF7970A

SLOS743K –AUGUST 2011–REVISED APRIL 2014

(pin 32), is able to deliver up to

DD_X

6.1.3 NFC Device Operation – Target

The desired system of operation (bit rate) is achieved by selecting the option bits in control registers in the same way as for RFID reader or NFC initiator operation. Also the communication to external MCU and data exchange is identical.

The activation of NFC target is done when a sufficient RF field level is detected on the antenna. The level needed for wake-up is selectable and is stored in non-volatile register.

When the activation occurs, the system performs automatic power-up and waits for the first command to be received. Based on this command, the system knows if it should operate as passive or active target and at what bit rate. After activation, the receiver system offers the same analog features (for example, AGC, AM/PM, and bandwidth selection) as in the case of an RFID reader.

When used as the NFC target, the chip is typically in a power down or standby mode. If EN2 = H, the chip keeps the supply system on. If EN2 = L and EN = L, the chip is in complete power down. To operate as NFC target or Tag emulator, the MCU must load a value different from zero (0) in Target Detection Level register (B0-B2) to enable the RF measurement system (supplied by VEXT, so it can operate also during complete power down and consumes only 3.5 µA). The RF measurement constantly monitors the RF signal on the antenna input. When the RF level on the antenna input exceeds the level defined in the in Target Detection Level register, the chip is automatically activated (EN is internally forced high).

When the voltage supply system and the oscillator are started and are stable, osc_ok goes high (B6 of RSSI Level and Oscillator Status register) and IRQ is sent with bit B2 = 1 of IRQ register (field change). Bit B7 NFC Target Protocol in register directly displays the status of RF level detection (running constantly also during normal operation). This informs the MCU that the chip should start operation as NFC TARGET device. When the first command from the INITIATOR is received another IRQ sent with B6 (RX start) set

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in IRQ register. The MCU must set EN = H (confirm the power-up) in the time between the two IRQs, because the internal power-up ends after the second IRQ. The type and coding of the first initiator (or reader in the case of a tag emulator) command defines the communication protocol type that the target must use. Therefore, the communication protocol type is available in the NFC Target Protocol register immediately after receiving the first command.

Based on the first command from the INITIATOR, the following actions are taken:

• If the first command is SENS_REQ or ALL_REQ the TARGET must enter the SDD protocol for 106kbps passive communication to begin; afterward, the baud rate can be changed to 212 kbps or 424 kbps, according to the system requirements. If bit B5 in the NFC Target Detection Level register is not set, the MCU handles the SDD and the command received is send to FIFO. If the RF field is turned off (B7 in NFC Target Protocol register is low) at any time, the system sends an IRQ to the MCU with bit B2 (RF field change) in the IRQ register set high. This informs the MCU that the procedure was aborted and the system must be reset. The clock extractor is automatically activated in this mode.

• If the command is SENS_REQ or ALL_REQ and the card emulation bit in ISO Control register is set, the system emulates an ISO14443A/B tag. The procedure does not differ from the one previously described for the case of a passive target at 106 kbps. The clock extractor is automatically activated in this mode. To emulate a FeliCa card, the ISO Control register must be set for passive target mode at either 212 kbps or 424 kbps.

• If the first command is a POLLING request, the system becomes the TARGET in passive communication using 212 kbps or 424 kbps. The SDD is relatively simple and is handled by the MCU directly. The POLLING response is sent in one of the slots automatically calculated by the MCU (first slot starts 2.416 ms after end of command, and slots follow in 1.208 ms).

• If the first command is ATR_REQ, the system operates as an active TARGET using the same communication speed and bit coding as used by the INITIATOR. Again, all of the replies are handled by MCU. The chip is only required to time the response collision avoidance, which is done on direct command from MCU. When the RF field is switched on and the minimum wait time is elapsed, the chip sends an IRQ with B1 (RF collision avoidance finished) set high. This signals the MCU that it can send the reply.

• If the first command is coded as ISO14443B and the Tag emulation bit is set in the ISO Control register, the system enters ISO14443B emulation mode. The anticollision must be handled by the MCU, and the chip provides all physical level coding, decoding, and framing for this protocol.

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6.1.3.1 Active Target

If the first command received by the RF interface defines the system as an active target, then the receiver selects the appropriate data decoders (ISO14443A\B reader or FeliCa) and framing option. Only the raw (decoded) data is forwarded to the MCU through the FIFO. SOF, EOF, preamble, sync bytes, CRC, and parity bytes are checked by the framer and discarded.

The transmitting system includes an RF level detector (programmable level) that is used for RF collision avoidance. The RF collision avoidance sequence is started by sending a direct command. If successful, the NFC initiator can send the data that the MCU has loaded in the FIFO register. The coding of this data is done by hardware coders either in ISO14443A format (106-kbps system) or in FeliCa format for (212kbps and 424-kbps systems). The coders also provide CRC and parity bits (if required) and automatically add preambles, SOF, EOF, and synchronization bytes as defined by selected protocol.

6.1.3.2 Passive Target

If the first command received by the RF interface defines the system as a passive target, then the receiver selects the appropriate data decoders (ISO14443A\B reader or FeliCa) and framing option. Again, only the raw (decoded) data is forwarded to the MCU through the FIFO; SOF, EOF, preamble, sync bytes, CRC, and parity bytes are checked by the framer and discarded. The receiver works same as in the case of an active target.

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MUX

RX_IN1

RX_IN2

PHASE&

AMPLITUDE

DETECTOR

GAIN

RSSI (AUX)

LOGIC

LEVEL SHI FTER

STATE

CONTROL

LOGIC

[CONTROL

REGISTERS&

COMMAND

LOGIC]

127-BYTE

FIFO

MCU

INTERFACE

VDD_I/O

I/O_0

I/O_1

I/O_2

I/O_3

I/O_4

I/O_5

I/O_6

I/O_7

IRQ

SYS_CLK

DATA_CLK

ISO PROTOCOL HANDLING

DECODER

RSSI

(EXTERNAL)

PHASE&

AMPLITUDE

DETECTOR

GAIN

RSSI

(MAIN)

FILTER & AGC

DIGITIZER

BIT

FRAMING

SERIAL

CONVERSION

CRC &PARITY

TRANSMITTER ANALOG

FRONT END

TX_OUT

VDD_PA

VSS_PA

DIGITAL CONTROL

STATE MACHINE

CRYSTAL OR OSCILLATOR

TIMING SYSTEM

EN2

ASK/OOK

MOD

OSC_IN

OSC_OUT

VOLTAGE SUPPLY REGULATOR SYSTEMS

(SUPPLY REGULATORS AND REFERENCE VOLTAGES)

VSS_A

VSS_RF

VDD_RF

VDD_X

VSS_D

VSS

VIN

VDD_A

BAND_GAP

RF LEVEL

DETECTOR

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The transmit system in passive target mode differs from active target and operates similar to the standard tag. There is no automatic RF collision avoidance sequence, and encoders are used to code the data for ISO14443A\B tag (at 106 kbps, to start) or FeliCa (at 212 kbps, to start) format. The collision avoidance must be handled by the firmware on the connected MCU. The coding system adds all of the SOF, EOF, CRC, parity bits, and synchronization bytes that are required by protocol. On the physical level, the modulation of the initiator's RF field is done by changing the termination impedance of the antenna between 4 Ω and open.

6.1.3.3 Card Emulation

The chip can enter this mode by setting appropriate option bits. There are two options to emulate a card. For ISO14443A\B, the emulation supports 106-kbps data rate to start. For ISO14443A, the anticollision algorithm can be performed using an internal state machine, which relieves the MCU of any real-time tasks. The unique ID required for anticollision is provided by the MCU after wake-up of the system.

6.2 System Block Diagram

Figure 6-2 shows a block diagram of the TRF7970A.

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6.3 Power Supplies

The TRF7970A positive supply input VIN(pin 2) sources three internal regulators with output voltages V

DD_RF

, V

DD_A

and V be connected as indicated in reference schematics. These regulators provide a high power supply reject ratio (PSRR) as required for RFID reader systems. All regulators are supplied by VIN(pin 2).

The regulators are not independent and have common control bits in register 0x0B for output voltage setting. The regulators can be configured to operate in either automatic or manual mode (register 0x0B,

. All regulators use external bypass capacitors for supply noise filtering and must

DD_X

Figure 6-2. System Block Diagram

bit 7). The automatic regulator setting mode ensures an optimal compromise between PSRR and the highest possible supply voltage for RF output (to ensure maximum RF power output). The manual mode allows the user to manually configure the regulator settings.

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6.3.1 Supply Arrangements

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Regulator Supply Input: V

The positive supply at VIN(pin 2) has an input voltage range of 2.7 V to 5.5 V. VINprovides the supply input sources for three internal regulators with the output voltages V

DD_RF

, V

DD_A

, and V

DD_X

. External

bypass capacitors for supply noise filtering must be used (per reference schematics).

NOTE

VINmust be the highest voltage supplied to the TRF7970A.

RF Power Amplifier Regulator: V

The V

(pin 3) regulator is supplying the RF power amplifier. The voltage regulator can be set for

DD_RF

either 5-V or 3-V operation. External bypass capacitors for supply noise filtering must be used (per reference schematics). When configured for 5-V manual-operation, the V

output voltage can be set

DD_RF

from 4.3 V to 5 V in 100-mV steps. In 3-V manual-operation, the output can be programmed from 2.7 V to

3.4 V in 100-mV steps. The maximum output current capability for 5-V operation is 150 mA and for 3-V operation is 100 mA.

Analog Supply Regulator: V

Regulator V

(pin 1) supplies the analog circuits of the device. The output voltage setting depends on

DD_A

the input voltage and can be set for 5-V and 3-V operation. When configured for 5-V manual-operation, the output voltage is fixed at 3.4 V. External bypass capacitors for supply noise filtering must be used (per reference schematics). When configured for 3-V manual-operation, the V

output can be set from 2.7 V

DD_A

to 3.4 V in 100-mV steps (see Table 6-2). Note: the configuration of V

DD_A

and V

regulators are not independent from each other. The V

DD_X

DD_A

output current should not exceed 20 mA.

Digital Supply Regulator: V

The digital supply regulator V

DD_X

(pin 32) provides the power for the internal digital building blocks and

DD_X

can also be used to supply external electronics within the reader system. When configured for 3-V operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV steps. External bypass capacitors for supply noise filtering must be used (per reference schematics).

Note: the configuration of the V

DD_A

and V

regulators are not independent from each other. The V

DD_X

output current should not exceed 20 mA. The RF power amplifier regulator (V

) can be configured to operate in either automatic or manual mode described in Section 6.3.2. The

DD_X

), analog supply regulator (V

DD_RF

) and digital supply regulator

DD_A

automatic regulator setting mode ensures an optimal compromise between PSRR and the highest possible supply voltage to ensure maximum RF power output.

By default, the regulators are set in automatic regulator setting mode. In this mode, the regulators are automatically set every time the system is activated by setting EN input High or each time the automatic regulator setting bit, B7 in register 0x0B is set to a 1. The action is started on the 0 to 1 transition. This means that, if the user wants to re-run the automatic setting from a state in which the automatic setting bit is already high, the automatic setting bit (B7 in register 0x0B) should be changed: 1-0-1.

By default, the regulator setting algorithm sets the regulator outputs to a "Delta Voltage" of 250 mV below VIN, but not higher than 5 V for V

and 3.4 V for V

DD_RF

DD_A

and V

. The "Delta Voltage" in automatic

DD_A

regulator mode can be increased up to 400 mV (for details, see bits B0 to B2 in register 0x0B).

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Power Amplifier Supply: V

The power amplifier of the TRF7970A is supplied through V power amplifier is externally connected to the regulator output V

I/O Level Shifter Supply: V

The TRF7970A has a separate supply input V

DD_PA

DD_I/O

(pin 4). The positive supply pin for the RF

DD_PA

(pin 3).

DD_RF

(pin 16) for the built-in I/O level shifter. The supported

DD_I/O

input voltage ranges from 1.8 V to VIN, not exceeding 5.5 V. Pin 16 is used to supply the I/O interface pins (I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, V directly connected to V

DD_X

, while V

also supplies the MCU. This ensures that the I/O signal levels of

DD_X

DD_I/O

the MCU match the logic levels of the TRF7970A.

Negative Supply Connections: VSS, V

The negative supply connections V

SS_X

The substrate connection is VSS(pin 10), the analog negative supply is V supply is V the RF receiver V

(pin 29), the RF output stage negative supply is V

SS_D

(pin 7).

SS_RX

SS_TX

, V

SS_RX

, V

SS_A

, V

SS_PA

of each functional block are all externally connected to GND.

(pin 15), the logic negative

SS_A

(pin 6), and the negative supply for

SS_PA

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6.3.2 Supply Regulator Settings

The input supply voltage mode of the reader needs to be selected. This is done in the Chip Status Control register (0x00). Bit 0 in register 0x00 selects between 5-V or 3-V input supply voltage. The default configuration is 5 V, which reflects an operating supply voltage range of 4.3 V to 5.5 V. If the supply voltage is below 4.3 V, the 3-V configuration should be used.

The various regulators can be configured to operate in automatic or manual mode. This is done in the Regulator and I/O Control register (0x0B) as shown in Table 6-1 and Table 6-2.

Table 6-1. Supply Regulator Setting: 5-V System

(hex)

B7 B6 B5 B4 B3 B2 B1 B0

Automatic Mode (default)

0B 1 x x x x x 0 0 Automatic regulator setting 400-mV difference

Manual Mode

0B 0 x x x x 1 1 1 V 0B 0 x x x x 1 1 0 V 0B 0 x x x x 1 0 1 V 0B 0 x x x x 1 0 0 V 0B 0 x x x x 0 1 1 V 0B 0 x x x x 0 1 0 V 0B 0 x x x x 0 0 1 V 0B 0 x x x x 0 0 0 V

(1) x = Don't care

(1)

DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF

= 5 V, V = 4.9 V, V = 4.8 V, V = 4.7 V, V = 4.6 V, V = 4.5 V, V = 4.4 V, V = 4.3 V, V

DD_A

DD_A DD_A DD_A DD_A DD_A DD_A DD_A

= 3.4 V, V

= 3.4 V, V = 3.4 V, V = 3.4 V, V = 3.4 V, V = 3.4 V, V = 3.4 V, V = 3.4 V, V

DD_X

DD_X DD_X DD_X DD_X DD_X DD_X DD_X

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= 3.4 V

= 3.4 V = 3.4 V = 3.4 V = 3.4 V = 3.4 V = 3.4 V = 3.4 V

Table 6-2. Supply Regulator Setting: 3-V System

(hex)

B7 B6 B5 B4 B3 B2 B1 B0

Automatic Mode (default)

0B 1 x x x x x 0 0 Automatic regulator setting 400-mV difference

Manual Mode

0B 0 x x x x 1 1 1 V 0B 0 x x x x 1 1 0 V 0B 0 x x x x 1 0 1 V 0B 0 x x x x 1 0 0 V 0B 0 x x x x 0 1 1 V 0B 0 x x x x 0 1 0 V 0B 0 x x x x 0 0 1 V 0B 0 x x x x 0 0 0 V

(1) x = Don't care

(1)

DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF

= 3.4 V, V = 3.3 V, V = 3.2 V, V = 3.1 V, V = 3.0 V, V = 2.9 V, V = 2.8 V, V = 2.7 V, V

DD_A DD_A DD_A DD_A DD_A DD_A DD_A DD_A

= 3.4 V, V = 3.3 V, V = 3.2 V, V = 3.1 V, V = 3.0 V, V = 2.9 V, V = 2.8 V, V = 2.7 V, V

DD_X DD_X DD_X DD_X DD_X DD_X DD_X DD_X

The regulator configuration function adjusts the regulator outputs by default to 400 mV below VINlevel, but not higher than 5 V for V

, 3.4 V for V

DD_RF

DD_A

and V

. This ensures the highest possible supply

DD_X

voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection ratio).

= 3.4 V = 3.3 V = 3.2 V = 3.1 V = 3.0 V = 2.9 V = 2.8 V = 2.7 V

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6.3.3 Power Modes

The chip has several power states, which are controlled by two input pins (EN and EN2) and several bits in the chip status control register (0x00) (see Table 6-3 and Table 6-4).

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Table 6-3. 3.3-V Operation Power Modes

Chip

Mode EN2 EN Control Transmitter Receiver (13.56 V

Power Down 0 0 XX XX OFF OFF OFF OFF OFF <0.001 Sleep Mode 1 0 XX XX OFF OFF OFF ON ON 0.120 Standby Mode at

+3.3 VDC Mode 1 at +3.3 VDC X 1 00 00 OFF OFF ON X ON 3 Mode 2 at +3.3 VDC X 1 02 00 OFF ON ON X ON 9 Mode 3 (Half Power) at

+3.3 VDC Mode 4 (Full Power) at

+3.3 VDC

X 1 80 00 OFF OFF ON X ON 2 -

X 1 30 07 ON ON ON X ON 53 14.5

X 1 20 07 ON ON ON X ON 67 17

Status SYS_CLK Typical

(0x00)

Regulator Typical

Control SYS_CLK Power

(0x0B) (dBm)

(1)

DD_X

Current

(1) X = Don't care

Table 6-4. 5-V Operation Power Modes

Chip

Mode EN2 EN Control Transmitter Receiver (13.56 V

Power Down 0 0 XX XX OFF OFF OFF OFF OFF <0.001 Sleep Mode 1 0 XX XX OFF OFF OFF ON ON 0.120 Standby Mode at

+5 VDC Mode 1 at +5 VDC X 1 01 07 OFF OFF ON X ON 5 Mode 2 at +5 VDC X 1 03 07 OFF ON ON X ON 10.5 Mode 3 (Half Power) at

+5 VDC Mode 4 (Full Power) at

+5 VDC

X 1 81 07 OFF OFF ON X ON 3 -

X 1 31 07 ON ON ON X ON 70 20

X 1 21 07 ON ON ON X ON 130 23

Status SYS_CLK Typical

(0x00)

Regulator Typical

Control SYS_CLK Power

(0x0B) (dBm)

(1)

DD_X

Current

(1) X = Don't care

Table 6-3 and Table 6-4 show the configuration for the different power modes when using a 3.3-V or 5-V

system supply, respectively. The main reader enable signal is pin EN. When EN is set high, all of the reader regulators are enabled, the 13.56-MHz oscillator is running and the SYS_CLK (output clock for external micro controller) is also available.

The input pin EN2 has two functions:

• A direct connection from EN2 to VINto ensure the availability of the regulated supply V

DD_X

and an auxiliary clock signal (60 kHz, SYS_CLK) for an external MCU. This mode (EN = 0, EN2 = 1) is intended for systems in which the MCU is also being supplied by the reader supply regulator (V

DD_X

and the MCU clock is supplied by the SYS_CLK output of the reader. This allows the MCU supply and clock to be available during sleep mode.

• EN2 enables the start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this case the EN input is being controlled by the MCU (or other system device) that is without supply voltage during complete power down (thus unable to control the EN input). A rising edge applied to the EN2 input (which has an approximately 1-V threshold level) starts the reader supply system and 13.56MHz oscillator (identical to condition EN = 1).

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)

VIN

EN2

5 ms

6 ms

VIN

EN2

2 ms

5 ms

6 ms

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When user MCU is controlling EN and EN2, a delay of 1 ms between EN and EN2 must be used. If the MCU controls only EN, EN2 is recommended to be connected to either VINor GND, depending on the application MCU requirements for V

Figure 6-3. Nominal Start-Up Sequence Using SPI With SS (MCU Controls EN2)

and SYS_CLK.

DD_X

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Figure 6-4. Nominal Start-Up Sequence Using Parallel (MCU Controls EN2)

This start-up mode lasts until all of the regulators have settled and the 13.56-MHz oscillator has stabilized. If the EN input is set high (EN = 1) by the MCU (or other system device), the reader stays active. If the EN input is not set high (EN = 0) within 100 µs after the SYS_CLK output is switched from auxiliary clock (60 kHz) to high-frequency clock (derived from the crystal oscillator), the reader system returns to complete Power-Down Mode 1. This option can be used to wake-up the reader system from complete Power Down (PD Mode 1) by using a pushbutton switch or by sending a single pulse.

After the reader EN line is high, the other power modes are selected by control bits within the chip status control register (0x00). The power mode options and states are listed in Table 6-3.

When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1) the supply regulators are activated and the 13.56-MHz oscillator started. When the supplies are settled and the oscillator frequency is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the 13.56-MHz frequency derived from the crystal oscillator. At this point, the reader is ready to communicate and perform the required tasks. The MCU can then program the chip status control register 0x00 and select the operation mode by programming the additional registers.

• Stand-by Mode (bit 7 = 1 of register 0x00), the reader is capable of recovering to full operation in 100 µs.

• Mode 1 (active mode with RF output disabled, bit 5 = 0 and bit 1 = 0 of register 0x00) is a low power mode which allows the reader to recover to full operation within 25 µs.

• Mode 2 (active mode with only the RF receiver active, bit 1 = 1 of register 0x00) can be used to measure the external RF field (as described in RSSI measurements paragraph) if reader-to-reader anticollision is implemented.

• Modes 3 and 4 (active modes with the entire RF section active, bit 5 = 1 of register 0x00) are the normal modes used for normal transmit and receive operations.

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6.4 Receiver – Analog Section

6.4.1 Main and Auxiliary Receivers

The TRF7970A has two receiver inputs: RX_IN1 (pin 8) and RX_IN2 (pin 9). Each of the input is connected to an external capacitive voltage divider to ensure that the modulated signal from the tag is available on at least one of the two inputs. This architecture eliminates any possible communication holes that may occur from the tag to the reader.

The two RX inputs (RX_IN1 and RX_IN2) are multiplexed into two receivers - the main receiver and the auxiliary receiver. Only the main receiver is used for reception, the auxiliary receiver is used for signal quality monitoring. Receiver input multiplexing is controlled by bit B3 in the Chip Status Control register (address 0x00).

After startup, RX_IN1 is multiplexed to the main receiver which is composed of an RF envelope detection, first gain and band-pass filtering stage, second gain and filtering stage with AGC. Only the main receiver is connected to the digitizing stage which output is connected to the digital processing block. The main receiver also has an RSSI measuring stage, which measures the strength of the demodulated signal (subcarrier signal).

The primary function of the auxiliary receiver is to monitor the RX signal quality by measuring the RSSI of the demodulated subcarrier signal (internal RSSI). After startup, RX_IN2 is multiplexed to the auxiliary receiver. The auxiliary receiver has an RF envelope detection stage, first gain and filtering with AGC stage and finally the auxiliary RSSI block.

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The default MUX setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary receiver. To determine the signal quality, the response from the tag is detected by the "main" (pin RX_IN1) and "auxiliary" (pin RX_IN2) RSSI. Both values measured and stored in the RSSI level register (address 0x0F). The MCU can read the RSSI values from the TRF7970A RSSI register and make the decision if swapping the input- signals is preferable or not. Setting B3 in Chip Status Control register (address 0x00) to 1 connects RX_IN1 (pin 8) to the auxiliary received and RX_IN2 (pin 9) to the main receiver. This mechanism needs to be used to avoid reading holes.

The main and auxiliary receiver input stages are RF envelope detectors. The RF amplitude at RX_IN1 and RX_IN2 should be approximately 3 VPP for a VINsupply level greater than 3.3 V. If the VINlevel is lower, the RF input peak-to-peak voltage level should not exceed the VINlevel.

6.4.2 Receiver Gain and Filter Stages

The first gain and filtering stage has a nominal gain of 15 dB with an adjustable band-pass filter. The band-pass filter has programmable 3d-B corner frequencies between 110 kHz to 450 kHz for the highpass filter and 570 kHz to 1500 kHz for the low-pass filter. After the band-pass filter, there is another gainand-filtering stage with a nominal gain of 8 dB and with frequency characteristics identical to the first bandpass stage.

The internal filters are configured automatically depending on the selected ISO communication standard in the ISO Control register (address 0x01). If required, additional fine tuning can be done by writing directly to the RX special setting registers (address 0x0A).

The main receiver also has a second receiver gain and digitizer stage which is included in the AGC loop. The AGC loop is activated by setting the bit B2 = 1 in the Chip Status Control register (0x00). When activated, the AGC continuously monitors the input signal level. If the signal level is significantly higher than an internal threshold level, gain reduction is activated.

By default, the AGC window comparator is set after the first 4 pulses of the subcarrier signal. This prevents the AGC from interfering with the reception of the remaining data packet. In certain situations, this AGC freeze is not optimal, so it can be removed by setting B0 = 1 in the RX special setting register (address 0x0A).

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Table 6-5. RX Special Setting Register (0x0A)

Function: Sets the gains and filters directly Default: 0x40 at POR = H or EN = L, and at each write to the ISO Control register 0x01. When bits B7, B6, B5 and B4 are all zero, the

filters are set for ISO14443B (240 kHz to 1.4 MHz).

Bit Name Function Description

B7 C212 Bandpass 110 kHz to 570 kHz Appropriate for 212-kHz subcarrier system (FeliCa) B6 C424 Bandpass 200 kHz to 900 kHz Appropriate for 424-kHz subcarrier used in ISO15693

B5 M848 Bandpass 450 kHz to 1.5 MHz

B4 hbt Appropriate for highest bit rate (848 kbps) used in high-bit-rate ISO14443 B3 gd1 00 = Gain reduction 0 dB

B2 gd2

B1 agcr AGC activation level change

B0 no-lim AGC action is not limited in time

Bandpass 100 kHz to 1.5 MHz Gain reduced for 18 dB

01 = Gain reduction for 5 dB 10 = Gain reduction for 10 dB 11 = Gain reduction for 15 dB

Appropriate for Manchester-coded 848-kHz subcarrier used in ISO14443A and B

Sets the RX gain reduction, and reduces sensitivity

AGC activation level changed from five times the digitizing level to three times the digitizing level. 1 = 3x 0 = 5x

AGC action can be done any time during receive process. It is not limited to the start of receive ("max hold"). 1 = continuously – no time limit 0 = 8 subcarrier pulses

Table 6-5 shows the various settings for the receiver analog section. It is important to note that setting B4,

B5, B6, and B7 to 0 results to a band-pass characteristic of 240 kHz to 1.4 MHz, which is appropriate for ISO14443B 106 kbps, ISO14443A/B data-rates of 212 kbps and 424 kbps and FeliCa 424 kbps.

6.5 Receiver – Digital Section

The output of the TRF7970A analog receiver block is a digitized subcarrier signal and is the input to the digital receiver block. This block includes a Protocol Bit Decoder section and the Framing Logic section.

The protocol bit decoders convert the subcarrier coded signal into a serial bit stream and a data clock. The decoder logic is designed for maximum error tolerance. This enables the decoder section to successfully decode even partly corrupted subcarrier signals that otherwise would be lost due to noise or interference.

In the framing logic section, the serial bit stream data is formatted in bytes. Special signals such as the start of frame (SOF), end of frame (EOF), start of communication, and end of communication are automatically removed. The parity bits and CRC bytes are also checked and removed. This "clean" data is then sent to the 127-byte FIFO register where it can be read by the external microcontroller system. Providing the data this way, in conjunction with the timing register settings of the TRF7970A means the firmware developer has to know about much less of the finer details of the ISO protocols to create a very robust application, especially in low cost platforms where code space is at a premium and high performance is still required.

The start of the receive operation (successfully received SOF) sets the IRQ-flags in the IRQ and Status register (0x0C). The end of the receive operation is signaled to the external system MCU by setting pin 13 (IRQ) to high. When data is received in the FIFO, an interrupt is sent to the MCU to signal that there is data to be read from the FIFO. The FIFO status register (0x1C) should be used to provide the number of bytes that should be clocked out during the actual FIFO read.

Any error in the data format, parity, or CRC is detected and notified to the external system by an interruptrequest pulse. The source condition of the interrupt request pulse is available in the IRQ status register (0x0C). The main register controlling the digital part of the receiver is the ISO Control register (0x01). By writing to this register, the user selects the protocol to be used. With each new write in this register, the default presets are reloaded in all related registers, so no further adjustments in other registers are needed for proper operation.

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The framing section also supports the bit-collision detection as specified in ISO14443A. When a bit collision is detected, an interrupt request is sent and a flag is set in the IRQ and Status register (0x0C). The position of the bit collision is written in two registers: Collision Position register (0x0E) and partly in Collision Position and Interrupt Mask register (0x0D) (bits B6 and B7).

The collision position is presented as sequential bit number, where the count starts immediately after the start bit. This means a collision in the first bit of a UID would give the value 00 0001 0000 in these registers when their contents are combined after being read. (the count starts with 0 and the first 16 bits are the command code and the Number of Valid Bits (NVB) byte).

The receive section also contains two timers. The RX wait time timer is controlled by the value in the RX Wait Time register (0x08). This timer defines the time interval after the end of the transmit operation in which the receive decoders are not active (held in reset state). This prevents false detections resulting from transients following the transmit operation. The value of the RX Wait Time register (0x08) defines the time in increments of 9.44 µs. This register is preset at every write to ISO Control register (0x01) according to the minimum tag response time defined by each standard.

The RX no response timer is controlled by the RX No Response Wait Time register (0x07). This timer measures the time from the start of slot in the anticollision sequence until the start of tag response. If there is no tag response in the defined time, an interrupt request is sent and a flag is set in the IRQ Status register (0x0C). This enables the external controller to be relieved of the task of detecting empty slots. The wait time is stored in the register in increments of 37.76 µs. This register is also preset, automatically for every new protocol selection.

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NOTE

If register setting changes are needed for fine tuning the system, they must be done after setting the ISO Control register (0x01).

The digitized output of the analog receiver is at the input of the digital portion of the receiver. This input signal is the subcarrier coded signal, which is a digital representation of modulation signal on the RF envelope.

The digital part of the receiver consists of two sections which partly overlap. The first section contains the bit decoders for the various protocols. The bit decoders convert the subcarrier coded signal to a bit stream and also the data clock. Thus the subcarrier coded signal is transformed to serial data and the data clock is extracted. The decoder logic is designed for maximum error tolerance. This enables the decoders to successfully decode even partly corrupted (due to noise or interference) subcarrier signals.

The second section contains the framing logic for the protocols supported by the bit decoder section. In the framing section, the serial bit stream data is formatted in bytes. In this process, special signals like the SOF (start of frame), EOF (end of frame), start of communication, end of communication are automatically removed. The parity bits and CRC bytes are checked and also removed. The end result is "clean or raw" data which is sent to the 127-byte FIFO register where it can be read out by the external microcontroller system.

The start of the receive operation (successfully received SOF) sets the flags in the IRQ and Status register. The end of the receive operation is signaled to the external system (MCU) by sending an interrupt request (pin 13 IRQ). If the receive data packet is longer than 96 bytes, an interrupt is sent to the MCU when the received data occupies 75% of the FIFO capacity to signal that the data should be removed from the FIFO.

Any error in data format, parity or CRC is detected and the external system is made aware of the error by an interrupt request pulse. The nature of the interrupt request pulse is available in the IRQ and Status register (address 0x0C). The bit coding description of this register is shown in Section 6.14.3.3.1. The information in IRQ and Status register differs if the chip is configured as RFID reader or as NFC device (including tag emulation). The case of NFC operation is presented in Section 6.12.

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The main register controlling the digital part of the receiver is the ISO Control register (address 0x01). By writing to this register, the user selects the protocol to be used. At the same time (with each new write in this register) the default preset in all related registers is done, so no further adjustments in other registers are needed for proper operation. Table 6-6 shows the coding of the ISO Control register (0x01).

Table 6-6. Coding of the ISO Control Register

Bit Signal Name Function Comments

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B7 rx_crc_n Receiving without CRC

B6 dir_mode Direct mode type

B5 rfid RFID mode

B4 iso_4 RFID protocol, NFC target

B3 iso_3 RFID protocol, NFC mode

B2 iso_2 RFID protocol, Card Emulation

1 = No RX CRC 0 = RX CRC

0 = output is subcarrier data 1 = output is bit stream and clock from decoder selected by ISO bits

0 = RFID reader mode 1 = NFC or Card Emulator mode

RFID: Mode selection NFC: 0 = NFC target 1 = NFC initiator

RFID: Mode selection (see Table 6-7) NFC: 0 = passive mode 1 = active mode

RFID: Mode selection NFC: 0 = NFC normal modes 1 = Card Emulation mode

B1 iso_1 RFID protocol, NFC bit rate

B0 iso_0 RFID protocol, NFC bit rate

RFID: Mode selection NFC: Bit rate selection or Card Emulation selection (see Table 6-8)

Table 6-7. Coding of the ISO Control Register For RFID Mode (B5 = 0)

Iso_4 Iso_3 Iso_2 Iso_1 Iso_0 Protocol Remarks

0 0 0 0 0 ISO15693 low bit rate, one subcarrier, 1 out of 4 0 0 0 0 1 ISO15693 low bit rate, one subcarrier, 1 out of 256 0 0 0 1 0 ISO15693 high bit rate, one subcarrier, 1 out of 4 Default for RFID IC 0 0 0 1 1 ISO15693 high bit rate, one subcarrier, 1 out of 256 0 0 1 0 0 ISO15693 low bit rate, double subcarrier, 1 out of 4 0 0 1 0 1 ISO15693 low bit rate, double subcarrier, 1 out of 256 0 0 1 1 0 ISO15693 high bit rate, double subcarrier, 1 out of 4 0 0 1 1 1 ISO15693 high bit rate, double subcarrier, 1 out of 256 0 1 0 0 0 ISO14443A, bit rate 106 kbps

0 1 0 0 1 ISO14443 A high bit rate 212 kbps different from RX rate (see

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RX bit rate when TX rate register 0x03)

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Table 6-7. Coding of the ISO Control Register For RFID Mode (B5 = 0) (continued)

Iso_4 Iso_3 Iso_2 Iso_1 Iso_0 Protocol Remarks

0 1 0 1 0 ISO14443 A high bit rate 424 kbps 0 1 0 1 1 ISO14443 A high bit rate 848 kbps 0 1 1 0 0 ISO14443B, bit rate 106 kbps

0 1 1 0 1 ISO14443 B high bit rate 212 kbps different from RX rate (see

0 1 1 1 0 ISO14443 B high bit rate 424 kbps 0 1 1 1 1 ISO14443 B high bit rate 848 kbps 1 0 0 1 1 Reserved 1 0 1 0 0 Reserved 1 1 0 1 0 FeliCa 212 kbps 1 1 0 1 1 FeliCa 424 kbps

RX bit rate when TX rate register 0x03)

Table 6-8. Coding of the ISO Control Register For NFC

Mode (B5 = 1, B2 = 0) or Card Emulation (B5 = 1,

B2 = 1)

Iso_1 Iso_0 NFC (B5 = 1, B2 = 0)

0 0 N/A ISO14443A 0 1 106 kbps ISO14443B 1 0 212 kbps N/A 1 1 424 kbps N/A

6.5.1 Received Signal Strength Indicator (RSSI)

The TRF7970A incorporates in total three independent RSSI building blocks: Internal Main RSSI, Internal Auxiliary RSSI, and External RSSI. The internal RSSI blocks are measuring the amplitude of the subcarrier signal; the External RSSI block measures the amplitude of the RF carrier signal at the receiver input.

6.5.1.1 Internal RSSI – Main and Auxiliary Receivers

Each receiver path has its own RSSI block to measure the envelope of the demodulated RF signal (subcarrier). Internal Main RSSI and Internal Auxiliary RSSI are identical however connected to different RF input pins. The Internal RSSI is intended for diagnostic purposes to set the correct RX path conditions.

The Internal RSSI values can be used to adjust the RX gain settings or decide which RX path (Main or Auxiliary) provides the greater amplitude and hence to decide if the MUX may need to be reprogrammed to swap the RX input signal. The measuring system latches the peak value, so the RSSI level can be read after the end of each receive packet. The RSSI register values are reset with every transmission (TX) by the reader. This ensures an updated RSSI measurement for each new tag response.

Card Emulation (B5 = 1, B2 = 1)

The Internal RSSI has 7 steps (3 bit) with a typical increment of approximately 4 dB. The operating range is between 600 mVPPand 4.2 VPPwith a typical step size of approximately 600 mV. Both Internal Main and Internal Auxiliary RSSI values are stored in the RSSI Levels and Oscillator Status register (0x0F). The nominal relationship between the input RF peak level and the RSSI value is shown in Figure 6-5.

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0 25 50 75 100 125 150 175 200 225 250 275 300 325

RF Input Voltage Level at RF_IN1 in mV

RSSI Levels and Oscillator Status Register value (0x0F)

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25

Input RF Carrier Level in V [V]

RSSI Levels and Oscillator Status Register value (0x0F)

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Figure 6-5. Digital Internal RSSI (Main and Auxiliary) Value vs RF Input Level in VPP(V)

This RSSI measurement is done during the communication to the Tag; this means the TX must be on. Bit 1 in the Chip Status Control register (0x00) defines if Internal RSSI or the External RSSI value is stored in the RSSI Levels and Oscillator Status register (0x0F). Direct command 0x18 is used to trigger an Internal RSSI measurement.

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6.5.1.2 External RSSI

The External RSSI is mainly used for test and diagnostic to sense the amplitude of any 13.56-MHz signal at the receivers RX_IN1 input. The External RSSI measurement is typically done in active mode when the receiver is on but transmitter output is off. The level of the RF signal received at the antenna is measured and stored in the RSSI Levels and Oscillator Status register 0x0F. The relationship between the voltage at the RX_IN1 input and the 3-bit code is shown in Figure 6-6.

Figure 6-6. Digital External RSSI Value vs RF Input Level in VPP(mV)

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Crystal

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Pin 31Pin 30

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The relation between the 3-bit code and the external RF field strength (A/m) sensed by the antenna must be determined by calculation or by experiments for each antenna design. The antenna Q-factor and connection to the RF input influence the result. Direct command 0x19 is used to trigger an Internal RSSI measurement.

For clarity, to check the internal or external RSSI value independent of any other operation, the user must:

1. Set transmitter to desired state (on or off) using Bit 5 of Chip Status Control register (0x00) and enable receiver using Bit 1.

2. Check internal or external RSSI using direct commands 0x18 or 0x19, respectively. This action places the RSSI value in the RSSI register.

3. Delay at least 50 µs.

4. Read the RSSI register using direct command 0x0F; values range from 0x40 to 0x7F.

5. Repeat steps 1-4 as desired, as register is reset after it is read.

6.6 Oscillator Section

The 13.56-MHz or 27.12-MHz crystal (or oscillator) is controlled by the Chip Status Control register (0x00) and the EN and EN2 terminals. The oscillator generates the RF frequency for the RF output stage as well as the clock source for the digital section. The buffered clock signal is available at pin 27 (SYS_CLK) for any other external circuits. B4 and B5 inside the Modulation and SYS_CLK register (0x09) can be used to divide the external SYS_CLK signal at pin 27 by 1, 2 or 4.

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Typical start-up time from complete power down is in the range of 3.5 ms. During Power Down Mode 2 (EN = 0, EN2 = 1) the frequency of SYS_CLK is switched to 60 kHz (typical). The crystal needs to be connected between pin 30 and pin 31. The external shunt capacitors values for C

and C2must be calculated based on the specified load capacitance of the crystal being used. The external shunt capacitors are calculated as two identical capacitors in series plus the stray capacitance of the TRF7970A and parasitic PCB capacitance in parallel to the crystal.

The parasitic capacitance (CS, stray and parasitic PCB capacitance) can be estimated at 4 to 5 pF (typical).

As an example, using a crystal with a required load capacitance (CL) of 18 pF, the calculation is shown in

Equation 1.

C1= C2= 2 × (CL– CS) = 2 × (18 pF – 4.5 pF) = 27 pF (1)

A 27-pF capacitor must be placed on pins 30 and 31 to ensure proper crystal oscillator operation.

Figure 6-7. Crystal Block Diagram

Any crystal used with TRF7970A should have minimum characteristics shown in Table 6-9.

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+ 61 hidden pages

Getac Technology A140N User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Device Overview

1.1 Features

1.2 Applications

1.3 Description

1.4 Functional Block Diagram

Table of Contents

2 Revision History

3 Device Characteristics

4 Terminal Configuration and Functions

4.1 Pin Assignments

4.2 Terminal Functions

5 Specifications

5.1 Absolute Maximum Ratings

5.2 Recommended Operating Conditions

5.3 Electrical Characteristics

5.4 Handling Ratings

5.5 Thermal Characteristics

5.6 Switching Characteristics

6 Detailed Description

6.1 Overview

6.1.1 RFID and NFC Operation – Reader and Writer

6.1.2 NFC Device Operation – Initiator

6.1.3 NFC Device Operation – Target

6.1.3.1 Active Target

6.1.3.2 Passive Target

6.1.3.3 Card Emulation

6.2 System Block Diagram

6.3 Power Supplies

6.3.1 Supply Arrangements

6.3.2 Supply Regulator Settings

6.3.3 Power Modes

6.4 Receiver – Analog Section

6.4.1 Main and Auxiliary Receivers

6.4.2 Receiver Gain and Filter Stages

6.5 Receiver – Digital Section

6.5.1 Received Signal Strength Indicator (RSSI)

6.5.1.1 Internal RSSI – Main and Auxiliary Receivers

6.5.1.2 External RSSI

6.6 Oscillator Section