Gericom LA-1331 ACL10, ACL10, E420, Navigator UT6, Navigator H470W Schematic

A

1 1

B

C

D

E

ACL10 LA-1331 Schematics Document

2 2

REV 2.0 (For 030)

INTEL Mobile P4 uFCBGA/uFCPGA Northwood

MCH-M(845-MP) + ICH3-M + SQ17

3 3

4 4

COMPAL ELECTRONICS, INC

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE

A

B

C

D

SCHEMATIC, M/B LA-1331

Size Document Number Rev

Custom

Date: Sheet

星期四 三月

401207

of

183, 18, 2004

E

2A

A

B

C

D

E

ACL10 LA-1331 BLOCK DIAGRAM

4 4

Mobile

CRT

Connector

Northwood

(uFCBGA/uFCPGA)

PAGE 4,5,6

PSB

400MHz

PAGE 15

Thermal Sensor
MAX6654MEE

NE1617

PAGE 5

Clock Generator

W320-04

ICS9508-05

PAGE13

CPU VID

PAGE 6

TV-OUT

3 3

2 2

Connector

Slot 0/1

PAGE 15

RJ-45

PAGE 20

PAGE 23

Parallel

1 1

PAGE 25

AGP

Connector

PAGE 14

Smart Media

PAGE 28

Mini PCI

PAGE 27

LAN

RTL8100-B(L)

CARDBUS

IEEE1394

OZ6933

VT6306

PAGE 20

PAGE 22,23

PAGE 21

FIR

PAGE 25

AGP Bus

Super I/O

LPC47N227

REV B

FDD

PAGE 19

PCI BUS

33MHz (3.3V)

PAGE 24

Brookdale-M

MCH-M 845MP

266MHz (1.8V)

ICH3-M

LPC BUS 33MHz (3.3V)

Embedded
Controller

NS PC87591

PAGE 14

625 BGA

REV B0

PAGE 7,8,9

HUB Interface

421 BGA

REV B1

PAGE 16,17,18

PAGE 32

BIOS & I/O PORTScan KB

200MHz (2.5V)

Memory Bus

48MHz (3.3V)

ATA 66/100

AC-LINK24.576MHz (3.3V)

PAGE 33

SO-DIMM x 2(DDR)

BANK 0,1,2,3

USB

PAGE 26

IDE HDD

Audio CD-DJ

AC97 CODEC

ALC 101/201

OZ165

MDC

Connector

PAGE 19

PAGE 29

PAGE 30

PAGE 14

PAGE 10,11,12

CD-ROM/DVD

RJ-11

PAGE 19

Audio Amplifier

TPA0132

PAGE 20

PAGE 31

FAN Controller

PAGE 34

DC/DC Interface

RTC Battery

PAGE 37

BATTERY

Charger

PAGE 38

Power Interface &
TEMP. sensing circuit

PAGE 38,39,40,42

COMPAL ELECTRONICS, INC

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE

A

B

C

D

SCHEMATIC, M/B LA-1331

Size Document Number Rev
Custom

Date: Sheet

星期四 三月

401207

of

283, 18, 2004

E

2A

A

B

C

D

E

Voltage Rails

Power Plane Description

VIN
B+

1 1

+CPU_CORE

1.2VP

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

1.2VP switched power rail for CPU VID
+1.25VS 1.25VS power rail ON OFF OFF
+1.5VS

AGP 4X ON OFF O FF
+1.8VALW 1.8V always power rail O N ON
+1.8VS
+2.5V
+3VALW
+3V
+3VS
+5VALW
+5V ON
+5VS
+12VALW
+12V

2 2

1.8V switched power rail

2.5V power rail

3.3V always on power rail ON*

3.3V power rail OF F

3.3V switched power rail OF F

5V always on power rail

5V power rail

5V switched power rail

12V always on power rail

12V power rail

Note : "ON*" mea ns t ha t th is p ow er p lan e is "ON" only with AC power available, otherwise it is "OFF".

S1 S3 S5

N/A N/A N/A

ON OFF
ON OFF

ON

OFF

ON

ON
ON

ON
ON

ON
OFF

ON
ON ON

ON
OFF

ON

ON

ON
ON

ON

ON OFFOFF12V switched power rail+12VS

ON+SDREF OFF+SDREF power ON

N/AN/AN/A
OFF
OFF

ON*
OFF
OFF

ON*
OFF
OFF
ON*
OFF

ONRTC powerRTCVCC ON ON

External PCI Devices

Device IDSEL # REQ # / GN T # Interrupts

Mini-PCI
CardBus

AD18
AD20

1/4
2

LAN AD17 3 PIRQB
SM AD22 PIRQC/PIRQD-

PIRQAIEEE 1394 AD16 0
PIRQC/PIRQD
PIRQA/PIRQB

PIR

REV 0.1

Date Description

Page

2001/12/29
2001/12/29
2001/12/29
2001/12/29
2001/12/29
2001/12/29
2001/12/29
2001/12/29
2001/12/29
2001/12/29
2001/12/29
2001/12/29
2001/12/29
2001/12/29
2001/12/29
2001/12/29
2001/12/29
2001/12/29

REV 0.2

Date DescriptionPage

Change R212,R214 & R213 to 8.2K ohm for Intel recommand7
14 Stuff R361=22 Ohm and no-stuff R360 for Data-IN1 of MDC module.
15 Change L28 & L29 to 0 Ohm for EMI issue.
16 Change R39 power-plane to +3VALW for Resume-well Power-plane(+3VALW)

DEL C73, C87, C371 for EMI issue.17

Change L37 power-plane to +1.8VS for Intel recommand.

17

Change R279 power-plane to +3VS for Intel recommand.17

Change U29 pinV22,U18 & P14 power-plane to +CPU_CORE for Intel recommand.17

Change R284 power-plane to +3VALW for Intel recommand.17

Change "SMB_ALERT#" power-plane to +3VALW for "RESUME-WELL" power-plane(+3VLAW).18

Exchang D13,D14,D16,D17,D18 and R28,R34,R30,R29 to RP135,R466,R468 for cost-down.18

Add D43 for leakage.20

Exchang L42 to L52,L53, L54, L55 for ME limitation.21
27 Add D42 fo r leakage.

Add R465 for PC99 Spec.31

Add C368, C369 for EMI solution.34
35 EC control "EC_RSMRST#". ->DEL R92, Stuff R48.
35 Change R97 to 100K for "VGATE" of Max1718A issue.-> Change PR134= 0 Ohm.

Change PR68 from 10k_1% to 10.5k_1%.(increase 5valwp to 5.125v).2002/01/07 39

Change PR81 from 2.15k_1% to 1.87k_1%.( CPU thermal OTP from 83+-3C to 85+-3C).2002/01/07 40

Add PR147, PR161 to 2.7_0805. for EMI requirement.2002/01/07 42

Add PC120, PC121, PC122 to 1000pf. for ESD.422002/01/07

Add PQ44 to 2N7002 for CPU SPEED STEP.422002/01/07

Change PR130, PR152 from 0 to 2.2. for EMI requirement.2002/01/07 42

Change PR143 from 53.6k_1% to 100k_1%. for CPU OCP.422002/01/07
422002/01/07 Change PR145 from 100k_1% to 53.6k_1%. for CPU OCP.
422002/01/07 Change PR148 from 30k_1% to 48.7k_1%. for CPU OCP.
42 Change PU12 VIN from +2.5VP to +3VALWP.2002/01/07

40 Change PH1 and PH2 design by high active for AC-IN issue.2002/01/11

EC SM Bus1 address

3 3

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

0001 011Xb
1010 000Xb
1011 000Xb

ICH3-M SM Bus address

Device

Clock Generator
W320-04 / ICS9508-05

Address

1101 0000

EC SM Bus2 address

Device

MAX6654MEE
OZ165
Smart Battery
Docking
DOT Board

1001 110Xb
1011 0100b (B4h)
0001 011Xb
0011 011Xb
XXXX XXXXb

REV 0.3

None

REV 1.0

Date

None

REV 2.0

Date

2002/04/10

DescriptionDate Page

Page

Page

20 GCR: (For LAN Issue)

<1>Isolation U1 8 p in6 for Realtek application notice.
<2>Change R204 from 5.9K+-1% to 5.6K +-1%.
<3>Change L23 from 4.7UH to 0 ohm.

DDR SODIMM SM Bus address

4 4

DDR SLOT SA2 SA1 SA0

DDR SODIMM0 (REVERSE)
DDR SODIMM1 (NORMAL)

A

000
001

COMPAL ELECTRONICS, INC

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE

B

C

D

SCHEMATIC, M/B LA-1331

Size Document Number Rev
Custom

401207

Date: Sheet

星期四 三月

E

of

383, 18, 2004

2A

A

+CPU_CORE

1 1

AB1

AC1
AA3

AC3

AF22
AF23

U7A

K2

A#3

K4

A#4

L6

A#5

K1

A#6

L3

A#7

M6

A#8

L2

A#9

M3

A#10

M4

A#11

N1

A#12

M1

A#13

N2

A#14

N4

A#15

N5

A#16

T1

A#17

R2

A#18

P3

A#19

P4

A#20

R3

A#21

T2

A#22

U1

A#23

P6

A#24

U3

A#25

T4

A#26

V2

A#27

R6

A#28

W1

A#29

T5

A#30

U4

A#31

V3

A#32

W2

A#33

Y1

A#34
A#35

J1

REQ#0

K5

REQ#1

J4

REQ#2

J3

REQ#3

H3

REQ#4

G1

ADS#

AP#0

V5

AP#1
BINIT#
IERR#

H6

BR0#

D2

BPRI#

G2

BNR#

G4

LOCK#

BCLK0
BCLK1

F3

HIT#

E3

HITM#

E2

DEFER#

HA#[3..31]7

2 2

HREQ#[0..4]7

HADS#7

+CPU_CORE

*

HBR0#7

3 3

HBPRI#7

HBNR#7

HLOCK#7

CLK_HCLK13
CLK_HCLK#13

HIT#7

HITM#7

HDEFER#7

HA#[3..31]

HREQ#[0..4]

1 2

R87 10K

1 2

R280 200_0603

CLK_HCLK
CLK_HCLK#

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

A10

VCC_0

A12

A14

VCC_1

A16

VCC_2

VSS_0H1VSS_1H4VSS_2

A18

VCC_3

H23

B

A20

VCC_4

H26

VCC_5

VSS_3

A11

AA10

AA12

VCC_6A8VCC_7

VSS_4

VSS_5

A13

A15

AA14

VCC_8

VSS_6

A17

AA16

VCC_9

VSS_7

A19

AA18

VCC_10

VCC_11

VSS_8

VSS_9

A21

AA8

VCC_12

VSS_10

A24

AB11

VCC_13

VSS_11

A26

AB13

VCC_14

VSS_12A3VSS_13A9VSS_14

AB15

VCC_15

AB17

VCC_16

AA1

AB19

VCC_17

VSS_15

AA11

AB7

AB9

VCC_18

VSS_16

AA13

AA15

AC10

VCC_19

VCC_20

VSS_17

VSS_18

AA17

AC12

VCC_21

VSS_19

AA19

AC14

AC16

VCC_22

VSS_20

AA23

AA26

AC18

AC8

AD11

AD13

AD15

AD17

AD19

AD7

AD9

AE10

VCC_23

VCC_24

VCC_25

VCC_26

VCC_27

VCC_28

VCC_29

VCC_30

VCC_31

VCC_32

VCC_33

Mobile

NorthWood

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

AA4

AA7

AA9

AB10

AB12

AB14

AB16

AB18

AB20

AB21

AE12

VCC_34

VSS_32

AB24

AE14

VCC_35

VSS_33

AB3

C

AE16

AE18

VCC_36

VSS_34

AB6

AB8

AE20

VCC_37

VCC_38

VSS_35

VSS_36

AC11

AE6

VCC_39

VSS_37

AC13

AE8

VCC_40

VSS_38

AC15

AF11

VCC_41

VSS_39

AC17

AF13

VCC_42

VSS_40

AC19

AF15

VCC_43

VSS_41

AC2

AF17

VCC_44

VSS_42

AC22

AF19

AF2

VCC_45

VSS_43

AC5

AC25

AF21

VCC_46

VCC_47

VSS_44

VSS_45

AC7

AF5

VCC_48

VSS_46

AC9

AF7

VCC_49

VSS_47

AD1

AF9

VCC_50

VSS_48

AD10

B11

VCC_51

VSS_49

AD12

B13

VCC_52

VSS_50

AD14

B15

VCC_53

VSS_51

AD16

B17

B19

VCC_54

VSS_52

AD18

AD21

VCC_55

VCC_56B7VCC_57B9VCC_58

VSS_53

VSS_54

VSS_55

AD4

AD23

C10

AD8

VSS_56

C12

VCC_59

C14

VCC_61

C16

VCC_62

VCC_81

F13

C18

VCC_63

VCC_82

F15

C20

VCC_64

VCC_83

F17

D11

VCC_65C8VCC_66

VCC_84

VCC_85

F9

F19

D13

VCC_67

F11

D15

VCC_68

VCC_79E8VCC_80

D17

VCC_69

VCC_78

E20

D

D19

VCC_70

VCC_77

E18

D9

VCC_71D7VCC_72

VCC_75

VCC_76

E14

E16

E10

VCC_73

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8

D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

VCC_74

NorthWood

E12

B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HD#[0..63]

E

HD#[0..63] 7

+CPU_CORE

4 4

COMPAL ELECTRONICS, INC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

A

B

C

D

Title

Size Document Number Rev
Custom

Date: Sheet

SCHEMATIC, M/B LA-1331

星期四

18, 2004

三月

401207

2A

483,

E

of

A

+CPU_CORE

H_A20M#

12

R282 200
R77 200
R84 200
R72 200

1 1

2 2

3 3

R222 200
R285 200
R71 200
R83 200

R80 56
R224 300

R220 51.1_1%

R78 200

Place resistor <100mils from
CPU pin

RP21

1 8
2 7
3 6
4 5

8P4R_1.5K

+CPU_CORE

12

R82 200_0603

12

R62 200_0603

12

R81 200_0603

12

R68 200_0603

Thermal Sensor
MAX6654MEE

C55

4 4

+5VALW

2200PF_0603

12

R65 1K

Address:1001_110X

12
12
12
12
12
12
12

12
12

12

12

+1.2VP

ITP_TMS
ITP_TCK
ITP_TRST#
ITP_TDI

ITP_PREQ#
ITP_PRDY#
ITP_BPM0
ITP_BPM1

12

H_SMI#
H_IGNNE#
H_STPCLK#
H_DPSLP#
H_NMI
H_INIT#
H_INTR

H_F_FERR#
H_PWRGD

H_RESET#

PM_CPUPERF#

Murata LQG2 1F4R7N00

L27

1 2

L3

1 2

H_THERMDA
H_THERMDC

A

4.7UH_80mA_0805

4.7UH_80mA_0805

12

C19

+

33UF_D2_16V

W=15mil

U6

1

NC

2

VCC

3

DXP

4

DXN

5

NC

SMBDATA

6

ADD1

7

GND

8

GND

NE1617/ MAX6654MEE

+1.2VP

C56
.1UF

1 2

STBY

SMBCLK

ALERT

ADD0

1 2

R66 56

16

NC

15
14
13

NC

12
11
10
9

NC

H_RS#07
H_RS#17
H_RS#27

H_TRDY#7

H_A20M#16

H_F_FERR#16

H_IGNNE#16

H_SMI#16

H_PWRGD16

H_STPCLK#16

H_DPSLP#16

H_INTR16
H_INIT#16

H_RESET#7

H_DBSY#7

H_DRDY#7

H_BSEL013
H_BSEL113

TP1

12

C231

+

33UF_D2_16V

H_VSSA

+5VALW

1 2

R38
1K

H_NMI16

R36

10K

1 2

+5VALW

H_THERMTRIP#

1

51.1_1%

R37
10K

1 2

H_A20M#

H_F_FERR#

H_IGNNE#
H_SMI#
H_PWRGD
H_STPCLK#
H_DPSLP#
H_INTR
H_NMI
H_INIT#
H_RESET#

H_THERMDA
H_THERMDC

ITP_BPM0
ITP_BPM1
ITP_PRDY#
ITP_PREQ#

ITP_TCK
ITP_TDI

ITP_TMS

ITP_TRST#

H_VCCA
H_VCCIOPLL

R215

B

G5

AB2

C6

AB23

AD25

D1
W5

AB25

H5

H2
AD6
AD5

C4

AC6
AB5
AC4

AA5
AB4

D4

C1

D5

AD20

AE23
AF25

AF3

AC26
AD26

L24

R67

51.1_1%

1 2

1 2

EC_SMC2 29,32
EC_SMD2 29,32

THRM# 33

B

F1
F4
J6

B6
B2
B5

Y4

E5

B3

A2

Y6

F7
E6

A5

P1

AE11

AE13

AE15

AE17

AE19

AE22

AE24

VSS_57

VSS_58

VSS_59

VSS_129F8VSS_130

G21

VSS_60

VSS_61

VSS_131

VSS_132G3VSS_133G6VSS_134J2VSS_135

G24

AE26

VSS_62

VSS_63

VSS_64

J22

U7B

RS#0
RS#1
RS#2
RSP#
TRDY#

A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#
DPSLP#
LINT0
LINT1
INIT#
RESET#

DBSY#
DRDY#
BSEL0
BSEL1

THERMDA
THERMDC

THERMTRIP#

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

TCK
TDI
TDO
TMS
TRST#

VCCA
VCCSENSE
VCCIOPLL

NC7
NC8

ITP_CLK0
ITP_CLK1

COMP0
COMP1

GTL Reference Voltage

+CPU_CORE

12

R24

R_A

49.9_1%

Trace width>=7mila

12

R25
100_1%

R_B

C

AE7

AE9

AF1

AF10

AF12

AF14

AF16

AF18

AF20

AF6

AF8

B10

B12

B14

B16

B18

B20

B23

AF26

VSS_65

VSS_66

VSS_67

VSS_68

VSS_69

VSS_70

VSS_71

VSS_72

VSS_73

VSS_75

VSS_76

SKTOCC#

B26

VSS_77

VSS_78

VSS_79

VSS_80

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85B4VSS_86B8VSS_87

NorthWood

VSS_136

VSS_137J5VSS_138

VSS_139

VSS_140K3VSS_141K6VSS_142L1VSS_143

VSS_144

VSS_145L4VSS_146M2VSS_147

VSS_148

VSS_149M5VSS_150

VSS_151

VSS_152N3VSS_153N6VSS_154P2VSS_155

VSS_156

VSS_157P5VSS_158R1VSS_159

J25

L23

L26

K21

K24

Layout note :

1. Place R_A and R_B near CPU.

2. Place decoupling cap 220PF near CPU.(Within
500mils)

M22

M25

C20

C21

1UF_0603

220PF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE

P22

P25

N21

N24

C

C11

C13

C15

C17

C19

C22

C25

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92C2VSS_93

VSS_94

VSS_95C5VSS_96C7VSS_97C9VSS_98

Mobile

VSS_160

VSS_161R4VSS_162

VSS_163

VSS_164T3VSS_165T6VSS_166U2VSS_167

T21

T24

R23

R26

+H_GTLREF1

U22

D10

VSS_168

U25

D12

D14

VSS_99

VSS_100

VSS_169U5VSS_170V1VSS_171

V23

D

D16

D18

D20

D21

D24

E11

E13

E15

E17

E19

E23

E26

F10

F12

F14

F16

F18

F22

F25

F5

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117E4VSS_118E7VSS_119E9VSS_120

VSS_121

VSS_122

VSS_123

VSS_124

VSS_125F2VSS_126

VSS_127

VSS_128

J26

DP#0

K25

DP#1

K26

DP#2
DP#3

GTLREF0
GTLREF1
GTLREF2
GTLREF3

NC1
NC2

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9

TESTHI10

GHI#

DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3

DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3

ADSTB#0
ADSTB#1

DBI#0
DBI#1
DBI#2
DBI#3

DBR#

PROCHOT#

MCERR#

SLP#

VSSA

VSSSENSE

NC3

VID0

VID1

VID2

VID3

VSS_172

VSS_173V4VSS_174

VSS_175

VSS_176W3VSS_177W6VSS_178Y2VSS_179

VSS_180

VSS_181

V26

W21

Y5

Y22

Y25

W24

VID4

NC5

NC6

AE5

AE4

AE3

AE2

AE1

AF24

AE21

D

NC4

VCCVID

NorthWood

AF4

CPU_VR_VID4 6,42
CPU_VR_VID3 6,42
CPU_VR_VID2 6,42
CPU_VR_VID1 6,42
CPU_VR_VID0 6,42

+H_GTLREF1

L25

AA21
AA6
F20
F6
A22
A7

TESTTHI0_1

AD24
AA2

TESTTHI2_7

AC21
AC20
AC24
AC23
AA20
AB22

TESTTHI8_10

U6
W4
Y3
A6

E22
K22
R22
W22

F21
J23
P23
W23

L5
R5

E21
G25
P26
V21

AE25

C3
V6
AB26

AD22
A4

AD2
AD3

+1.2VP

C359
.1UF

PROCHOT#33

Title

Size Document Number Rev

Date: Sheet

PM_CPUPERF#
H_DSTBN#[0..3]

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#[0.. 3]

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DBI#[0..3]
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3

H_PROCHOT#

H_SLP#

H_VSSA

1

R275
1K

Q22
3904

R79 56

TP2

+5VALW

1 2

3 1

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

星期四 三月

E

All of these pin
connected inside

1 2

R221 56

1 2

R223 56

1 2

R70 56

1 2

R218 200

R274
470

1 2

2

2

3 1

Q23
3904

401207

E

+CPU_CORE

PM_CPUPERF# 16
H_DSTBN#[0..3] 7

H_DSTBP#[0..3] 7

H_ADSTB#0 7
H_ADSTB#1 7

H_DBI#[0..3] 7

H_SLP# 16

12

+CPU_CORE

1 2

R287 470

+CPU_CORE

583, 18, 2004

H_PROCHOT#

2A

of

A

B

C

D

E

Layout note :

Place close to CPU, Use 2~3 vias per PAD.
Place .22uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.

1 1

2 2

Please place these cap in the socket cavity area

+CPU_CORE

12

C300

10UF_6.3V_1206_X5R

+CPU_CORE

12

C299

10UF_6.3V_1206_X5R

Please place these cap on the socket north side

+CPU_CORE

12

C24

10UF_6.3V_1206_X5R

+CPU_CORE

12

C62

10UF_6.3V_1206_X5R

+CPU_CORE

12

C320

10UF_6.3V_1206_X5R

12

C308
10UF_6.3V_1206_X5R

12

C307
10UF_6.3V_1206_X5R

12

C26
10UF_6.3V_1206_X5R

12

C65
10UF_6.3V_1206_X5R

12

C329
10UF_6.3V_1206_X5R

12

C317
10UF_6.3V_1206_X5R

12

C316
10UF_6.3V_1206_X5R

12

C30
10UF_6.3V_1206_X5R

12

C22
10UF_6.3V_1206_X5R

12

C344
10UF_6.3V_1206_X5R

12

C323
10UF_6.3V_1206_X5R

12

C322
10UF_6.3V_1206_X5R

12

C45
10UF_6.3V_1206_X5R

12

C302
10UF_6.3V_1206_X5R

12

C351
10UF_6.3V_1206_X5R

12

C332
10UF_6.3V_1206_X5R

12

C331
10UF_6.3V_1206_X5R

12

C52
10UF_6.3V_1206_X5R

12

C311
10UF_6.3V_1206_X5R

Layout note :

Place close to CPU power and
ground pin as possible
(<1inch)

+CPU_CORE

12

C380

+

220UF_D2_4V_25m

+CPU_CORE

12

C385

+

220UF_D2_4V_25m

+CPU_CORE

12

12

C297
.22UF_X7R

Used ESR 25m ohm cap total ESR=2.5m ohm

+

12

C294
.22UF_X7R

12

C382

+

220UF_D2_4V_25m

12

C68
220UF_D2_4V_25m

12

C293
.22UF_X7R

C296
.22UF_X7R

12

C381

+

@220UF_D2_4V_25m

12

C57

+

220UF_D2_4V_25m

12

C295
.22UF_X7R

CPU Voltage ID

12

C383

+

220UF_D2_4V_25m

12

C86

+

@220UF_D2_4V_25m

12

C338
.22UF_X7R

12

C339
.22UF_X7R

12

C384

+

220UF_D2_4V_25m

12

C390

+

220UF_D2_4V_25m

12

C340
.22UF_X7R

12

C341
.22UF_X7R

12

C342
.22UF_X7R

R362
1K

+3VS

182736

45

12

RP50
8P4R_1K

CPU_VID1 5,42
CPU_VID2 5,42
CPU_VID3 5,42
CPU_VID4 5,42

Please place these cap on the socket south side

3 3

4 4

+CPU_CORE

12

C23

10UF_6.3V_1206_X5R

+CPU_CORE

12

C59

10UF_6.3V_1206_X5R

+CPU_CORE

12

C315

10UF_6.3V_1206_X5R

12

C25
10UF_6.3V_1206_X5R

12

C64
10UF_6.3V_1206_X5R

12

C325
10UF_6.3V_1206_X5R

12

C28
10UF_6.3V_1206_X5R

12

C286
10UF_6.3V_1206_X5R

12

C335
10UF_6.3V_1206_X5R

12

C37
10UF_6.3V_1206_X5R

12

C298
10UF_6.3V_1206_X5R

12

C348
10UF_6.3V_1206_X5R

12

C49
10UF_6.3V_1206_X5R

12

C305
10UF_6.3V_1206_X5R

CPU_VR_VID05,42 CPU_VID0 5,42
CPU_VR_VID15,42
CPU_VR_VID25,42
CPU_VR_VID35,42
CPU_VR_VID45,42

EMI Clip PAD for CPU

PAD1

1

PAD-2.5X3

PAD2

PAD-2.5X3

A

PAD3

1

PAD-2.5X3

1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE

B

C

D

Title

Size Document Number Rev

Date: Sheet

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

星期四 三月

401207

E

2A

of

683, 18, 2004

A

B

C

D

E

HA#[3..31]4

1 1

H_ADSTB#05
H_ADSTB#15

H_RESET#5

H_TRDY#5

2 2

3 3

+CPU_CORE

R254

301_1%

R260

150_1%

+CPU_CORE

R210

301_1%

4 4

R209

150_1%

HDEFER#4

HBPRI#4
HLOCK#4

H_DBSY#5

H_DRDY#5

HIT#4
HITM#4
HBR0#4

HADS#4

HBNR#4

H_RS#05
H_RS#15
H_RS#25

HREQ#[0..4]4

CLK_GHT13

CLK_GHT#13

H_DBI#[0..3]5

12

12

C290
.01UF

12

12

12

C238
.01UF

12

HA#[3..31]

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

PCIRST#14,16,19,20,21,22,23,24,27,28,34

HREQ#[0..4]

H_DBI#[0..3]

24.9_0603_1%

A

R238

+1.5VS

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

CLK_GHT
CLK_GHT#

H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3

H_SWNG0
H_SWNG1

12

R262 8.2K

R247 8.2K

R230 8.2K

AE17

AD15

AD13

AC13

12

R252

24.9_0603_1%

12

12

12

T4
T5

T3
U3
R3

P7
R2

P4
R6

P5

P3
N2
N7
N3

K4
M4
M3

L3

L5

K3

J2
M5

J3

L2
H4
N5
G2
M6

L7
R5

N6

U7

Y4

Y7
W5

J27

H26

V5

V4

Y5

Y3

V7

V3

W3

W2
W7
W6

U6

T7
R7
U5
U2

J8

K8

AD5
AG4
AH9

AA7

AC2

AGP_ADSTB0

AGP_ADSTB1

AGP_SBSTB

U5A

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HADSTB#0
HADSTB#1

CPURST#
HTRDY#
DEFER#
BPRI#
HLOCK#
RSTIN#
TESTIN#
DBSY#
DRDY#
HIT#
HITM#
BREQ#0
ADS#
BNR#

RS#0
RS#1
RS#2

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

BCLK
BCLK#

DBI#0
DBI#1
DBI#2
DBI#3

HSWNG0
HSWNG1

HRCOMP0
HRCOMP1

H_DSTBN#[0..3]
H_DSTBP#[0..3]

HOST

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

BROOKDALE(MCH-M)

H_DSTBN#[0..3] 5
H_DSTBP#[0..3] 5

R265 @8.2K

R239 @8.2K

R231 @8.2K

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8

HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

HVREF0
HVREF1
HVREF2
HVREF3
HVREF4

AA2
AB5
AA5
AB3
AB4
AC5
AA3
AA6
AE3
AB7
AD7
AC7
AC6
AC3
AC8
AE2
AG5
AG2
AE8
AF6
AH2
AF3
AG3
AE5
AH7
AH3
AF4
AG8
AG7
AG6
AF8
AH5
AC11
AC12
AE9
AC9
AE10
AD9
AG9
AC10
AE12
AF10
AG11
AG10
AH11
AG12
AE13
AF12
AG13
AH13
AC14
AF14
AG14
AE14
AG15
AG16
AG17
AH15
AC17
AF16
AE15
AH17
AD17
AE16

AD4
AE6
AE11
AC15
AD3
AE7
AD11
AC16

M7
R8
Y8
AB11
AB17

12

12

12

B

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

AGP_ADSTB0#

AGP_ADSTB1#

AGP_SBSTB#

HD#[0..63]

+V_MCH_GTLREF

GTL Reference Voltage

Layout note :

1. Place R_E and R_F near MCH

2. Place decoupling cap 220PF near MCH pin.(Within 500mils)

AGP_ST0
0=System memory is DDR
1=System memory is SDR

HD#[0..63] 4

+CPU_CORE

12

R_E

12

R_F

100_1%

AGP_AD[0..31]14

AGP_C/BE#[0..3]14

AGP_ST[0..2]14

R273

49.9_1%

R269

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE

AGP_AD[0..31] HUB_PD[0..10]

AGP_ADSTB014
AGP_ADSTB0#14
AGP_ADSTB114
AGP_ADSTB1#14
AGP_SBSTB14
AGP_SBSTB#14

AGP_FRAME#14
AGP_DEVSEL#14
AGP_IRDY#14
AGP_TRDY#14
AGP_STOP#14
AGP_PAR14
AGP_REQ#14
AGP_GNT#14
AGP_PIPE#14

Trace
width>=7mila

C313

C337

1UF_0603

220PF

AGP_ST0 AGP_ST1

R213 2K

C

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3

AGP_ST0
AGP_ST1
AGP_ST2

AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#
AGP_SBSTB
AGP_SBSTB#

AGP_FRAME#
AGP_DEVSEL#
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_REQ#
AGP_GNT#
AGP_PIPE#

12

**

*

U5B

R27
R28
T25
R25
T26
T27
U27
U28
V26
V27
T23
U23
T24
U24
U25
V24
Y27

Y26
AA28
AB25
AB27
AA27
AB26

Y23
AB23
AA24
AA25
AB24
AC25
AC24
AC22
AD24

V25

V23

Y25
AA23

AG25
AF24
AG26

R24

R23
AC27
AC28
AF27
AF26

Y24

W28
W27
W24
W23

W25
AG24
AH25
AF22

N22
K27

K5

L24

M23

K7

J26

A3

A7
A11
A15

12

R216 @8.2K

G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31

G_C/BE#0
G_C/BE#1
G_C/BE#2
G_C/BE#3

ST0
ST1
ST2

AD_STB0
AD_STB#0
AD_STB1
AD_STB#1
SB_STB
SB_STB#

G_FRAME#
G_DEVSEL#
G_IRDY#
G_TRDY#
G_STOP#
G_PAR
G_REQ#
G_GNT#
PIPE#

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10

AGP_FRAME#
AGP_TRDY#
AGP_PAR
AGP_STOP#

AGP_GNT#
AGP_REQ#
AGP_IRDY#
AGP_DEVSEL#

AGP_WBF#
AGP_PIPE#
AGP_RBF#

AGP_ST2

HUB

HLRCOMP

AGP

GRCOMP

BROOKDALE(MCH-M)

RP18 @8P4R_8.2K

1 8
2 7
3 6
4 5

RP17 @8P4R_8.2K

1 8
2 7
3 6
4 5

RP15 @8P4R_8.2K

1 8
2 7
3 6
4 5

12

*

R212 8.2K

12

*

R214 8.2K

HI_0
HI_1
HI_2
HI_3
HI_4
HI_5
HI_6
HI_7
HI_8
HI_9

HI_10

HI_STB

HI_STB#

HI_REF

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

AGPREF

66IN

RBF#

WBF#

VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40

+1.5VS

D

P25
P24
N27
P23
M26
M25
L28
L27
M27
N28
M24

N25
N24

P27
P26

AH28
AH27
AG28
AG27
AE28
AE27
AE24
AE25

AA21
AD25
P22

AE22
AE23

A19
A23
A27
D5
D9
D13
D17
D21
E1
E4
E26
E29
F8
F12
F16
F20
F24
G26
H9
H11
H13
H15
H17
H19
H21
J1
J4
J6
J22
J29

AGP_ST1
0=533Mhz
1=400Mhz

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10

HLRCOMP

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

R237 36.5_1%

CLK_AGP_MCH

AGP_RBF#
AGP_WBF#

+AGP_NBREF

HUB_PD[0..10] 16

HUB_PSTRB 16
HUB_PSTRB# 16

1 2

R270 36.5_1%

AGP_SBA[0..7]

AGP_SBA[0..7] 14

Place this cap near MCH

+AGP_VGAREF

12

C292
.1UF

12

CLK_AGP_MCH 13

AGP_RBF# 14
AGP_WBF# 14

+1.5VS

12

R51

12

R290

301_1%

1K_1%_0603

R56
1K_1%_0603

+1.8VS

Place this cap near AGP Conn.

HUB Interface Reference

Layout note :

1. Place R_C and R_D in middle of Bus.

2. Place capacitors near MCH.

12

R_C

12

R289
301_1%

R_D

Title

Size Document Number Rev

Date: Sheet

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

星期四 三月

401207

+1.8VS

12

C120
.1UF

12

C373
@470PF

12

R291
@56.2_1%

12

R286
0

12

C368
.01UF

E

+VS_HUBREF

12

C319
.01UF

Place closely
ball P26

Place closely pin P22

CLK_AGP_MCH

R268
@33

1 2

C326

@10PF

+VS_HUBREF

of

783, 18, 2004

2A

A

B

C

D

E

U5D

+CPU_CORE

1 1

+2.5V

2 2

3 3

4 4

M8

VTT_0

U8

VTT_1

AA9

VTT_2

AB8

VTT_3

AB18

VTT_4

AB20

VTT_5

AC19

VTT_6

AD18

VTT_7

AD20

VTT_8

AE19

VTT_9

AE21

VTT_10

AF18

VTT_11

AF20

VTT_12

AG19

VTT_13

AG21

VTT_14

AG23

VTT_15

AJ19

VTT_16

AJ21

VTT_17

AJ23

VTT_18

A5

VCCSM1

A9

VCCSM2

A13

VCCSM3

A17

VCCSM4

A21

VCCSM5

A25

VCCSM6

C1

VCCSM7

C29

VCCSM8

D7

VCCSM9

D11

VCCSM10

D15

VCCSM11

D19

VCCSM12

D23

VCCSM13

D25

VCCSM14

F6

VCCSM15

F10

VCCSM16

F14

VCCSM17

F18

VCCSM18

F22

VCCSM19

G1

VCCSM20

G4

VCCSM21

G29

VCCSM22

H8

VCCSM23

H10

VCCSM24

H12

VCCSM25

H14

VCCSM26

H16

VCCSM27

H18

VCCSM28

H20

VCCSM29

H22

VCCSM30

H24

VCCSM31

K22

VCCSM32

K24

VCCSM33

K26

VCCSM34

L23

VCCSM35

K6

VCCSM36

J5

VCCSM37

J7

VCCSM38

L1

VSS41

L4

VSS42

L6

VSS43

L8

VSS44

L22

VSS45

L26

VSS46

N1

VSS47

N4

VSS48

N8

VSS49

N13

VSS50

N15

VSS51

N17

VSS52

N29

VSS53

P6

VSS54

P8

VSS55

P14

VSS56

P16

VSS57

R1

VSS58

R4

VSS59

R13

VSS60

R15

VSS61

R17

VSS62

R26

VSS63

T6

VSS64

T8

VSS65

T14

VSS66

T16

VSS67

T22

VSS68

U1

VSS69

U4

VSS70

U15

VSS71

U29

VSS72

V6

VSS73

V8

VSS74

V22

VSS75

W1

VSS76

W4

VSS77

W8

VSS78

W26

VSS79

Y6

VSS80

Y22

VSS81

AA1

VSS82

BROOKDALE(MCH-M)

POWER/GND

VCC1_5_0
VCC1_5_1
VCC1_5_2
VCC1_5_3
VCC1_5_4
VCC1_5_5
VCC1_5_6
VCC1_5_7
VCC1_5_8

VCC1_5_9
VCC1_5_10
VCC1_5_11
VCC1_5_12
VCC1_5_13
VCC1_5_14
VCC1_5_15

VCC1_5_16
VCC1_5_17
VCC1_5_18
VCC1_5_19
VCC1_5_20
VCC1_5_21
VCC1_5_22
VCC1_5_23
VCC1_5_24
VCC1_5_25

VCC1_8_0

VCC1_8_1

VCC1_8_2

VCC1_8_3

VCC1_8_4

VCCGA1

VCCHA1

VSSGA2
VSSHA2

VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141

R22
R29
U22
U26
W22
W29
AA22
AA26
AB21
AC29
AD21
AD23
AE26
AF23
AG29
AJ25

N14
N16
P13
P15
P17
R14
R16
T15
U14
U16

L29
N26
L25
M22
N23

T17
T13

U17
U13

AA4
AA8
AA29
AB6
AB9
AB10
AB12
AB13
AB14
AB15
AB16
AB19
AB22
AC1
AC4
AC18
AC20
AC21
AC23
AC26
AD6
AD8
AD10
AD12
AD14
AD16
AD19
AD22
AE1
AE4
AE18
AE20
AE29
AF5
AF7
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF25
AG1
AG18
AG20
AG22
AH19
AH21
AH23
AJ3
AJ5
AJ7
AJ9
AJ11
AJ13
AJ15
AJ17
AJ27

VCC_MCH_PLL1
VCC_MCH_PLL0

VSS_MCH_PLL1
VSS_MCH_PLL0

+1.5VS

+1.8VS

"Trace A"

"Trace A"

"Trace A"

Layout note :
Trace width 5mil ; Spacing

10mil
Trace A to ball U7/T13 or
U7/T7 =1.5" Max

+1.5VS

12

12

+

L34

4.7UH_30mA

"Trace A"

C310
33UF_D2_16V

Murata LQG21N4R7K10

12

L33

4.7UH_30mA

12

C309

+

33UF_D2_16V

DDR_SDQ[0..63]10

DDR_CB[0..7]10

DDR_SDQ[0..63]

DDR_CB[0..7]

DDR_SDQ0
DDR_SDQ1
DDR_SDQ2
DDR_SDQ3
DDR_SDQ4
DDR_SDQ5
DDR_SDQ6
DDR_SDQ7
DDR_SDQ8
DDR_SDQ9
DDR_SDQ10
DDR_SDQ11
DDR_SDQ12
DDR_SDQ13
DDR_SDQ14
DDR_SDQ15
DDR_SDQ16
DDR_SDQ17
DDR_SDQ18
DDR_SDQ19
DDR_SDQ20
DDR_SDQ21
DDR_SDQ22
DDR_SDQ23
DDR_SDQ24
DDR_SDQ25
DDR_SDQ26
DDR_SDQ27
DDR_SDQ28
DDR_SDQ29
DDR_SDQ30
DDR_SDQ31
DDR_SDQ32
DDR_SDQ33
DDR_SDQ34
DDR_SDQ35
DDR_SDQ36
DDR_SDQ37
DDR_SDQ38
DDR_SDQ39
DDR_SDQ40
DDR_SDQ41
DDR_SDQ42
DDR_SDQ43
DDR_SDQ44
DDR_SDQ45
DDR_SDQ46
DDR_SDQ47
DDR_SDQ48
DDR_SDQ49
DDR_SDQ50
DDR_SDQ51
DDR_SDQ52
DDR_SDQ53
DDR_SDQ54
DDR_SDQ55
DDR_SDQ56
DDR_SDQ57
DDR_SDQ58
DDR_SDQ59
DDR_SDQ60
DDR_SDQ61
DDR_SDQ62
DDR_SDQ63

DDR_CB0
DDR_CB1
DDR_CB2
DDR_CB3
DDR_CB4
DDR_CB5
DDR_CB6
DDR_CB7

+SDREF

12

C346
.1UF_0402_X5R

Layout note
Please closely pinJ21 and J9

U5C

G28

SDQ0

F27

SDQ1

C28

SDQ2

E28

SDQ3

H25

SDQ4

G27

SDQ5

F25

SDQ6

B28

SDQ7

E27

SDQ8

C27

SDQ9

B25

SDQ10

C25

SDQ11

B27

SDQ12

D27

SDQ13

D26

SDQ14

E25

SDQ15

D24

SDQ16

E23

SDQ17

C22

SDQ18

E21

SDQ19

C24

SDQ20

B23

SDQ21

D22

SDQ22

B21

SDQ23

C21

SDQ24

D20

SDQ25

C19

SDQ26

D18

SDQ27

C20

SDQ28

E19

SDQ29

C18

SDQ30

E17

SDQ31

E13

SDQ32

C12

SDQ33

B11

SDQ34

C10

SDQ35

B13

SDQ36

C13

SDQ37

C11

SDQ38

D10

SDQ39

E10

SDQ40

C9

SDQ41

D8

SDQ42

E8

SDQ43

E11

SDQ44

B9

SDQ45

B7

SDQ46

C7

SDQ47

C6

SDQ48

D6

SDQ49

D4

SDQ50

B3

SDQ51

E6

SDQ52

B5

SDQ53

C4

SDQ54

E5

SDQ55

C3

SDQ56

D3

SDQ57

F4

SDQ58

F3

SDQ59

B2

SDQ60

C2

SDQ61

E2

SDQ62

G5

SDQ63

C16

SDQ64/CB0

D16

SDQ65/CB1

B15

SDQ66/CB2

C14

SDQ67/CB3

B17

SDQ68/CB4

C17

SDQ69/CB5

C15

SDQ70/CB6

D14

SDQ71/CB7

J21

SDREF0

J9

SDREF1

BROOKDALE(MCH-M)

E14

SCK0

F15

SCK#0

J24

SCK1

G25

SCK#1

G6

SCK2

G7

SCK#2

G15

SCK3

G14

SCK#3

E24

SCK4

G24

SCK#4

H5

SCK5

F5

SCK#5

K25

SCK6

J25

SCK#6

G17

SCK7

G16

SCK#7

H7

SCK8

H6

SCK#8

E9

SCS#0

F7

SCS#1

F9

SCS#2

E7

SCS#3

G9

SCS#4
SCS#5

SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8

SMA2/CS#6
SMA3/CS#9
SMA4/CS#5
SMA5/CS#8
SMA6/CS#7
SMA7/CS#4
SMA8/CS#3
SMA9/CS#0

SMA10

SBS0
SBS1

SCKE0
SCKE1
SCKE2
SCKE3
SCKE4
SCKE5

SMRCOMP

RCVENIN#

SSI_ST
SRAS#

SWE#

SCAS#

NC0
NC1

G10

F26
C26
C23
B19
D12
C8
C5
E3
E15

E12
F17
E16
G18
G19
E18
F19
G21
G20
F21
F13
E20
G22

G12
G13

G23
E22
H23
F23
J23
K23

J28
G3
H3

H27
F11

G11
G8

AD26
AD27

MEMORY

SMA0/CS#11
SMA1/CS#10

SMA11/CS#2
SMA12/CS#1

RCVENOUT#

DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3

DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_SDQS8

DDR_SMA0
DDR_SMA1
DDR_SMA2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6

DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12

DDR_SBS0
DDR_SBS1

DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3

SM_RCOMP

RCVIN#
RCVOUT#

DDR_SRAS#
DDR_SWE#
DDR_SCAS#

R283

DDR_SMA[0..12]

R75 30.1_1%

12

0_0402

R_J

DDR_CLK0 10
DDR_CLK0# 10
DDR_CLK1 10
DDR_CLK1# 10
DDR_CLK2 10
DDR_CLK2# 10

DDR_CLK3 11
DDR_CLK3# 11
DDR_CLK4 11
DDR_CLK4# 11
DDR_CLK5 11
DDR_CLK5# 11

DDR_SCS#0 10,11
DDR_SCS#1 10,11
DDR_SCS#2 11
DDR_SCS#3 11

DDR_SDQS0 10
DDR_SDQS1 10
DDR_SDQS2 10
DDR_SDQS3 10
DDR_SDQS4 10
DDR_SDQS5 10
DDR_SDQS6 10
DDR_SDQS7 10
DDR_SDQS8 10

DDR_SBS0 10,11
DDR_SBS1 10,11

DDR_CKE0 10,11
DDR_CKE1 10,11
DDR_CKE2 11
DDR_CKE3 11

12

C69 .1UF_0402_X5R
C358 @47PF

DDR_SRAS# 10,11
DDR_SWE# 10,11
DDR_SCAS# 10,11

DDR_SMA[0..12] 10,11

Layout note

+1.25VS

Layout note
Place R_J closely Ball
H3<40mil,Ball H3 to G3 trace
must
routing 1"

Place R637
closely pinJ28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE

A

B

C

D

Title

Size Document Number Rev

Date: Sheet

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

星期四 三月

401207

E

2A

of

883, 18, 2004

5

4

3

2

1

Layout note :

Distribute as clo se as possible
to MCH Processor Quadrant.(between VTTFSB and VSS pin)

+CPU_CORE

D D

12

C284
.1UF_0402_X5R

+CPU_CORE

12

C265
.1UF_0402_X5R

+CPU_CORE

12

C245

10UF_6.3V_1206_X5R

C C

Layout note :

Distribute as clo se as possible
to MCH Processor Quadrant.(between VCCAGP/VCCCORE
and VSS pin)

Processor system bus

12

C283
.1UF_0402_X5R

12

C261
.1UF_0402_X5R

12

C289

10UF_6.3V_1206_X5R

12

C270
.1UF_0402_X5R

12

C266
.1UF_0402_X5R

AGP/CORE

12

C251
.1UF_0402_X5R

12

C256
.1UF_0402_X5R

12

C288

10UF_6.3V_1206_X5R

12

C247
.1UF_0402_X5R

12

C250
.1UF_0402_X5R

Layout note :

Distribute as clo se as possible
to MCH Processor Quadrant.(between VCCSM and VSS pin)

+2.5V

12

C362
.1UF_0402_X5R

+2.5V

12

C366
.1UF_0402_X5R

+2.5V

12

C349
.1UF_0402_X5R

+2.5V

12

C378

+

150UF_D2_6.3V

DDR Memory interface

12

C374
.1UF_0402_X5R

12

C343
.1UF_0402_X5R

12

C352
.1UF_0402_X5R

12

C365
.1UF_0402_X5R

12

C364
.1UF_0402_X5R

12

C360
.1UF_0402_X5R

12

C375
.1UF_0402_X5R

12

C367
.1UF_0402_X5R

12

C345
.1UF_0402_X5R

12

C353
.1UF_0402_X5R

12

C363
.1UF_0402_X5R

12

C369
.1UF_0402_X5R

12

C377

22UF_10V_1206

12

C347

22UF_10V_1206

+1.5VS

12

C303
.1UF_0402_X5R

B B

+1.5VS

12

C314

10UF_6.3V_1206_X5R

Layout note :

Distribute as clo se as possible
to MCH Processor Quadrant.(between VCCHL and VSS pin)

+1.8VS

A A

12

C58

10UF_6.3V_1206_X5R

12

C304
.1UF_0402_X5R

12

C334

10UF_6.3V_1206_X5R

Hub-Link

12

C328
.1UF_0402_X5R

5

12

C268
.1UF_0402_X5R

12

C324
.1UF_0402_X5R

12

C244

+

150UF_D2_6.3V

12

12

C285
.1UF_0402_X5R

C333
.1UF_0402_X5R

12

C291
.1UF_0402_X5R

4

12

C312
.1UF_0402_X5R

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE

3

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

SCHEMATIC, M/B LA-1331

星期四

18, 2004

三月

401207

1

2A

of

983,

A

DDR_SBS0
DDR_SWE#

RP47 4P2R_22

1 4
2 3

RP46 4P2R_22

1 4
2 3

RP45 4P2R_22

1 4
2 3

RP44 4P2R_22

1 4
2 3

RP43 4P2R_22

1 4
2 3

RP42 4P2R_22

1 4
2 3

RP41 4P2R_22

1 4
2 3

RP40 4P2R_22

1 4
2 3

RP39 4P2R_22

1 4
2 3

RP38 4P2R_22

1 4
2 3

RP37 4P2R_22

1 4
2 3

RP48 4P2R_10

1 4
2 3

RP36 4P2R_10

1 4
2 3

RP35 4P2R_10

1 4
2 3

RP34 4P2R_10

1 4
2 3

RP33 4P2R_22

1 4
2 3

RP32 4P2R_22

1 4
2 3

RP31 4P2R_22

1 4
2 3

RP30 4P2R_22

1 4
2 3

RP29 4P2R_22

1 4
2 3

RP28 4P2R_22

1 4
2 3

RP27 4P2R_22

1 4
2 3

RP26 4P2R_22

1 4
2 3

RP49 4P2R_22

1 4
2 3

DDR_SDQ0
DDR_SDQ6

DDR_SDQ3
DDR_SDQ2

DDR_SDQ8

1 1

DDR_SDQ12

DDR_SDQS1
DDR_SDQ14

DDR_SDQ19
DDR_SDQ17

DDR_SDQS2
DDR_SDQ21

DDR_SDQ23
DDR_SDQ31

DDR_SDQ25

DDR_SDQ26
DDR_SDQS3

2 2

DDR_SBS08,11
DDR_SWE#8,11

3 3

DDR_CB4
DDR_CB5

DDR_CB6
DDR_CB3

DDR_SMA12
DDR_SMA9

DDR_SMA8
DDR_SMA6

DDR_SMA3
DDR_SMA1

DDR_SDQ36
DDR_SDQ37

DDR_SDQS4
DDR_SDQ33

DDR_SDQ34 DDR_DQ34
DDR_SDQ44 DDR_DQ44

DDR_SDQ41 DDR_DQ41

DDR_SDQ47
DDR_SDQ46

DDR_SDQ48
DDR_SDQ49

DDR_SDQ50

4 4

DDR_SDQ60 DDR_DQ60

DDR_SDQ62
DDR_SDQ59

A

DDR_DQ0
DDR_DQ6

DDR_DQ3
DDR_DQ2

DDR_DQ8
DDR_DQ12

DDR_DQS1
DDR_DQ14

DDR_DQ19
DDR_DQ17

DDR_DQS2
DDR_DQ21

DDR_DQ23
DDR_DQ31

DDR_DQ27DDR_SDQ27
DDR_DQ25

DDR_DQ26
DDR_DQS3

DDR_F_CB4
DDR_F_CB5

DDR_F_CB6
DDR_F_CB3

DDR_F_SMA12
DDR_F_SMA9

DDR_F_SMA8
DDR_F_SMA6

DDR_F_SMA3
DDR_F_SMA1

DDR_F_SBS0
DDR_F_SWE#

DDR_DQ36
DDR_DQ37

DDR_DQS4
DDR_DQ33

DDR_DQ43DDR_SDQ43

DDR_DQ47
DDR_DQ46

DDR_DQ48
DDR_DQ49

DDR_DQ50
DDR_DQ54DDR_SDQ54

DDR_DQ57DDR_SDQ57

DDR_DQ62
DDR_DQ59

B

DDR_SDQ4
DDR_SDQ5

DDR_SDQ1
DDR_SDQS0

DDR_SDQ7
DDR_SDQ15

DDR_SDQ9
DDR_SDQ13

DDR_SDQ11
DDR_SDQ10

DDR_SDQ20
DDR_SDQ16

DDR_SDQ22
DDR_SDQ18

DDR_SDQ29
DDR_SDQ24

DDR_SDQ28
DDR_SDQ30

DDR_SDQS8
DDR_CB7

DDR_CB0

DDR_CB2

DDR_SMA7
DDR_SMA11

DDR_SMA4
DDR_SMA5

DDR_SMA10
DDR_SMA0

DDR_SCAS#8,11
DDR_SRAS#8,11

DDR_SCAS#
DDR_SRAS# DDR_F_SRAS#

DDR_SDQ32 DDR_DQ32
DDR_SDQ39

DDR_SDQ35 DDR_DQ35

DDR_SDQ42
DDR_SDQS5

DDR_SDQ40
DDR_SDQ45

DDR_SDQ55 DDR_DQ55
DDR_SDQ52

DDR_SDQS6
DDR_SDQ53

DDR_SDQ51

DDR_SDQ61
DDR_SDQS7

DDR_SDQ58
DDR_SDQ63

B

C

RP75 4P2R_22

1 4
2 3

RP74 4P2R_22

1 4
2 3

RP73 4P2R_22

1 4
2 3

RP72 4P2R_22

1 4
2 3

RP71 4P2R_22

1 4
2 3

RP70 4P2R_22

1 4
2 3

RP69 4P2R_22

1 4
2 3

RP68 4P2R_22

1 4
2 3

RP67 4P2R_22

1 4
2 3

RP66 4P2R_22

1 4
2 3

RP65 4P2R_22

1 4
2 3

RP64 4P2R_22

1 4
2 3

RP63 4P2R_10

1 4
2 3

RP62 4P2R_10

1 4
2 3

RP61 4P2R_10

1 4
2 3

RP60 4P2R_10

1 4
2 3

RP59 4P2R_22

1 4
2 3

RP58 4P2R_22

1 4
2 3

RP56 4P2R_22

1 4
2 3

RP57 4P2R_22

1 4
2 3

RP55 4P2R_22

1 4
2 3

RP54 4P2R_22

1 4
2 3

RP53 4P2R_22

1 4
2 3

RP52 4P2R_22

1 4
2 3

RP51 4P2R_22

1 4
2 3

C

DDR_DQ4
DDR_DQ5

DDR_DQ1
DDR_DQS0

DDR_DQ7
DDR_DQ15

DDR_DQ9
DDR_DQ13

DDR_DQ11
DDR_DQ10

DDR_DQ20
DDR_DQ16

DDR_DQ22
DDR_DQ18

DDR_DQ29
DDR_DQ24

DDR_DQ28
DDR_DQ30

DDR_DQS8
DDR_F_CB7

DDR_F_CB1DDR_CB1
DDR_F_CB0

DDR_F_CB2

DDR_F_SMA7
DDR_F_SMA11

DDR_F_SMA4
DDR_F_SMA5

DDR_F_SMA10
DDR_F_SMA0

DDR_F_SCAS#

DDR_DQ39

DDR_DQ38DDR_SDQ38

DDR_DQ42
DDR_DQS5

DDR_DQ40
DDR_DQ45

DDR_DQ52

DDR_DQS6
DDR_DQ53

DDR_DQ51
DDR_DQ56DDR_SDQ56

DDR_DQ61
DDR_DQS7

DDR_DQ58
DDR_DQ63

D

DDR_DQ4
DDR_DQ0 DDR_DQ6

DDR_DQS0
DDR_DQ3

DDR_DQ7

DDR_DQ8
DDR_DQS1

DDR_DQ9
DDR_DQ14

DDR_CLK18
DDR_CLK1#8

DDR_DQ19
DDR_DQ20

DDR_DQS2
DDR_DQ22

DDR_DQ23
DDR_DQ29

DDR_DQ27
DDR_DQS3

DDR_DQ28
DDR_DQ30

DDR_F_CB4
DDR_F_CB6

DDR_DQS8
DDR_F_CB1

DDR_CLK08
DDR_CLK0#8

DDR_CKE18,11

DIMM_SMDATA11,13

DIMM_SMCLK11,13

DDR_CKE1 DDR_CKE0

DDR_F_SMA12
DDR_F_SMA9

DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA3
DDR_F_SMA1

DDR_F_SMA10
DDR_F_SBS0
DDR_F_SWE# DDR_F_SCAS#
DDR_SCS#0

DDR_DQ36
DDR_DQ32

DDR_DQS4
DDR_DQ35

DDR_DQ34
DDR_DQ42

DDR_DQ41
DDR_DQS5

DDR_DQ40
DDR_DQ47

DDR_DQ55
DDR_DQ48

DDR_DQS6
DDR_DQ50

DDR_DQ51
DDR_DQ57

DDR_DQ60
DDR_DQS7

DDR_DQ62
DDR_DQ58

+3VS

E

F

+2.5V +2.5V

JP26

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

VREF

DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQ30
DQ31

DU/RESET#

CKE0

DU/BA2

RAS#
CAS#

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQ46
DQ47

CK1#

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQ62
DQ63

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

VDD
DM1

VSS

VDD
VDD
VSS
VSS

VDD
DM2

VSS

VDD
DM3

VSS

VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7

VSS
VSS
VDD
VDD

VSS

VDD

VSS

VDD
DM4

VSS

VDD
DM5

VSS

VDD
CK1

VSS

VDD
DM6

VSS

VDD
DM7

VSS

VDD

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

A11

102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116

BA1

118
120
122

S1#

124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194

SA0

196

SA1

198

SA2

200

DU

DDR_DQ5

DDR_DQ1
DDR_DQ2

DDR_DQ12DDR_DQ15
DDR_DQ13

DDR_DQ11
DDR_DQ10

DDR_DQ17
DDR_DQ16

DDR_DQ21
DDR_DQ18

DDR_DQ31
DDR_DQ24

DDR_DQ25
DDR_DQ26

DDR_F_CB5
DDR_F_CB7

DDR_F_CB0
DDR_F_CB2DDR_F_CB3

DDR_F_SMA11
DDR_F_SMA8

DDR_F_SMA6
DDR_F_SMA4
DDR_F_SMA2
DDR_F_SMA0

DDR_F_SRAS#

DDR_DQ37
DDR_DQ39

DDR_DQ33
DDR_DQ38

DDR_DQ44
DDR_DQ43

DDR_DQ45
DDR_DQ46

DDR_DQ52
DDR_DQ49

DDR_DQ53
DDR_DQ54

DDR_DQ56
DDR_DQ61

DDR_DQ59
DDR_DQ63

+SDREF

12

C475
.1UF

DDR_CKE0 8,11

R157 10

R158 10

DDR_SCS#1 8,11DDR_SCS#08,11

DDR_CLK2# 8
DDR_CLK2 8

G

12

12

DDR_SMA2

DDR_SBS1DDR_F_S BS1

DDR_DQ[0..63]
DDR_F_CB[0..7]
DDR_DQS[0..8]
DDR_SMA[0..12]
DDR_SDQ[0..63]
DDR_CB[0..7]
DDR_SDQS[0..8]

DDR_SBS1 8,11

H

DDR_DQ[0..63] 11
DDR_F_CB[0..7] 11
DDR_DQS[0..8] 11
DDR_SMA[0..12] 8,11
DDR_SDQ[0..63] 8
DDR_CB[0..7] 8
DDR_SDQS[0..8] 8

DDR-SODIMM_200_REVERSE

DIMM0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE

Title

Size Document Number Rev

D

E

F

Date: Sheet

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

401207

G

星期四 三月

2A

of

10 83, 18, 2004

H

A

DDR_F_CB[0..7]10

DDR_DQS[0..8]10
DDR_DQ[0..63]10

DDR_SMA[0..12]8,10

1 1

2 2

DDR_CKE08,10
DDR_CKE18,10

3 3

DDR_F_CB[0..7]
DDR_DQS[0..8]
DDR_DQ[0..63]
DDR_SMA[0..12]

DDR_DQ4
DDR_DQ0

DDR_DQ3
DDR_DQ7

DDR_DQ15
DDR_DQ8

DDR_DQ9
DDR_DQ14

DDR_DQ19
DDR_DQ20

DDR_DQ22
DDR_DQ23

DDR_DQ27

DDR_DQ28
DDR_DQ30

DDR_F_CB4
DDR_F_CB6

DDR_F_CB1
DDR_F_CB3

DDR_CKE0
DDR_CKE1

DDR_CKE2
DDR_CKE3

DDR_SMA11
DDR_SMA8

DDR_SMA6
DDR_SMA4

DDR_SMA2
DDR_SMA0

RP134 4P2R_56

1 4
2 3

RP133 4P2R_56

1 4
2 3

RP132 4P2R_56

1 4
2 3

RP131 4P2R_56

1 4
2 3

RP129 4P2R_56

1 4
2 3

RP101 4P2R_56

1 4
2 3

RP100 4P2R_56

1 4
2 3

RP99 4P2R_56

1 4
2 3

RP98 4P2R_56

1 4
2 3

RP97 4P2R_56

1 4
2 3

RP123 4P2R_56

1 4
2 3

RP96 4P2R_56

1 4
2 3

RP122 4P2R_56

1 4
2 3

RP121 4P2R_56

1 4
2 3

RP120 4P2R_56

1 4
2 3

+1.25VS +1.25VS

RP107 4P2R_56

RP106 4P2R_56

RP105 4P2R_56

RP104 4P2R_56

RP130 4P2R_56

RP103 4P2R_56

RP102 4P2R_56

RP128 4P2R_56

RP127 4P2R_56

RP126 4P2R_56

RP125 4P2R_56

RP124 4P2R_56

RP95 4P2R_56

RP94 4P2R_56

RP93 4P2R_56

1 2

R444 56

1 2

R159 56

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

14
23

DDR_DQ5
DDR_DQ6

DDR_DQS0
DDR_DQ1

DDR_DQ2
DDR_DQ12

DDR_DQ13
DDR_DQS1

DDR_DQ11
DDR_DQ10

DDR_DQ17
DDR_DQ16

DDR_DQS2DDR_DQ29
DDR_DQ21

DDR_DQ18
DDR_DQ31

DDR_DQ24
DDR_DQS3

DDR_DQ25
DDR_DQ26

DDR_F_CB5
DDR_F_CB7

DDR_DQS8
DDR_F_CB0

DDR_SMA12
DDR_F_CB2

DDR_SMA7
DDR_SMA9

DDR_SMA3
DDR_SMA5

DDR_SMA1
DDR_SMA10

*

EMI Clip PAD for Memory DoorFor EC Tools

4 4

JP22

@ FCI SFW06R-2ST E1

+5VALW

1
2

EC_URXD

3

EC_UTXD

4

EC_USCLK

5
6

EC_URXD 32
EC_UTXD 32
EN_WOL# 27,32

A

PAD4

PAD-2.5X3

PAD7

PAD-2.5X3

PAD5

1

1

1

PAD-2.5X3

PAD8

1

PAD-2.5X3

PAD6

PAD-2.5X3

PAD9

PAD-2.5X3

B

DDR_SBS18,10
DDR_SRAS#8,10

DDR_SCS#08,10
DDR_SCS#18,10

DDR_SCAS#8,10

1

DDR_SBS1
DDR_SRAS#

DDR_SCS#0
DDR_SCS#1

DDR_SCAS#
DDR_SCS#3

DDR_DQ36
DDR_DQ32

DDR_DQ35
DDR_DQ34

DDR_DQ42

DDR_DQ41

DDR_DQ40
DDR_DQ47

DDR_DQ55
DDR_DQ48

DDR_DQ50
DDR_DQ51

DDR_DQ57
DDR_DQ60

DDR_DQ62
DDR_DQ58

DDR_DQ63

RP119 4P2R_56

1 4
2 3

RP91 4P2R_56

1 4
2 3

RP118 4P2R_56

1 4
2 3

RP90 4P2R_56

1 4
2 3

RP89 4P2R_56

1 4
2 3

RP88 4P2R_56

1 4
2 3

RP87 4P2R_56

1 4
2 3

RP85 4P2R_56

1 4
2 3

RP84 4P2R_56

1 4
2 3

RP83 4P2R_56

1 4
2 3

RP82 4P2R_56

1 4
2 3

RP108 4P2R_56

1 4
2 3

C

RP92 4P2R_56

14
23

RP117 4P2R_56

14
23

RP116 4P2R_56

14
23

RP115 4P2R_56

14
23

RP114 4P2R_56

14
23

RP113 4P2R_56

14
23

RP86 4P2R_56

14
23

RP112 4P2R_56

14
23

RP111 4P2R_56

14
23

RP110 4P2R_56

14
23

RP109 4P2R_56

14
23

DDR_SWE#
DDR_SBS0

DDR_SCS#2
DDR_DQ37

DDR_DQ39
DDR_DQS4

DDR_DQ33
DDR_DQ38

DDR_DQ44
DDR_DQ43

DDR_DQS5
DDR_DQ45

DDR_DQ46
DDR_DQ52

DDR_DQ49
DDR_DQS6

DDR_DQ53
DDR_DQ54

DDR_DQ56
DDR_DQ61

DDR_DQS7
DDR_DQ59

DDR_SWE# 8,10
DDR_SBS0 8,10

DDR_CLK48
DDR_CLK4#8

DDR_CLK38
DDR_CLK3#8

DIMM_SMDATA10,13

DIMM_SMCLK10,13

D

+2.5V +2.5V

JP27

1

VREF

3

DDR_DQ5
DDR_DQ6

DDR_DQS0
DDR_DQ1

DDR_DQ2
DDR_DQ12

DDR_DQ13
DDR_DQS1

DDR_DQ11
DDR_DQ10

DDR_DQ17
DDR_DQ16

DDR_DQS2
DDR_DQ21

DDR_DQ18
DDR_DQ31

DDR_DQ24
DDR_DQS3

DDR_DQ25
DDR_DQ26

DDR_F_CB5
DDR_F_CB7

DDR_DQS8
DDR_F_CB0

DDR_F_CB2

DDR_CKE3 DDR_CKE2
DDR_SMA12

DDR_SMA9
DDR_SMA7

DDR_SMA5
DDR_SMA3
DDR_SMA1

DDR_SMA10
DDR_SBS0
DDR_SWE#

DDR_DQ37
DDR_DQ39

DDR_DQS4
DDR_DQ33

DDR_DQ38
DDR_DQ44

DDR_DQ43
DDR_DQS5

DDR_DQ45
DDR_DQ46

DDR_DQ52
DDR_DQ49

DDR_DQS6
DDR_DQ53

DDR_DQ54
DDR_DQ56

DDR_DQ61
DDR_DQS7

DDR_DQ59
DDR_DQ63

+3VS

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0#

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2#

93

VDD

95

CKE1

97

DU/A13

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE#

121

S0#

123

DU

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD_SPD

199

VDD_ID

DDR-SODIMM_200_NORMAL

VREF

VSS
DQ4
DQ5
VDD

DM0

DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS

DQ20
DQ21

VDD

DM2

DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

DU/RESET#

VSS

VSS

VDD

VDD
CKE0

DU/BA2

VSS

VDD

BA1
RAS#
CAS#

VSS
DQ36
DQ37

VDD

DM4

DQ38

VSS
DQ39
DQ44

VDD
DQ45

DM5

VSS
DQ46
DQ47

VDD

CK1#

CK1

VSS
DQ52
DQ53

VDD

DM6

DQ54

VSS
DQ55
DQ60

VDD
DQ61

DM7

VSS
DQ62
DQ63

VDD

SA0

SA1

SA2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

A11

102

A8

104
106

A6

108

A4

110

A2

112

A0

114
116
118
120
122

S1#

124

DU

126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DU

E

DDR_DQ4
DDR_DQ0

DDR_DQ3
DDR_DQ7

DDR_DQ15
DDR_DQ8

DDR_DQ9
DDR_DQ14

DDR_DQ19
DDR_DQ20

DDR_DQ22
DDR_DQ23

DDR_DQ29
DDR_DQ27

DDR_DQ28
DDR_DQ30

DDR_F_CB4
DDR_F_CB6

DDR_F_CB1
DDR_F_CB3

DDR_SMA11
DDR_SMA8

DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0

DDR_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_SCS#3

DDR_DQ36
DDR_DQ32

DDR_DQ35
DDR_DQ34

DDR_DQ42
DDR_DQ41

DDR_DQ40
DDR_DQ47

DDR_DQ55
DDR_DQ48

DDR_DQ50
DDR_DQ51

DDR_DQ57
DDR_DQ60

DDR_DQ62
DDR_DQ58

+3VS

+SDREF

DDR_CKE2 8DDR_CKE38

DDR_SCS#3 8DDR_SCS#28

DDR_CLK5# 8
DDR_CLK5 8

12

C518
.1UF

DIMM1

1

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE

C

D

Title

Size Document Number Rev

Date: Sheet

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

星期四 三月

401207

E

2A

of

11 83, 18, 2004

A

B

C

D

E

Layout note :

Distribute as close as possible
to DDR-SODIMM.

+2.5V

1 1

12

C150
.1UF_0402_X5R

+2.5V +2.5V

12

C135
.1UF_0402_X5R

12

C134
.1UF_0402_X5R

12

C158
.1UF_0402_X5R

12

C151
.1UF_0402_X5R

12

C157
.1UF_0402_X5R

12

C155
.1UF_0402_X5R

12

C152
.1UF_0402_X5R

12

C132
.1UF_0402_X5R

12

C162
.1UF_0402_X5R

12

C156
.1UF_0402_X5R

12

***

C160
@.1UF_0402_X5R

12

C163
.1UF_0402_X5R

12

C112

+

150UF_D2_6.3V

12

C133
.1UF_0402_X5R

12

C159

+

150UF_D2_6.3V

12

C154
.1UF_0402_X5R

12

***

C161
@.1UF_0402_X5R

Layout note :

Place one cap close to every 2 pull up resistors termination to
+1.25V

2 2

+1.25VS

12

C538
.1UF_0402_X5R

+1.25VS

12

C548
.1UF_0402_X5R

12

C539
.1UF_0402_X5R

12

C549
.1UF_0402_X5R

12

C540
.1UF_0402_X5R

12

C550
.1UF_0402_X5R

12

C541
.1UF_0402_X5R

12

C551
.1UF_0402_X5R

12

C542
.1UF_0402_X5R

12

C552
.1UF_0402_X5R

12

C543
.1UF_0402_X5R

12

C553
.1UF_0402_X5R

12

C544
.1UF_0402_X5R

12

C554
.1UF_0402_X5R

12

C545
.1UF_0402_X5R

12

C555
.1UF_0402_X5R

12

C546
.1UF_0402_X5R

12

C556
.1UF_0402_X5R

12

C547
.1UF_0402_X5R

12

C557
.1UF_0402_X5R

+1.25VS

12

C558

3 3

4 4

.1UF_0402_X5R

+1.25VS

12

C568
.1UF_0402_X5R

+1.25VS

12

C578
.1UF_0402_X5R

+1.25VS

12

C594
.1UF_0402_X5R

12

C559
.1UF_0402_X5R

12

C569
.1UF_0402_X5R

12

C579
.1UF_0402_X5R

12

C593
.1UF_0402_X5R

A

12

C560
.1UF_0402_X5R

12

C570
.1UF_0402_X5R

12

C580
.1UF_0402_X5R

12

C592
.1UF_0402_X5R

12

C561
.1UF_0402_X5R

12

C571
.1UF_0402_X5R

12

C581
.1UF_0402_X5R

12

C591
.1UF_0402_X5R

12

C562
.1UF_0402_X5R

12

C572
.1UF_0402_X5R

12

C582
.1UF_0402_X5R

12

C563
.1UF_0402_X5R

12

C573
.1UF_0402_X5R

12

C583
.1UF_0402_X5R

B

12

C564
.1UF_0402_X5R

12

C574
.1UF_0402_X5R

12

C584
.1UF_0402_X5R

12

C565
.1UF_0402_X5R

12

C575
.1UF_0402_X5R

12

C585
.1UF_0402_X5R

12

C566
.1UF_0402_X5R

12

C576
.1UF_0402_X5R

12

C586
.1UF_0402_X5R

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE

12

C567
.1UF_0402_X5R

12

C577
.1UF_0402_X5R

12

C595
.1UF_0402_X5R

C

Title

Size Document Number Rev

D

Date: Sheet

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

星期四 三月

401207

E

2A

of

12 83, 18, 2004

A

B

C

+3VS

L6
BLM21A601SPT

1 2

L7
BLM21A601SPT

1 2

D

+3V_CLK

+3V_CLK

+

12

C104
22UF_10V_1206

E

C102
.1UF

12

12

C100
.1UF

12

C110
.1UF

12

C125
.1UF

F

12

C98
.1UF

12

C99
.1UF

12

C108
.1UF

G

H

1 1

H_BSEL0H_BSEL1

00

01

*

1

11

2 2

100Mhz Host CLK

200Mhz Host CLK

0

133Mhz Host CLK

H_BSEL05
H_BSEL15

Function

66Mhz Host CLK

R143

1K

1 2

R99 @0

12

R102
@1K

H_BSEL2
H_BSEL0

R106

+3VS +3VS

12

12

1K

MULT0

0
1 2.32mA

Place Crystal within 500 mils of CK_Titan

C97 10PF

CK408_PWRGD#32,35
+3VS

BSEL0

PM_SLP_S1#16,32
PM_SLP_S3#16,32

PM_STPPCI#16

PM_STPCPU#16,42

caps are internal
to CK_TITAN

C101 10PF

R135 10K
R130 @ 10K

12

R103

1K

12

R107
@1K

Iref

5.00mA

12

12

1 2
1 2

DIMM_SMDATA
DIMM_SMCLK

1 2

R148 0

1 2

R146 @0

1 2

R108 0

Please closely pin42

1 2

R140 475_1%

CLK_ICH4816

3 3

CLK_ICH1416
CLK_SIO1424

1 2

R144 33

CLK_ICH14M
CLK_SIO14M

CLK_ICH48M CLKPCI_F2

1 2

R101 33

1 2

R100 33

12

Y1

14.318MHZ

+3V_CLK = 40mils

U8

2

XTAL_IN

3

XTAL_OUT

40

SEL2

55

SEL1

54

SEL0

25

PWR_DWN#

34

PCI_STOP#

53

CPU_STOP#

28

VTT_PWRGD#

43

MULT0

29

SDATA

30

SCLK

33

3V66_0/DRCG

35

3V66_1/VCH_CLK

42

IREF

39

48MHZ_USB

38

48MHZ_DOT

56

REF

W320-04

or ICS 9508-05

+3V_CLK

32

37

14

1

50

VDD_PCI8VDD_PCI

VDD_REF

VDD_CPU46VDD_CPU

VDD_3V6619VDD_3V66

VDD_48MHZ

66MHZ_IN/3V66_5

66MHZ_OUT2/3V66_4
66MHZ_OUT1/3V66_3
66MHZ_OUT0/3V66_2

GND_REF4GND_PCI9GND_PCI15GND_3V6620GND_3V6631GND_48MHZ36GND_IREF41GND_CPU

47

+3VS_VDD48M = 10mils

+3VS_CLKVDD

26

VDD_CORE

GND_CORE

CPUCLKT2

CPU_CLKC2

CPUCLKT1

CPUCLKC1
CPUCLKT0

CPUCLKC0

PCICLK_F2
PCICLK_F1
PCICLK_F0

PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0

27
45

44
49

48
52

51
24

23
22
21

7
6
5

18
17
16
13
12
11
10

12

C127
.1UF

CLK66MCH

CLK66AGP

CLKICHHUB

R137 33
R138 33
R131 33
R127 33
R118 33
R117 33
R114 33

12

C124
10UF_10V_1206

CLK_BCLK

CLK_BCLK#
CLK_HT

CLK_HT#

R139 33

1 2
1 2
1 2
1 2
1 2
1 2
1 2

+3VS_VDD48M

L9
BLM21A601SPT

1 2

1 2

R145 33

1 2

1 2

R112 33

+3VS_VDD48M

+3VS

1 2

R129 33

1 2

R133 33

1 2

R113 33

1 2

R116 33

R142 33

Place caps. near
CK_Titan (U10)

12

C123
.1UF

1 2

1 2

L8

BLM21A601SPT

12

C118
10UF_10V_1206

1 2

R128 49.9_1%

R134 49.9_1%

1 2

1 2

R110 49.9_1%

R115 49.9_1%

1 2

12

12

C115

C119

@10PF

@10PF

12

C122
@10PF

+3VS

CLK_HCLK 4

CLK_HCLK# 4
CLK_GHT 7

CLK_GHT# 7

CLK_AGP_MCH 7
CLK_AGP 14
CLK_ICHHUB 16

CLK_ICHPCI 16

CLK_LPC_SIO 24
CLK_PCI_LAN 20
CLK_PCI_CB 22
CLK_PCI_1394 21
CLK_PCI_SD/SM 28
CLK_LPC_EC 32
CLK_MINIPCI 27

Place resistor near R645,R653
;Trace<=400mils

Place resistor near R653, R655
;Trace<=400mils

+5VS

2

G

1 3

D

4 4

SMB_CLK16,18

A

S

Q6 2N7002

+5VS

2

G

1 3

D

S

Q7 2N7002

B

DIMM_SMDATA 10,11SMB_DATA16,18

DIMM_SMCLK 10,11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE

C

D

E

F

Title

Size Document Number Rev

Date: Sheet

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

401207

G

星期四 三月

2A

of

13 83, 18, 2004

H

5

4

3

2

1

KSI[0..7]32

KSO[0..15]32

KSI[0..7]
KS0[0..15]

AGP CONN.

JP8

D D

C C

B B

A A

AGP_IRDY#7

AGP_DEVSEL#7

CRT_R15
CRT_G15

CRT_B15

CRT_HSYNC115

CRT_VSYNC115

CRT_DDCDATA15

CRT_DDCCLK15

+5VALW

DAC_BRIG32

CBRST#20,22,23,27,28

+5VALW +5VALW

+1.5VS

SUS_STAT#16,24,34
AGP_BUSY#16

AGP_REQ#7

AGP_RBF#7

AGP_SBSTB7

CLK_AGP13

AGP_ADSTB17

AGP_ADSTB07

C3_STAT#16

+AGP_NBREF

DAC_BRIG

AGP_ST0
AGP_ST2

AGP_SBA0
AGP_SBA2

AGP_SBA4
AGP_SBA6
CLK_AGP

AGP_AD31
AGP_AD29
AGP_AD27
AGP_AD25

AGP_AD23
AGP_AD21
AGP_AD19
AGP_AD17

AGP_C/BE#2

AGP_IRDY#
AGP_DEVSEL#

AGP_C/BE#1

AGP_AD14
AGP_AD12
AGP_AD10
AGP_AD8

AGP_AD7
AGP_AD5
AGP_AD3
AGP_AD1

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119

CLK_AGP

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119

HEADER 2X60

R94

1 2

@33

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96

98
100
102
104
106
108
110
112
114
116
118
120

1 2

2
4
6
8

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120

C92

@15PF

INVT_PWM

ENBKL
ENVEE

AGP_ST1

AGP_SBA1
AGP_SBA3

AGP_SBA5
AGP_SBA7

AGP_C/BE#3
AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24

AGP_AD22
AGP_AD20
AGP_AD18
AGP_AD16

AGP_FRAME#

AGP_AD15
AGP_AD13
AGP_AD11
AGP_AD9

AGP_C/BE#0
AGP_AD6
AGP_AD4
AGP_AD2
AGP_AD0

PCI_RST#

TV_CRMA 15
TV_LUMA 15
TV_COMPS 15
TV_SYNC 15
PID0 24
PID1 24
PID2 24
PID3 24
INVT_PWM 32

+5VALW

ENBKL 32
ENVEE 32

+1.5VS

PIRQA# 16 , 18,21,22
PCIRST# 7,16,19,20,21,22,23,24,27,28,34
AGP_GNT# 7

AGP_PIPE# 7
AGP_WBF# 7

AGP_SBSTB# 7

AGP_ADSTB1# 7

AGP_FRAME# 7
AGP_TRDY# 7
AGP_STOP# 7
AGP_PAR 7

AGP_ADSTB0# 7

+AGP_VGAREF

JP8 PIN

25,26,27,28

VGA/B
SQ17 V
NV11

ACL10

ATL02/ACL00

+5VALW +1.5V

X

VV

MD_MIC30

+3.3VAUX

IAC_SDATAO16,30

IAC_RST#16,30

+3VS

1 2

L40

CHB1608B121

AGP_ST[0..2]7
AGP_AD[0..31]7
AGP_SBA[0..7]7

AGP_C/BE#[0..3]7

+3VS_MDC

AGP_ST[0..2]

AGP_C/BE#[0..3]

JP13

1

MONO_OUT/PC_BEEP

3

GND

5

AUXA_RIGHT

7

AUXA_LEFT

9

CD_GND

11

CD_RIGHT

13

CD_LEFT

15

GND

17

3.3Vaux

19

GND

21

3.3Vmain

23

AC97_SDATA_OUT

25

AC97_RESET#

27

GND

29

AC97_MSTRCLK

AMP-108-5424

AGP_AD[0..31]
AGP_SBA[0..7]

MDC CONN.

+3V

+3VS
+5VS

AUDIO_PWDN

MONO_PHONE

RESERVED

GND

RESERVED
RESERVED
RESERVED
RESERVED
RESERVED

AC97_SYNC
AC97_SDATA_IN1
AC97_SDATA_IN0

GND

AC97_BITCLK

+3.3VAUX

12

+5V

KSI0
KSI2
KSI4
KSI6
KSO0
KSO2
KSO4
KSO6
KSO8
KSO10
KSO12

C117
1UF_25V_0805

MDC_SPK

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

Int. Keyboard CONN.

NC

NC

MDC_SPK

JP11

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

HEADER 2X20

12

C116

1UF_25V_0805

C469 1UF_25V_0805

1 2

C472

1 2

1000PF

+5VS_MDC

1 2

L43 CHB1608B121

1 2

R374 10K

1 2

R361 22

1 2

*

R360 @22

*

R357 10K

IAC_BITCLK 16,30

+5VS_MDC+3VS_MDC

MD_SPK 30

+5VS

+3VS

1 2

KSI1
KSI3
KSI5
KSI7
KSO1
KSO3
KSO5
KSO7
KSO9
KSO11
KSO13
KSO15KSO14

12

C129

1UF_25V_0805

MDC_DN# 33

+12V
+3V

+5V

TP_CLK 32TP_DATA32

IAC_SYNC 16,30

IAC_SDATAI1 16

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND

PROPRIETARY NOTE

5

4

TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Rev

Date: Sheet of

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA -1331

B

星期四

18, 2004

三月

401207

2A

14 83,

1

A

B

C

D

E

D10

DAN217

1

12

C227

270PF

2

C222 22PF

1 2

FBM-11-160808-121

C221 22PF

1 2

FBM-11-160808-121

C223 22PF

1 2

FBM-11-160808-121

1 1

L20

R201

12

75

1 2

@FBM-11-160808-121

12

12

C226

C228

270PF

270PF

TV_SYNC14

TV_LUMA14

TV_CRMA14

TV_COMPS14

12

12

R200

2 2

R202

75

75

3

1 2

L25

1 2

L24

1 2

L26

D9

DAN217

C192

330PF

D8

12

C191
330PF

12

C202

DAN217

330PF

2

12

1

3

C201
@470PF

R203 For CH7011/SQ17

**

1 2

R203 0

1 2

R196 @0

R196 For CH7007

**

JP2

1
2
3
4
5
6
7

S CONN._SUYIN

+3VS

+5VS

TV_OUT CONNECTOR

1

2

3

12

**

+3VS

1

D6

@DAN217

2

3 3

L13

1 2

13

2N7002

2

1 2

FCM2012C80_0805

L14

1 2

FCM2012C80_0805

L15

1 2

FCM2012C80_0805

12

C198
10PF

Q12

13

Q11

2N7002

2

12

C185
22PF

L2

1 2

CHB1608B121

L1

1 2

CHB1608B121

CRT_R14

CRT_G14

CRT_B14

CRT_HSYNC114

CRT_VSYNC114

4 4

R182

75

1 2

+12VS

12

C197
10PF

R185 100K

R183

75

12

C196

R184

10PF

1 2

75

1

D5

@DAN217

2

3

3

12

C184
22PF

12

12

C6

22PF

12

C3
22PF

D4

@DAN217

2

C183
22PF

1

+5VS

3

D7

2 1

RB491D

+R_CRT_VCC

220PF

F1

FUSE_1A

C5

C7
.1UF

12

**

+CRT_VCC

21

12

12

+CRT_VCC

C182
220PF

JP3
CRT-15P

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

5VDDCDA

5VDDCCL

*

CRT CONNECTOR

+CRT_VCC

+12VS

12

12

R5

R6

2.2K

2.2K

Q1

2N7002

2

1 3

12

Q3
2N7002

R8
100K

2

1 3

CRT_DDCDATA 14

CRT_DDCCLK 14

COMPAL ELECTRONICS, INC

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

A

B

C

D

SCHEMATIC, M/B LA -1331

Size Document Number Rev
Custom

401207

Date: Sheet

星期四

18, 2004

三月

15 83,

E

of

2A

A

ECSMI#18
ECSCI#18

IDE_PATADET19 LPC_DRQ#0 18,32

RTCCLK22,23,28

IAC_RST#14,30
IAC_SDATAI030
IAC_SDATAI114

IAC_SDATAO14,30

IAC_SYNC14,30

1 1

IAC_BITCLK14,30

Place closely to ICH3

CLK_ICH14

12

R304
@10

12

C406
@15PF

CLK_ICH48

12

2 2

R307
@10

12

C399
@15PF

3 3

+RTCVCC

12

R259

R261 22M

+1.8VS

4 4

R85

301_1%

R_G

R86

301_1%

ECSMI#
ECSCI#
LID#

LID#18

IDE_PATADET

PM_SUSCLK

12

R44 0

IAC_RST#

IAC_SDATAI0
IAC_SDATAI1

IAC_SDATAO
IAC_SYNC
IAC_BITCLK

12

R351 10K

1 2

+3VS

C/BE#020,21,22,27,28
C/BE#120,21,22,27,28
C/BE#220,21,22,27,28
C/BE#320,21,22,27,28

GNT#018,21
GNT#118,27
GNT#218,22
GNT#318,20
GNT#418,27

REQ#018,21
REQ#118,27
REQ#218,22
REQ#318,20
REQ#418,27

1 2

R272 10M
R264

C336

2.4M
12PF

R278 @ 10K

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

1 2

R271 10M_0603

12

32.768KHZ

AD[0..31]20,21,22,27,28

1K

C306

1 2

.047UF_0603

1 2

12

HUB Interface VSwing Voltage

12

1. Place R_G and R_H in middle of Bus.

12

C79
.1UF

+VS_HUBVSWING

12

ICH_VGATE35

PM_CPUPERF#5

PM_GMUXSEL42

ATF_INT#32

SUS_STAT#14,24,34

PM_STPPCI#13

PM_STPCPU#13,42

PM_SLP_S5#32
PM_SLP_S3#13,32
PM_SLP_S1#13,32

PM_RSMRST#35

ICH_RI#18

PM_PWROK35

PBTN#18

PM_DPRSLPVR42

PM_CLKRUN#18,22,24,27,28,32

C3_STAT#14

PM_BATLOW#32

AGP_BUSY#14

U29A

J2

PCI_AD0

K1

PCI_AD1

J4

PCI_AD2

K3

PCI_AD3

H5

PCI_AD4

K4

PCI_AD5

H3

PCI_AD6

L1

PCI_AD7

L2

PCI_AD8

G2

PCI_AD9

L4

PCI_AD10

H4

PCI_AD11

M4

PCI_AD12

J3

PCI_AD13

M5

PCI_AD14

J1

PCI_AD15

F5

PCI_AD16

N2

PCI_AD17

G4

PCI_AD18

P2

PCI_AD19

G1

PCI_AD20

P1

PCI_AD21

F2

PCI_AD22

P3

PCI_AD23

F3

PCI_AD24

R1

PCI_AD25

E2

PCI_AD26

N4

PCI_AD27

D1

PCI_AD28

P4

PCI_AD29

E1

PCI_AD30

P5

PCI_AD31

K2

PCI_C/BE#0

K5

PCI_C/BE#1

N1

PCI_C/BE#2

R2

PCI_C/BE#3

A4

PCI_GNT#0

E3

PCI_GNT#1

D2

PCI_GNT#2

D5

PCI_GNT#3

B4

PCI_GNT#4

D3

PCI_REQ#0

F4

PCI_REQ#1

A3

PCI_REQ#2

R4

PCI_REQ#3

E4

PCI_REQ#4

ICH3-M

RTC_VBIAS
RTC_X1

RTC_X2

X2

12

C327
12PF

1 2

PM_LANPWROK

V4

PM_AGPBUSY#/GPIO6

PCI

Interface

VSS0A1VSS1

A13

Y5

PM_AUXPWROK

VSS2

A16

R_K

R_L

AB3

PM_BATLOW#

VSS3

A17

V5

AC2

PM_C3_STAT#/GPIO21

VSS4

A20

A23

R88

301_1%

R91

301_1%

R260

PM_SUSCLK

U21

AB1

AB21

PM_DPRSLPVR

PM_CLKRUN#/GPIO24

V21

AA7

AA6

AA1

PM_RI#

PM_PWROK

PM_PWRBTN#

AB4

W20

PM_RSMRST#

AA5

PM_SLP_S3#

PM_SLP_S1#/GPIO19

AA2

PM_SLP_S5#

PM_STPPCI#/GPIO18

PM_STPCPU#/GPIO20

AA4

PM_SUS_CLK

U5

PM_SUS_STAT#

GeyservillePower Management

VSS5

VSS6B8VSS7

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15C3VSS16C6VSS17

B18

B19

B20

+RTCVCC

B22

CLK_ICH1413
CLK_ICH4813

F19

C14

1 2

R258 15K

+VS_HUBREF

B10

B13

B14

B15

HUB Reference Voltage

+1.8VS

12

Place R_K and R_L
Closely ICH3

12

PM_THRM#

VSS18

R_H

A

B

C44

IAC_SDATAO

@ 10PF

12

R58

@ 33

1 2

IAC_SDATAI0

IAC_SDATAI1

IAC_BITCLK

IAC_RST#

R55 0

V19

U20

Y20

PM_GMUXSEL/GPIO23

PM_CPUPREF#/GPIO22

PM_VGATE/VRMPWRGD

D11

B7

B11

AC_RST#

AC_BITCLK

AC_SDATAIN0

AC'97

Interface

C7

C11

AC_SDATAIN1

AC_SDATAOUT

ICH3-M (1/2)

VSS

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

VSS27D9VSS28

VSS29

VSS30

C15

C16

C17

C18

C19

C20

C21

C22

D13

D16

D17

CLK_ICH14
CLK_ICH48

C301

1UF_10V_0603

B

IAC_SYNC

1 2

ECSMI#

U1

U4

U2

LPC_DRQ#0T2LPC_DRQ#1

IDE_PATADET

W2

GPIO_7V2GPIO_8

LPC_FRAME#

unMUX

GPIO

R54 33

A7

AC_SYNC

LPC_AD0V1LPC_AD1U3LPC_AD2T3LPC_AD3

LPC

Interface

Clocks EEPROM

CLK_RTCX2

CLK_RTCX1

CLK_RTEST#Y7CLK_48

CLK_14

VSS31

VSS32

VSS33

VSS34

E5

D20

D21

D22

12

CLK_VBIAS

J23

F20

AB7

AC6

AC7

RTC_VBIAS

RTC_RST#

RTC_X2

RTC_X1

12

J1
JOPEN

12

R253
1K

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE

PIDEPWR

ECSCI#

LID#

GPIO_25

GPIO_12Y4GPIO_13Y2GPIO_25W3GPIO_27W4GPIO_28

LAN

Interface

LAN_TXD2

LAN_JCLK

LAN_RSTSYNC

C9

D7

A10

C10

Y3

LAN_TXD0B9LAN_TXD1

A9

J19

J20

INT_APICD0

INT_APICCLK

LAN_RXD0

LAN_RXD1

LAN_RXD2

A8

C8

PIRQC#

PIRQB#

PIRQA#

B1

J21

B2

INT_APICD1

INT_PIRQB#C1INT_PIRQA#

Interrupt
Interface

Interface

D10

12

R63
@0

*

+3VS

PIRQD#

INT_PIRQD#A2INT_PIRQC#

EEP_CSE9EEP_DIND8EEP_DOUTE8EEP_SHCLK

ICH_PID1

ICH_PID0

B5

A6

INT_PIRQF#/GPIO3

INT_PIRQE#/GPIO2

ICH_PID2

1 2

C5

INT_PIRQG#/GPIO4

HUB_VSWING

L19

R43 100K

C

CLK_ICHAPIC

H_PICD0
H_PICD1

ICH_PID3

A5

H22

W19

AB14

INT_IRQ15

INT_IRQ14

INT_SERIRQ

INT_PIRQH#/GPIO5

HUB_VREF

L20

PCI_DEVSEL#

PCI_GPIO0/REQA#

PCI_GPIO1/REQB#/REQ5#

PCI_GPIO16/GNTA#

PCI_GPIO17/GNTB#/GNT5#

PCI

Interface

SM_INTRUDER#

System

Managment

Interface

SMB_ALERT#/GPIO11

CPU_A20GATE

CPU_DPSLP#

CPU

Interface

CPU_PWRGOOD

HubLink

Interface

HUB_CLK

HUB_PAR

HUB_PSTRB

HUB_PSTRB#

HUB_RCOMP

T19

P23

K19

R19

N22

CLK_ICHHUB

HUB_ICH_RCOMP

PM_LANPWROK

1 2

C29 .1UF

C

LPC_AD0 24,32
LPC_AD1 24,32
LPC_AD2 24,32
LPC_AD3 24,32

LPC_DRQ#1 18,24
LPC_FRAME# 24,32

SIDEPWR 19

INT_IRQ14 18,19
INT_IRQ15 18,29
INT_SERIRQ 18,22,24,32

PCI_CLK

PCI_FRAME#

PCI_IRDY#

PCI_PAR
PCI_PERR#
PCI_LOCK#

PCI_PME#

PCI_RST#

PCI_SERR#

STOP#

PCI_TRDY#

SMLINK0

SMLINK1

SMB_CLK

SMB_DATA

CPU_A20M#

CPU_FERR#

CPU_IGNNE#

CPU_INIT#
CPU_INTR

CPU_NMI

CPU_RCIN#

CPU_SLP#
CPU_SMI#

STPCLK#

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9

HUB_PD10

CLK_ICHPCI

T5
M3
F1
C4
D4
B6
B3
N3
G5
M2
M1
W1
Y1
L5
H2
H1

Y6
AC3
AB2
AC4
AB5
AC5

Y22
V23
AB22

H_FERR#

J22
AA21
AB23
AA23
Y21
W23
U22
W21
Y23
U23

HUB_PD0

L22

HUB_PD1

M21

HUB_PD2

M23

HUB_PD3

N20

HUB_PD4

P21

HUB_PD5

R22

HUB_PD6

R20

HUB_PD7

T23

HUB_PD8

M19

HUB_PD9

P19

HUB_PD10

N19

CLK_ICHHUB 13
HUB_PSTRB 7
HUB_PSTRB# 7

GNTA#

+VS_HUBREF

PIRQA#
PIRQB#
PIRQC#
PIRQD#

CLK_ICHAPIC
H_PICD0
H_PICD1

R305

CLK_ICHPCI 13
DEVSEL# 18,20,21,2 2, 2 7, 2 8
FRAME# 18,20,21,22,27,28
PCI_REQA# 18
PCI_REQB# 18

IRDY# 18,20,21,22,27,28
PAR 18,20,21,22,27,28
PERR# 18,20,21,22,27
PLOCK# 18,22
ICH_WAKE_UP# 32

SERR# 18,20,22,27
STOP# 18,20,21,22,27,28
TRDY# 18,20,21,22,27,28

SM_INTRUDER# 18
SMLINK0 18
SMLINK1 18
SMB_CLK 13,18
SMB_DATA 13,18
SMB_ALERT# 18

GATEA20 32
H_A20M# 5

H_IGNNE# 5
H_INIT# 5
H_INTR 5
H_NMI 5
H_PWRGD 5
RC# 32
H_SLP# 5
H_SMI# 5
H_STPCLK# 5

HUB_PD[0..10]

+VS_HUBVSWING

12

C394
.01UF

12

Close to ICH3-M.

D

PIRQA# 14,18,21,22
PIRQB# 18,20,22
PIRQC# 18,27,28
PIRQD# 18,27,28

12

1K

+3VS

12

12

R308

R306

0

1K

RP14

1 8
2 7
3 6
4 5

8P4R_4.7K

R49 @10K

GNTA#

1 2

GPIO_25

1 2

R39 @10K

ICH_PID0
ICH_PID1
ICH_PID2
ICH_PID3

Place closely to ICH3

12

R50
@10

12

C27
@15PF

1 2

*

R467

33

+CPU_CORE

12

1 2

R298 0

H_FERR#

HUB_PD[0..10] 7

1 2

R315 36.5_1%

C393
.01UF

COMPAL ELECTRONICS, INC

Title

SCHEMATIC, M/B LA-1331

Size Document Number Rev
Custom

Date: Sheet

星期四 三月

PCIRST# 7,1 4,19,20,21,22,23,24,27,28,34

C637
@10PF

*

(for use if CPU unable

R217
@10K

to support DPSLP#)

H_DPSLP# 5

+3VS

12

R327
300

2

Q25

3 1

3904

H_F_FERR#5

CLK_ICHHUB

R309
10

1 2

C395

5PF

401207

D

CLK_ICHAPICCLK_ICHPCI

R312
@33

1 2

C405
@10PF

12

R326
470

2

Q24

3 1

3904

1 2

R325 470

16 83, 18, 2004

of

*

+3VS
+3VALW

2A

A

+5VS +3VS

R59

1K

1 1

DEL:C73, C87, C371.

*

USB_PP026
USB_PN026

USB_PP126
USB_PN126

USB_PP326
USB_PN326

2 2

+3V

RP20
8P4R_10K

1 8
2 7
3 6
4 5

3 3

+3VS

USB_OC#2
USB_OC#4

USB_OC#5

12

R293

18.2_1%

Disable Timeout Feature

1 2

R313 @1K

ICH_SPKR

ICH_IDE_PRST#19
ICH_IDE_SRST#19

USB_D_PP0
USB_D_PN0

USB_D_PP1
USB_D_PN1

USB_D_PP3
USB_D_PN3

USB_OC#026
USB_OC#126

USB_OC#326

FWH_WP#18

FWH_TBL#18

EC_FLASH#33

ICH_SPKR31

+3VALW

USB_RBIAS

+1.8VS

+V3A_ICH

+1.8VALW

1 2

R294

0_0805

U29B

USB_D_PP0
USB_D_PP1

USB_D_PP3

USB_D_PN0
USB_D_PN1

USB_D_PN3

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5

1 2

R90 @0

ICH_ACIN

ICH_SPKR IDE_SDD12

R288

1 2

0_0805

D19
A19
E17
B17
D15
A15
D18
A18
E16
B16
D14
A14

*

E12
D12
C12
B12
A12
A11

H20

G22

F21

G19

E22
E21
H21

G23

F23

G21

D23
E23

B21

H23

U19

F17
F18
K14

E10

USB_PP0
USB_PP1
USB_PP2
USB_PP3
USB_PP4
USB_PP5
USB_PN#0
USB_PN#1
USB_PN#2
USB_PN#3
USB_PN#4
USB_PN#5

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5

USB_LEDA#0/GPIO32
USB_LEDA#1/GPIO33
USB_LEDA#2/GPIO34
USB_LEDA#3/GPIO35
USB_LEDA#4/GPIO36
USB_LEDA#5/GPIO37
USB_LEDG#0/GPIO38
USB_LEDG#1/GPIO39
USB_LEDG#2/GPIO40
USB_LEDG#3/GPIO41
USB_LEDG#4/GPIO42
USB_LEDG#5/GPIO43

USB_RBIAS

SPKR

VCCA

VCCPSUS3/VCCPUSB0
VCCPSUS4/VCCPUSB1
VCCPSUS5/VCCPUSB2

VCCPSUS0

V8

VCCPSUS1

V9

VCCPSUS2

12

+1.8VS

*

B

21

D27
1SS355

12

C43
.1UF

L37

1 2

CHB2012U170

E13

F14

K12

P10

VCC_SUS0

VCC_SUS1

VCC_SUS2

USB

Interface

Misc

Power

12

V7

VCC_SUS3

VCC_SUS4V6VCC_SUS5

+V5S_ICHREF

C330
1UF_10V_0603

+V1.8_ICHLAN

F15

F16

VCC_USB0/VCC_SUS6

VCC_USB1/VCC_SUS7

VCC_AUX0/VCCLAN1_8F7VCC_AUX1/VCCLAN1_8F8VCC_AUX2/VCCLAN1_8

+RTCVCC

K10

AB6

VCC_RTC

+V5S_ICHREF

VCC5REFSUS

W8

C13

VCC5REF1E6VCC5REF2

VCC5REFSUS1

C

+5VALW

*

*

12

R284
0

12

C361
.1UF

**

+CPU_CORE

R279
0_0805

P14

U18

V22

VCCPCPU0

VCCPCPU1

VCCPCPU2

+1.8VALW

C23

VCCUSBBG/VCC_SUS8

12

R310
0_0805

+1.8VA_ICH

B23

N/C0E7N/C1

Power

VCCUSBPLL/VCC_SUS9

T21

C2

N/C2D6N/C3T1N/C4

+3VS +1.8VS

G18

VSS103

M10

VCCPPCI0F6VCCPPCI1G6VCCPPCI2H6VCCPPCI3J6VCCPPCI4

A21

A22

VSS102

VCCPPCI5R6VCCPPCI6T6VCCPPCI7

H18

U6

P12

V15

V16

V17

V18

VCCP0

VCCP1

VCCPIDE0

VCCPIDE1

VCCPIDE2

VCCPIDE3

VCCPIDE4

+3VS

12

F10

W5

VCC5REFSUS2

VCCPAUX0/VCCLAN3_3F9VCCPAUX1/VCCLAN3_3

ICH3-M (2/2)

VSS

D

E11

K18

P18

V10

VCCCORE0

VCCCORE1K6VCCCORE2

IDE

Interface

VCCCORE3P6VCCCORE4

V14

IDE_PDCS1#
IDE_PDCS3#

VCCCORE5

VCCCORE6

IDE_SDCS1#
IDE_SDCS3#

IDE_PDA0
IDE_PDA1
IDE_PDA2
IDE_SDA0
IDE_SDA1
IDE_SDA2

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8

IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

IDE_SDD0

IDE_SDD1

IDE_SDD2

IDE_SDD3

IDE_SDD4

IDE_SDD5

IDE_SDD6

IDE_SDD7

IDE_SDD8

IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

IDE_PDDACK#
IDE_SDDACK#

IDE_PDDREQ
IDE_SDDREQ

IDE_PDIOR#

IDE_SDIOR#
IDE_PDIOW#
IDE_SDIOW#
IDE_PIORDY
IDE_SIORDY

AC15
AB15
AC21
AC22

AA14
AC14
AA15
AC20
AA19
AB20

W12
AB11
AA10
AC10
W11
Y9
AB9
AA9
AC9
Y10
W9
Y11
AB10
AC11
AA11
AC12

Y17
W17
AC17
AB16
W16
Y14
AA13
W15
W13
Y16
Y15
AC16
AB17
AA17
Y18
AC18

Y13
Y19
AB12
AB18
AC13
AC19
Y12
AA18
AB13
AB19

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11

IDE_SDD13
IDE_SDD14
IDE_SDD15

J18

M14

R18

T18

VCCPHL0

VCCPHL1

VCCPHL2

VCCPHL3

E

IDE_PDCS1# 19
IDE_PDCS3# 19
IDE_SDCS1# 29
IDE_SDCS3# 29

IDE_PDA0 19
IDE_PDA1 19
IDE_PDA2 19
IDE_SDA0 29
IDE_SDA1 29
IDE_SDA2 29
IDE_PDD[0..15] 19

IDE_SDD[0..15] 29

IDE_PDDACK# 19
IDE_SDDACK# 29
IDE_PDDREQ 19
IDE_SDDREQ 29
IDE_PDIOR# 19
IDE_SDIOR# 29
IDE_PDIOW# 19
IDE_SDIOW# 29
IDE_PIORDY 19
IDE_SIORDY 29

VSS35

VSS36

VSS37

VSS38

VSS39

VSS40

VSS41G3VSS42

VSS43

VSS44

VSS45J5VSS46

VSS47

VSS48

VSS49

VSS50

VSS51

VSS52L3VSS53

VSS54

VSS55

VSS56

VSS57

VSS58

VSS59

VSS60

VSS61

VSS62

VSS63

VSS64

VSS65N5VSS66

VSS67

VSS68

VSS69

VSS70

VSS71

VSS72

VSS73

VSS74

VSS75

VSS76

VSS77R3VSS78R5VSS79

VSS80

VSS81T4VSS82

VSS83

VSS84V3VSS85

VSS86

VSS87W6VSS88W7VSS89

VSS90

VSS91

VSS92

VSS93Y8VSS94

VSS95

VSS96

VSS97

VSS98

VSS99

VSS100

4 4

ACIN37

D32 RB751V

A

21

R295
100K

+3VS

12

ICH_ACIN

ICH3-M

L10

L11

L12

L13

L14

L21

F22

E14

E15

E18

E19

E20

B

G20

H19

K11

K13

K20

K21

K22

AA22

K23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

L23

M11

M12

M13

M20

M22

N10

C

N11

N12

N13

N14

N21

N23

P11

P13

P20

P22

R21

R23

T20

T22

V20

AC23

W10

W14

W18

W22

AA3

AA8

VSS101

AB8

AC1

AC8

AA12

AA16

AA20

COMPAL ELECTRONICS, INC

Title

Size Document Number Rev
Custom

D

Date: Sheet

SCHEMATIC, M/B LA -1331

401207

星期四

18, 2004

三月

E

2A

17 83,

of

A

B

C

D

E

+3VS PULL-UP/BY-PASS

RP12

FRAME#16,20,21,22,27,28

IRDY#16,20,21,22,27,28

TRDY#16,20,21,22,27,28

STOP#16,20,21,22,27,28

1 1

PCI_REQA#16
REQ#016,21

REQ#116,27

GNT#116,27

PIRQD#16,27,28

INT_IRQ1416,19

+3VALW PULL-UP

2 2

1
2
3
4
5

+3VS +3VS

+3VS

10P8R_8.2K

RP19

1
2
3
4
5

10P8R_8.2K

RP13

1
2
3
4
5

10P8R_8.2K

+3VS+3VS

10
9
8
7
6

10
9
8
7
6

+3VS

10
9
8
7
6

SERR# 16 ,20,22,27
DEVSEL# 16,20,21,22,27,28
PERR# 16 ,2 0,21,22,27
PLOCK# 16,22

REQ#2 16,22PCI_REQB#16
REQ#3 16,20
REQ#4 16,27
INT_SERIRQ 16,22,24,32

INT_IRQ15 16,29GNT#216,22
PIRQA# 14 , 16,21,22
PIRQB# 1 6,20,22
PIRQC# 16,27,28

+3V PULL-UP/BY-PASS

+3VALW

*

SMLINK016
SMLINK116

SMB_ALERT#16

3 3

ON/OFF32,34

PBTN_OUT#

ON/OFF

1 2

R250 4.7K

1 2

R246 4.7K

1 2

R263 10K

1 2

R466 0

*

1 2

R468 @0

*

PBTN#

*

+3VALW

+1.8SV BY-PASS +V 1. 8S_ICHLAN BY-PASS

PBTN# 16PBTN_OUT#32

+1.8VS

+

SMB_DATA13,16

SMB_CLK13,16

12

C241
150UF_6.3V_D2

+3VS

12

+

C269
22UF_16V_1206

R46 4.7K

R45 4.7K

12

12

C67
.1UF

12

+

C287
22UF_16V_1206

FWH_WP#17
FWH_TBL#17

PM_CLKRUN#16,22,24,27,28,32

LPC_DRQ#016,32
LPC_DRQ#116,24

PAR16,20,21,22,27,28

1 2

1 2

12

47PF

.1UF

12

12

C35
.1UF

R57 @100

1 2

12

12

C78

C61

.1UF

47PF

12

C31
C32
.1UF

47PF

RP22

1 8
2 7
3 6
4 5

8P4R_10K

1 2

R32 10K

1 2

R40 10K

+3V

12

C80
.1UF

12

C81
.1UF

12

C34
.1UF

+3V

12

+

C267

22UF_16V_1206

12

C40
.1UF

12

+3VS

+3VS

+V1.8_ICHLAN

C41
47PF

12

C42
.1UF

12

C63
47PF

12

C75
.1UF

GNT#016,21
GNT#316,20
GNT#416,27

12

C50
.1UF

12

12

C70

C76

.1UF

.1UF

12

C71
47PF

12

12

C82

C84

.1UF

.1UF

1 2

R41 8.2K

1 2

R47 8.2K

1 2

R42 8.2K

12

12

C130
.1UF

12

C60
.1UF

C131
47PF

+3VS

+RTCVCC PULL-UP

12

12

C355
.1UF

C354
.1UF

12

12

C357
.1UF

C356
47PF

SM_INTRUDER#16

1 2

R256 100K

+RTCVCC

+V5S_ICHREF BY-PASS

+V5S_ICHREF

C54
.1UFC36

C47
.1UFC77

C39
.1UF

12

+

C321

1UF_10V_0603

12

C33
.1UF

12

C48
.1UF

RP135

EC_SWI#32

EC_SMI#32
EC_SCI#32

EC_LID_OUT#32

4 4

EC_SWI#
EC_SMI#
EC_SCI#
EC_LID_OUT#

A

*

4 5
3 6
2 7
1 8

8P4R_0

ICH_RI#
ECSMI#
ECSCI#
LID#

ICH_RI# 16
ECSMI# 16
ECSCI# 16
LID# 16

+CPU_CORE BY-PASS

+CPU_CORE

+V3A_ICH

C74

C66

C46

C51

C85

C53

.1UF

.1UF

.1UF

.1UF

.01UF

.01UF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF

B

C

*

12

+

C376
1UF_10V_0603

12

C83
.1UF

D

12

C88
.1UF

+1.8VA_ICH BY-PASS+V3A_ICH BY-PASS

+1.8VA_ICH

12

+

C389

22UF_16V_1206

COMPAL ELECTRONICS, INC

Title

SCHEMATIC, M/B LA-1331

Size Document Number Rev
Custom

401207

Date: Sheet of

星期四

18, 2004

三月

12

12

C396
.1UF

18 83,

E

C397
.1UF

12

C398
.1UF

2A

+5VS

IDE,CD-ROM Module CONN.

C89

IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

PCSEL

1 2

*

+5VS

CD_AGND
CDD8
CDD9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15
CD_DREQ

EXTID0
EXTID1
EXTID2
HDSEL#

WGATE#

FDDIR#
3MODE#

INDEX#

C145
10UF_16V_1206

12

1 2

R73 470

W=80mils

12

C90

C379
10UF_16V_1206

IDE_PDD[0..15]17

IDE_PDDREQ17

IDE_PDIOW#17

IDE_PDIOR#17
IDE_PIORDY17
IDE_PDDACK#17

INT_IRQ1416,18
IDE_PDA117
IDE_PDA017
IDE_PDCS1#17 IDE_PDCS3# 17
PHDD_LED#33

1 2

+5VS

R89 100K

1 2

+5VMOD

R155 100K

CD_RSTDRV#29

CD_SIORDY29

SHDD_LED#33

+5VS

RP2

DSKCHG#

18

INDEX#

27

WP#

36

TRACK0#

45

8P4R_1K

+5VS

DRV0#

RP1

6
7
8
9

10

10P8R_1K

EXTCSEL

1 2

R235 1K

WDATA#
WGATE#
HDSEL#
FDDIR#

1 2

R154 470

IDE_PDD[0..15]

PIDE_RST#
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

IDE_PDDREQ

IDE_PIORDY
INT_IRQ14

+5VS

SHDD_LED#

5
4
3
2
1

CDD[0..15]

CD_AGND
CD_RSTDRV#
CDD7
CDD6
CDD5
CDD4
CDD3
CDD2
CDD1
CDD0

CD_SIORDY
CD_IRQ

SHDD_LED#
EXTCSEL

RDATA#
WP#
TRACK0#
WDATA#
STEP#
MTR0#
DSKCHG#
DRV0#

STEP#
MTR0#
RDATA#

CDD[0..15]29

INT_CD_L30 INT_CD_R 30
CD_AGND30

CD_SIOW#29

CD_IRQ29
CD_SBA129
CD_SBA029

CD_SCS1#29

RDATA#24

WP#24

TRACK0#24

WDATA#24

STEP#24

MTR0#24

DSKCHG#24

DRV0#24,33

1000PF

Place component's closely IDE CONN.

JP7

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44

HDD 44P SUYIN 20225A-44G5-A

JP17

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60

HEADER 2X30

+3VALW

1 8
2 7
3 6
4 5

+5VMOD

+5VS

RP3

8P4R_100K

12

C93

1UF_25V_0805

R302 @10K

EXTID0
EXTID1
EXTID2

12

C148
1000PF

Place compo nent's c losely CD-ROM CO NN.

.1UF

IDE_PDA2 17

CD_DREQ 29
CD_SIOR# 29
CD_DACK# 29
CD_SBA2 29
CD_SCS3# 29
EXTID0 33
EXTID1 33
EXTID2 33
HDSEL# 24

WGATE# 24

FDDIR# 24
3MODE# 24

INDEX# 24

+5VMOD

12

C149
1UF_25V_0805

12

C147
.1UF

+5VS

12

12

*

+3VS

+5VMOD

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF T

HDD Manual ATA Type Selection:

ATA33 : populate R31, de- populate R33.
ATA66/100 : populate R33, de-populate R31.

R31

@10K

IDE_PATADET 16

R33
@10K

*

1 2

1 2

IDE_PDD7

CDD7

IDE_PIORDY

CD_SIORDY

1 2

R61 @10K

1 2

R407 10K

R76 4.7K

R406 4.7K

EXTIDEPWR#33

SIDEPWR16

*

1 2

R69 @5.6K

1 2

R141 5.6K

*

ICH_IDE_SRST#17

R398 1K

G1

IDE_PDDREQ

CD_DREQ

ICH_IDE_PRST#17

+5VCD

+12VALW

D1 S1

61

2

PCIRST#7 ,1 4 ,1 6 , 20 , 2 1,22,23,24,27,28,34

Q37A

SI1906DL

C113

1 2

.1UF

PCIRST#

PCIRST#

1
2

Q8
SI3456DV

6
5
2
1

R152

12

100K

47K

2

47K

+5VS

C114

1 2

.1UF

5

1
2

3

+5VS

U10

5

4

3

7SH08FU

Title

SCHEMATIC, M/B LA-1331

Size Document Number Rev

B

401207

Date: Sheet of

星期四

+5VMOD

4

3

1

3

U9

7SH08FU

Q36
DTC144EKA

4

12

C137

+

4.7UF_16V_1206

<1st Part Field>

12

PIDE_RST#

12

R150
1K

D2

34

EXTIDE_EN#

5

G2

Q37B

S2

C140
.01UF

SI3456DV: N CHANNEL
VGS: 4.5V, RDS: 65 mOHM
Id(MAX): 5.1A
VGS,+-20V

SIDE_RST# 29

SI1906DL

COMPAL ELECTRONICS, INC

18, 2004

三月

19 83,

2A

5

4

3

2

1

+3V

AVDD-1

AVDD-2

AVDD-3

12

VCTRL

VDD25

AUX

EECS

EESK

EEDI

EEDO

AD0
AD1

GND

AD2
AD3

VDD25

VDD
AD4
AD5
AD6

VDD25

VDD
AD7

CBE0B

GND

RTL8100-B(L)

RX+

RX-

CT
NC
NC
CT

TX-

C233

0.1UF

U4

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

16
15
14
13
12
11
10
9

D D

* ***

+3VS

C C

+3VLAN

+2.5VLAN

12

12

R227
@22

C246
@10PF

12

C10

0.1UF

AD17

5

12

C274

0.1UF

B B

CLK_PCI_LAN

A A

PIRQB#16,18,22

PCIRST#7 ,1 4 ,1 6 , 19 , 2 1,22,23,24,27,28,34

CBRST#14,22,23,27,28

1 2

R243 100

AD[0..31]16,21,22,27,28

2 1

D43
RB751V

CLK_PCI_LAN13

GNT#316,18

REQ#316,18

C/BE#316,21,22,27,28

1 2

R208 1K

1 2

R23 0

1 2

R22 @0

*

AD[0..31]

CLK_PCI_LAN

AD31
AD30

AD29
AD28

AD27
AD26
AD25
AD24

AD23

C/BE#216,21,22,27,28

FRAME#16,18,21,22,27,28

IRDY#16,18,21,22,27,28

TRDY#16,18,21,22,27,28

DEVSEL#16,18,21,22,27,28

STOP#16,18,21,22,27,28
PERR#16, 18,21,22,27
SERR#16,18,22,27

C/BE#116,21,22,27,28

R14
50

R205
15K

LAN_PME#32

LAN_RD­LAN_RD+

LAN_TD­LAN_TD+

12

5.6K_1%

12

R204

*

ACTIVITY#

LINK10_100#

67

71

74

75

70

73

78

76

79

77

NC

LED2

AVDD

AVDD25

ISOLATEB

AD20

AD21

AD19

12

R12
50

PROPRIETARY NOTE

GND

AD18

AD17

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

PAR16,18,21,22,27,28

12

12

R15
50

12

C8

0.1UF

LED080LED1

INTAB
RSTB
CLK
GNTB
REQB
AD31
AD30
GND
AD29
VDD
AD28
AD27
AD26
AD25
AD24
VDD25
VDD
CBE3B
IDSEL
AD23

AD221GND2AD213AD204AD195VDD6VDD257AD188AD179AD1610CBE2B11FRAMEB12IRDYB13TRDYB14DEVSELB15GND16STOPB17PERRB18SERRB19PAR20CBE1B21VDD22AD1523AD1424AD1325AD1226AD1127AD1028AD929AD8

AD22

1 2

C11 0.1UF

4

66

69

68

72

GND

TXD-

TXD+

RXIN-

AVDD

RXIN+

AVDD25

DEVSEL#

TRDY#

AD16

IRDY#

FRAME#

C/BE#2

LAN_RD+
LAN_RD-

LAN_TD+
LAN_TD-

12

R13
50

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

65

RTSET

STOP#

C13

0.1UF

63

RTT264RTT3

PERR#

SERR#

62

GND

PAR

X161X2

12

59

60

AVDD

12

***

58

AVDD25

AD15

C264

0.1UF

57

AD14

LAN_X1
LAN_X2

+2.5VLAN

51

56

52

55

NC54NC53NC

GND

PMEB

VCTRL

30

AD9

AD12

AD8

AD10

AD11

AD13

+3VLAN

Layout Note
The H0013 pls close to JP5

U18

1

RD+

2

RD-

3

CT

4

NC

5

NC

6

CT
TD+7TX+

8

TD-

Pulse H0013

3

1 2

12

C218

0.1UF

R175

75

L23 0

AUX

AD0
AD1

AD2
AD3

AD4
AD5
AD6

AD7

12

12

C235

0.1UF

***

+3V

12

+2.5VLAN

R207

5.6K

LAN_EECS
LAN_EECLK
LAN_EEDI
LAN_EEDO

RJ45_RX+
RJ45_RX-

RJ45_TX+
RJ45_TX-

12

R174
75

LAN_GND

1 2

L32 4.7UH

1 2

L31 4.7UH

1 2

L30 4.7UH

12

C234

0.1UF

+3VLAN

LAN_X1 LAN_X2

12

C237
18PF

U3

1

CS

VCC

2

SK

3
4

C255

4.7UF_10V_1206

NC

DI

NC

DO

GND

9346

C/BE#0 16,21,22,27,28

ACTIVITY#

Q14

DTA114YKA

LINK10_100#

2

2

Y2
25 MHz

8
7
6
5

B

C224

4.7UF_10V_1206

12

C236

12

18PF

+3V

12

C15

0.1UF

C

10K

47K

E

3 1

+3V

1 2

C

10K

B

47K

E

Q16
DTA114YKA

3 1

+3V

2

C254

0.1UF

12

C260

0.1UF

R179
510_0603

1 2

RJ45_RX-

RJ45_RX+
RJ45_TX­RJ45_TX+

R167

510_0603

R165

75

Termination plane should be copled to chassis ground

Title

Size Document Number Rev

B

Date: Sheet of

+3VLAN To +2.5VLAN Transfer

+3VLAN

Q15

31

2

12

C213
@ 0.1UF

12

12

C180

12

C275

0.1UF

12

C271

0.1UF

JP5

12

Amber LED+

11

Amber LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

AMP RJ45/RJ11 with LED

C181

0.1UF

C252

1000PF

C262

1000PF

12

12

12

C273

1000PF

12

C248

1000PF

12

R166
75

LAN_GND

VCTRL

@ 2SB1197K

1000P_2KV_1206

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA -1331

18, 2004

三月

401207

1

星期四

+2.5VLAN

C214
@ 10UF_10V_1206

+3VLAN

R228 0_1206

12

C253

+2.5VLAN

12

C272

SHLD4
SHLD3

SHLD2
SHLD1

LANGND

12

C187

4.7UF_10V_0805

20 83,

1 2

0.1UF

1 2

R189 0_1206

0.1UF

16
15

14
13

+3V

+2.5V

2A

A

B

C

D

E

IEEE1394 Controller/PHY

1 1

12

C612
.1UF

VCC

WC#

SCL

1 2

L52 0

1 2

L53 0

1 2

L54 0

1 2

L55 0

8
7
6
5

*
*
*
*

+3VS

12

C611
.1UF

+3VS

EECK_LAN
EEDI_LAN

12

R439
510

JP12

4

4

3

3

2

2

1

1

Molex SD-54030-0411

X4

12

12

12

12

12

12

C533
.1UF

R410

56.2_1%

R408

56.2_1%

R418

5.11K

12

C599
.1UF

U44

1

A0

2

A1

3

A2
GND4SDA

24C02-27

12

C489
1UF_25V_0805

12

C504

.1UF

Enable I2C EEPROM

R438 2K

C512

C517

.1UF

.1UF

57

53

56

52

55

59

58

61

60

XI

XO

VDDATX0

GNDATX0

AD25

AD24

CBE3#

IDSEL

106

107

108

109

AD24

AD23

AD25

PHYRESET

LREQ/TSOJMP

LINKON/TSIJMP

AD23

AD22

VSS3

AD21

110

111

112

AD22

AD21

113

CTL0/PC0JMP54CTL1/PC1JMP

VDD2

114

D7/PC2JMP

D6/CMCJMP

VDDC1

VSSC1

115

51

116

AD20

D5

AD20

50

PGND2

AD19

117

AD19

49

PVDD2

AD18

118

AD18

C520
.1UF

41

43

39

48

AD17

119

120

AD16

AD17

40

D044D145D246D347D4

SCLK

PVDD1

PGND1

MODE142MODE0

CBE2#

122

STOP#

FRAME#

IRDY#

VDD3

TRDY#

DEVSEL#

128

123

124

125

126

127

AD16

VSS4

121

LPS/CMC

PME#
VSSC2
VDDC2

VSS9

VDD6

SCL/EECK

SDA/EEDI

EEDO

EECS

AD0
AD1

VSS8

RAMVSS

RAMVDD

AD2
AD3
AD4

VDD5

AD5
AD6
AD7

VSS7

CBE0#

AD8

AD9
AD10
AD11
AD12
VSS6

VDD4

AD13
AD14
AD15

CBE1#

PAR

PERR#

VSS5

1394 VT6306

+3VS

+3VS

U45

38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

AD0
AD1

AD2
AD3
AD4

AD5
AD6
AD7

AD8
AD9
AD10
AD11
AD12

AD13

+3VS

R436

1K

R426

1K

C513
47PF

PIRQA#14,16,18,22

PCIRST#7,14,16,19,20,22,23,24,27,28,34

CLK_PCI_139413

GNT#016,18

REQ#016,18

33

22PF

AD[0..31]

R442

6.34K 1%

AD[0..31]16,20,22,27,28

2 2

3 3

CLK_PCI_1394

12

R449

12

C600

+3VS

C590

.1UF

C597

.1UF

C603

.1UF

XTPB0­XTPB0+ EECK_LAN
XTPA0- EEDI _ LAN
XTPA0+
XTPBIAS0

C610

.1UF

CLK_PCI_1394

AD31 AD14
AD30 AD15
AD29
AD28
AD27

C507
10PF

24.576MHz

R437

C506

1M_0402

10PF_0402

C503

.1UF

62

64

63

XCPS

65

VDDARX0

66

XREXT

67

NC

68

GNDARX1

69

GNDATX1

70

XTPB0M

71

XTPB0P

72

XTPA0M

73

XTPA0P

74

XTPBIAS0

75

VDDARX1

76

VDDATX1

77

XTPB1M

78

XTPB1P

79

XTPA1M

80

XTPA1P

81

XTPBIAS1

82

GNDARX2

83

GNDATX2

84

XTPB2M

85

XTPB2P

86

XTPA2M

87

XTPA2P

88

XTPBIAS2

89

VDDARX2

90

VDDATX2

91

INTA#

92

PCIRST#

93

PCICLK

94

VSS1

95

GNT#

96

REQ#

97

AD31

98

AD30

99

AD29

100

AD28

101

AD27

102

VDD1

GNDARX0

VSS2

AD26

103

104

105

AD26

12

C508
.1UF

1394_PME# 32

1/20 EECK,EEDI RENAMED TO EECK_LAN,EEDI_LAN

C/BE#0 16,20,22,27,28

C/BE#1 16,20,22,27,28
PAR 16,18,20,22,27,28
PERR# 16,18,20,22,27

C509
.1UF

12

C514
.1UF

XTPBIAS0
XTPA0+

XTPA0-

XTPB0+

XTPB0-

C515
.1UF

R409

56.2_1%

C487

220PF

12

12

12

C525
.1UF

R411

56.2_1%

STOP# 16,18,20,22,27,28

C/BE#316,20,22,27,28

AD16

4 4

1 2

R452 100

DEVSEL# 16,18,20,2 2, 2 7, 2 8
TRDY# 16,18,20,22,27,28
IRDY# 16,18,20,22,27,28
FRAME# 16,18,20,22,27,28
C/BE#2 16,20,22,27,28

@X3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPE

A

B

C

D

Title

Size Document Number Rev

Custom

Date: Sheet

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA-1331

星期四 三月

401207

E

2A

of

21 83, 18, 2004

A

CardBus Controller
OZ6933T (uBGA)

1 1

AD[0..31]16,20,21,27,28

S1_IOWR#
S1_IORD#
S1_OE#
S1_CE2#

2 2

3 3

CLK_PCI_CB

R450
@33

1 2

C604
@10PF

S1_IOWR# 23
S1_IORD# 23
S1_OE# 23
S1_CE2# 23

C/BE#316,20,21,27,28
C/BE#216,20,21,27,28
C/BE#116,20,21,27,28
C/BE#016,20,21,27,28

CLK_PCI_CB13

DEVSEL#16,18,20,21,27,28

FRAME#16,18,20,21,27,28

IRDY#16,18,20,21,27,28

TRDY#16,18,20,21,27,28

STOP#16,18,20,21,27,28

PAR16,18,20,21,27,28
PERR#16,18,20,21,27
SERR#16,18,20,27
REQ#216,18

GNT#216,18

PIRQA#14,16,18,21

PIRQB#16,18,20

PLOCK#16,18

PCIRST#7,14,16,19,20,21,23,24,27,28,34

PCM_PME#32

PM_CLKRUN#16,18,24,27,28,32

PCM_RI#28

PCM_SPK#31
PCM1_LED33

PCM2_LED33

INT_SERIRQ16,18,24,32

R451 100

AD20

1 2

CLK_PCI_CB

CardBus-OZ6933T-1

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

B

C617
.1UF

U49

E1

AD31

E2

AD30

F3

AD29

F1

AD28

G5

AD27

H6

AD26

G3

AD25

G2

AD24

H2

AD23

H1

AD22

J1

AD21

J2

AD20

J3

AD19

J6

AD18

K1

AD17

K2

AD16

M5

AD15

N2

AD14

N1

AD13

N3

AD12

N6

AD11

P1

AD10

P3

AD9

N5

AD8

P6

AD7

R2

AD6

R3

AD5

T1

AD4

W4

AD3

R6

AD2

U5

AD1

P7

AD0

G1

C/BE3#

K3

C/BE2#

M3

C/BE1#

R1

C/BE0#

H5

IDSEL

E3

PCI_CLK

L3

DEVSEL#

K6

FRAME#

L1

IRDY#

L2

TRDY#

L5

STOP#

M2

PAR

L6

PERR#

M1

SERR#

G6

PCI_REQ#

F5

PCI_GNT#

B5

IRQ9/INTA#

F6

IRQ4/INTB#

V5

LOCK#

D1

RST#

B14

IRQ12/PME#

A4

IRQ14/CLKRUN#

V9

IRQ15/RING_OUT

K19

SPKR_OUT#

J19

LED_OUT/SKT_ACTIVITY

E8

SKTB_ACTV

C5

IRQ5/SERIRQ

E6

IRQ7/SIN#/B_VPP_PGM

+3V

+3VS

+3VS

L15

AUX_VCC

2

CARDBUS CONTROLLER

PCI_VCCF2PCI_VCCJ5PCI_VCCM6PCI_VCC

MICROO

P5

R10

J18

B10

CORE_VCC

CORE_VCC

CORE_VCC

OZ6933 209PIN CSP

PCI

GNDH3GNDK5GNDP2GNDW5GND

GND

NCE5IRQ3/VCC3#

GND

V15

K18NCB15

E11

C

CBRST# 14,20,23,27,28

S1_A6

S1_A7

S1_A1

S1_A4

S1_A2

S1_A0

S1_A3

S1_D0

N17

P18

R19

N14

R17

M17

A_A0/CAD26

A_A1/CAD25

A_A2/CAD24

A_A3/CAD23

A_A4/CAD22

A_D8/CAD28

A_D0/CAD27

B_D10/CAD31

B_D9/CAD30A6B_D1/CAD29B7B_D8/CAD28C7B_D0/CAD27A7B_A0/CAD26B8B_A1/CAD25A8B_A2/CAD24E9B_A3/CAD23B9B_A4/CAD22

S1_A5

T19

R14

A_A5/CAD21

S1_D10

S1_D1

S1_D8

S1_D9

N18

W12

GRST#

SCLK/A_VCC_5#

K14

L18

M19

M18

M15

A_D9/CAD30

A_D1/CAD29

A_D10/CAD31

SDATA/B_VCC_3#

SLATCH/B_VCC_5#

IRQ9/A_VPP_VCC

IRQ10/B_VPP_VCC

B6

F19

K15

K17

P19

S1_IORD#

S1_IOWR#

S1_A9

S1_A25

U15

A_A6/CAD20

A_A25/CAD19

S1_A17

S1_A24

P14

W15

U11

A_A7/CAD18

A_A24/CAD17

A_A17/CAD16

P10

A_IOWR/CAD15

U10

W11

A_A9/CAD14

A_IORD#/CAD13

S1_OE#

S1_A11

V10

P9

A_A11/CAD12

Slot
A

Slot B

B_A5/CAD21

B_A6/CAD20

B_A25/CAD19

B_A7/CAD18

B_A24/CAD17

B_A17/CAD16

B_IOWR#/CAD15

F10

F11

E10

F15

B11

A11

E14

C11

D19

S1_CE2#

S1_D15

S1_D7

S1_A10

U9

U8

R9

W9

A_D7/CAD7

A_A10/CAD9

A_D15/CAD8

A_OE#/CAD11

A_CE2#/CAD10

B_A9/CAD14

B_IORD#/CAD13

B_A11/CAD12

B_OE#/CAD11

B_CE2#/CAD10

F14

E17

E19

G15

S1_D13

S1_D12

S1_D6

W7

R8

V7

A_D6/CAD5

A_D13/CAD6

A_D12/CAD4

B_A10/CAD9

B_D15/CAD8

B_D7/CAD7

F18

F17

G18

S1_D11

S1_D3

S1_D5

S1_D4

U7

W6

A_D5/CAD3

A_D4/CAD1P8A_D3/CAD0

A_D11/CAD2

B_D13/CAD6

B_D6/CAD5

B_D12/CAD4

H15

H14

H17

U6

B_D5/CAD3

B_D11/CAD2

J14

H18

H19

B_D4/CAD1

A_SOCKET_VCC
A_SOCKET_VCC

A_REG#/CCBE3#

A_CE1#/CCBE0#

A_A23/CFRAME#

A_A21/CDEVSEL#

A_WAIT#/CSERR#

A_INPACK#/CREQ#

A_RDY_IRQ#/CINT#

A_A19/CBLOCK#

A_WP/CCLKRUN#

A_RST/CRESET#

A_BVD2/CAUDIO

A_BVD1/CSTSCHG
B_BVD1/CSTSCHG

B_BVD2/CAUDIO

B_RESET/CRESET#

B_WP/CCLKRUN#

B_A19/CBLOCK#

B_RDY_IRQ#/CINT#

B_INPACK#/CREQ#

B_WAIT#/CSERR#

B_A21/CDEVSEL#

B_A23/CFRAME#

B_CE1#/CCBE0#

B_REG#/CCBE3#

B_D3/CAD0

J17

A_A12/CCBE2#

A_A8/CCBE1#

A_A16/CCLK

A_A15/CIRDY#

A_A22/CTRDY#
A_A20/CSTOP#

A_A13/CPAR

A_A14/CPERR

A_WE#/CGNT#

A_D2/RFU
A_D14/RFU
A_A18/RFU

A_VS1/CVS1

A_VS2/CVS2
A_CD1#/CCD1#
A_CD2#/CCD2#

B_CD2#/CCD2#
B_CD1#/CCD1#

B_VS2/CVS2

B_VS1/CVS1

B_A18/RFU
B_D14/RFU

B_D2/RFU

B_WE#/CGNT#

B_A14/CPERR#

B_A13/CPAR
B_A20/CSTOP#

B_A22/CTRDY#

B_A15/CIRDY#

B_A16/CCLK

B_A8/CCBE1#

B_A12/CCBE2#

B_SKT_VCC

B_SKT_VCC

B_SKT_VCC

D

R7
R13

N15
V14
V11
W8

V13
U14
P13
W14
U13
W13
R11
V12
R18
P17
R12
P12
U12
L17
P15
L19
V8
P11
W10
W16
V6
L14
M14
N19

F8
C8
C6
J15
A10
E18
C14
G17
F7
C10
A5
A14
F12
E13
C9
A9
A15
C15
C13
B13
A13
C12
B12
E12

G14
A16
A12
F9

G19
F13
E7

C632
.1UF

S1_A12
S1_A8

R457

1 2

S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A13
S1_A14

S1_A19

S1_D2
S1_D14
S1_A18

S2_A18
S2_D14
S2_D2

S2_A19

S2_A14
S2_A13
S2_A20
S2_A21
S2_A22
S2_A15
S2_A23

R446 33

S2_A8
S2_A12

+S2_VCC

C537
.1UF

33

1 2

C535
.1UF

+3VS

+3VS

+S1_VCC

C633
.1UF

S1_REG# 23

S1_CE1# 23

S1_A16

S1_WAIT# 23
S1_INPACK# 23

S1_WE# 23

S1_RDY# 23

S1_WP 23
S1_RST 23

S1_VS1 23
S1_VS2 23

S1_CD1# 23
S1_CD2# 23
S1_BVD2 23
S1_BVD1 23

S2_BVD1 23
S2_BVD2 23
S2_CD2# 23

S2_CD1# 23
S2_VS2 23
S2_VS1 23

S2_RST 23
S2_WP 23

S2_RDY# 23
S2_WE# 23

S2_INPACK# 23

S2_WAIT# 23

S2_A16

S2_CE1# 23

S2_REG# 23

C536
.1UF

C634
.1UF

12

C616

4.7UF_10V_0805

C626
.1UF

C631
.1UF

S1_A[0..25]

S2_A[0..25]
S2_D[0..15]

E

C607
.1UF

C620
.1UF

C630
.1UF

S1_A[0..25] 23
S1_D[0..15] 23

S2_A[0..25] 23
S2_D[0..15] 23

C622
.1UF

C534
.1UF

S2_A0

S2_A1

S2_A2

S2_A3

S2_A4

S2_A5

S2_A6

S2_A7

S2_A9

S2_D15

S2_D13

S2_D12

S2_D10

S2_D9

S2_D1

S2_D8

S2_D0

SLATCH 23
SLDATA 23
RTCCLK 16,23,28

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE

A

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

S2_A25

S2_A17

S2_A11

S2_A24

C

S2_A10

S2_D7

S2_CE2#
S2_OE#
S2_IORD#
S2_IOWR#

S2_D6

S2_D5

S2_D11

S2_D3

S2_D4

S2_CE2# 23
S2_OE# 23
S2_IORD# 23
S2_IOWR# 23

COMPAL ELECTRONICS, INC

Title

SCHEMATIC, M/B LA-1331

Size Document Number Rev
Custom

Date: Sheet

D

星期四 三月

401207

22 83, 18, 2004

E

2A

of

PCMCIA POWER CTRL.

+5V

+12V

+3V

C176
1UF_25V_0805

1 2

C177

1 2

.1UF
C179

1 2

.1UF

C178

1 2

.1UF

C170

1 2

.1UF

C172

S1_A[0..25]22
S1_D[0..15]22
S2_A[0..25]22
S2_D[0..15]22

+S2_VPP

+S1_VPP

C529
10UF_16V_1206

C587
10UF_16V_1206

1 2
1 2

.1UF
.1UF

+3V

12

12

C171

OCCB#33

C523

.01UF

C524

.01UF

1 2

R162
100K

S1_A[0..25]
S1_D[0..15]
S2_A[0..25]
S2_D[0..15]

W=30mils

W=30mils

12

C528

56PF

12

C530

56PF

12

12

12

C531

.1UF

C527

.1UF

SLDATA22
SLATCH22

RTCCLK16,22,28

12

C521

1UF_25V_0805

C522

1UF_25V_0805

+S1_VCC

12

C526

1000PF

+S2_VCC

12

C532

1000PF

U15

25

VCC_5V

7

12V

24

12V

1

5V

2

5V

30

5V

15

3.3V

16

3.3V

17

3.3V

3

DATA

5

LATCH

4

CLOCK

13

APWR_GOOD#

19

BPWR_GOOD#

18

OC#

TPS2206AI/TPS2216

PCIRST#7 ,1 4 ,1 6 , 19 , 2 0,21,22,24,27,28,34

G_RST#32

AVPP
AVCC
AVCC
AVCC

BVPP
BVCC
BVCC
BVCC

RESET

RESET#

GND

CARDBUS

+S1_VPP

8
9
10
11

+S2_VPP

23
20
21
22

6
14

26

NC

27

NC

28

NC

29

NC

12

12

C94
.1UF

W=40mils

12

C174

W=40mils

12

C175

CBRST#

+3V

2 3

+S1_VPP
+S1_VCC

4.7UF_10V_0805

+S2_VPP
+S2_VCC

4.7UF_10V_0805

U33A

1

147

74LVC125

+3V POWER

S1_CD2#22

S1_WP22

S1_BVD122

S1_BVD222
S1_REG#22

S1_INPACK#22

S1_WAIT#22

S1_RST22
S1_VS222

PCMRST# 33

1 2

R322 0

1 2

R318 @0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF T

CBRST#

+3V

12

R323
10K

CBRST# 14,20,22,27,28

S1_CD1#

@1000PF

S1_CD2#

@1000PF

S2_CD1#

@1000PF

S2_CD2#

@1000PF

+S1_VPP

+S1_VCC +S2_VCC

S1_RDY#22

S1_WE#22

S1_IOWR#22

S1_IORD#22

S1_VS122
S1_OE#22

S1_CE2#22

S1_CE1#22

S1_CD1#22

C625

1 2

C486

1 2

C624

1 2

C485

1 2

S1_CD2#
S1_WP

S1_D10
S1_D2
S1_D9
S1_D1
S1_D8
S1_D0
S1_BVD1

S1_A0
S1_BVD2
S1_A1
S1_REG#
S1_A2
S1_INPACK#
S1_A3

S1_WAIT#
S1_A4
S1_RST
S1_A5
S1_VS2
S1_A6
S1_A25

S1_A7
S1_A24
S1_A12
S1_A23
S1_A15
S1_A22

S1_A16

S1_A21
S1_RDY#
S1_A20
S1_WE#
S1_A19
S1_A14
S1_A18
S1_A13

S1_A17
S1_A8
S1_IOWR#
S1_A9
S1_IORD#

S1_A11
S1_VS1
S1_OE#
S1_CE2#
S1_A10

S1_D15
S1_CE1#
S1_D14
S1_D7
S1_D13
S1_D6

S1_D12 S2_D12
S1_D5
S1_D11

S1_D4

S1_CD1#

S1_D3

SOCKET

JP19

A77

a68

A76

a34

A75

a67

A74

a33

A73

GND

A72

a66

A71

a32

A70

a65

A69

a31

A68

a64

A67

a30

A66

a63

A65

GND

A64

a29

A63

a62

A62

a28

A61

a61

A60

a27

A59

a60

A58

a26

A57

GND

A56

a59

A55

a25

A54

a58

A53

a24

A52

a57

A51

a23

A50

a56

A49

GND

A48

a22

A47

a55

A46

a21

A45

a54

A44

a20

A43

a53

A42

GND

A41

a19

A40

a52

A39

a18

A38

a51

A37

a17

A36

a50

A35

a16

A34

a49

A33

a15

A32

a48

A31

a14

A30

a47

A29

a13

A28

GND

A27

a46

A26

a12

A25

a45

A24

a11

A23

a44

A22

GND

A21

a10

A20

a43

A19

a9

A18

a42

A17

a8

A16

GND

A15

a41

A14

a7

A13

a40

A12

a6

A11

a39

A10

a5

A9

GND

A8

a38

A7

a4

A6

a37

A5

a3

A4

a36

A3

a2

A2

a35

A1

a1

PCMC154PIN

Title

Size Document Number Rev

B

Date: Sheet of

B77

b68

B76

b34
b67
b33

GND

b66
b32
b65
b31
b64
b30
b63

GND

b29
b62
b28
b61
b27
b60
b26

GND

b59
b25
b58
b24
b57
b23
b56

GND

b22
b55
b21
b54
b20
b53

GND

b19
b52
b18
b51
b17
b50
b16
b49
b15
b48
b14
b47
b13

GND

b46
b12
b45
b11
b44

GND

b10
b43

b42

GND

b41
b40
b39

GND

b38
b37
b36
b35

b9
b8

b7
b6
b5

b4
b3
b2
b1

B75
B74
B73
B72
B71
B70
B69
B68
B67
B66
B65
B64
B63
B62
B61
B60
B59
B58
B57
B56
B55
B54
B53
B52
B51
B50
B49
B48
B47
B46
B45
B44
B43
B42
B41
B40
B39
B38
B37
B36
B35
B34
B33
B32
B31
B30
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1

S2_CD2#
S2_WP

S2_D10
S2_D2
S2_D9
S2_D1
S2_D8
S2_D0
S2_BVD1

S2_A0
S2_BVD2
S2_A1
S2_REG#
S2_A2
S2_INPACK#
S2_A3

S2_WAIT#
S2_A4
S2_RST
S2_A5
S2_VS2
S2_A6
S2_A25

S2_A7
S2_A24
S2_A12
S2_A23
S2_A15
S2_A22

S2_A16

S2_A21
S2_RDY#
S2_A20
S2_WE#
S2_A19
S2_A14
S2_A18
S2_A13

S2_A17
S2_A8
S2_IOWR#
S2_A9
S2_IORD#

S2_A11
S2_VS1
S2_OE#
S2_CE2#
S2_A10

S2_D15
S2_CE1#
S2_D14
S2_D7
S2_D13
S2_D6

S2_D5
S2_D11
S2_D4
S2_CD1#
S2_D3

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA -1331

401207

星期四

18, 2004

三月

S2_CD2# 22
S2_WP 22

S2_BVD1 22

S2_BVD2 22
S2_REG# 22

S2_INPACK# 22

S2_WAIT# 22
S2_RST 22
S2_VS2 22

+S2_VPP

S2_RDY# 22
S2_WE# 22

S2_IOWR# 22
S2_IORD# 22

S2_VS1 22
S2_OE# 22
S2_CE2# 22

S2_CE1# 22

S2_CD1# 22

23 83,

2A

A

SUPER I/O SMsC FDC47N227

1 1

B

C

.1UF

C276

1 2

PCIRST#7 ,1 4 ,1 6 , 19 , 2 0,21,22,23,27,28,34

LPCRST

1 2

R251
10K

+3V

D

U28

VCC5Y1

1

A1

3

C277
.1UF

A2

GND

NC7WZ14

12

LPCRST

6

4

Y2

2

D23

21

RB751V

1 2

R248 10K

LPC_RST#

E

+3VS

LPC_RST# 32

1 2

1 2

R211

@33

C232

@22PF

LPC_AD[0..3]

LPC_FRAME#16,32

LPC_DRQ#116,18

SUS_STAT#14,16,34

INT_SERIRQ16,18,22,32
PM_CLKRUN#16,18,22,27,28,32
CLK_LPC_SIO13

CLK_SIO1413

1 2

R177 10K

1 2

R178 10K

+3VS

+3VS

PID014
PID114
PID214
PID314

+3VS

C209

4.7UF_10V_0805

10V

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

1 2

R192 10K

CLK_LPC_SIO

CLK_SIO14

1 2

R3 10K

12

C230
.1UF

LPC_RST#

R233 10K

12

C257
.1UF

1 2

12

C208
.1UF

U24

20

LAD0

21

LAD1

22

LAD2

23

LAD3

24

LFRAME#

25

LDRQ#

26

PCIRST#

27

LPCPD#

50

GPIO12/IO_SMI#

17

IO_PME#

30

SIRQ

28

CLKRUN#

29

PCICLK

19

CLK14

48

GPIO10

54

GPIO15

55

GPIO16

56

GPIO17

57

GPIO20

58

GPIO21

59

GPIO22

6

GPIO24

32

GPIO30

33

GPIO31

34

GPIO32

35

GPIO33

36

GPIO34

37

GPIO35

38

GPIO36

39

GPIO37

40

GPIO40

41

GPIO41

42

GPIO42

43

GPIO43

44

GPIO44

45

GPIO45

46

GPIO46

47

GPIO47

51

GPIO13/IRQIN1

52

GPIO14/IRQIN2

64

GPIO23/FDC_PP

18

VTR

53

VCC

65

VCC

93

VCC

7

VSS

31

VSS

60

VSS

76

VSS

SMsC LPC47N227

PD0/INDEX#

PD1/TRK0

PD2/WRTPRT#

PD3/RDATA#

PD4/DSKCHG#

PD5

PD6/MTR0#

PD7

BUSY/MTR1#

PE/WDATA#

SLCT/WGATE#

ERROR#/HDSEL#

ACK#/DS1#

INIT#/DIR#

AUTOFD#/DRVDEN0#

STROBE#/DS0#
SLCTIN#/STEP#

DTR2#
CTS2#
RTS2#

DSR2#

TXD2

RXD2

DCD2#

RI2#

DTR1#
CTS1#
RTS1#

DSR1#

TXD1

RXD1

DCD1#

RI1#

IRMODE/IRRX3

IRRX2
IRTX2

RDATA#
WDATA#

WGATE#

HDSEL#

DIR#

STEP#

DS0#

INDEX#
DSKCHG#
WRTPRT#

TRK0#

MTR0#

DRVDEN0
DRVDEN1

GPIO11/SYSOPT

LPD0

68

LPD1

69

LPD2

70

LPD3

71

LPD4

72

LPD5

73

LPD6

74

LPD7

75

LPTBUSY

79

LPTPE

78

LPTSLCT

77

LPTERR#

81

LPTACK#

80
66
82
83
67

100

CTS#2

99
98

DSR#2

97
96
95

DCD#2

94

RI#2

92

DTR#1

89

CTS#1

88

RTS#1

87

DSR#1

86

TXD1

85

RXD1

84

DCD#1

91

RI#1

90
63

61
62

16
10
11
12
8
9
5
13
4
15
14
3
1

2
49

Base I/O Address

0 = 02Eh

*

1 = 04Eh

R206 1K

R197 1K

RDATA#
WDATA#
WGATE#

HDSEL#

FDDIR#

STEP#

DRV0#

INDEX#

DSKCHG#

WP#

TRACK0#

MTR0#

LPTBUSY 25
LPTPE 25
LPTSLCT 25
LPTERR# 25
LPTACK# 25
INIT# 25
LPTAFD# 25
LPTSTB# 25
SLCTIN# 25

1 2

1 2

R232 10K

1 2

R191 1K

IRMODE 25
IRRX 25
IRTXOUT 25

RDATA# 19
WDATA# 19
WGATE# 19
HDSEL# 19
FDDIR# 19
STEP# 19
DRV0# 19,33
INDEX# 19
DSKCHG# 19
WP# 19
TRACK0# 19
MTR0# 19
3MODE# 19

12

+5VS

LPD[0..7]

DCD#1
RI#1
CTS#1
DSR#1

LPD[0..7] 25

1 8
2 7
3 6
4 5

RP9

8P4R_4.7K

+3VS

CTS#2
DSR#2
DCD#2
RI#2

+5V

RXD128
TXD128

DSR#128

RTS#128
CTS#128

DTR#128

RI#128

DCD#128

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

1 8
2 7
3 6
4 5

RP10

8P4R_4.7K

JP24

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

@96212-1011S

+3VS

LPC_AD[0..3]16,32

2 2

3 3

CLK_SIO14

CLK_LPC_SIO

R234
10

1 2

C258

1 2

15PF

4 4

COMPAL ELECTRONICS, INC

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND

PROPRIETARY NOTE

A

B

TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

SCHEMATIC, M/B LA -1331

Size Document Number Rev

B

Date: Sheet

星期四

18, 2004

三月

401207

24 83,

E

of

2A

12

C188
1UF_0805

12

C1
100PF

+3VS

+5V_PRN

+5V_PRN

R163
47_1206

1 2

12

C4
.1UF

109876

12345

109876

12345

FIR Module

+IR_VCC

+IR_GND

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

RP4
10P8R_2.7K

+5V_PRN

AFD#/3M#
LPTERR#
LPTINIT#
LPTSLCTIN#

FD4
FD5
FD6
FD7

RP5
10P8R_2.7K

+5V_PRN

FD3
FD2
FD1
FD0

+3VS

1 2

R2 3.3_1206

12

C190

4.7UF_1206

12

R164 @ 10K

IRRX24

IRRX

U1

SD/Mode

Mode

1
3

Txd

5
7

2

IRED Cathode

4

Rxd

6

Vcc

8

GND

SD/MODE: SHUTDOWN MODE, HIGH ACTIVE
MODE: HIGH/LOW SPEED SELECT

IRED Anode

FIR TFDU6101E

1 2

R1 @3.3_1206

+IR_ANODE
IRTXOUT
IRMODE

+IR_ANODE

IRTXOUT 24
IRMODE 24

PARALLEL PORT

+5V_PRN

+5VS

LPTSTB#24

R172
33

R171
33

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

LPTINIT#

LPTSLCTIN#

RP7

8P4R_68

RP6

8P4R_68

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF T

INIT#24

SLCTIN#24

LPD[0..7]24

1 2

1 2

LPD0 FD0
LPD1 FD1
LPD2 FD2
LPD3 FD3

LPD7 FD7
LPD6 FD6
LPD5 FD5
LPD4 FD4

LPD[0..7]

LPTAFD#24

LPTERR#24

LPTACK#24
LPTBUSY24

LPTPE24

LPTSLCT24

LPTSTB#
AFD#/3M#

FD0
LPTERR#

LPTINIT#
FD2
LPTSLCTIN#
FD3

FD4
FD5
FD6
FD7
LPTACK#
LPTBUSY
LPTPE
LPTSLCT

RB420D

R169

R168

33

R170

C186

2.2K
220PF

33

1

14

2

15

3

16

4

17

5

18

6

19

7

20

8

JP4

21

9

LPTCN-25

22
10
23
11
24
12
25
13

Title

Size Document Number Rev

Date: Sheet of

COMPAL ELECTRONICS, INC

SCHEMATIC, M/B LA -1331
401207

星期四

18, 2004

三月

D3

2 1

AFD#/3M#
LPTERR#
LPTINIT#
LPTSLCTIN#

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

FD0
FD1
FD2
FD3FD1

FD4
FD5
FD6
FD7

CP2

1 8
2 7
3 6
4 5

8P4C_220PF
CP1

4 5
3 6
2 7
1 8

8P4C_220PF

CP4

1 8
2 7
3 6
4 5

8P4C_220PF

CP3

1 8
2 7
3 6
4 5

8P4C_220PF

25 83,

2A

USB PORT

+5V

USB_OC#017

F4

POLYSWITCH_0.75A

12

**

C408

1000PF

+USB_VCCA

12

12

R324

470K

R321

560K

12

C400
.1UF

USB_AGND

150UF_D2_6.3V

+C413

+5V

F2

POLYSWITCH_0.75A

USB_OC#317

+USB_VCCC

12

R176

470K

C204

1000PF

12

R180

560K

12

12

C195
.1UF

USB_CGND

150UF_D2_6.3V

+C199

L5

USB_PN017

USB_PP017

USB0_D­USB0_D+

FBM-11-160808-121

1 2
1 2

L4

FBM-11-160808-121

12

12

C96

C103

47PF

47PF

L38

CHB4516G750_1806

4516

12

12

JP9

1
2
3
4

SUYIN USB Connector 2569A-04G3T-B

C391
.1UF

+5V

USB_OC#117

USB_PN317

USB_PP317

F3

POLYSWITCH_0.75A

12

USB_PN117

USB_PP117

*

C206

1000PF

+USB_VCCB

12

12

USB3_D­USB3_D+

R186

470K

R187

560K

USB1_D­USB1_D+

L22

FBM-11-160808-121

1 2
1 2

L21

FBM-11-160808-121

L16

CHB4516G750_1806

4516

150UF_D2_6.3V

12

C205
.1UF

USB_BGND

L19

FBM-11-160808-121

1 2
1 2

L18

FBM-11-160808-121

L17

CHB4516G750_1806

4516

12

12

C203

.1UF

+C217

12

12

C194

C207

.1UF

C193
47PF

47PF

12

12

12

12

C212

C211

47PF

47PF

JP1

1
2
3
4
5
6
7
8

SUYIN 2553A-0BG5T-A

COMPAL ELECTRONICS, INC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF T

Title

SCHEMATIC, M/ B LA-1331

Size Document Number Rev

B

401207

Date: Sheet of

星期四

18, 2004

三月

26 83,

2A