Gennum Corporation GS1545-CQR Datasheet

™

HD-LINX

GS1545
HDTV Serial Digital
Equalizing Receiver

PRELIMINARY DATA SHEET

FEATURES

• SMPTE 292M compliant

• 1.485 and 1.485/1.001Gb/s operation

• integrated adaptive cable equalizer

• integrated adjustment-free reclocker

• 1:20 serial to parallel conversion

• selectable reclocked serial output

• analog/digital input MUX

• carrier detect

• LOCK detect

• input jitter indicator (IJI)

• cable length indication

• maximum cable length adjust

• 20 bit output

• 74.25MHz or 74.25/1.001MHz clock output

• single +5.0V power supply

• minimal component count for HD SDI receive
solutions

APPLICATIONS

SMPTE 292M Serial Digital Interfaces for Video Cameras,
Camcorders, VTR's, Signal Generators, Portable
Equipment, and NLE's.

DESCRIPTION

The GS1545 is a high performance integrated Equalizing
Receiver designed for HDTV component signals,
conforming to the SMPTE 292M standard. The GS1545
includes adjustment free, adaptive cable equalization, clock
and data recovery, and serial to parallel conversion.

The Equalizer stage features DC restoration for immunity to
the DC content in pathological test patterns.

The Clock and Data Recovery stage was designed to
automatically recover the embedded clock signal and
retime the data from SMPTE 292M compliant digital video
signals. There is also a selectable reclocked serial data
output and the ability to bypass the reclocker stage.

A unique feature, Input Jitter Indicator (IJI), is included for
robust system design. This feature is used to indicate
excessive input jitter before the chip mutes the outputs.

The Serial to Parallel conversion stage provides 1:20 S/P
conversion

The GS1545 uses the GO1515 external VCO connected to
the internal PLL circuitry to achieve ultra low noise PLL
performance.

ORDERING INFORMATION

PART NUMBER PACKAGE TEMPERATURE

GS1545

GS1545-CQR 128 pin MQFP 0°C to 70°C

SDOint

ANALOG-

(opt)

SDOint

DDI A/D

TT

DIGITAL

MUX &

BUFFER

RECLOCKER

CORE

S/P CONVERTER

BUFFER2

SDO_EN

DATA_OUT[19:0]

PCLK_OUT

SDO

SDO

SDI

SDI

EQUALIZER

CORE

DDI DDI_V

SIMPLIFIED BLOCK DIAGRAM

Revision Date: August 2000 Document No. 522 - 28 - 00

GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3

Tel. [phone] Fax. [phone] E-mail: [e-mail]

www.gennum.com

GO1515

LFA

CLICD

LFS LFS PLCAP PLCAP IJI

MCLADJ

SDI

SDI

CABLE LENGTH INDICATOR

MAXIMUM CABLE LENGTH ADJUST

CARRIER DETECT

EQ

CORE

AGC

EQUALIZER CORE

DC

RESTORE

BUFFER1

DDI DDI_V

CHARGE

PUMP

SDOint-

(opt)

VCO

SDOint+

ANALOG-

DIGITAL

MUX &

BUFFER

DDI

TT

A/D

PHASE

DETECTOR

RECLOCKER CORE

FUNCTIONAL BLOCK DIAGRAM

PHASE

MUTE

LOCK

BYPASS

BYPASS

MUX

LOGIC

S/P CONVERTER

CORE

BUFFER2

SDO_EN

PLL_LOCK

PCLK_OUT

DATA_OUT[19:0]

SDO

SDO

GS1545

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise shown.

PARAMETER VALUE

Supply Voltage (V

Input Voltage Range (any input) V

Operating Temperature Range 0°C ≤ T

Storage Temperature Range -40°C ≤ T

Power Dissipation (V

Lead Temperature (soldering 10 seconds) 260°C

Input ESD Voltage TBD

Junction Temperature 125°C

)5.5V

S

– 0.5 < VIN < VCC+ 0.5

EE

≤ 70°C

A

≤ 150°C

S

= 5.25V) 2.1W

CC

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DC ELECTRICAL CHARACTERISTICS

VCC = 5V, VEE = 0V, TA = 0°C to 70°C, Data Rate = 1.485Gb/s.

PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS

Positive Supply Voltage Operating range V

Power Consumption V

Supply Current V

= 5; TA = 25°CPD- 1250 - mW 5

CC

= 5; TA = 25°C

CC

Output CM Voltage (SDO, SDO)

Input DC Voltage (DDI, DDI

Input DC Voltage (SDI, SDI

Serial Inputs (DDI, DDI

)-4.0-V1

)-2.7-V1

) Differential mode V

Common mode V

High Level Input Voltage

(A/D

, BYPASS)

Low Level Input Voltage (A/D
BYPASS

)

High Level Output Voltage

(D[19:0], PCLK)

Low Level Output Voltage

(D[19:0], PCLK)

,

= 5, TA = 25°CV

V

CC

V

= 5, TA = 25°CVIL--0.8V1

CC

V

= 5, TA = 25°C,

CC

= 1.0mA

I

SOURCE

VCC = 5, TA = 25°C,

= 1.0mA

I

SINK

TEST

LEVEL

CC

4.75 5.00 5.25 V 1

GS1545

I

S

V

CM

SID

CM

IH

V

OH

V

OL

- 250 - mA 1

3.75 4.0 4.25 V 5

100 - 1000 mV 7

2.5+V

SID/2

-VCC-V

SID/2

V7

2.0 - - V 1

2.4 - 3.0 V 1

--0.4V1

High Level Output Voltage
(PLL_LOCK)

Low Level Output Voltage

(PLL_LOCK)

Low Level Output Voltage (CD)

V

= 5, TA = 25°C,

CC

= 200µA

I

SOURCE

= 5, TA = 25°C,

V

CC

= 500µA

I

SINK

= 500µA V

I

SINK

V

OH

V

OL

OL

3.0 - - V 1

--0.4V1

-0.2- V1

CLI DC Voltage 1 meter, 800mV p-p Input - 3.3 - V 1

CLI DC Voltage

100 meters, 800mV p-p Input - 1.3 - V 1

(max cable length)

MCLADJ DC Voltage 1 meter, 800mV p-p Input - 4.1 - V 1

MCLADJ DC Voltage

100 meters, 800mV p-p Input - 3.1 - V 1

(max cable length)

TEST LEVELS

1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.

2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.

3. Production test at room temperature and nominal supply voltage.

4. QA sample test.

5. Calculated result based on Level 1,2, or 3.

6. Not tested. Guaranteed by design simulations.

7. Not tested. Based on characterization of nominal parts.

8. Not tested. Based on existing design/characterization data of similar product.

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AC ELECTRICAL CHARACTERISTICS - RECLOCKER STAGE

VCC = 5V, TA = 0°C to 70°C unless otherwise shown.

PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS

Serial Input – Data Rate SMPTE 292M BR

Serial Input – Jitter Tolerance Sinewave Modulation (p – p) J

Phase Lock Time ­Asynchronous

Loop bandwidth approximately

1.4MHz @ 0.2 UI input jitter

T

ALOCK

SDI

TOL

1.485/1.001 1.485 - Gb/s 1

-0.5-UI1

- 200 250 ms 7

modulation (LBCONT floating).

Phase Lock Time ­Synchronous

Loop bandwidth approximately

1.4MHz @ 0.2 UI input jitter

T

SLOCK

-24µs7

modulation (LBCONT floating).

Carrier Detect Timer Loop bandwidth approximately

-12-ms7

1.4MHz @ 0.2 UI input jitter
modulation (LBCONT floating).

Phase Lock/Unlock Timer

(1nF PLCAP)

Serial Output – Signal Swing V

Serial Digital Output –

Loop bandwidth approximately

1.4MHz @ 0.2 UI input jitter
modulation (LBCONT floating).

t

R-SDO

SDO

, t

F-SDO

60 - - µs 7

320 400 480 mV 1

- 150 270 ps 7

Rise and Fall Time

Serial Digital Output –

- - 100 ps 7

Rise and Fall Time Mismatch

Serial Digital Output –
Intrinsic Jitter

(RMS Jitter for clean PRN 2
input on DDI/DDI

inputs)

Loop bandwidth @ 0.2UI jitter modulation

23

– 1

t

IJ

-10-ps2

-1.4-MHz7

LBCONT floating

Jitter peaking --0.1dB7

TEST LEVELS

1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.

2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated
test.

3. Production test at room temperature and nominal supply voltage.

4. QA sample test.

5. Calculated result based on Level 1,2, or 3.

6. Not tested. Guaranteed by design simulations.

7. Not tested. Based on characterization of nominal parts.

8. Not tested. Based on existing design/characterization data of similar product

TEST

LEVEL

GS1545

GENNUM CORPORATION

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AC ELECTRICAL CHARACTERISTICS - EQUALIZER STAGE

V

= 5V, TA = 0°C to 70°C unless otherwise shown.

CC

PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS

Equalization Belden 1694A - 110 - m 2

Input Resistance (SDI, SDI

Input Capacitance (SDI, SDI

)-2.8-k

)C

IN

-2.0-pF7

Ω

AC ELECTRICAL CHARACTERISTICS - SERIAL TO PARALLEL STAGE

V

= 5V, TA = 0°C to 70°C unless otherwise shown.

CC

PARAMETER CONDITIONS SYMBOL MIN TYP MAX UNITS

Parallel Output Clock Frequency SMPTE 292M P

Clock Pulse Width Low 15pF load t

Clock Pulse Width High 15pF load t

Output signal Rise/Fall time 15pF load t

Output Signal Rise/Fall Time Matching 15pF load t

Output Setup Time 15pF load t

Output Hold Time 15pF load t

CLK_OUT

PWL

PWH

, t

r

f

rfm

OD

OH

74.25/1.001 74.25 - MHz 1

57-ns7

56-ns7

- 2000 4000 ps 7

- 1000 2000 ps 7

46-ns2

57-ns2

LEVEL

TEST

LEVEL

7

GS1545

TEST

TEST LEVELS

1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.

2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using
correlated test.

3. Production test at room temperature and nominal supply voltage.

4. QA sample test.

5. Calculated result based on Level 1,2, or 3.

6. Not tested. Guaranteed by design simulations.

7. Not tested. Based on characterization of nominal parts.

8. Not tested. Based on existing design/characterization data of similar product.

GENNUM CORPORATION

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522 - 28 - 00

GENNUM CORPORATION

PIN CONNECTIONS

PLL_LOCK

NC

95

8

NC

94

9

PLCAP

NC

92

93

11

10

VCO

91

12

NC

90

13

VCO

89

14

NC

88

15

NC

87

16

LFS

NC

IJI

84

85

86

19

18

17

NC

NC

82

83

VIEW

TOP

21

20

LFS

DM

80

81

GS1545

23

22

DM

79

24

PLCAP

NC

NC

NC

NC

NC

96

97

98

99

100

101

102

103

NC

104

NC

NC
DDI
DDI

CC

A/D

EE

EE

NC

NC

NC

CC

NC

NC

EE

NC
SDI

NC
SDI

NC

EE

NC

NC

105
106

TT

107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

4

3

2

1

7

6

5

BYPASS

DDI_V

PD_V

PDSUB_V

PD_V

6

EQI_V

EQI_V

EQI_V

NC

78

25

NC

77

26

DFT_V

EE

EE

76

27

LFA_V

75

28

LBCONT

LFA

CC

73

74

30

29

LFA_V

72

31

NC

71

32

NC

70

33

NC

69

34

NC

68

35

NC

67

36

NC

66

37

NC

65

38

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

DATA_OUT[19]
DATA_OUT[18]
DATA_OUT[17]
DATA_OUT[16]
DATA_OUT[15]
DATA_OUT[14]
NC
NC
DATA_OUT[13]
DATA_OUT[12]
DATA_OUT[11]
DATA_OUT[10]
NC
NC
DATA_OUT[9]
DATA_OUT[8]
DATA_OUT[7]
DATA_OUT[6]
DATA_OUT[5]
DATA_OUT[4]
DATA_OUT[3]
DATA_OUT[2]
DATA_OUT[1]
DATA_OUT[0]
NC
NC

522 - 28 - 00

NC

NC

PCLK_V

PCLK_V

PCLK_OUT

SP_V

SP_V

SP_V

SP_V

NC

NC

NC

NC

NC

NC

NC

NC

SDO_V

SDO_EN

SDO_V

SDO

SDO

EQO_V

NC

NC

EQO_V

CD

NC

NC

NC

NC

CLI

NC

MCLADJ

NC

NC

NC

NC

EE

EE

CC

CC

EE

CC

EE

CC

CC

EE

GS1545