Gennum Corporation GS1515-CTM, GS1515-CQM Datasheet

FEATURES

• SMPTE 292M compliant

• fully automatic adjustment free reclocker for HDTV
signals

• 1.485Gb/s and 1.485/1.001Gb/s operation

•dual 75Ω co-axial cable driver outputs

• reclocker bypass mode

• seamless input Interface to the GS1504 HD adaptive
equalizer

•low power

• lock detect

• +5V or -5V power supply operation

• 44 pin MQFP

APPLICATIONS

SMPTE 292M Serial Digital Routers; SMPTE 292M Serial
Digital Distribution Amplifiers.

ORDERING INFORMATION

PART NUMBER PACKAGE TEMPERATURE

™

HD-LINX

GS1515

HDTV Serial Digital Reclocker

PRELIMINARY DATA SHEET

DESCRIPTION

The GS1515 HDTV Serial Digital Reclocker is designed to
automatically recover the embedded clock signal and re­time the data from a SMPTE 292M compliant digital video
signal.

An internal low pass filter removes the high frequency jitter
components from the bit-serial stream. 100Ω differential
input termination is on-chip for seamless matching to 50Ω
transmission lines. A dual SMPTE 292M compliant output
Cable Driver is also included on-chip. The GS1515 uses the
GO1515 external VCO connected to the internal PLL
circuitry in order to achieve ultra low noise PLL
performance.

Two diagnostic features are included in the GS1515 for
robust system design. The Input Jitter Indicator (IJI)
indicates excessive input jitter before the Serial Digital
outputs are muted and the Jitter Demodulator Function
(DM) helps to debug systems and locate the source of jitter.

The GS1515 is packaged in a 44 pin MQFP package and
requires a single 5V power supply. The GS1515 typically
draws 100mA of current.

GS1515

GS1515-CQM 44 pin MQFP 0°C to 70°C

GS1515-CTM 44 pin MQFP Tape 0°C to 70°C

LFS LFS PLCAP PLCAP IJI

LFA

CHARGE

PUMP

GO1515

VCO

DDI_V

VCO

DDI

50

TT

50

DDI

PATENT PENDING

PHASE

DETECTOR

INPUT

BUFFER

BYPASS

PHASE

LOCK

MUTE

BYPASS

LOGIC

JITTER

DEMODULATOR

CABLE
DRIVER

R

SET

PLL_LOCK

DM

DM

DFT_V

EE

SDO

SDO

BLOCK DIAGRAM

Revision Date: January 2000 Document No. 522 - 23 - 01

GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3

Tel. [phone] Fax. [phone] E-mail: [e-mail]

www.gennum.com

ABSOLUTE MAXIMUM RATINGS

PARAMETER VALUE

Supply Voltage -0.5 V

Input Voltage Range -0.3 < VIN < VDD + 0.3V

Input ESD Voltage 2000V

Operating Temperature Range 0°C T

Storage Temperature Range -40°C T

GS1515

Lead Temperature (soldering, 10 sec) 260°C

DC ELECTRICAL CHARACTERISTICS

VCC = +5V, TA = 0°C to 70°C unless otherwise specified

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Positive Supply Voltage V

Power Consumption
(without GO1515 VCO)
T

= 25°C

A

Supply Current
(without GO1515 VCO)
T

= 25°C

A

V

= 5V

CC

to +5.5V

DC

CC

P

Cable Driver Output

D

to 70°C

A

to 125°C

S

DC

4.75 5.00 5.25 V 1

- 500 - mW 1

800mV into 75Ω load,
R

= 52.3Ω, ± 1%

SET

Used as a buffer O/P

- 420 - mW 3

200mV into 75Ω load,

= 210Ω, ± 1%

R

SET

Ι

Cable Driver Output

C

- 100 125 mA 1

800mV into 75Ω load,
R

= 52.3Ω, ± 1%

SET

Used as a buffer O/P

- 84 111 mA 3

200mV into 75Ω load,

= 210Ω, ± 1%

R

SET

Logic Input Low V

Logic Input High V

Logic Output Low V

Logic Output High V

Serial Input, common mode V

Serial Input, differential V

Serial Outputs, tuning range V

IL

IH

OL

OH

DDI-CM

SID

SOD

-0.5 - 0.8 V 1

2.0 -

0.5

V

+

CC

V1

at 400µA - - 0.5 V 1

at 150µA 2.4 3.5 - V 1

2.5 + V

/2 - VCC - V

SID

/2 V 2, 4

SID

100 - 800 mV 2, 4

0 800 880 mV 4

522 - 23 - 01

2

AC ELECTRICAL CHARACTERISTICS

VCC = +5 V, TA = 0 °C to 70 °C unless otherwise specified

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Serial Input Data Rate - 1.485 or

1.485/1.001

Serial Input Jitter Tolerance Worst case modulation

- 0.5 - UI 3, 4

Eg. Square wave or histogram
with two peaks

Onset of errors with histogram

-0.8-UI4
extending tails (outliers) with
major (75%) transitions within

0.4UI

PLL Lock Time - Asynchronous t

ALOCK

Loop Bandwidth approximately

- 60 100 ms 1

1.41MHz at 0.2UI input jitter
modulation

Loop Bandwidth approximately

- 340 560 ms 3
129kHz at 0.2UI input jitter
modulation

PLL Lock Time - Synchronous t

SLOCK

Loop Bandwidth approximately

-1.25-µs3

1.41MHz at 0.2UI input jitter
modulation

Loop Bandwidth approximately

- 12.5 - µs 3
129kHz at 0.2UI input jitter
modulation

Serial Output Data Rate BR

SDO

- 1.485 or

1.485/1.001

-Gb/s1

GS1515

-Gb/s1, 2

Serial Output - Signal Swing

Serial Output - Rise Time

SDO

20% - 80%

Serial Output - Fall Time

SDO

20% - 80%

Serial Output - Intrinsic Jitter t

Loop Bandwidth at 0.2UI input

BW

jitter modulation

V

SDO

IJ

LOOP

R

= 52.3

SET

No Compensation for Return

tr

Loss

± 1% 750 800 850 mV 1

Ω,

Return Loss Compensation

= 75Ω, 1%

R

COMP

L

= 10nH

COMP

= 1.5pF

C

COMP

No Compensation for Return

tf

Loss

Return Loss Compensation

= 75Ω, 1%

R

COMP

L

= 10nH

COMP

C

= 1.5pF

COMP

Loop Bandwidth approximately

1.41MHz at 0.2UI input jitter
modulation (jitter for clean
PRN23 input and SMPTE
pathological)

C

, C

CP2

= Open

= Open

= 1µF

CP1

C

CP3

R

CP1

- 150 230 ps 1

- 220 255 ps 4

- 150 230 ps 1

- 220 255 ps 4

-4290ps p-p3

-1.41-MHz4

C

C

R

CP1

CP3

CP1

, C

CP2

=1.0µF

= 50

= 5.6µF

Ω

- 129 - kHz 4

3

522 - 23 - 01

AC ELECTRICAL CHARACTERISTICS (continued)

VCC = +5 V, TA = 0 °C to 70 °C unless otherwise specified

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Jitter Peaking Loop Bandwidth approximately

GS1515

Phaselock Unlock Timer 10nF PLCAP - 67 - µs 2, 4

NOTES

1. 100% Tested at 25°C

2. Guaranteed by Design

3. Correlated Value

4. Using EB1515

PIN CONNECTIONS

NC

LFS

NC

1.41MHz at 0.2UI input jitter
modulation

Loop Bandwidth approximately
129kHz at 0.2UI input jitter
modulation

LFS

BYPASS

PLL_LOCK

IJI

DM

DM

NC

SDO

44 43 42 41 40 39 38 37 36 35 34

1

2

3

-0.05-dB4

-0.05-dB4

NC

SDO

NC

33

32

31

NC

CD_V

NC

CC

LFA_V

LFA_V

NC

EE

NC

NC

CC

NC

NC

LFA

4

5

6

7

8

9

10

11

12 13 14 15 16 17 18 19 20 21 22

EE

PLCAP

DFT_V

PLCAP

TOP VIEW

SHIELD

GS1515

VCO

VCO

SHIELD

TT

DDI_V

DDI

DDI

30

29

28

27

26

25

24

23

SHIELD

R

SET

NC

CD_V

NC

PD_V

NC

NC

PD_V

EE

EE

CC

522 - 23 - 01

4

PIN DESCRIPTIONS

NUMBER SYMBOL TYPE DESCRIPTION

1, 3, 4, 6, 7, 9, 10,

NC No connection. These pins are not bonded to the die.
24, 25, 27, 29, 31,
33, 34, 36, 38

2 LFS

5LFA_V

8LFA_V

EE

CC

INPUT Loop filter capacitor connection.

POWER Most negative power supply connection - loop filter circuitry.

POWER Most positive power supply connection - loop filter circuitry.

11 LFA OUTPUT Control signal output: control voltage for the external GO1515 VCO.

12 DFT_V

EE

POWER Most negative power supply connection - that enables the jitter demodulator

functionality, this pin should be connected to ground. If left floating, the DM
function is disabled resulting in a current saving of 340µA.

13, 14 PLCAP,

INPUT Control signal input: PLL lock detect time constant capacitor connection.

PLCAP

15, 18, 22 SHIELD No connect pins separating the DDI inputs, the VCO inputs and the loop filter

components to improve noise performance. Connection to be made to ground
in most cases depending upon PCB performance.

16, 17 VCO, VCO

19 DDI_V

TT

20, 21 DDI, DDI

23 PD_V

CC

INPUT Control signal inputs: differential inputs for the external VCO. The GO1515 has

single ended output. In this case, the VCO

input is decoupled to ground.

INPUT Centre tap of the two 50Ω on-chip termination resistors between the DDI and

inputs.

the DDI

INPUT Differential inputs for the serial digital signals.

POWER Most positive power supply connection - phase detector circuitry.

GS1515

26 PD_V

28 CD_V

30 R

SET

EE

EE

POWER Most negative poser supply connection - phase detector circuitry.

POWER Most negative power supply connection - cable driver circuitry.

INPUT Resistor used to set the serial digital output signal swing. It is connected

between here and ground with a very short trace length.

32 CD_V

35, 37 SDO

, SDO OUTPUT Differential serial digital outputs from the on-chip cable driver. These outputs

CC

POWER Most positive power supply connection - cable driver circuitry.

require 75Ω pull-up resistors.

39, 40 DM

, DM OUTPUT Diagnostic signal: if the jitter demodulator function is not used, these pins must

be left floating.

41 IJI OUTPUT Status signal output: indicates the amount of excessive jitter on the incoming

DDI and DDI

signals.

42 PLL_LOCK OUTPUT Status signal output: lock detect and carrier detect: PLL lock indicator output

used to indicate when the PLL is locked. This output is TTL compatible. When
the PLL_LOCK = LOW, the serial digital outputs are muted.

43 BYPASS

INPUT Control signal input: operational TTL compatible input that controls whether the

input DDI and DDI
the device, unreclocked (BYPASS

signal is reclocked (BYPASS = HIGH) or is passed through

= LOW). Muting does not affect the

bypassed signal.

44 LFS INPUT Loop filter capacitor connection.

5

522 - 23 - 01

INPUT / OUTPUT CIRCUITS

LFA_V

EE

LFA_V

CC

25k

400µA

LFS

PD_V

CC

5k

20k 10k

PLCAP PLCAP

PD_V

CC

GS1515

20k

100µA

PD_V

DDI_V

EE

TT

50 50

Fig. 1 DDI/DDI Input

PD_V

CC

5k 5k

DDIDDI

Fig. 4 PLCAP/PLCAP

PD_V

500

EE

LFA

Output

LFA_V

CC

10k

50

Fig. 2 VCO/VCO

10k 10k

DM DM

DFT_V

Fig. 3 DM/DM

EE

PD_V

85µA

EE

Input

PD_V

Output

10k

CC

31p

40 40

5mA 100µA

VCOVCO

LFA_V

EE

LFA_V

EE

Fig. 5 LFA Circuit

Fig. 6 LFS Output

522 - 23 - 01

6