Gennum Corporation GS1510-CQR Datasheet

™

HD-LINX

GS1510

HDTV Serial Digital Deformatter

PRELIMINARY DATA SHEET

FEATURES

• SMPTE 292M compliant

• standards detectio n/ind ica tion for SMPTE 292M levels
A/B,C,D/E,F,G/H,I,J/K,L/M

• NRZI decoding and SMPTE descrambling with
BYPASS option

• line CRC calculation, comparison

• selectable line based CRC re-Insertion

• H, V, F timing reference signal (TRS) extraction

• selectable flywhe el for noise immune H, V, F extraction

• selectable automatic switch line handling

• selectable TRS and line number re-insertion

• selectable active picture illegal code re-mapping

• configurable FIFO LOAD pulse

• 20 bit 3.3V CMOS input data bus

• optimized input interface to GS1545 or GS1540

• single +3.3V power supply

• 5V tolerant I/O

APPLICATIONS

SMPTE 292M Serial Digital Interfaces.

DESCRIPTION

When interfaced to the Gennum GS1545 HDTV Equalizing
Receiver or GS1540 Non-Equalizing Receiver, the GS1510
performs the final conversion to word aligned data. The
device performs NRZI decoding and de-scrambling as per
SMPTE 292M and word-aligns to the incoming data stream.
Line based CRCs are calculated on the incoming data
stream and are compared against the CRCs embedded
within the data stream.

HVF timing information is extracted from the data stream. A
selectable internal HVF flywheel provides superior noise
immunity against TRS signal errors. The device also detects
and indicates the input video signal standard.

The GS1510 can detect and re-map illegal code words
contained within the active portion of the video signal. Prior
to exiting the device, TRS, Line Numbers and CRCs based
on internal calculations may be re-inserted into the data
stream.

ORDERING INFORMATION

PART NUMBER PACKAGE TEMPERATURE

GS1510-CQR 128 pin MQFP 0°C to 70°C

GS1510

DATA_IN

[19:0]

PCLK_IN

INPUT

BUFFER

WB_NI

BP_DSC

BP_FR

3

DESCRAMBLE

FRAME

FW_EN/DIS

FAST_LOCK

2 2

RESET

TRS DETECTION

FLYWHEEL

STANDARD DETECTION

TRS EXTRACTION

3

[H:V:F]

3

LN_ERR
SAV_ERR
EAV_ERR

FIFO_L

TRS_Y/C

F_E/S

MUTE

VD_STD [3:0]

BLOCK DIAGRAM

CODE

PROTECT

CRC CALCULATION

CRC COMPARISON

ILLEGAL CODE REMAPPING

24

LINE_CRC_ERR [Y:C]

TRS_INS

LN_INS

CRC_INS

3

TRS,

LNUM,

AND CRC

INSERTION

OEN

DATA_OUT

[19:10]

(LUMA)

DATA_OUT

[9:0]

(CHROMA)

Revision Date: November 2000 Document No. 522 - 47 - 00

GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3

Tel. [phone] Fax. [phone] E-mail: [e-mail]

www.gennum.com

ABSOLUTE MAXIMUM RATINGS

PARAMETER VALUE

Supply Voltage -0.5V to +4.6V

Input Voltage Range (any input) -0.5V < V

Operating Temperature Range 0°C ≤ T

Storage Temperature Range -40°C ≤ T

< 5.5V

IN

≤ 70°C

A

≤ 125°C

S

Lead Temperature (soldering 10 seconds) 260°C

DC ELECTRICAL CHARACTERISTICS

VDD = 3.0 to 3.6V, TA = 0°C to 70°C, unless otherwise shown

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Positive Supply Voltage V

Supply Current

Input Logic LOW Voltage V

Input Logic HIGH Voltage V

Output Logic LOW Voltage V

Output Logic HIGH Voltage V

DD

Ι

DD

IL

IH

OL

OH

ƒ = 74.25MHz, TA = 25°C - 402 480 mA

I

LEAKAGE

I

LEAKAGE

VDD = 3.0 to 3.6V,

VDD = 3.0 to 3.6V,

AC ELECTRICAL CHARACTERISTICS

VDD = 3.0 to 3.6V, TA = 0°C to 70°C

3.0 3.3 3.6 V

< 10µA - - 0.8 V

< 10µA 2.1 3.3 5.0 V

= 4mA - 0.2 0.4 V

I

OL

= -4mA 2.6 - - V

I

OH

GS1510

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Clock Input Frequency F

Input Data Setup Time t

Input Data Hold Time t

HSCI

SU

IH

- 74.25 80 MHz Also supports 74.25/1.001MHz

2.5 - - ns 50% levels

1.5 - - ns 50% levels

Input Clock Duty Cycle 40 - 60 %

Output Data Hold Time t

Output Enable Time t

Output Disable Time t

Output Data Delay Time t

Output Data Rise/Fall Time t

ROD/tFOD

OH

OEN

ODIS

OD

With 15pF load 2.0 - - ns

With 15pF load - - 8 ns

With 15pF load - - 9 ns

With 15pF load - - 10 ns

With 15pF load - - 2.5 ns 20% to 80% levels

GENNUM CORPORATION

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522 - 47 - 00

PIN CONNECTIONS

DATA_OUT[19]

DATA_OUT[18]

DATA_OUT[17]

DATA_OUT[16]

DATA_OUT[15]

VDDGND

DATA_OUT[14]

DATA_OUT[13]

DATA_OUT[12]

DATA_OUT[11]

DATA_OUT[10]

DATA_OUT[9]

VDDGND

DATA_OUT[8]

DATA_OUT[7]

VDDGND

DATA_OUT[6]

DATA_OUT[5]

DATA_OUT[4]

DATA_OUT[3]

DATA_OUT[2]

DATA_OUT[1]

DATA_OUT[0]

LN_ERR
SAV_ERR
EAV_ERR

V

DD

GND

TEST

NC
NC
NC
NC
NC
NC
NC

V

DD

GND

NC

V

DD

GND

NC
NC
NC
NC
NC
NC
NC

V

DD

GND

V

DD

V

DD

GND
GND

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

GND

64636261605958575655545352515049484746454443424140

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83

GS1510

TOP

VIEW

84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

39

38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

128

V

DD

GND
OEN
TN
FIFO_L
LINE_CRC_ERR_Y
LINE_CRC_ERR_C
VD_STD[0]
VD_STD[1]
VD_STD[2]
VD_STD[3]
NC
NC
V

DD

GND
F
V
H
V

DD

GND
RESET
FAST_LOCK
CRC_INS
LN_INS
GND
TRS_INS
TRS_Y/C
WB_NI
BP_DSC
BP_FR
CODE_PROTECT
FW_EN/DIS
MUTE
F_E/S
GND
V

DD

GND
PCLK_IN

GS1510

GENNUM CORPORATION

DATA_IN[19]

DATA_IN[18]

DATA_IN[17]

DATA_IN[16]

DATA_IN[15]

DATA_IN[14]

DATA_IN[11]

DATA_IN[10]

DD

V

GND

DATA_IN[9]

DATA_IN[8]

DATA_IN[7]

DATA_IN[6]

DATA_IN[5]

DATA_IN[4]

DATA_IN[3]

DATA_IN[2]

DD

V

GND

DATA_IN[13]

DATA_IN[12]

DATA_IN[1]

DATA_IN[0]

DD

V

GND

3

522 - 47 - 00

PIN DESCRIPTIONS

NUMBER SYMBOL TIMING TYPE DESCRIPTION

1 PCLK_IN Synchronous

wrt PCLK_IN

2, 4, 14, 19, 24, 37,

GND Gnd Ground power supply connections.
46, 50, 58, 69, 79,
82, 91, 94, 110,
116, 128

3, 20, 25, 38, 47,

V

DD

51, 59, 68, 78, 81,
90, 93, 109, 115,
127

5F_E/S

Non-

synchronous

6MUTE

Synchronous
wrt PCLK_IN

7 FW_EN/DIS

Non-

synchronous

Input

Input Clock.

The device uses PCLK_IN for clocking the input
data stream into DATA_IN[19:0]. This clock is generated by
the GS1545 or GS1540

Power Positive power supply connections.

Input

Control Signal Input.

is generated. When F_E/S

signal at EAV. When F_E/S is low, the GS1510

FIFO_L
generates FIFO_L

Used to control where the FIFO_L signal

is high, the GS1510 generates

signal at SAV. See Fig. 4 for timing

information.

Input

Control Signal Input.

Used to enable or disable blanking of
the LUMA (DATA_OUT[19:10]) and CHROMA
(DATA_OUT[9:0]). When MUTE

is low, the device sets the
accompanying LUMA and CHROMA data to their appropriate
blanking levels. When MUTE

is high, the LUMA and CHROMA

data streams pass through this stage of the device unaltered.

Input

Control Signal Input.

flywheel. When FW_EN/DIS
enabled. When FW_EN/DIS

Used to enable or disable the internal

is high, the internal flywheel is
is low, the internal fly-wheel is

disabled.

GS1510

8 CODE_PROTECT Non-

synchronous

9 BP_FR Non-

synchronous

10 BP_DSC Non-

synchronous

11 WB_NI Non-

synchronous

12 TRS_Y/C

Non-

synchronous

Input

Input

Input

Input

Input

Control Signal Input.

Used to enable or disable re-mapping of
out-of-range words contained in the active portion of the video
signal. When this signal is high, the device re-maps out-of­range words contained within the active portion of the video
signal into CCIR-601 compliant words. Values between
000-003 are re-mapped to 004. Values between 3FC and 3FF
are re-mapped to 3FB. When this signal is low, out-of-range
words in the active video region pass through the device
unaltered.

Control Signal Input.

Used to enable or disable word
boundary framing. When BP_FR is low internal framing is
enabled. When BP_FR is high internal framing is bypassed.

Control Signal Input.

Used to enable or disable the SMPTE
292M descrambler. When BP_DSC is low, the internal SMPTE
292M descrambler is enabled. When BP_DSC is high, the
internal SMPTE 292M de-scrambler is bypassed.

Control Signal Input.

Used to enable or disable noise immune
operation of the word boundary framer. When WB_NI is high,
noise-immune word boundary alignment is enabled. The
device switches to a new word boundary only when it has
detected two consecutive identical new TRS positions. When
WB_NI is low, the device re-aligns the word boundary position
at every instance of a TRS.

Control Signal Input.

CHROMA TRS IDs are detected and used. When TRS_Y/C

Used to control whether LUMA or

is
high, the device detects and uses TRS signals embedded in
the LUMA channel. When TRS_Y/C

is low, the device detects

and uses TRS signals embedded in the CHROMA channel.

GENNUM CORPORATION

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522 - 47 - 00