Gennum Corporation GS1500-CQR Datasheet

™

HD-LINX

GS1500

HDTV Serial Digital Deformatter

with ANC FIFOs

PRELIMINARY DATA SHEET

FEATURES

• SMPTE 292M compliant

• standards detectio n/ind ica tion for SMPTE 292M levels
A/B,C,D/E,F,G/H,I,J/K,L/M

• NRZI decoding and SMPTE descrambling with
BYPASS option

• line CRC calculation, comparison

• selectable line based CRC re-insertion

• H, V, F timing reference signal (TRS) extraction

• selectable flywhe el for noise immune H, V, F extraction

• selectable automatic switch line handling

• selectable TRS and line number re-insertion

• selectable active picture illegal code re-mapping

• ANC data position indication

• ANC data extraction via internal FIFOs
(1024 bytes on Y and C channels)

• configurable FIFO LOAD pulse

• 20 bit 3.3V CMOS input data bus

• optimized input interface to GS1545 or GS1540

• single +3.3V power supply

• 5V tolerant I/O

DESCRIPTION

When interfaced to the Gennum GS1545 HDTV Equalizing
Receiver or GS1540 Non-Equalizing Receiver, the GS1500
performs the final conversion to word aligned data. The
device performs NRZI decoding and de-scrambling as per
SMPTE 292M and word-aligns to the incoming data stream.
Line based CRCs are calculated on the incoming data
stream and are compared against the CRCs embedded
within the data stream.

HVF timing information is extracted from the data stream. A
selectable internal HVF flywheel provides superior noise
immunity against TRS signal errors. The device also detects
and indicates the input video signal standard.

The GS1500 can detect and re-map illegal code words
contained within the active portion of the video signal. The
positions of the embedded ANC data are indicated and the
ANC data may be extracted and accessed by the user
through an internal FIFO interface. Prior to exiting the
device, TRS, Line Numbers and CRCs based on internal
calculations may be re-inserted into the data stream.

ORDERING INFORMATION

PART NUMBER PACKAGE TEMPERATURE

GS1500

APPLICATIONS

SMPTE 292M Serial Digital Interfaces.

FW_EN/DIS

FAST_LOCK

3

[H:V:F]

DATA_IN

[19:0]

PCLK_IN

INPUT

BUFFER

WB_NI

BP_DSC

BP_FR

DESCRAMBLE

FRAME

TRS_Y/C

F_E/S

2 2

RESET

TRS DETECTION

FLYWHEEL
STANDARD

DETECTION

TRS

EXTRACTION

3

3

FIFO_L

LN_ERR
SAV_ERR
EAV_ERR

MUTE

4

VD_STD

[3:0]

LINE_CRC_ERR[Y:C]

CRC

CALCULATION

CRC

COMPARISON

2

GS1500-CQR 128 pin MQFP 0°C to 70°C

FM_I/E

ANC_Y/C

2

FFRST

FOEN

2

R_CLK

2

REN
WEN

2

ANC/DATA

3

FF_STA

[2:0]

YCS_ERR
CCS_ERR

2

TRS_INS

LN_INS

CRC_INS

3

TRS,

LNUM,

AND CRC

INSERTION

OEN

DATA_OUT

[19:10]

(LUMA)

DATA_OUT
(CHROMA)

EX/CP

CODE

PROTECT

ILLEGAL CODE REMAPPING

ANC DATA DETECTION &

EXTRACTION FIFO'S

10

ANC_OUT

[9:0]

ANC_DATA

[Y:C]

[9:0]

BLOCK DIAGRAM

Revision Date: November 2000 Document No. 522 - 33 - 00

GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3

Tel. [phone] Fax. [phone] E-mail: [e-mail]

www.gennum.com

ABSOLUTE MAXIMUM RATINGS

PARAMETER VALUE

Supply Voltage -0.5V to +4.6V

Input Voltage Range (any input) -0.5V < V

Operating Temperature Range 0°C ≤ T

Storage Temperature Range -40°C ≤ T

< 5.5V

IN

≤ 70°C

A

≤ 125°C

S

Lead Temperature (soldering 10 seconds) 260°C

DC ELECTRICAL CHARACTERISTICS

VDD = 3.0 to 3.6V, TA = 0°C to 70°C, unless otherwise shown

PA RAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Positive Supply Voltage V

Supply Current

Input Logic LOW Voltage V

Input Logic HIGH Voltage V

Output Logic LOW Voltage V

Output Logic HIGH Voltage V

DD

Ι

DD

IL

IH

OL

OH

ƒ = 74.25MHz, TA = 25°C - 402 480 mA

< 10µA - - 0.8 V

I

LEAKAGE

< 10µA 2.1 3.3 5.0 V

I

LEAKAGE

VDD = 3.0 to 3.6V,

VDD = 3.0 to 3.6V,

AC ELECTRICAL CHARACTERISTICS

VDD = 3.0 to 3.6V, TA = 0°C to 70°C

3.0 3.3 3.6 V

= 4mA - 0.2 0.4 V

I

OL

= -4mA 2.6 - - V

I

OH

GS1500

PA RAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Clock Input Frequency ƒ

Input Data Setup Time t

Input Data Hold Time t

HSCI

SU

IH

- 74.25 80 MHz Also supports 74.25/1.001MHz

2.5 - - ns 50% levels

1.5 - - ns 50% levels

Input Clock Duty Cycle 40 - 60 %

Output Data Hold Time t

Output Enable Time t

Output Disable Time t

Output Data Delay Time t

Output Data Rise/Fall Time t

ROD/tFOD

FIFO Input Data Setup Time t

FIFO Input Data Hold Time t

OH

OEN

ODIS

OD

FSU

FIH

With 15pF load 2.0 - - ns Note 3

With 15pF load - - 8 ns

With 15pF load - - 9 ns

With 15pF load - - 10 ns Note 2

With 15pF load - - 2.5 ns 20% to 80% levels

8.0 - - ns Note 1

4.0 - - ns Note 1

NOTES:

1. The following signals need to adhere to this timing: ANC_Y/C

, REN, WEN, FFRST

2. Timing of the FF_STA[2:0] outputs may be greater than specified.

3. Output timing characteristics also apply to FIFO outputs.

GENNUM CORPORATION

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PIN CONNECTIONS

DATA_OUT[19]

DATA_OUT[18]

DATA_OUT[17]

DATA_OUT[16]

DATA_OUT[15]

VDDGND

DATA_OUT[14]

DATA_OUT[13]

DATA_OUT[12]

DATA_OUT[11]

DATA_OUT[10]

DATA_OUT[9]

VDDGND

DATA_OUT[8]

DATA_OUT[7]

VDDGND

DATA_OUT[6]

DATA_OUT[5]

DATA_OUT[4]

DATA_OUT[3]

DATA_OUT[2]

DATA_OUT[1]

DATA_OUT[0]

LN_ERR
SAV_ERR
EAV_ERR

V

DD

GND

TEST
YCS_ERR
CCS_ERR
FF_STA[0]
FF_STA[1]
FF_STA[2]

ANC_OUT[9]
ANC_OUT[8]

V

DD

GND

ANC_OUT[7]

V

DD

GND
ANC_OUT[6]
ANC_OUT[5]
ANC_OUT[4]
ANC_OUT[3]
ANC_OUT[2]
ANC_OUT[1]
ANC_OUT[0]

V

DD

GND

R_CLK

V

DD

GND

FOEN

FFRST

WEN

REN

ANC/DATA

FM_I/E

ANC_Y/C

EX/CP

64636261605958575655545352515049484746454443424140

65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83

GS1500

TOP

VIEW

84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

39

38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

128

V

DD

GND
OEN
TN
FIFO_L
LINE_CRC_ERR_Y
LINE_CRC_ERR_C
VD_STD[0]
VD_STD[1]
VD_STD[2]
VD_STD[3]
ANC_DATA_C
ANC_DATA_Y
V

DD

GND
F
V
H
V

DD

GND
RESET
FAST_LOCK
CRC_INS
LN_INS
GND
TRS_INS
TRS_Y/C
WB_NI
BP_DSC

9

BP_FR

8

CODE_PROTECT

7

FW_EN/DIS

6

MUTE

5

F_E/S

4

GND

3

V

DD

2

GND

1

PCLK_IN

GS1500

GENNUM CORPORATION

DATA_IN[19]

DATA_IN[18]

DATA_IN[17]

DATA_IN[16]

DATA_IN[15]

DATA_IN[14]

DD

V

GND

DD

V

GND

DD

V

GND

DATA_IN[9]

DATA_IN[8]

DATA_IN[7]

DATA_IN[6]

DATA_IN[5]

DATA_IN[4]

DATA_IN[3]

DATA_IN[2]

DATA_IN[1]

DATA_IN[13]

DATA_IN[12]

DATA_IN[11]

DATA_IN[10]

DATA_IN[0]

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PIN DESCRIPTIONS

NUMBER SYMBOL TIMING TYPE DESCRIPTION

1 PCLK_IN Synchronous

wrt PCLK_IN

2, 4, 14, 19,

GND GND Ground power supply connections.
24, 37, 46, 50,
58, 69, 79, 82,
91, 94, 110,
116, 128

3, 20, 25, 38,

V

DD

47, 51, 59, 68,
78, 81, 90, 93,
109, 115, 127

5F_E/S

Non-

synchronous

6MUTE

Synchronous
wrt PCLK_IN

7FW_EN/DIS

Non-

synchronous

Input

Input Clock.

The device uses PCLK_IN for clocking the input data
stream into DATA_IN[19:0]. This clock is generated by the GS1545
or GS1540.

Power Positive power supply connections.

Input

Control Signal Input.

generated. When F_E/S
signal at EAV. When F_E/S

Used to control where the FIFO_L signal is

is high, the GS1500 generates FIFO_L

is low, the GS1500 generates FIFO_L

signal at SAV. See Fig. 4 for timing information.

Input

Control Signal Input.

Used to enable or disable blanking of the

LUMA (DATA_OUT[19:10]) and CHROMA (DATA_OUT[9:0]). When

is low, the device sets the accompanying LUMA and

MUTE
CHROMA data to their appropriate blanking levels. When MUTE
high, the LUMA and CHROMA data streams pass through this
stage of the device unaltered.

Input

Control Signal Input.

When FW_EN/DIS
FW_EN/DIS

is low, the internal fly-wheel is disabled.

Used to enable or disable the internal flywheel.

is high, the internal flywheel is enabled. When

GS1500

is

8 CODE_PROTECT Non-

synchronous

9 BP_FR Non-

synchronous

10 BP_DSC Non-

synchronous

11 WB_NI Non-

synchronous

12 TRS_Y/C

Non-

synchronous

Input

Input

Input

Input

Input

Control Signal Input.

Used to enable or disable re-mapping of out­of -range words contained in the active portion of the video signal.
When this signal is high, the device re-maps out-of-range words
contained within the active portion of the video signal into CCIR-601
compliant words. Values between 000-003 are re-mapped to 004.
Values between 3FC and 3FF are re-mapped to 3FB. When this
signal is low, out-of-range words in the active video region pass
through the device unaltered.

Control Signal Input.

Used to enable or disable word boundary
framing. When BP_FR is low, internal framing is enabled. When
BP_FR is high, internal framing is bypassed.

Control Signal Input.

Used to enable or disable the SMPTE 292M
descrambler. When BP_DSC is low, the internal SMPTE 292M de­scrambler is enabled. When BP_DSC is high, the internal SMPTE
292M de-scrambler is bypassed.

Control Signal Input.

Used to enable or disable noise immune
operation of the word boundary framer. When WB_NI is high, noise­immune word boundary alignment is enabled. The device switches
to a new word boundary only when it has detected two consecutive
identical new TRS positions. When WB_NI is low, the device re­aligns the word boundary position at every instance of a TRS.

Control Signal Input.

TRS ID's are detected and used. When TRS_Y/C

Used to control whether LUMA or CHROMA

is high, the device
detects and uses TRS signals embedded in the LUMA channel.
When TRS_Y/C

is low, the device detects and uses TRS signals

embedded in the CHROMA channel.

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PIN DESCRIPTIONS (Continued)

NUMBER SYMBOL TIMING TYPE DESCRIPTION

13 TRS_INS Non-

15 LN_INS Non-

16 CRC_INS Non-

17 FAST_LOCK Synchronous

18 RESET

synchronous

synchronous

synchronous

wrt PCLK_IN

Non-

synchronous

Input

Input

Input

Input

Input

Control Signal Input.

TRS into the data stream. When TRS_INS is high, the device re­inserts TRS into the incoming data stream based on the internal
calculation. The original TRS packets are set to the blanking levels.
If the flywheel is enabled, TRS calculated by the flywheel is used for
insertion. When TRS_INS is low, the device will not re-insert TRS
even if errors in TRS signals are detected.

Control Signal Input.

line number into the data stream. When LN_INS is high, the device
re-inserts the line number into the incoming data stream based on
the internal calculation. The original line number packets are set to
the blanking levels. If the flywheel is enabled, the line number
calculated by the flywheel is used for insertion. When LN_INS is low,
the device will not re-insert the line number.

Control Signal Input.

CRC into the data stream. When CRC_INS is high, the device is
enabled to re-insert line CRCs based on the internal calculation.
When CRC_INS is low, the device will not re-insert the CRCs.

Control Signal Input.

when a switch line occurs. When a low to high transition occurs on
the FAST_LOCK signal, the internal flywheel will immediately re­synchronize to the next valid EAV or SAV TRS in the incoming data
stream. See Fig. 5 for timing information.

Control Signal Input.

default 720p parameters. When RESET
Detection, and ANC Detection operate normally. When RESET
low, the flywheel, TRS Detection, and ANC Detection are reset to the
720p parameters after a rising edge on PCLK_IN. The read and
write counters are not affected.

Used to enable or disable re-insertion of the

Used to enable or disable re-insertion of the

Used to enable or disable re-insertion of the

Used to control the flywheel synchronization

Used to reset the system state registers to their

is high, the fly wheel, TRS

is

GS1500

21 H Synchronous

wrt PCLK_IN

22 V Synchronous

wrt PCLK_IN

23 F Synchronous

wrt PCLK_IN

26 ANC_DATA_Y Synchronous

wrt PCLK_IN

Output

Output

Output

Output

Control Signal Output.

period of the video signal. Refer to Fig. 2 for timing information of H
relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and
CHROMA respectively.

Control Signal Output.

period of the video signal. Refer to Fig. 2 for timing information of V
relative to DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and
CHROMA respectively.

Control Signal Output.

the video signal. Refer to Fig. 2 for timing information of F relative to
DATA_OUT[19:10] and DATA_OUT[9:0], LUMA and CHROMA
respectively. When locked and the input signal is of a progressive
scan nature, F stays low at all times.

Control Signal Output.

embedded ANC data in the outgoing LUMA (DATA_OUT [19:10])
data stream. ANC_DATA_Y goes high for the entire time that an
ANC_DATA packet is present in the LUMA (DATA_OUT[19:10]) data
stream whether it be in the active video area or the ANC area. Refer
to Fig. 17 for timing of ANC_DATA_Y relative to LUMA
(DATA_OUT[19:10]). During detection of ANC data, any errors in the
data count (DC) packet will consequently cause errors in the
duration of the flags. Bit errors in an ANC header will prevent the
packet from being detected.

This signal indicates the Horizontal blanking

This signal indicates the Vertical blanking

This signal indicates the ODD/EVEN field of

This signal indicates the position of the

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PIN DESCRIPTIONS (Continued)

NUMBER SYMBOL TIMING TYPE DESCRIPTION

27 ANC_DATA_C Synchronous

wrt PCLK_IN

28, 29, 30, 31 VD_STD[3:0] Synchronous

wrt PCLK_IN

32 LINE_CRC_ERR_C Synchronous

wrt PCLK_IN

33 LINE_CRC_ERR_Y Synchronous

wrt PCLK_IN

Output

Output

Output

Output

Control Signal Output.

This signal indicates the position of the
embedded ANC data in the outgoing CHROMA (DATA_OUT[9:0])
data stream. ANC_DATA_C goes high for the entire time that an
ANC_DATA packet is present in the CHROMA (DATA_OUT[9:0])
data stream whether it be in the active video area or the HANC
area. Refer to Fig. 17 for timing of ANC_DATA_C relative to
CHROMA (DATA_OUT[9:0]). During detection of ANC data, any
errors in the data count (DC) packet will consequently cause errors
in the duration of the flags. Bit errors in an ANC header will prevent
the packet from being detected.

Control Signal Output.

VD_STD[3:0] indicates which input video
standard the device has detected. The GS1500 will indicate all of
the formats in SMPTE292M (see Table 3) plus it will indicate an
unknown interlace or progressive scan format.

Status Signal Output.

Indicates a difference in the calculated versus
embedded CRC in the CHROMA channel. When LINE_CRC_ERR_C
is high, it indicates that the GS1500 has detected a difference
between the line based CRCs it calculates for the CHROMA
channel and the line based CRCs embedded within the CHROMA
channel. When LINE_CRC_ERR_C is low, the embedded and
calculated CRC's match. Refer to Fig. 19 for timing information of
LINE_CRC_ERR_C.

Status Signal Output.

Indicates a difference in the calculated versus
embedded CRC in the LUMA channel. When LINE_CRC_ERR_Y is
high, it indicates that the GS1500 has detected a difference
between the line based CRCs it calculates for the LUMA channel
and the line based CRCs embedded within the LUMA channel.
When LINE_CRC_ERR_Y is low, the embedded and calculated
CRC's match. Refer to Fig. 19 for timing information of
LINE_CRC_ERR_Y.

GS1500

34 FIFO_L

Synchronous
wrt PCLK_IN

35 TN

36 OEN

Non-

synchronous

39, 40, 41, 42,
43, 44, 45, 48,
49, 52

53, 54, 55, 56,
57, 60, 61, 62,

DATA_OUT[9:0]

(CHROMA

channel)

DATA_OUT[19:10]

(LUMA channel)

Synchronous
wrt PCLK_IN

Synchronous
wrt PCLK_IN

63, 64

65 LN_ERR Synchronous

wrt PCLK_IN

Output

TEST

Input

Output

Output

Output

Control Signal Output.

Used to control an external FIFO(s). FIFO_L
is normally high, but is set low for the EAV or SAV word depending
on the state of F_E/S

. Refer to Fig. 4 for timing information of FIFO_L
relative to LUMA (DATA_OUT[19:10]) and CHROMA
(DATA_OUT[9:0]).

Test Pin.

V

Control Signal Input.

bus or set it in a high Z state. When OEN

Used for test purposes only. This pin must be connected to

for normal operation

DD

Used to enable the DATA_OUT[19:0] output

is low, the LUMA
(DATA_OUT[19:10]) and CHROMA (DATA_OUT [9:0]) busses are
enabled. When OEN

CHROMA Output Data Bus.

is high, these busses are in a high Z state.

DATA_OUT [9] is CHROMA_OUT[9]
which is the MSB of the CHROMA output signal (pin 52). DATA_OUT
[0] is CHROMA_OUT[0] which is the LSB of the CHROMA output
signal (pin 39).

LUMA Output Data Bus.

DATA_OUT [19] is LUMA_OUT[9] which is
the MSB of the LUMA output signal. (pin 64) DATA_OUT [10] is
LUMA_OUT[0] which is the LSB of the LUMA output signal (pin 53).

Status Signal Output.

Used to indicate a Line Number error or a
mismatch between the embedded line number and the flywheel line
number when the flywheel is enabled. When LN_ERR is high, a line
number error is detected or the internal flywheel indicates
mismatching line numbers. Refer to Fig. 3 for timing information of
LN_ERR relative to LUMA (DATA_OUT[19:10]) and CHROMA
(DATA_OUT [9:0]) Since LN_ERR depends on the sequence of line
numbers, a line number error will actually cause LN_ERR to go high
for two lines.

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