Gennum Corporation GP520A Datasheet
GENNUM
C␣␣O␣␣R␣␣P␣␣O␣␣R␣␣A␣␣T␣␣I␣␣O␣␣N
FEATURES
• programmable parameters
- gain
- low pass filter
- high pass filter
- AGC threshold
- release time
- MPO
- receiver bias voltage
• on-chip voltage regulator
• typical gain 60 dB
• voltage drive output stage
• telecoil preamp
STANDARD PACKAGING
• Chip (136 x 110 mils)
Au Bump
CIRCUIT DESCRIPTION
The GP520A is a programmable analog signal path IC
designed for use in hearing instruments. The GP520A’s
programmable parameters are adjusted by external
programming currents, such as generated by the GP521.
The GP520A provides a 2.5 µA reference current for use by
the GP521. Sixteen settings are possible in the GP521,
allowing the Programmable Current Sink (PCS) to sink
between 0 and 1.875 x I
The GP520A is composed of five functional blocks. The
input preamp, a filter block, the AGC block, MPO clipper
and the output stage.
REF
.
Programmable Analog
Signal Processor
GP520A - DATA SHEET
Principle features of the preamp are the input impedance
100 kΩ and a gain of 14 dB.
The programmable filter block is composed of a low pass
and high pass filter which generates a range of high and
low pass corner frequencies. Although the control current
to this block varies linearly, linear to logarithmic conversion
is performed internally in order to adjust the corner frequencies
logarithmically. Both filters feature a 12 dB/octave rolloff
and unity gain.
The filters are followed by an AGC block. Up to 35␣ dB of
adjustable gain is provided as well as programmable
threshold and release time. The attack time of the AGC
block remains fixed and is independent of the release
time. The output current is driven into the preamp of the
clipper, thus, the AGC converts a voltage input into a
current output and is therefore, a transconductance block.
The next stage is an electronic MPO control peak “clipper”
providing electronic clipping of the signal and setting of
the maximum output level. The clipper output is also a
transconductance block and drives a 40 kΩ resistor (R
tied to the supply.
The input of the final stage is an inverting operational
amplifier. A feedback resistance of 240 kΩ is provided
internally and this final stage is thus configured as a
voltage drive output stage. The DC bias current through
the receiver is also programmable.
OUT␣ 8
)
A
V
V
REG
13
28
29
A
IN
14
All resistors in ohms, all capacitors in farads unless otherwise stated.
50k
P GND
VOLTAGE
REGULATOR
R
IN14
12
CC
9
+
PREAMP
-
10K
GND
40K
6
OUT
HPFB
15
LIN/LOG
CONVERTER
20
I
HP
HP
18
+
2R
FILTER
-
R
Revision Date: May 1998
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 tel. +1 (905) 632-2996
Web Site: www.gennum.com E-mail: hipinfo@gennum.com
LPFB
22 24 26
19
R
HP
CONVERTER
R
LIN/LOG
I
LP
IN
+
LP
FILTER
-
OUT
I
REF
I
1621
REF
IN
27
FULL WAVE
RECTIFIER
RECT.
BUFFER
BUFFER
FUNCTIONAL BLOCK DIAGRAM
C
AGC
1
AVERAGING
CIRCUIT
25
I
REL
THRESHOLD
LIN/LOG
CONVERTER
2
I
THRESH
C
COMP
31
AGC
I
GAIN
23
DELTA
OUT
B
IN
3
5
4
I
CLIP
C
B
OUT
CLIP
7
30
V
cc
R
OUT 8
VC AMP CLIPPER
R
-
OUTPUT
+
V
BIAS
17
I
BIAS
8
10
F
11
Document No. 510 - 78 - 06
C
OUT
D
IN
D
OUT
CHIP PAD DIAGRAM
ABSOLUTE MAXIMUM RATINGS
PARAMETER VALUE / UNITS
Supply Voltage 5 V
Pad 3, 8, 10, 11, 13, 17 -0.1 V to VCC + 0.1 V
Pad 1, 15, 16, 18, 19, 22, 24, 26 -0.1 V to V
REG
+ 0.1 V
Pad 4, 5, 7, 14, 20, 21, 23, 25, 27 -0.1 V to 0.7 V
Pad 2 V
-0.7 V to V
REG
REG
+ 0.1 V
CAUTION
CLASS 1 ESD SENSITIVITY
ELECTRICAL CHARACTERISTICS
31
C
1
2
3
4
5
6
7
8
9
10
11
12
COMP
C
AGC
I
THRESH
DELTA OUT
I
CLIP
B
IN
GND
B
OUT
C
OUT
V
CC
D
IN
D
OUT
P
GND
V
13
C
REG
30
CLIP
29
TEL-B
BUFFER OUT
GP520A
All parameters are measured at TA = 25oC
All gains are calculated from equation G = 20 LOG (∆OUT/∆IN) where ∆OUT and ∆IN are appropriate voltage or current increases.
All resistances are calculated according to equation R = (V
- quiescent (unbias) voltage measured on the pad, (nothing connected to the pin).
V
Q
is the actual voltage measured on the pad at given condition (where P is pad number).
V
P
For all graphs I
is measured with 0.5V biased voltage on pin 16.
REF
- VQ) / I
P
where VP is voltage on the pad loaded with I
COND
COND
current.
GENERAL
27
28
RECT.IN
TEL-C
I
REL
BUFFER IN
I
GAIN
LPFB
I
I
HP
HPFB
I
BIAS
I
REF
A
OUT
A
IN
14
LP
HP
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
26
25
24
23
22
21
20
19
18
17
16
15
Amplifier Current I
Minimum Voltage V
REGULATOR TESTS
Regulator Voltage (Pad 13) V
Short Circuit Current (Pad 13) I
CURRENT REFERENCE
Current Reference (Pad 16) I
PREAMPLIFIER
Quiescent Voltage on Pad 14 V
Quiescent Voltage on Pad 15 V
Input Resistance (Pad 14) R
Output Swing High (Pad 15) V
Output Swing Low (Pad 15) V
Max Source Current (Pad 15) I
Max Sinking Current (Pad 15) I
AMP
CC
REG
SC
R
Q14
Q15
IN 14 I14
OH
OL
V
SOURCE
V
V
SINK
V
All PCS set to 15 - 600 - µA
1.1 - - V
- 0.98 - V
S1 — closed - 2.0 - mA
- 2.5 - µA
600 - - mV
600 - - mV
= 0.3µA (S2 closed)(Note 1) - 100 - kΩ
V
=
0.8V (S3 closed)(Note 1) 200 - - mV
14
V
=
0.4V (S3 closed) -200 - - mV
1
=
0.8V (S3, S4 closed) 30 - - µA
14
=
V
+100mV
15
Q15
=
0.4V (S3,S4 closed) 30 - - µA
14
=
V
-100mV
15
Q15
Preamp Voltage Gain GAIN V
NOTE: 1. VOL= V
510 - 78 - 06
OH
= V
P15
– V
Q15
=
V
±10mV (S3 closed) - 14 - dB
14
Q14
All switches remain OPEN unless otherwise stated in CONDITIONS column.
2
10n
AGC
10n
10K
B
B
OUT
OUT
30
31
V
CC
2k2
11
D
OUT
S4
68n
68n
C
1
26
27
9
+
PREAMP
40K
-
V15
+
A
OUT
15 5 7
1.3V
-
+
V
CC
V
REG
S1
3µ3
A
S2
S3
VOLTAGE
13
REGULATOR
IN
14
R
IN14
I14
V14
+
-
P GND
10K
12
6
GND
All resistors in ohms, all capacitors in
farads unless otherwise stated.
Fig. 1 Preamplifier and Regulator Test Circuit
HIGH PASS FILTER
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Quiescent Voltage on Pad 18 V
Quiescent Voltage on Pad 19 V
Quiescent Voltage on Pad 20 V
Maximum DC Current from Pad 19 I
Minimum DC Current from Pad 19 I
Q18
Q19
Q20
I
HP MAX
HP MIN
IHP=1.875 x I
Buffer Gain GAIN V
Input Resistance Pad 20 R
All switches remain OPEN unless otherwise stated in CONDITIONS column.
IN20
I
= 0µA ( S3 closed) -2-µA
HP
(S3 closed) - 200 - nA
R
= V
± 100mV
Q19
(S2 closed) -0-dB
R
HP
19
= I
- 650 - mV
- 650 - mV
- 550 - mV
-13-kΩ
3µ3
+ -
V19
S2
V
CC
V
REG
P GND
9
13
LIN/LOG
CONVERTER
12
6
GND
HP
HPFB
19
18
+
HP
2R
FILTER
-
R
0.6 V
R
IN
20
I
HP
I
HP
68n
S3
LPFB
22 5 7
26
R
LIN/LOG
CONVERTER
21
I
LP
All resistors in ohms, all capacitors in
farads unless otherwise stated.
10n
AGC
30 31
10n
10K
B
IN
68n
C
1
27
B
OUT
V
CC
2k2
11
D
OUT
Fig. 2 High Pass Filter DC Test Circuit
3
510 - 78 - 06
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