Gennum Corporation GF9103-CTS, GF9103-CPS Datasheet
MultiGEN
Color Space Converter for Video
™
GF9103 Over-Sampling
Monitoring
DATA SHEET
FEATURES
• 4:2:2 to over-sampled RGB or YC
conversion in a
BCR
single device
• single 10 bit 4:2:2 input
• internal 4:2:2 de- multiplexer
• 4:2:2 to 8:8:8 interpolation filters
• internal YC
• optional YC
CR to RGB color space conversion
B
(8:8:8) output mode
BCR
• setup insertion in Luminance channel under user
control
• user selectable digital SIN X/X correction
• rounding to 10/8 bit resolution per output channel
• 40 MHz maximum clock rate
• single +5 V power supply
APPLICATIONS
• Over-Sampling 4:2:2 to Analog RGB Conversions for
video monitoring
• Over-Sampling 4:2:2 to Analog YCBCR Conversions for
video monitoring
DEVICE DESCRIPTION
The GF9103 is specifically designed to simplify conversions
from 4:2:2 component digital video to analog RGB or
analog YC
component video. The GF9103 simplifies
BCR
this process by performing 4:2:2 to 8:8:8 interpolation,
digital color space conversion and digital SIN X/X
correction in a single device. Immediately following the
GF9103, three over-sampled channels of RGB or YCBC
data may be passed through Digital to Analog converters
and simplified analog reconstruction filters.
The GF9103 accepts a single 10 bit stream of 4:2:2 data
and internally de-multiplexes it into three 10 bit channels of
data. The YCBCR data is then passed through
YC
BCR
three linear phase FIR filters that over-sample the Y data by
a factor of 2 and the C
and CR data by a factor of 4.
B
While operating in an over-sampled RGB output mode, the
interpolated YCBCR data is passed through the internal
color space converter to convert the YC
data to RGB
BCR
data according to CCIR-601. Alternatively, the color space
converter may be bypassed to obtain over-sampled YC
BCR
(8:8:8) output data. While operating in YCBCR output mode,
setup may be dynamically inserted into the Luminance
channel.
R
ORDERING INFORMATION
PART NUMBER PACKAGE TEMPERATURE RANGE
GF9103-CPS 68 pin PLCC 0° to 70° C
GF9103-CTS 68 pin PLCC Tape 0° to 70° C
SELECT_MATRIX
Y
YCBCR
CB
MATRIX
CR
TO
RGB
MULTIPLEXED
4:2:2 DATA
STREAM IN
CLK
SYNC
SETUP
Y
10
4:2:2
CB
DEMUX
CR
Y
X2
X4
X4
SETUP
CB
CR
FUNCTIONAL BLOCK DIAGRAM
Prior to output rounding, over-sampled YC
or RGB data
BCR
may be corrected for SIN X/X characteristics of D/A
conversion. Output data may be rounded to 10 or 8 bit
resolution per channel. C
and C
B
may be presented as
R
signed or unsigned data.
The GF9103 is packaged in a 68 pin PLCC package,
operates with a single +5 V power supply and typically
consumes only 85 mA of current when operated at 27 MHz.
CB/B
CR/R
CONVERT
2's COMP
2's COMP
Y/G
CB/B
CR/R
OE
10
10
10
Y/G
CB/B
CR/R
BYPASS
SIN X/X
SIN X/X
SIN X/X
Y/G
CB/B
CR/R
CLIP & ROUND
CLIP & ROUND
CLIP & ROUND
Y/G
CB/B
CR/R
Revision Date: August 1997 Document No. 521 - 33 - 04
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
PIN DESCRIPTION
PIN NO. SYMBOL DESCRIPTION
10, 18, 27, 36, 44, 52,
61, 68
1, 6, 7, 9, 26, 30, 35,
V
DD
±5 V ± 5% power supply.
GND Ground.
40, 43, 60, 64
3 SCAN_EN Set Low.
8, 11-17, 19, 20 SI
9..0
4OE
Input Data Port: Input data port with internal pull-downs. Input data is assumed to be a
multiplexed stream of C
is the Most Significant Bit and SI0 is the Least Significant Bit.
SI
9
[Y] CB..., where [Y] denotes an isolated Luminance sample.
BYCR
Output Enable: Active low input with internal pull-up. When OE is high, the output data ports
are in high impedance state.
59-53, 51-49 SOA
48-45, 42, 41, 39-37,
SOB
34
33-31, 29, 28, 25-21 SOC
9..0
9..0
9..0
Output Data Port A: Depending on device configuration, SOA
Y or G video. SOA
is the Most Significant Bit and SOA0 is the Least Significant Bit.
9
Output Data Port B: Depending on device configuration, SOB
C
or B video. SOB9 is the Most Significant Bit and SOB0 is the Least Significant Bit.
B
Output Data Port C: Depending on device configuration, SOC
or R video. SOC
C
R
is the Most Significant Bit and SOC0 is the Least Significant Bit.
9
may output over-sampled
9..0
may output over-sampled
9..0
may output over-sampled
9..0
2 CLK System Clock: All timing information relative to rising edge of clock.
5 SYNC Synchronization: Control signal input with internal pull-up. This input is used to synchronize
the incoming data by holding SYNC high on clock period N and low on clock period N+1
when the first C
synchronization is desired or may be toggled at every occurrence of a C
sample is presented to the SI
B
inputs. SYNC may be held low until re-
9..0
sample.
B
65 SELECT_MATRIX Select Color Space Conversion: Control signal input with internal pull-down.
SELECT_MATRIX is used to enable and disable the internal YC
to RGB color space
BCR
converter. Color space conversion is enabled while SELECT_MATRIX is high and is
disabled while SELECT_MATRIX is low.
66 BYPASS
Bypass SIN X/X Correction: Control signal input with internal pull-up. When BYPASS is
high, SIN X/X correction for the three output channels is enabled. While BYPASS
is low, SIN
X/X correction is by-passed.
63 SETUP Setup: Control signal input with internal pull-down. SETUP is used to enable and disable
setup insertion in the Luminance channel.
62 CONVERT Two's Complement Conversion: Control signal input with internal pull-up. While CONVERT
is high, SOB
CONVERT is low, SOB
operating in RGB output mode, the CONVERT pin is over-ridden and both SOB
output unsigned digital data. SOA
SOC
9..0
9..0
and SOC
9..0
output signed (two’s complement) digital data. While
9..0
and SOC
output unsigned (offset binary) data. When
9..0
outputs unsigned digital data in all operating
9..0
9..0
and
modes.
67 RND10/8
Output Rounding: Control signal input with internal pull-up. RND10/8 selects rounding to
10 bit resolution per channel when high and rounding to 8 bit resolution per channel when
low.
521 - 33 - 04
2
GND
SI9
GND
GND
SYNCOESCAN_EN
CLK
GND
VDD
RND10/8
BYPASS
SELECT_MATRIX
GND
SETUP
CONVERT
VDD
VDD
SI8
SI7
SI6
SI5
SI4
SI3
SI2
VDD
SI1
SI0
SOC0
SOC1
SOC2
SOC3
SOC4
GND
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
11
12
13
14
15
16
17
18
19
GF9103
TOP VIEW
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
VDD
SOC5
SOC6
GND
SOC7
SOC8
SOC9
SOB0
GND
VDD
SOB1
SOB2
SOB3
GND
SOB4
Fig. 1 GF9103 Pin Connections
SOB5
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
GND
GND
SOA9
SOA8
SOA7
SOA6
SOA5
SOA4
SOA3
VDD
SOA2
SOA1
SOA0
SOB9
SOB8
SOB7
SOB6
VDD
n SUBSTRATE
CONTROL
INPUT
p WELL
p+
n+
D1
D2
GND
V
DD
p
n
V
DD
p
p+
n+
n
GND
Fig. 2a Equivalent Input Circuit Fig. 2b Equivalent Output Circuit
n SUBSTRATE
D1
D2
p WELL
3
521 - 33 - 04
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