GENNUM GS9025A User Manual

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GS9025A

GENLINX

II

Serial Digital Receiver

PRELIMINARY DATA SHEET

FEATURES

• SMPTE 259M compliant

• operational to 540Mb/s

• automatic cable equalization (typically greater than
350m of high quality cable at 270Mb/s)

• adjustment-free operation

• auto-rate selection (5 rates) with manual override

• single external VCO resistor for operation with five
input data rates

• data rate indication output

• serial data outputs muted and serial clock remains
active when input data is lost

• operation independent of SAV/EAV sync signals

• signal strength indicator output

• carrier detect with programmable threshold level

• power savings mode (output serial clock disable)

APPLICATIONS

Cable equalization plus clock and data recovery for all high
speed serial digital interface applications involving SMPTE
259M and other data standards.

DESCRIPTION

The GS9025A provides automatic cable equalization and
high performance clock and data recovery for serial digital
signals. The GS9025A receives either single-ended or
differential serial digital data and outputs differential clock
and retimed data signals at PECL levels (800mV). The on­board cable equalizer provides up to 40dB of gain at
200MHz which typically results in equalization of greater
than 350m of high quality cable at 270Mb/s.

The GS9025A operates in either auto or manual data rate
selection mode. In both modes, the GS9025A requires only
one external resistor to set the VCO centre frequency and
provides adjustment free operation.

The GS9025A has dedicated pins to indicate signal
strength/carrier detect, LOCK and data rate. Optional
external resistors allow the carrier detect threshold level to
be customized to the user's requirement. In addition, the
GS9025A provides an 'Output Eye Monitor Test'
(OEM_TEST) for diagnostic testing of signal integrity after
equalization, prior to reslicing. The serial clock outputs can
also be disabled to reduce power. The GS9025A operates
from a single +5 or -5 volt supply.

ORDERING INFORMATION

PART NUMBER PACKAGE TEMPERATURE

GS9025ACQM 44 pin MQFP Tray 0°C to 70°C

GS9025ACTM 44 pin MQFP Tape 0°C to 70°C

GS9025A

C

OSC

LOGIC

DECODER

MUTE

3 BIT

COUNTER

LOCK

SDO

SDO

CLK_EN

SCO

SCO

SMPTE

AUTO/MAN

SS0
SS1
SS2

DDI

DDI

SDI
SDI

OEM_TEST

+

+

-

-

EYE

MONITOR

VARIABLE

GAIN EQ

STAGE

AUTO EQ

CONTROL

+ -

AGC CAP CD_ADJ

A/D

ANALOG

DIGITAL

MUX

SSI/CD

CARRIER DETECT

PHASELOCK

HARMONIC

FREQUENCY
ACQUISITION

PHASE

DETECTOR

DIVISION

CHARGE

PUMP

LF+ LFS LF- CBG R

VCO

VCO

BLOCK DIAGRAM

Revision Date: June 2000 Document No. 522 - 75 - 00

GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3

Tel. [phone] Fax. [phone] E-mail: [e-mail]

www.gennum.com

ABSOLUTE MAXIMUM RATINGS

PARAMETER VALUE

Supply Voltage (V

Input Voltage Range (any input) V

Operating Temperature Range 0°C ≤ T

Storage Temperature Range -65°C ≤ T

)5.5V

S

+ 0.5 to V

CC

- 0.5V

EE

≤ 70°C

A

≤ 150°C

S

Lead Temperature (soldering, 10 sec) 260°C

DC ELECTRICAL CHARACTERISTICS

VCC = 5.0V, TA = 25°C unless otherwise stated, RLF = 1.8k, C

PARAMETER CONDITION MIN

Supply Voltage 4.75 5 5.25 V 1

Supply Current CLK_EN = 0 - 115 mA 1

CLK_EN = 1 - 125

SDI Common Mode Voltage - 2.5 - V 1

DDI Common Mode Input
Voltage Range

DDI Differential Input Drive 200 800 2000 mV 1

SSI/CD

Output Current Source,

= 50pF,

C

LMAX

R

= open cct.

L

= 15nF, C

LF1

V

EE

= 3.3pF

LF2

TYPICAL

+(V

/2) 0.4 to 4.6 VCC-(V

DIFF

1

MAX UNITS NOTES

/2) V 2 1

DIFF

- - 18 µA 3

GS9025A

TEST

LEVEL

Source,
C

LMAX

R

=5K

L

= 50pF,

- - 110 µA 3

Sink - 1.0 1.5 mA 3

AGC Common Mode Voltage - 2.7 - V 1

OEM_TEST Bias Potential - 4.5 - V 5 1

A/D

, AUTO/MAN, SMPTE,

High 2.0 - - V 1

SS[2:0] Input Voltage

Low - - 0.8

CLK_EN Input Voltage High 2.5 - - V 1

Low - - 0.8

LOCK Output Sink Current 500 - - µA 3 1

SS[2:0] Output Voltage High 4.4 4.7 - V 1

Low - 0.2 0.4

SS[2:0] Source Current Auto Mode 180 300 - µA 1

SS[2:0] Sink Current Auto Mode 0.6 1.0 - mA

SS[2:0] Source Current Manual Mode - 0 - µA 4 1

GENNUM CORPORATION

2

522 - 75 - 00

DC ELECTRICAL CHARACTERISTICS (continued)

VCC = 5.0V, TA = 25°C unless otherwise stated, RLF = 1.8k, C

= 15nF, C

LF1

= 3.3pF

LF2

PARAMETER CONDITION MIN

TYPICAL

1

MAX UNITS NOTES

SS[2:0] Sink Current Manual Mode - 0.8 5 µA

CLK_EN Source Current Low - 26 55 µA 1

NOTES

1. TYPICAL - measured on EB9025A board.
is the differential input signal swing.

2. V

DIFF

3. LOCK is an open collector output and requires an external pullup

resistor.

4. Pins SS[2:0] are outputs in AUTO mode and inputs in MANUAL

mode.

5. If OEM_TEST is permanently enabled, operating temperature

range is limited from 0°C to 60°C inclusive.

TEST LEVELS

1. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature
ranges.

2. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature
ranges using correlated test.

3. Production test at room temperature and nominal supply
voltage.

4. QA sample test.

5. Calculated result based on Level 1,2, or 3.

6. Not tested. Guaranteed by design simulations.

7. Not tested. Based on characterization of nominal parts.

8. Not tested. Based on existing design/characterization
data of similar product.

AC ELECTRICAL CHARACTERISTICS

VCC = 5.0V, VEE = 0V, TA = 25°C unless otherwise stated, RLF = 1.8k, C

PARAMETER CONDITIONS MIN

= 15nF, C

LF1

= 3.3pF

LF2

TYPICAL

1

MAX UNITS NOTES

TEST

LEVEL

GS9025A

TEST

LEVEL

Serial Data Rate SDI 143 - 540 Mb/s 1

Maximum Equalizer Gain @ 200MHz - 40 - dB 7

Additive Jitter

[Pseudorandom (2

23

-1)]

270Mb/s, 300m
(Belden 8281)

540Mb/s, 100m

- 300 - ps p-p 2, 8 3

- 275 -

(Belden 8281)

Intrinsic Jitter

23

[Pseudorandom (2

-1)]

Intrinsic Jitter
[Pathological (SDI checkfield)]

270Mb/s - 185 see Figure 12 ps p-p 2, 7 4

540Mb/s - 164

270Mb/s - 462 see Figure 13 ps p-p 2, 7 1

360Mb/s - 308

540Mb/s - 260

Input Jitter Tolerance 270Mb/s 0.40 0.56 - UI p-p 3, 7 1

540Mb/s 0.35 0.43 -

Lock Time ­Synchronous Switch

Lock Time ­Asynchronous Switch

t

< 0.5µs, 270Mb/s - 1 - µs 4 7

switch

0.5µs< t

t

switch

Loop Bandwidth

<10ms - 1 - ms

switch

> 10 ms - 4 - ms

-10 - ms57

= 6MHz @ 540Mb/s

Carrier Loss Time 0.5 1 2 µs 6 7

SDO to SCO Synchronization -200 0 200 ps 7

3

GENNUM CORPORATION

522 - 75 - 00

AC ELECTRICAL CHARACTERISTICS

VCC = 5.0V, VEE = 0V, TA = 25°C unless otherwise stated, RLF = 1.8k, C

= 15nF, C

LF1

= 3.3pF

LF2

PARAMETER CONDITIONS MIN

SDO, SCO Output Signal

TYPICAL

1

MAX UNITS NOTES

75Ω DC load 600 800 1000 mV p-p 1

TEST

LEVEL

Swing

SDO, SCO Rise & Fall times 20%-80% 200 300 400 ps 7

SDI/SDI

Input Resistance - 10 - k

SDI/SDI

Input Capacitance - 1.0 - pF 8 6

SDI/SDI

Input Return Loss at 270MHz 15 20 - dB 8 6

Carrier Detect Response Time Carrier Applied,

<50pF, RL=open cct.

C

L

Carrier Removed,
C

<50pF, RL=open cct.

L

NOTES

1. TYPICAL - measured on EB9025A board.

2. Characterized 6 sigma rms.

3. IJT measured with sinusoidal modulation beyond Loop
Bandwidth (at 6.5MHz).

4. Synchronous switching refers to switching the input data from
one source to another source which is at the same data rate (ie.
line 10 switching for component NTSC).

5. Asynchronous switching refers to switching the input data from
one source to another source which is at a different data rate.

6. Carrier Loss Time refers to the response of the SDO output from
valid re-clocked input data to mute mode when the input signal
is removed.

7. Using the DDI input, A/D

8. Using the SDI input, A/D

=0.

=1.

-3 - µs86

-30 -

TEST LEVELS

1. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature
ranges.

2. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature ranges
using correlated test.

3. Production test at room temperature and nominal supply
voltage.

4. QA sample test.

5. Calculated result based on Level 1,2, or 3.

6. Not tested. Guaranteed by design simulations.

7. Not tested. Based on characterization of nominal parts.

8. Not tested. Based on existing design/characterization data
of similar product.

Ω

86

GS9025A

TEKTRONIX

GigaBERT

TRANSMITTER

GENNUM CORPORATION

1400

DATA

DATA

CLOCK

BELDEN 8281

GS9028

CABLE

DRIVER

CABLE

Fig. 1 Test Setup for Figures 6 - 13

4

EB9025A

BOARD

TEKTRONIX

GigaBERT

1400

ANALYZER

TRIGGER

522 - 75 - 00

PIN CONNECTIONS

DDI
DDI

V

_75

CC

V

CC

V
SDI

SDI

V
V

CD_ADJ

AGC-

EE

CC

EE

LFS

OSC

LOCK

C

EE

LF-

V

EE

V

_RTN
R

_75

CC

OEM_TEST

SMPTE

A/D

V

EE

SSI/CD

GS9025A

TOP VIEW

LF+

V

44 43 42 41 40 39 38 37 36 35 34

1
2
3
4
5
6
7
8
9
10
11

12 13 14 15 16 17 18 19 20 21 22

CC

V

AGC+

CLK_EN

R

VCO

VCO

CC

V

CBG

EE

V

GS9025A

33
32
31
30
29
28
27
26
25
24
23

CC

V

V

EE

SDO
SDO
V

EE

SCO
SCO
V

EE

AUTO/MAN
SS0

SS1
SS2

PIN DESCRIPTIONS

NUMBER SYMBOL TYPE DESCRIPTION

1, 2 DDI/DDI

3, 44 V

4, 8, 13, 22, 35 V

5, 9, 14, 18, 27,

_75 I Power supply connection for internal 75Ω pullup resistors connected to DDI/DDI.

CC

CC

V

EE

30, 33, 34, 37

6, 7 SDI/SDI

10 CD_ADJ I Carrier detect threshold adjust.

11, 12 AGC-, AGC+ I External AGC capacitor.

15 LF+ I Loop filter component connection.

16 LFS I Loop filter component connection.

17 LF- I Loop filter component connection.

19 R

20 R

_RTN I Frequency setting resistor return connection.

VCO

VCO

21 CBG I Internal bandgap voltage filter capacitor.

23, 24, 25 SS[2:0] I/O Data rate indication (auto mode) or data rate select (manual mode). TTL/CMOS

I Digital data inputs (Differential ECL/PECL).

I Most positive power supply connection.

I Most negative power supply connection.

I Differential analog data inputs.

I Frequency setting resistor connection.

compatible I/O. In auto mode, these pins can be left unconnected.

26 AUTO/MAN

GENNUM CORPORATION

I Auto or manual mode select. TTL/CMOS compatible input.

5

522 - 75 - 00

PIN DESCRIPTIONS (continued)

NUMBER SYMBOL TYPE DESCRIPTION

28, 29 SCO/SCO O Serial clock output. SCO/SCO are differential current mode outputs and require

31, 32 SDO/SDO

36 CLK_EN I Clock enable. When HIGH, the serial clock outputs are enabled.

38 COSC I Timing control capacitor for internal system clock.

39 LOCK O Lock indication. When HIGH, the GS9025A is locked. LOCK is an open collector output

40 SSI/CD

41 A/D

42 SMPTE I SMPTE/Other data rate select. TTL/CMOS compatible input.

43 OEM_TEST O Output ‘Eye’ monitor test. Single-ended current mode output that requires an external

external 75Ω pullup resistors.

O Equalized and reclocked serial digital data outputs. SDO/SDO are differential current

mode outputs and require external 75Ω pullup resistors.

and requires an external 10kΩ pullup resistor.

O Signal strength indicator/Carrier detect.

I Analog/Digital select.

50Ω pullup resistor. This feature is recommended for debugging purposes only. If
enabled during normal operation, the maximum operating temperature is rated to
60°C.

GS9025A

GENNUM CORPORATION

6

522 - 75 - 00