GENNUM GS9002 User Manual

GENLINX

Serial Digital Encoder

FEATURES DEVICE DESCRIPTION

™

GS9002

DATA SHEET

• fully compatible with SMPTE-259M serial digital
standard

• supports up to four serial bit rates to 400 Mb/s

• accepts 8 bit and 10 bit TTL and CMOS
compatible parallel data inputs

9

• X

+ X4 + 1 scrambler, NRZI converter and sync

detector may be disabled for transparent data

transmission

• pseudo-ECL serial data and clock outputs

• single +5 or -5 volt supply

• 713 mW typical power dissipation (including ECL

pull-down loads).

• 44 pin PLCC packaging

APPLICATIONS

•4ƒ

, 4:2:2 and 360 Mb/s serial digital interfaces for

SC

Video cameras, VTRs, Signal generators

ORDERING INFORMATION

Part Number Package Type Temperature Range

GS9002 - CPM 44 Pin PLCC 0° to 70°C

The GS9002 is a monolithic bipolar integrated circuit designed
to serialize SMPTE 125M and SMPTE 244M bit parallel digital
signals as well as other 8 or 10 bit parallel formats. This device
performs the functions of sync detection, parallel to serial
conversion, data scrambling (using the X

9

+ X4 +1 algorithm),
10x parallel clock multiplication and conversion of NRZ to
NRZI serial data. It supports any of four selectable serial data
rates from 100 Mb/s to over 360 Mb/s. The data rates are set
by resistors and are selected by an on-board 2:4 decoder
having two TTL level input address lines.

Other features such as a sync detector output, a sync detector
disable input, and a lock detect output are also provided. The

9

X

+ X4 + 1 scrambler and NRZ to NRZI converter may be
bypassed to allow the output of the parallel to serial converter
to be directly routed to the output drivers.

The GS9002 provides pseudo-ECL outputs for the serial data
and serial clock as well as a single-ended pseudo-ECL output
of the regenerated parallel clock.

The GS9002 directly interfaces with cable drivers GS9007,
GS9008 and GS9009. The device requires a single +5 volt or

-5 volt supply and typically consumes 713 mW of power while
driving 100 Ω loads. The 44 pin PLCC packaging assures a
small footprint for the complete encoder function.

SCRAMBLER/

SERIALIZER

SELECT

SYNC DETECT

DISABLE

PARALLEL DATA

IN (10 BITS)

NOT RECOMMENDED

PCLK IN

LOOP FILTER

PCLK OUT

26

3

6

7-16

17

22

19

INPUT
LATCH

FOR NEW DESIGNS

SYNC

DETECT

PLD

PHASE

FREQUENCY

DETECT

P/S

CONVERTER

CHARGE

PUMP

DIV BY 10

GENERATOR

SCRAMBLER

VCO

SCLK

NRZ

NRZI

DATA RATE

SWITCH

2:1 MUX

LOCK

DETECT

GS9002

Patent No.5,357,220

38

39

42

43

20

29

36

35

34
33
32
31

SYNC DETECT

SERIAL DATA

SERIAL DATA

SERIAL CLOCK

SERIAL CLOCK

LOCK DETECT

REGULATOR CAP

DRS0

DRS1

RVC00
RVC01
RVC02
RVC03

FUNCTIONAL BLOCK DIAGRAM

Revision Date: March 2001

GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. [phone] fax: [phone]

Gennum Japan Corporation C-101 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168-0081, Japan tel. [phone] fax [phone]

Document No. 520 - 27 - 08

GS9002 - ENCODER DC ELECTRICAL CHARACTERISTICS

V

= 5V, VEE = 0V, T

CC

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Supply Voltage V

Power Consumption P

Supply Current I

TTL Inputs-HIGH V

TTL Inputs-LOW V

Logic Input Current I

TTL Outputs-HIGH V

TTL Outputs-LOW V

= 0°C to 70°C unless otherwise shown

A

S

D

S

IHmin

ILmax

INmax

OHminTA

OLmaxTA

Operating Range 4.75 5.0 5.25 V

SDO/SDO connected to (V
thru 100Ω resistors, PCK OUT
connected to VEE via 1kΩ

Same as above with SCK/SCK
also connected to (VCC-2V)
thru 100Ω resistors.

SDO/SDO connected to (V
thru 100Ω resistors, PCK OUT
connected to V

Same as above with SCK/SCK
to (V

CC

TA = 25°C 2.0 - - V

T

= 25°C - - 0.8 V

A

= 25°C 2.4 - - V

= 25°C - - 0.5 V

EE

-2V) V thru 100Ω resistors. - 170 205 mA see Figure 15

via 1kΩ

-2V)

CC

-2V) - 155 190 mA

CC

- 690 870 mW

- 710 900 mW

- 2.5 10 µA

Sync Detect O/P I

Serial Outputs High V

(SDO & SCK) Low V

OSYNC

OH

OL

TA=25°C, RL=100Ω to VCC-2V -0.875 - -0.7 V
(V

-2V) -1.8 - -1.5 V

CC

- - 4.0 mA SINK & SOURCE

with respect to V

GS9002 - ENCODER AC ELECTRICAL CHARACTERISTICS

V

= 5V, VEE = 0V, T

CC

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES

Serial Data Outputs bit rates BR

(SDO and SDO)

Serial Clock Outputs frequency ƒ
(SCK and SCK)

Serial Data to Clock Timing t

NOT RECOMMENDED

Lock Time t

Parallel Clock Output frequency ƒ

(PCK OUT)

Parallel Data & Clock Inputs

= 0°C to 70°C, V

A

signal swing V

rise/fall times tR, t

jitter t

signal swing V

LOOP FILTER

FOR NEW DESIGNS

signal swing V

rise/fall times tR, t
jitter t

risetime t

setup t

hold t

=2.6 V unless otherwise shown,

SDO

SDO

J(SDO)

SCK

SCK

D

LOCK

PCKO

PCKO

JPCKO

R

SU

HOLD

RL = 100Ω to 100 - 400 Mb/s
(V

-2 volts)

CC

TA = 25°C

F

143 Mb/s - 400 - ps p-p see Note 1
270 Mb/s - 300 - ps p-p see Fig. 16

RL = 100Ω to 100 - 400 MHz see Fig. 12, 13
(V

-2 volts)

CC

See Figure 9 - 1.4 - ns Data lags Clock

C

LOOP FILT

R

LOOP FILT

RL = 1kΩ to V

F

TA = 25°C 500 - - ps

= 0.1µF - 1 1.2 ms
= 3.9kΩ

EE

700 850 1000 mV p-p

- 500 - ps 20% - 80%

- 800 - mV p-p see Fig. 14

10 - 40 MHz ƒ

- 800 - mV p-p

- 700 - ps 20% - 80%

- 400 - ps p-p

3--ns

3--ns

PCKO

= ƒ

CC

SCK

/10

NOTE 1: Measured using PCK-IN as trigger source on 1GHz analog oscilloscope.

520 - 27 - 08

2

ABSOLUTE MAXIMUM RATINGS

PARAMETER VALUE/UNITS

Supply Voltage 5.5 V
Input Voltage Range (any input) -V
DC Input Current (any one input) 10 mA
Power Dissipation (V
Operating Temperature Range 0°C ≤ TA ≤ 70°C
Storage Temperature Range -65°C ≤ TS ≤150°C
Lead Temperature (soldering 10 seconds) 260°C

SYNC
DET.
DIS.

V

CC1VEE

SYNC
DET.

= 5.25 V) 1 W

S

V

CC3VEEVEE

SCK SCK

< VI < V

EE

CC

a

V

V

CC2

b

CC2

6 5 4 3 2 44 43 42 41 40

PD0

PD1

PD2

PARALLEL
DATA
INPUTS

NOT RECOMMENDED

PD3

PD4

PD5

PD6

PD7

PD8

PD9

7

8

9

10

11

12

13

14

15

16

GS9002
TOP VIEW

39

38

37

36

35

34

33

32

31

30

SDO

SDO

V

EE

DRS0

DRS1

RVC00

RVC01

RVC02

RVC03

V

EE

VCO
FREQUENCY
SET
RESISTORS

FOR NEW DESIGNS

PCK IN

17

18 19 20 21 22 23 24 25 26 27 28

29

C. REG

EE

OUT

DET.

LOCK

PCK

V

LOOP

V

CC3

FILT.

NC

V

EE

EE

SSSV

V

V

CC3

EE

Fig. 1 GS9002 Encoder Pin Connections

3

520 - 27 - 08

GS9002 Serial Digital Encoder - Detailed Device Description

The GS9002 Encoder is a bipolar integrated circuit used to
convert parallel data into a serial format according to the
SMPTE 259M standard. The device encodes both eight and
ten bit TTL-compatible parallel signals producing serial data
rates up to 400 Mb/s. It operates from a single five volt supply
and is packaged in a 44 pin PLCC.

Functional blocks within the device include the input latches,
sync detector, parallel to serial converter, scrambler, NRZ to
NRZI converter, ECL output buffers for data and clock, PLL for
10x parallel clock multiplication and lock detect.

The parallel data (PD0-PD9) and parallel clock (PCK-IN) are
applied via pins 7 through 17 respectively.

Sync Detector

The Sync Detector looks for the reserved words 000-003 and
3FC-3FF, in ten bit Hex, or 00 and FF in eight bit Hex, used in
the TRS-ID sync word. When the occurrence of either all zeros
or ones at inputs PD2-PD9 is detected, the lower two bits PD0
and PD1 are forced to zeros or ones, respectively. This makes
the system compatible with eight or ten bit data. For non ­SMPTE standard parallel data, a logic input, Sync Disable (6)
is available to disable this feature.

VCO Centre Frequency Selection

The wide VCO pull range allows the PLL to compensate for
variations in device processing, temperature variations and
changes in power supply voltage, without external adjustment.
A single external resistor is used to set the VCO current for
each of four centre frequencies as selected by a two bit code
through a 2:4 decoder.

The current setting resistors are connected to the RVCO0
through RVCO3 inputs (34, 33, 32 and 31). The decoder
inputs DRS0 and DRS1 (36, 35) are TTL compatible inputs
and select the four resistors according to the following truth
table.

DRS1 DRS0 Resistor Selected

0 0 RVCO0 (34)

0 1 RVCO1 (33)

1 0 RVCO2 (32)

1 1 RVCO3 (31)

Scrambler

The Scrambler is a linear feedback shift register used to
pseudo-randomize the incoming serial data according to the
fixed polynomial (X
in the output serial data stream. The NRZ to NRZI converter
uses another polynomial (X+1) to convert a long sequence of
ones to a series of transitions, minimizing polarity effects.

Phase Locked Loop

The PLL performs parallel clock multiplication and provides
the timing signal for the serializer. It is composed of
a phase/frequency detector, charge pump, VCO and a
divide-by-ten counter.

The phase/frequency detector allows a wider capture range
and faster lock time than that which can be achieved with a
phase discriminator alone. The discrimination of frequency
also eliminates harmonic locking. With this type of discriminator,
the PLL can be over-damped for good stability without
sacrificing lock time.

The charge pump delivers a 'charge packet' to the loop filter
which is proportional to the system phase error. Internal
voltage clamps are used to constrain the loop filter voltage
between approximately 1.8 and 3.4 volts.

NOT RECOMMENDED

9+X4

+1). This minimizes the DC component

FOR NEW DESIGNS

A 2:1 multiplexer (MUX) selects either the direct data from the
P/S Converter (Serializer) or the NRZI data from the Scrambler.
This MUX is controlled by the Scrambler/Serializer Select
(SSS) input pin 26. When this input is LOW the MUX selects
the Scrambler output. (This is the mode used for SMPTE
259M data). When this input is HIGH the MUX directly routes
the serialized data to the output buffer with no scrambling or
NRZ to NRZI

The lock detect circuit disables the serial data output when the
loop is not locked by turning off the 2:1 MUX. The Lock Detect
output is available from pin 20 and is HIGH when the loop is
locked.

The true and complement serial data, SDO and SDO are
available from pins 38 and 39 while the true and complement
serial clock, SCK and SCK are available from pins 43 and 42
respectively. If the serial clock is not used pins 43 and 42 can
be connected to V

The regenerated parallel clock (PCK OUT) is available at pin

19. This output is a single ended pseudo-ECL output requiring
a pull down resistor. If regenerated parallel clock is not used
pin 19 can be connected to V

conversion.

.

CC

CC

.

The VCO, constructed from a current-controlled multivibrator,
features operation in excess of 400 Mb/s and a wide pull range
(≈±40% of centre frequency).

520 - 27 - 08

4