GENNUM GS4915 User Manual
GS4915 ClockCleaner™
GS4915 Data Sheet
Key Features
• Reduces jitter for clocks of 148.5MHz,
148.5/1.001MHz, 74.25MHz, 74.25/1.001MHz and
27MHz
• Output jitter as low as 20ps peak to peak
• Automatic bypass mode for all other clock rates
• Loop bandwidth adjustable as low as 2kHz
• Output skew control
• Input selectable as differential or single-ended
• Both single-ended and differential outputs
• Uses the GO1555 VCO
• Small 6mm x 6mm 40-pin QFN package
• Pb-free and RoHS compliant
Applications
High definition video systems. Digital video recording,
playback, processing and display devices.
Description
The GS4915 provides a low jitter clock output when fed
with an HD or SD video clock input. Other input clock
frequencies between 12MHz and 165MHz can be
automatically passed through to the GS4915 outputs.
An internal 2:1 mux allows the user to select between a
differential or single-ended (LVCMOS) input clock. Both
a single-ended LVCMOS- compatible and an
LVDS-compatible differential output are provided.
The GS4915 may operate in either auto or fixed
frequency mode. In auto mode, the device will
automatically clean the selected input clock if its
frequency is found to be one of the supported SD or HD
clock rates. In fixed mode, the user selects only one of
these frequencies to be cleaned.
In addition, the device allows the user to select between
auto or manual bypass operation. In autobypass mode,
the GS4915 will automatically bypass its cleaning stage
and pass the input clock signal directly to the output
whenever the device is unlocked, which includes the
case where the input frequency is something other than
the five frequencies supported. In manual bypass
mode, the input signal passes through directly to the
output.
The GS4915 can optionally double the output frequency
for 74.25MHz or 74.175MHz HD clocks in order to
provide optimal jitter performance of some serializers.
The GS4915 also provides the user with a 2-state skew
control. The output clocks produced by the device may
be advanced by ¼ of an output CLK period in order to
accommodate downstream setup and hold
requirements.
The GS4915 is designed to operate with the GO1555
VCO.
The GS4915 Clock Cleaner complements Gennum's
GS4911B Clock and Timing Generator for
implementing a video genlock solution. Whereas the
GS4911B itself cleans low-frequency jitter, the GS4915
is designed to clean primarily the higher frequency jitter
of clocks generated by the GS4911B.
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Functional Block Diagram
2.5V Regulator
Phase
Detector
Charge
Pump
Divide
by N
Skew
Select
Digital Control Block
Frequency
Detection
DIFF I/P
Buffer
S-E I/P
Buffer
Clock Cleaning PLL
DIFF O/P
Buffer
S-E O/P
Buffer
CLKIN
CLKIN
CLKIN_SE
IPSEL
CLKOUT_SE
CLKOUT
CLKOUT
SKEW_EN
BYPASS
AUTOBYPASS
FCTRL[1:0]
DOUBLE
REG_VDD
VCO_VDD
CP_VDD
LF
VCO
Receiver
VCO
CP_RES
LOCK
clkout
clkin
bypass
RESET
VCO
0
1
0
1
GS4915 Data Sheet
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GS4915 Functional Block Diagram
GS4915 Data Sheet
Contents
Key Features.................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
Functional Block Diagram .............................................................................................2
1. Pin Out ......................................................................................................................4
1.1 Pin Assignment ...............................................................................................4
1.2 Pin Descriptions ..............................................................................................5
2. Electrical Characteristics...........................................................................................8
2.1 Absolute Maximum Ratings ............................................................................8
2.2 DC Electrical Characteristics ..........................................................................8
2.3 AC Electrical Characteristics .........................................................................10
2.4 Solder Reflow Profiles ...................................................................................11
3. Detailed Description ................................................................................................12
3.1 Functional Overview .....................................................................................12
3.2 Clock Inputs ..................................................................................................12
3.2.1 Differential Clock Input.........................................................................13
3.2.2 Single-Ended Clock Input ....................................................................13
3.2.3 Input Clock Selection ...........................................................................13
3.2.4 Unused Clock Inputs............................................................................13
3.3 Clock Cleaning PLL ......................................................................................13
3.3.1 Phase Detector ....................................................................................14
3.3.2 Charge Pump.......................................................................................14
3.3.3 Loop Filter............................................................................................14
3.3.4 External VCO.......................................................................................15
3.4 Modes of Operation ......................................................................................15
3.4.1 Frequency Modes ................................................................................15
3.4.2 Bypass Modes .....................................................................................17
3.5 Output Clock Frequency and Jitter ...............................................................18
3.6 Output Skew .................................................................................................20
3.7 Clock Outputs ...............................................................................................21
3.7.1 Differential Clock Output......................................................................21
3.7.2 Single-Ended Clock Output .................................................................21
3.8 Device Reset .................................................................................................21
3.8.1 Hardware Reset...................................................................................21
4. Typical Application Circuit .......................................................................................22
5. References & Relevant Standards..........................................................................23
6. Package & Ordering Information.............................................................................24
6.1 Package Dimensions ....................................................................................24
6.2 Recommended PCB Footprint ......................................................................25
6.3 Packaging Data .............................................................................................25
6.4 Ordering Information .....................................................................................25
7. Revision History ......................................................................................................26
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1. Pin Out
AGND
VCO_ VDD
CP_ VDD
CP_ RES
LF
VCO_ GND
VCO
VCO
DIV_VDD
AGND
REG_VDD
AGND
PD_VDD
CLKIN
CLKIN
AGND
IN_VDD
CLKIN_SE
AGND
RESET
GS4915
40-pin QFN
(Top View )
AGND
CLKOUT
DIFF_OUT_VDD
AGND
D_VDD
CLKOUT_SE
SE_ VDD
GND
LOCK
IPSEL
GND
BYPASS
AUTOBYPASS
D_ V DD
FCTRL0
FCTRL1
DOUBLE
SKEW_EN
GND
1
2
3
4
5
6
7
8
9
10 21
22
23
24
25
26
27
28
29
30
31323334353637383940
11 12 13 14 15 16 17 18 19 20
Ground Pad
(Bottom of Package)
CLKOUT
1.1 Pin Assignment
GS4915 Data Sheet
Figure 1-1: 40-Pin QFN
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1.2 Pin Descriptions
Table 1-1: Pin Descriptions
GS4915 Data Sheet
Pin
Name Timing Type Description
Number
1 REG_VDD – Power Positive power supply connection for the internal voltage regulator.
Connect to filtered +3.3V DC.
2, 6, 9, 26,
30, 31, 40
3 PD_VDD – Power Positive power supply connection for the phase detector. Connect to
4, 5 CLKIN, CLKIN
7 IN_VDD – Power Positive power supply connection for the single-ended and differential
8 CLKIN_SE – Input CLOCK SIGNAL INPUT
10 RESET
11 IPSEL Non
AGND – Power Ground connection for analog blocks and IO’s. Connect to clean analog
– Input CLOCK SIGNAL INPUTS
Non
synchronous
synchronous
Input CONTROL SIGNAL INPUT
Input CONTROL SIGNAL INPUT
GND.
filtered +1.8V DC.
Signal levels are CML/LVDS compatible.
A differential clock input signal is applied to these pins.
input clock buffers. Supplies CLKIN_SE. Connect to filtered +1.8V DC.
Signal levels are LVCMOS compatible.
A single-ended video clock input signal is applied to this pin.
Signal levels are LVCMOS/LVTTL compatible.
See Section 3.8.1 for operation.
Signal levels are LVCMOS compatible.
Selects which input clock is cleaned by the device.
See Section 3.2.3 for operation.
12, 20, 22 GND – Power Ground connection for digital blocks and IO’s. Connect to GND.
13 BYPASS Non
synchronous
14 AUTOBYPASS
15 D_VDD – Power Positive power supply connection for digital block. Connect to filtered
17, 16 FCTRL1, FCTRL0 Non
Non
synchronous
synchronous
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Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS compatible.
See Manual Bypass Section 3.4.2.
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS compatible.
Selects the bypass mode of the device.
See Manual Bypass Section 3.4.2.
+1.8V DC. The digital block includes pins 10 - 21.
Input CONTROL SIGNAL INPUTS
Signal levels are LVCMOS compatible.
Selects the frequency mode of the device.
See Section 3.4.1 for operation.
Table 1-1: Pin Descriptions (Continued)
GS4915 Data Sheet
Pin
Name Timing Type Description
Number
18 DOUBLE Non
synchronous
19 SKEW_EN Non
synchronous
21 LOCK Non
synchronous
23 SE_VDD – Power Positive power supply connection for the single-ended clock driver.
24 CLKOUT_SE – Output CLOCK SIGNAL OUTPUT
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS compatible.
Controls the output frequency of the cleaned clock, for HD input clocks.
See Section 3.5 for operation.
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS compatible.
Selects the phase of the output clock with respect to the selected input
clock.
See Section 3.6 for operation.
Output STATUS SIGNAL OUTPUT
Signal levels are LVCMOS compatible.
This pin will be HIGH when the output clock is locked to the selected input
clock.
It will be LOW otherwise.
Determines the output level of CLKOUT_SE. Connect to filtered +1.8V DC
or +3.3V DC.
NOTE: If the single-ended clock output is not used, this pin should be tied
to ground.
Signal levels are LVCMOS compatible.
Single-ended video clock output signal.
See Section 3.7.2 for operation.
25 D_VDD – Power Positive power supply connection for the single-ended output clock buffer.
27 DIFF_OUT_VDD – Power Positive power supply connection for the LVDS clock outputs. Connect to
29, 28 CLKOUT,
CLKOUT
32 DIV_VDD – Power Positive power supply connection for the divider block. Connect to filtered
33,34 VCO, VCO
35 VCO_GND – Power Ground reference for the external voltage controlled oscillator. Connect to
– Output CLOCK SIGNAL OUTPUT
Analog Input Differential input for the external VCO reference signal. When using the
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Connect to filtered +1.8V DC.
NOTE: If the single-ended clock output is not used, this pin should be tied
to ground.
filtered +1.8V DC.
NOTE: If the LVDS clock outputs are not used, this pin should be tied to
ground.
Differential video clock output signal.
This is the lowest jitter output of the device.
See Section 3.7.1 for operation.
+1.8V DC.
recommended VCO, leave VCO
See Section 3.3.4 for operation.
pins 2, 4, 6, and 8 of the GO1555.
unconnected.
Table 1-1: Pin Descriptions (Continued)
GS4915 Data Sheet
Pin
Name Timing Type Description
Number
36 LF Analog Output Control voltage for the external voltage controlled oscillator. Connect to pin
5 of the GO1555 via a low pass filter. See Typical Application Circuit on
page 22.
37 CP_RES Analog Input Charge pump current control.
Connect to VCO_GND via a 10kΩ resistor.
38 CP_VDD – Power Power supply for the internal charge pump block (nominally +2.5V DC).
Connect to VCO_VDD (pin 39).
39 VCO_VDD – Power Power supply for the external voltage controlled oscillator (+2.5V DC).
Connect to pin 7 of the GO1555. This pin is an output.
Must be isolated from all other power supplies.
– Ground Pad – Power Ground pad on bottom of package must be soldered to AGND plane of
PCB.
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Parameter Value
GS4915 Data Sheet
Supply Voltage (SE_VDD, REG_VDD) -0.3 to +4.0 V
Core Supply Voltage (all 1.8V supplies) -0.3 to +2.2 V
Input ESD Voltage 1 kV HBM
Storage Temperature -50ºC < T
Operating Temperature -20ºC < T
NOTE: Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions or at any other condition beyond those
indicated in the AC/DC Electrical Characteristic sections is not implied.
DC
DC
< 125ºC
S
< 85ºC
A
2.2 DC Electrical Characteristics
Table 2-1: DC Electrical Characteristics
VDD = 1.8V ±5%, 3.3V ±5%; TA = -20ºC to 85ºC, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Notes
Operating Temperature Range T
Power Consumption
(SE_VDD = 1.8V Nominal)
A
P
1.8V
– -20 25 85 ºC –
1.8V Rail – 156 270 mW –
3.3V Rail – 58 87 mW –
Power Consumption
(SE_VDD = 3.3V Nominal)
+1.8V Power Supply Voltage – – 1.71 1.8 1.89 V –
+3.3V Power Supply Voltage – – 3.135 3.3 3.465 V –
+2.5V Regulator Output Voltage – Output load of 3-12mA 2.375 2.5 2.625 V –
Input Voltage, Logic LOW V
Input Voltage, Logic HIGH V
Output Voltage, Logic LOW V
Output Voltage, Logic HIGH V
P
3.3V
IL
IH
OL
OH
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1.8V Rail – 132 243 mW –
3.3V Rail – 133 156 mW –
– – 0 0.35 x
IO_VDD
– 0.65 x
IO_VDD
1.8V or 3.3V operation – 0 0.4 V 2,3,5
1.8V operation 0.65 x
IO_VDD
3.3V operation 0.65 x
IO_VDD
1.8 – V 1,5
1.8 – V 2,3,5
3.3 – V 2,3,5
V1,5
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