GENNUM GS4911B, GS4910B User Manual
GS4911B/GS4910B
HD/SD/Graphics Clock and
Timing Generator with GENLOCK
GS4911B/GS4910B Data Sheet
Key Features
Video Clock Synthesis
• Generates any video or graphics clock up to 165MHz
• Pre-programmed for 8 video and 13 graphics clocks
• Accuracy of free-running clock frequency limited only by
crystal reference
• One differential and two single-ended video/graphics
clock outputs
• Each clock may be individually delayed for skew control
• Video output clock may be directly connected to
Gennum’s serializers for a SMPTE-compliant HD-SDI
output
Audio Clock Synthesis (GS4911B only)
• Three audio clock outputs
• Generates any audio clock up to 512*96kHz
• Pre-programmed for 7 audio clocks
Timing Generation
• Generates up to 8 timing signals at a time
• Choose from 9 pre-programmed timing signals: H and V
sync and blanking, F Sync, F Digital, AFS (GS4911B
only), Display Enable, 10FID, and up to 4 user-defined
timing signals
• Pre-programmed to generate timing for 35 different video
formats and 13 different graphic display formats
Genlock Capability
• Clocks may be free-running or genlocked to an input
reference with a variable offset step size of 100-200ps
(depending on exact clock frequency)
• Variable timing offset step size of 100-200ps up to one
frame
• Output may be cross-locked to a different input reference
• Freeze operation on loss of reference
• Optional crash or drift lock on application of reference
• Automatic input format detection
General Features
• Reduces design complexity and saves board space 9mm x 9mm package plus crystal reference replaces
multiple VCXOs, PLLs and timing generators
• Pb-free and RoHS Compliant
• Low power operation typically 300mW
• 1.8V core and 1.8V or 3.3V I/O power supplies
• 64-PIN QFN package
Applications
• Video cameras; Digital audio and/or video recording/play
back devices; Digital audio and/or video processing
devices; Computer/video displays; DVD/MPEG devices;
Digital Set top boxes; Video projectors; High definition
video systems; Multi-media PC applications
Description
The GS4911B is a highly flexible, digitally controlled
clock synthesis circuit and timing generator with
genlock capability. It can be used to generate video and
audio clocks and timing signals, and allows multiple
devices to be genlocked to an input reference.
The GS4910B includes all the features of the GS4911B,
but does not offer audio clocks or AFS pulse generation.
The GS4911B/GS4910B will recognize input reference
signals conforming to 36 different video standards and
16 different graphic formats, and will genlock the output
timing information to the incoming reference. The
GS4911B/GS4910B supports cross-locking, allowing
the output to be genlocked to an incoming reference
that is different from the output video standard selected.
The user may select to output one of 8 different video
sample clock rates or 13 different graphic display clock
rates, or may program any clock frequency between
13.5MHz and 165MHz. The chosen clock frequency
can be further divided using internal dividers, and is
available on two video clock outputs and one LVDS
video clock output pair. The video clocks are frequency
and phased-locked to the horizontal timing reference,
and can be individually delayed with respect to the
timing outputs for clock skew control.
Eight user-selectable timing outputs are provided that
can automatically produce the following timing signals
for 35 different video formats and 13 different graphics
formats: HSync, Hblanking, VSync, Vblanking, F sync,
F digital, AFS (GS4911B only), DE, and 10FID. These
timing outputs may be locked to the input reference
signal for genlock timing and may be phase adjusted via
internal registers.
In addition, the GS4911B provides three audio sample
clock outputs that can produce audio clocks up to 512fs
with fs ranging from 9.7kHz to 96kHz. Audio to video
phasing is accomplished by an external 10FID input
reference, a 10FID signal specified via internal
registers, or a user-programmed audio frame
sequence.
The GS4911B/GS4910B is Pb-free, and the
encapsulation compound does not contain halogenated
flame retardant (RoHS Compliant).
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www.gennum.com
X1
ASR_SEL[2:0]
X2
VID_STD[5:0]
GENLOCK
GS4911B/GS4910B Data Sheet
LOCK_LOST
REF_LOST
HSYNC
VSYNC
FSYNC
10FID
Input Reference
Rate Identification
and Control
27MHz
ref_rate
Clock Synthesis
and Control
Clock
Phase
Adjust
Application Programming Interace
Flywheel and Video
Timing Generator
pclk
aclk_512
aclk_384
user[4:1]
AFS
10FID
DE
F digital
F sync
V blanking
V sync
H blanking
H sync
Video Clock
Divide
Audio Clock
Divide
Crosspoint
3x Video Clock
Delay Adjust
TIMING_OUT_8
TIMING_OUT_7
TIMING_OUT_6
TIMING_OUT_5
TIMING_OUT_4
TIMING_OUT_3
TIMING_OUT_2
TIMING_OUT_1
PCLK1
PCLK2
PCLK3
PCLK3
ACLK1
ACLK2
ACLK3
JTAG/HOST
SDIN_TDI
SCLK_TCLK
SDOUT_TDO
CS_TMS
GS4911B Functional Block Diagram
36655 - 4 April 2007 2 of 113
GS4911B/GS4910B Data Sheet
VID_STD[5:0]
X1
X2
GENLOCK
LOCK_LOST
REF_LOST
HSYNC
VSYNC
FSYNC
10FID
Input Reference
Rate Identification
and Control
27MHz
ref_rate
Clock Synthesis
and Control
Clock
Phase
Adjust
Application Programming Interace
Flywheel and Video
Timing Generator
pclk
user[4:1]
10FID
DE
F digital
F sync
V blanking
V sync
H blanking
H sync
Video Clock
Divide
Crosspoint
3x Video Clock
Delay Adjust
TIMING_OUT_8
TIMING_OUT_7
TIMING_OUT_6
TIMING_OUT_5
TIMING_OUT_4
TIMING_OUT_3
TIMING_OUT_2
TIMING_OUT_1
PCLK1
PCLK2
PCLK3
PCLK3
JTAG/HOST
SDIN_TDI
SCLK_TCLK
SDOUT_TDO
CS_TMS
GS4910B Functional Block Diagram
36655 - 4 April 2007 3 of 113
GS4911B/GS4910B Data Sheet
Contents
Key Features.................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
1. Pin Out ......................................................................................................................8
1.1 GS4911B Pin Assignment ..............................................................................8
1.2 GS4910B Pin Assignment ..............................................................................9
1.3 Pin Descriptions ............................................................................................10
1.4 Pre-Programmed Recognized Video and Graphics Standards ....................20
1.5 Output Timing Signals ...................................................................................25
2. Electrical Characteristics.........................................................................................29
2.1 Absolute Maximum Ratings ..........................................................................29
2.2 DC Electrical Characteristics ........................................................................29
2.3 AC Electrical Characteristics .........................................................................31
2.4 Solder Reflow Profiles ...................................................................................35
3. Detailed Description ................................................................................................36
3.1 Functional Overview .....................................................................................36
3.2 Modes of Operation ......................................................................................36
3.2.1 Genlock Mode......................................................................................37
3.2.2 Free Run Mode....................................................................................40
3.3 Output Timing Format Selection ...................................................................42
3.4 Input Reference Signals ................................................................................43
3.4.1 HSYNC, VSYNC, and FSYNC.............................................................43
3.4.2 10FID ...................................................................................................44
3.4.3 Automatic Polarity Recognition............................................................45
3.5 Reference Format Detector ..........................................................................45
3.5.1 Horizontal and Vertical Timing Characteristic Measurements .............45
3.5.2 Input Reference Validity.......................................................................45
3.5.3 Behaviour on Loss and Re-acquisition of the Reference Signal..........47
3.5.4 Allowable Frequency Drift on the Reference .......................................49
3.6 Genlock .........................................................................................................50
3.6.1 Automatic Locking Process .................................................................50
3.6.2 Manual Locking Process......................................................................54
3.6.3 Adjustable Locking Time......................................................................58
3.6.4 Adjustable Loop Bandwidth .................................................................58
3.6.5 Locking to Digital Timing from a Deserializer ......................................60
3.7 Clock Synthesis ............................................................................................61
3.7.1 Video Clock Synthesis .........................................................................61
3.7.2 Audio Clock Synthesis (GS4911B only) ..............................................63
3.8 Video Timing Generator ................................................................................67
3.8.1 10 Field ID Pulse .................................................................................67
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GS4911B/GS4910B Data Sheet
3.8.2 Audio Frame Synchronizing Pulse (GS4911B only) ............................68
3.8.3 USER_1~4...........................................................................................69
3.8.4 TIMING_OUT Pins...............................................................................71
3.9 Custom Clock Generation .............................................................................72
3.9.1 Programming a Custom Video Clock...................................................72
3.9.2 Programming a Custom Audio Clock (GS4911B only) ........................73
3.10 Custom Output Timing Signal Generation ..................................................74
3.10.1 Custom Input Reference....................................................................74
3.11 Extended Audio Mode for HD Demux using the Gennum Audio Core .......75
3.12 GSPI Host Interface ....................................................................................76
3.12.1 Command Word Description..............................................................77
3.12.2 Data Read and Write Timing .............................................................77
3.12.3 Configuration and Status Registers ...................................................79
3.13 JTAG .........................................................................................................105
3.14 Device Power-Up ......................................................................................106
3.14.1 Power Supply Sequencing...............................................................106
3.15 Device Reset .............................................................................................106
4. Application Reference Design ...............................................................................107
4.1 GS4911B Typical Application Circuit ..........................................................107
4.2 GS4910B Typical Application Circuit ..........................................................108
5. References & Relevant Standards........................................................................109
6. Package & Ordering Information...........................................................................110
6.1 Package Dimensions ..................................................................................110
6.2 Recommended PCB Footprint ....................................................................111
6.3 Packaging Data ...........................................................................................111
6.4 Ordering Information ...................................................................................112
7. Revision History ....................................................................................................113
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GS4911B/GS4910B Data Sheet
List of Figures
GS4911B Functional Block Diagram........................................................................... 2
GS4910B Functional Block Diagram........................................................................... 3
Figure 1-1: XTAL1 and XTAL2 Reference Circuits ....................................................19
Figure 2-1: PCLK to TIMING_OUT Signal Output Timing ..........................................34
Figure 2-2: Maximum Pb-free Solder Reflow Profile (preferred) ................................35
Figure 2-3: Standard Pb Solder Reflow Profile .........................................................35
Figure 3-1: HD-SD Calculation ...................................................................................39
Figure 3-2: Output Accuracy and Modes of Operation ...............................................41
Figure 3-3: Example HSYNC, VSYNC, and FSYNC Analog Input Timing from
a Sync Separator .......................................................................................................43
Figure 3-4: Example H Blanking, V Blanking, and F Digital Input Timing from
an SDI Deserializer ....................................................................................................43
Figure 3-5: 10FID Input Timing ..................................................................................44
Figure 3-6: Internal Video Genlock Block ...................................................................54
Figure 3-7: Internal Audio Genlock Block ...................................................................56
Figure 3-8: Default 10FID Output Timing ...................................................................67
Figure 3-9: Optional 10FID Output Timing .................................................................68
Figure 3-10: AFS Output Timing ................................................................................69
Figure 3-11: USER Programmable Output Signal .....................................................70
Figure 3-12: Custom Timing Parameters ...................................................................74
Figure 3-13: Audio Clock Block Diagram for HD Demux Operation ...........................75
Figure 3-14: GSPI Application Interface Connection .................................................76
Figure 3-15: Command Word Format ........................................................................77
Figure 3-16: Data Word Format .................................................................................77
Figure 3-17: GSPI Read Mode Timing .......................................................................78
Figure 3-18: GSPI Write Mode Timing .......................................................................78
Figure 3-19: In-Circuit JTAG ....................................................................................105
Figure 3-20: System JTAG .......................................................................................106
36655 - 4 April 2007 6 of 113
GS4911B/GS4910B Data Sheet
List of Tables
Table 1-1: Pin Descriptions ........................................................................................ 10
Table 1-2: Recognized Video and Graphics Standards ............................................. 21
Table 1-3: Output Timing Signals............................................................................... 25
Table 2-1: DC Electrical Characteristics .................................................................... 29
Table 2-2: AC Electrical Characteristics..................................................................... 31
Table 2-3: Suggested External Crystal Specification ................................................. 34
Table 3-1: Clock_Phase_Offset[15:0] Encoding Scheme .......................................... 38
Table 3-2: Ambiguous Standard Identification ........................................................... 47
Table 3-3: Max_Ref_Delta Encoding Scheme ........................................................... 49
Table 3-4: Cross-reference Genlock Table ................................................................ 52
Table 3-5: Integer Constant Value ............................................................................. 57
Table 3-6: Video Clock Phase Adjustment Host Settings .......................................... 62
Table 3-7: Audio Sample Rate Select ........................................................................ 63
Table 3-8: Audio Clock Divider................................................................................... 64
Table 3-9: Encoding Scheme for AFS_Reset_Window ............................................. 65
Table 3-10: Audio Sampling Frequency to Video Frame Rate Synchronization ........ 66
Table 3-11: Crosspoint Select.................................................................................... 71
Table 3-12: GSPI Timing Parameters ........................................................................ 78
Table 3-13: Configuration and Status Registers ........................................................ 79
Table 5-1: References & Relevant Standards.......................................................... 109
36655 - 4 April 2007 7 of 113
1. Pin Out
1.1 GS4911B Pin Assignment
LOCK_LOST
REF_LOST
VID_PLL_VDD
VID_PLL_GND
XTAL_VDD
X1
X2
XTAL_GND
CORE_GND
ANALOG_VDD
NC
ANALOG_GND
AUD_PLL_GND
AUD_PLL_VDD
10FID
HSYNC
GENLOCK
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18 19 20 21 23 24 25 26 27 28 29 30 3122
17
IO_VDD
6263
61
RESET
CS_TMS
JTAG/HOST
SDIN_TDI
SCLK_TCLK
SDOUT_TDO
GS4911B
64-pin QFN
(Top View)
PhS_GND
PhS_VDD
PCLK1&2_VDD
GS4911B/GS4910B Data Sheet
PCLK1
IO_VDD
PCLK1&2_GND
PCLK2
4964
5051525354555657585960
32
LVDS/PCLK3_GND
48
PCLK3
47
PCLK3
46
LVDS/PCLK3_VDD
45
44
CORE_VDD
TIMING_OUT_8
43
TIMING_OUT_7
42
TIMING_OUT_6
41
TIMING_OUT_5
40
TIMING_OUT_4
39
IO_VDD
38
TIMING_OUT_3
37
TIMING_OUT_2
36
TIMING_OUT_1
35
ASR_SEL0
34
33
ASR_SEL1
Ground Pad
(bottom of package)
36655 - 4 April 2007 8 of 113
IO_VDD
VSYNC
FSYNC
NC
VID_STD0
VID_STD2
VID_STD1
CORE_VDD
VID_STD4
VID_STD3
ACLK2
ACLK1
VID_STD5
IO_VDD
ACLK3
ASR_SEL2
1.2 GS4910B Pin Assignment
LOCK_LOST
REF_LOST
VID_PLL_VDD
VID_PLL_GND
XTAL_VDD
X1
X2
XTAL_GND
CORE_GND
ANALOG_VDD
NC
ANALOG_GND
ANALOG_GND
ANALOG_GND
10FID
HSYNC
GENLOCK
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18 19 20 21 23 24 25 26 27 28 29 30 3122
17
IO_VDD
6263
61
RESET
CS_TMS
JTAG/HOST
SDIN_TDI
SCLK_TCLK
SDOUT_TDO
GS4910B
64-pin QFN
(Top View)
PhS_GND
PhS_VDD
PCLK1&2_VDD
GS4911B/GS4910B Data Sheet
PCLK1
IO_VDD
PCLK1&2_GND
PCLK2
4964
5051525354555657585960
32
LVDS/PCLK3_GND
48
PCLK3
47
PCLK3
46
LVDS/PCLK3_VDD
45
44
CORE_VDD
TIMING_OUT_8
43
TIMING_OUT_7
42
TIMING_OUT_6
41
TIMING_OUT_5
40
TIMING_OUT_4
39
IO_VDD
38
TIMING_OUT_3
37
TIMING_OUT_2
36
TIMING_OUT_1
35
34
ANALOG_GND
33
ANALOG_GND
Ground Pad
(bottom of package)
IO_VDD
VSYNC
FSYNC
NC
VID_STD0
VID_STD2
VID_STD1
CORE_VDD
VID_STD4
VID_STD3
NC
NC
VID_STD5
NC
IO_VDD
ANALOG_GND
36655 - 4 April 2007 9 of 113
1.3 Pin Descriptions
Table 1-1: Pin Descriptions
Pin Number Name Timing Type Description
GS4911B/GS4910B Data Sheet
1 LOCK_LOST Non
Synchronous
2 REF_LOST Non
Synchronous
3 VID_PLL_VDD – Power
4 VID_PLL_GND – Power
5 XTAL_VDD – Power
6X1 Non
Synchronous
7X2 Non
Synchronous
8XTAL_GND – Power
9 CORE_GND – Power
10 ANALOG_VDD – Power
11, 20, 63 NC – – Do not connect.
Output STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be HIGH if the output is not genlocked to the input.
The GS4911B/GS4910B monitors the output pixel/line counters, as well
as the internal lock status from the genlock block and asserts
LOCK_LOST HIGH if it is determined that the output is not genlocked to
the input. This pin will be LOW if the device successfully genlocks the
output clock and timing signals to the input reference.
If LOCK_LOST is LOW, the reference timing generator outputs will be
phase locked to the detected reference signal, producing an output in
accordance with the video standard selected by the VID_STD[5:0] pins.
Output STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be HIGH if:
• No input reference signal is applied to the device; or
• The input reference applied does not meet the minimum/maximum
timing requirements described in Section 3.5.2 on page 46.
This pin will be LOW otherwise.
If the reference signal is removed when the device is in Genlock mode,
REF_LOST will go HIGH and the GS4911B/GS4910B will enter Freeze
mode (see Section 3.2.1.2 on page 41).
Most positive power supply connection for the video clock synthesis
Supply
Supply
Supply
Input ANALOG SIGNAL INPUT
Output ANALOG SIGNAL OUTPUT
Supply
Supply
Supply
internal block. Connect to +1.8V DC.
Ground connection for the video clock synthesis internal block. Connect
to GND.
Most positive power supply connection for the crystal buffer. Connect to
either +1.8V DC or +3.3V DC.
NOTE: Connect to +3.3V for minimum output PCLK jitter.
Connect to a 27MHz crystal or a 27MHz external clock source. See
Figure 1-1.
Connect to a 27MHz crystal, or leave this pin open circuit if an external
clock source is applied to pin 6. See Figure 1-1.
Ground connection for the crystal buffer. Connect to GND.
Ground connection for core and I/O. Solder to the ground plane of the
application board.
NOTE: The CORE_GND pin should be soldered to the same main
ground plane as the exposed ground pad on the bottom of the device.
Most positive power supply connection for the analog input block.
Connect to +1.8V DC.
36655 - 4 April 2007 10 of 113
Table 1-1: Pin Descriptions (Continued)
Pin Number Name Timing Type Description
GS4911B/GS4910B Data Sheet
12 ANALOG_GND – Power
13 AUD_PLL_GND
14 AUD_PLL_VDD
15 10FID Non
16 HSYNC Non
17 VSYNC Non
18, 31, 38,
50, 62
(GS4911B only)
ANALOG_GND
(GS4910B only)
(GS4911B only)
ANALOG_GND
(GS4910B only)
IO_VDD – Power
– Power
– Power
– Power
– Power
Synchronous
Synchronous
Synchronous
Ground connection for the analog input block. Connect to GND.
Supply
Supply
Supply
Supply
Supply
Input REFERENCE SIGNAL INPUT
Input REFERENCE SIGNAL INPUT
Input REFERENCE SIGNAL INPUT
Supply
Ground connection for the audio clock synthesis internal block. Connect
to GND.
Ground connection for the analog input block. Connect to GND.
Most positive power supply connection for the audio clock synthesis
internal block. Connect to +1.8V DC.
Ground connection for the analog input block. Connect to GND.
Signal levels are LVCMOS/LVTTL compatible.
The 10FID external reference signal is applied to this pin by the
application layer. 10FID defines the field in which the video and audio
clock phase relationship is defined according to SMPTE 318-M. It is also
used to define a 3:2 video cadence.
NOTE: If the input reference format does not include a 10 Field ID signal,
this pin should be held LOW. See Section 3.4.2 on page 45.
Signal levels are LVCMOS/LVTTL compatible.
The HSYNC external reference signal is applied to this pin by the
application layer. When the GS4911B/GS4910B is operating in Genlock
mode, the device senses the polarity of the HSYNC input automatically,
and references to the leading edge.
If the user wishes to select one of the pre-programmed video and/or
timing output signals provided by the device, then this signal must
adhere to one of the 36 defined video or 16 different graphics display
standards supported by the device. In this mode of operation, the
HSYNC input provides a horizontal scanning reference signal.
The HSYNC signal may have analog timing, such as from a sync
separator, or may be digital such as from an SDI deserializer. Section 1.4
on page 20 describes the 36 video formats and 16 graphic formats
recognized by the GS4911B/GS4910B.
Signal levels are LVCMOS/LVTTL compatible.
The VSYNC external reference signal is applied to this pin by the
application layer. When the GS4911B/GS4910B is operating in Genlock
mode, the device senses the polarity of the VSYNC input automatically,
and references to the leading edge.
If the user wishes to select one of the pre-programmed video and/or
timing output signals provided by the device, then this signal must
adhere to one of the 36 defined video or 16 different graphics display
standards supported by the device. In this mode of operation, the
VSYNC input provides a vertical scanning reference signal.
The VSYNC signal may have analog timing, such as from a sync
separator, or may be digital such as from an SDI deserializer. Section 1.4
on page 20 describes the 36 video formats and 16 graphic formats
recognized by the GS4911B/GS4910B.
Most positive power supply connection for the digital I/O signals.
Connect to either +1.8V DC or +3.3V DC.
NOTE: All five IO_VDD pins must be powered by the same voltage.
36655 - 4 April 2007 11 of 113
Table 1-1: Pin Descriptions (Continued)
Pin Number Name Timing Type Description
GS4911B/GS4910B Data Sheet
19 FSYNC Non
Synchronous
27, 25, 24,
23, 22, 21
26, 44 CORE_VDD – Power
VID_STD[5:0] Non
Synchronous
Input REFERENCE SIGNAL INPUT
Input CONTROL SIGNAL INPUTS
Supply
Signal levels are LVCMOS/LVTTL compatible.
The FSYNC external reference signal is applied to this pin by the
application layer.
The first field is defined as the field in which the first broad pulse (also
known as serration) is in the first half of a line. The FSYNC signal should
be set HIGH during the first field for sync-based references.
If the user wishes to select one of the pre-programmed video and/or
timing output signals provided by the device, then this signal must
adhere to one of the 36 defined video or 16 different graphics display
standards supported by the device. In this mode of operation, the
FSYNC input provides an odd/even field input reference.
The FSYNC signal may have analog timing, such as from a sync
separator, or may be digital such as from an SDI deserializer. Section 1.4
on page 20 describes the 36 video formats and 16 graphic formats
recognized by the GS4911B/GS4910B.
For blanking-based references, the FSYNC signal should be set HIGH
during the second field.
NOTE: If the input reference format does not include an F sync signal,
this pin should be held LOW.
Signal levels are LVCMOS/LVTTL compatible.
Video Standard Select.
Used to select the desired video/graphic display format for video clock
and timing signal generation.
8 different video and 13 different graphic sample clocks, as well as 35
different video format and 13 different graphic format timing signal
outputs may be selected using these pins.
For details on the supported video standards and video clock frequency
selection, please see Section 1.4 on page 20.
Most positive power supply connection for the digital core. Connect to
+1.8V DC.
36655 - 4 April 2007 12 of 113
Table 1-1: Pin Descriptions (Continued)
Pin Number Name Timing Type Description
GS4911B/GS4910B Data Sheet
28, 29, 30 ACLK1
ACLK2
ACLK3
(GS4911B only)
NC
(GS4910B only)
32, 33, 34 ASR_SEL[2:0]
(GS4911B only)
ANALOG_GND
(GS4910B only)
35 TIMING_OUT_1 Synchronous
– Output CLOCK SIGNAL OUTPUTS
– – Do not connect.
Non
Synchronous
– Power
with PCLK1 ~
PCLK3
Signal levels are LVCMOS/LVTTL compatible.
Audio output clock signals.
ACLK1, ACLK2, and ACLK3 present audio sample rate clock outputs to
the application layer.
By default, after system reset, the audio clock output pins of the device
provide clock signals as follows:
ACLK1 = 256fs
ACLK2 = 64fs
ACLK3 = fs, where fs is the fundamental sampling frequency.
The fundamental sampling frequency is selected using ASR_SEL[2:0].
Additional sampling frequencies may be programmed in the host
interface.
It is also possible to select different division ratios for each of the audio
clock outputs by programming designated registers in the host interface.
Clock outputs of 512fs, 384fs, 256fs, 192fs, 128fs, 64fs, fs and z bit are
selectable on a pin-by-pin basis.
NOTE: ACLK1-3 will have a 50% duty cycle, unless fs is selected as
96kHz and the host interface is configured such that one of the three
ACLK pins is set to output a clock signal at 192fs or 384fs. If this is the
case, then a 512fs clock will have a 33% duty cycle.
These signals will be high impedance when ASR_SEL[2:0] = 000b.
Input CONTROL SIGNAL INPUTS
Signal levels are LVCMOS/LVTTL compatible.
Audio Sample Rate Select.
Used to select the fundamental sampling frequency, fs, of the audio clock
outputs. See Table 3-7.
When ASR_SEL[2:0] = 000b, audio clock generation will be disabled and
the ACLK1 to ACLK3 pins will be high impedance. In this case,
AUD_PLL_VDD (pin 14) may be connected to GND to minimize noise
and power consumption.
Ground connection for the analog input block. Connect to GND.
Supply
Output TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See Section 1.5 on page 26 for signal descriptions.
NOTE: Default output is H Sync.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
36655 - 4 April 2007 13 of 113
Table 1-1: Pin Descriptions (Continued)
Pin Number Name Timing Type Description
GS4911B/GS4910B Data Sheet
36 TIMING_OUT_2 Synchronous
with PCLK1 ~
PCLK3
37 TIMING_OUT_3 Synchronous
with PCLK1 ~
PCLK3
39 TIMING_OUT_4 Synchronous
with PCLK1 ~
PCLK3
40 TIMING_OUT_5 Synchronous
with PCLK1 ~
PCLK3
Output TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See Section 1.5 on page 26 for signal descriptions.
NOTE: Default output is H blanking.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
Output TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See Section 1.5 on page 26 for signal descriptions.
NOTE: Default output is V Sync.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
Output TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See Section 1.5 on page 26 for signal descriptions.
NOTE: Default output is V blanking.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
Output TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See Section 1.5 on page 26 for signal descriptions.
NOTE: Default output is F Sync.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
36655 - 4 April 2007 14 of 113
Table 1-1: Pin Descriptions (Continued)
Pin Number Name Timing Type Description
GS4911B/GS4910B Data Sheet
41 TIMING_OUT_6 Synchronous
with PCLK1 ~
PCLK3
42 TIMING_OUT_7 Synchronous
with PCLK1 ~
PCLK3
43 TIMING_OUT_8 Synchronous
with PCLK1 ~
PCLK3
45 LVDS/PCLK3_VDD – Power
Output TIMING SIGNAL OUTPUT
Output TIMING SIGNAL OUTPUT
Output TIMING SIGNAL OUTPUT
Supply
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See Section 1.5 on page 26 for signal descriptions.
NOTE: Default output is F digital.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See Section 1.5 on page 26 for signal descriptions.
NOTE: Default output is 10 Field ID (10FID).
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4911B only); USER_1~4.
See Section 1.5 on page 26 for signal descriptions.
NOTE: Default output is Display Enable (DE).
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
Most positive power supply connection for PCLK3 output circuitry and
LVDS driver. Connect to +1.8V DC.
36655 - 4 April 2007 15 of 113
Table 1-1: Pin Descriptions (Continued)
Pin Number Name Timing Type Description
GS4911B/GS4910B Data Sheet
46, 47 PCLK3
, PCLK3 – Output CLOCK SIGNAL OUTPUTS
Signal levels are LVDS compatible.
Differential video clock output signal.
PCLK3/PCLK3 present a differential video sample rate clock output to
the application layer.
By default, after system reset, this output will operate at the fundamental
frequency determined by the setting of the VID_STD[5:0] pins. It is
possible to define other non-standard fundamental clock rates using the
host interface.
It is also possible to select different division ratios for the
PCLK3/PCLK3 outputs by programming designated registers in the
host interface. A clock output of the fundamental rate, fundamental rate
÷2, or fundamental rate ÷4 may be selected.
The
PCLK3/PCLK3 outputs will be high impedance when
VID_STD[5:0] = 00h.
48 LVDS/PCLK3_GND – Power
Supply
49 PCLK2 – Output CLOCK SIGNAL OUTPUT
51 PCLK1 – Output CLOCK SIGNAL OUTPUT
Ground connection for PCLK3 output circuitry and LVDS driver. Connect
to GND.
Signal levels are LVCMOS/LVTTL compatible.
Video clock output signal.
PCLK2 presents a video sample rate clock output to the application
layer.
By default, after system reset, the PCLK2 output pin will operate at the
fundamental frequency determined by the setting of the VID_STD[5:0]
pins. It is possible to define other non-standard fundamental clock rates
using the host interface.
It is also possible to select different division ratios for the PCLK2 output
by programming designated registers in the host interface. A clock
output of the fundamental rate, fundamental rate ÷2, or fundamental rate
÷4 may be selected.
By setting designated registers in the host interface, the current drive
capability of this pin may be set high or low. By default, the current drive
will be low. It must be set high if the clock rate is greater than 100MHz.
The PCLK2 output will be held LOW when VID_STD[5:0] = 00h.
Signal levels are LVCMOS/LVTTL compatible.
Video clock output signal.
PCLK1 presents a video sample rate clock output to the application
layer.
By default, after system reset, the PCLK1 output pin will operate at the
fundamental frequency determined by the setting of the VID_STD[5:0]
pins. It is possible to define other non-standard fundamental clock rates
using the host interface.
It is also possible to select different division ratios for the PCLK1 output
by programming designated registers in the host interface. A clock
output of the fundamental rate, fundamental rate ÷2, or fundamental rate
÷4 may be selected.
By setting designated registers in the host interface, the current drive
capability of this pin may be set high or low. By default, the current drive
will be low. It must be set high if the clock rate is greater than 100MHz.
The PCLK1 output will be held LOW when VID_STD[5:0] = 00h.
36655 - 4 April 2007 16 of 113
Table 1-1: Pin Descriptions (Continued)
Pin Number Name Timing Type Description
GS4911B/GS4910B Data Sheet
52 PCLK1&2_GND – Power
Supply
53 PCLK1&2_VDD – Power
54 PhS_VDD – Power
55 PhS_GND – Power
56 JTAG/HOST
57 SCLK_TCLK Non
58 SDIN_TDI Synchronous
59 SDOUT_TDO Synchronous
Non
Synchronous
Synchronous
with
SCLK_TCLK
with
SCLK_TCLK
Supply
Supply
Supply
Input CONTROL SIGNAL INPUT
Input SIGNAL INPUT
Input SIGNAL INPUT
Output SIGNAL INPUT
Ground connection for PCLK1&2 circuitry. Connect to GND.
Most positive power supply connection for PCLK1&2 circuitry. Connect to
+1.8V DC.
Most positive power supply connection for the video clock phase shift
internal block. Connect to +1.8V DC.
Ground connection for the video clock phase shift internal block. Connect
to GND.
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS
are configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SCLK_TCLK, SDOUT_TDO, and SDIN_TDI
are configured as GSPI pins for normal host interface operation.
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Clock / Test Clock.
All JTAG / Host Interface address and data are shifted into/out of the
device synchronously with this clock.
Host Mode (JTAG/HOST
SCLK_TCLK operates as the host interface serial data clock, SCLK.
JTAG Test Mode (JTAG/HOST = HIGH):
SCLK_TCLK operates as the JTAG test clock, TCLK.
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Input / Test Data Input.
Host Mode (JTAG/HOST
SDIN_TDI operates as the host interface serial input, SDIN, used to write
address and configuration information to the internal registers of the
device.
JTAG Test Mode (JTAG/HOST
SDIN_TDI operates as the JTAG test data input, TDI.
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Output / Test Data Output.
Host Mode (JTAG/HOST
SDOUT_TDO operates as the host interface serial output, SDOUT, used
to read status and configuration information from the internal registers of
the device.
JTAG Test Mode (JTAG/HOST
SDOUT_TDO operates as the JTAG test data output, TDO.
_TMS, SCLK_TCLK, SDOUT_TDO, and SDIN_TDI
= LOW):
= LOW):
= HIGH):
= LOW):
= HIGH):
36655 - 4 April 2007 17 of 113
Table 1-1: Pin Descriptions (Continued)
Pin Number Name Timing Type Description
GS4911B/GS4910B Data Sheet
60 CS
61 RESET
64 GENLOCK
– Ground Pad – – Ground pad on bottom of package must be soldered to main ground
_TMS Synchronous
with
SCLK_TCLK
Non
Synchronous
Non
Synchronous
Input SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Chip Select / Test Mode Select.
Host Mode (JTAG/HOST
CS
_TMS operates as the host interface chip select, CS, and is active
LOW.
JTAG Test Mode (JTAG/HOST
CS
_TMS operates as the JTAG test mode select, TMS, and is active
HIGH.
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to their default settings or
to reset the JTAG test sequence.
Host Mode (JTAG/HOST
When asserted LOW, all host registers and functional blocks will be set
to their default conditions. All input and output signals will become high
impedance, except PCLK1 and PCLK2, which will be set LOW.
When set HIGH, normal operation of the device will resume.
The user must hold this pin LOW during power-up and for a minimum of
500 uS after the last supply has reached its operating voltage.
JTAG Test Mode (JTAG/HOST
When asserted LOW, all host registers and functional blocks will be set
to their default conditions and the JTAG test sequence will be held in
reset.
When set HIGH, normal operation of the JTAG test sequence will
resume.
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Selects Genlock mode or Free Run mode.
When this pin is set LOW and the device has successfully genlocked the
output to the input reference, the device will enter Genlock mode. The
video clock and timing outputs will be frequency and phase locked to the
detected reference signal.
When this pin is set HIGH, the video clock and the reference-timing
generator will free-run.
By default, the GS4911B’s audio clocks will be genlocked to the output
video clock regardless of the setting of this pin.
NOTE: The user must apply a reference to the input of the device prior to
setting GENLOCK
reference signal is present, the generated clock and timing outputs of the
device may correspond to the internal default settings of the chip until a
reference is applied.
plane of PCB.
= LOW):
= LOW):
= LOW. If the GENLOCK pin is set LOW and no
= HIGH):
= HIGH):
36655 - 4 April 2007 18 of 113
GS4911B/GS4910B Data Sheet
External Crystal Connection External Clock Source Connection
38pF
1M
24pF
6
X1
external
clock
7
X2
Notes:
1. Capacitor values listed represent the total capacitance,
including discrete capacitance and parasitic board capacitance.
2. X1 serves as an input, which may alternatively accept a 27MHz clock
source. To accomodate this, mismatched capacitor values are recommended.
Figure 1-1: XTAL1 and XTAL2 Reference Circuits
NC
6
X1
7
X2
36655 - 4 April 2007 19 of 113
1.4 Pre-Programmed Recognized Video and Graphics Standards
Table 1-2 describes the video and graphics standards automatically recognized by
the GS4911B/GS4910B. Any one of the 36 different video formats and 16 different
graphic display formats listed below can be applied to the GS4911B/GS4910B and
automatically detected by the reference format detector. Moreover, each format,
with the exception of VID_STD[5:0] = 2, 52, 53, or 54, is available for output on the
timing output pins by setting the VID_STD[5:0] pins.
In addition to the pre-programmed video standards listed in Table 1-2, custom
output timing signals may be generated by the GS4911B/GS4910B. The custom
timing parameters are programmed in the host interface when VID_STD[5:0] is set
to 62 (see Section 3.10 on page 75).
Setting VID_STD[5:0] to 63 will cause the device to produce an output format with
identical timing to the detected input reference.
If desired, the external VID_STD[5:0] pins may be ignored by setting bit 1 of the
Video_Control register, and the video standard may instead be selected via the
VID_STD[5:0] register of the host interface (see Section 3.12.3 on page 80).
Although the external VID_STD[5:0] pins will be ignored in this case, they should
not be left floating.
GS4911B/GS4910B Data Sheet
36655 - 4 April 2007 20 of 113
GS4911B/GS4910B Data Sheet
Standard
Scan Format
Active
Lines /
V Sync
Polarity
Width
V Sync
H Sync
Polarity
Width
H Sync
Active
PCLKS /
Frame
(Lines)
(Clocks)
Line
125M/267M
/ SMPTE 347M
/ SMPTE 347M
/ SMPTE 347M
21 of 113
/ SMPTE 347M
Table 1-2: Recognized Video and Graphics Standards
Frame
Total Lines /
/ Total
PCLKS
Frequency
Video PCLK
System
Nomenclature
[5:0]
VID_STD
Line
––––––––––
(MHz)
= High
PCLK3/PCLK3
0 PCLK1&2 =LOW.
14.32 910 525 768 67 negative 3 negative 486 SMPTE 244M
Impedance
interlace
1 4fsc 525 / 2:1
– – 625 – – negative 2.5 negative 576 –
/ 2:1 interlace / 25
3 601 525 / 2:1 interlace 27 1716 525 1440 127 negative 3 negative 486 SMPTE
2* Composite PAL 625
4‡ 601 625 / 2:1 interlace 27 1728 625 1440 127 negative 2.5 negative 576 ITU-R BT.601-5
36 2288 525 1920 169 negative 3 negative 486 SMPTE 267M
36 2304 625 1920 169 negative 2.5 negative 576 ITU-R BT.601-5
/ 2:1 interlace
5 601 – 18MHz 525
6‡ 601 – 18 MHz 625
54 3432 525 2880 252 negative 3 negative 486 SMPTE RP174
/ 2:1 interlace
interlace
7 720x486/59.94/2:1
54 3456 625 2880 252 negative 2.5 negative 576 ITU-R BT.799
8‡ 720x576/50/2:1
interlace
54 1716 525 1440 127 negative 6 negative 483 SMPTE 293M
9 720x483/59.94/1:1
progressive
54 1728 625 1440 127 negative 5 negative 576 ITU-R BT.1358
progressive
10 720x576/50/1:1
74.25 1650 750 1280 80 tri 5 negative 720 SMPTE 296M
11 1280x720/60/1:1
progressive
74.175 1650 750 1280 80 tri 5 negative 720 SMPTE 296M
12 1280x720/59.94/1:1
progressive
74.25 1980 750 1280 80 tri 5 negative 720 SMPTE 296M
36655 - 4 April 2007
progressive
13 1280/720/50/1:1
GS4911B/GS4910B Data Sheet
Standard
Scan Format
Active
Lines /
V Sync
Polarity
Width
V Sync
H Sync
Polarity
Width
H Sync
Active
PCLKS /
22 of 113
Frame
(Lines)
(Clocks)
Line
Frame
Total Lines /
Line
/ Total
PCLKS
74.25 3300 750 1280 80 tri 5 negative 720 SMPTE 296M
(MHz)
Frequency
Video PCLK
System
Nomenclature
[5:0]
VID_STD
Table 1-2: Recognized Video and Graphics Standards (Continued)
progressive
14 1280x720/30/1:1
74.175 3300 750 1280 80 tri 5 negative 720 SMPTE 296M
15 1280x720/29.97/1:1
progressive
74.25 3960 750 1280 80 tri 5 negative 720 SMPTE 296M
16 1280x720/25/1:1
progressive
74.25 4125 750 1280 80 tri 5 negative 720 SMPTE 296M
17 1280x720/24/1:1
progressive
74.175 4125 750 1280 80 tri 5 negative 720 SMPTE 296M
18 1280x720/23.98/1:1
progressive
74.25 2200 1125 1920 80 tri 5 negative 1035 SMPTE 260M
19 1920x1035/60/2:1
interlace
74.175 2200 1125 1920 80 tri 5 negative 1035 SMPTE 260M
interlace
20 1920x1035/59.94/2:1
148.5 2200 1125 1920 80 tri 5 negative 1080 SMPTE 274M
21 1920x1080/60/1:1
progressive
148.35 2200 1125 1920 80 tri 5 negative 1080 SMPTE 274M
progressive
22 1920x1080/59.94/1:1
148.5 2640 1125 1920 80 tri 5 negative 1080 SMPTE 274M
23 1920x1080/50/1:1
progressive
74.25 2200 1125 1920 80 tri 5 negative 1080 SMPTE 274M
interlace
24 Reserved – – – – – – – – – –
25 1920x1080/60/2:1
74.175 2200 1125 1920 80 tri 5 negative 1080 SMPTE 274M
interlace
26 1920x1080/59.94/2:1
74.25 2640 1125 1920 80 tri 5 negative 1080 SMPTE 274M
27 1920x1080/50/2:1
36655 - 4 April 2007
interlace
28 Reserved – – – – – – – – – –
GS4911B/GS4910B Data Sheet
Standard
Scan Format
Active
Lines /
V Sync
Polarity
Width
V Sync
H Sync
Polarity
Width
H Sync
Active
PCLKS /
Frame
(Lines)
(Clocks)
Line
VDMT75HZ
VDMTPROP
VG900602
VDMT75HZ
VDMTPROP
VG901101A
23 of 113
Frame
Total Lines /
Line
/ Total
PCLKS
74.25 2200 1125 1920 80 tri 5 negative 1080 SMPTE 274M
(MHz)
Frequency
Video PCLK
System
Nomenclature
[5:0]
VID_STD
Table 1-2: Recognized Video and Graphics Standards (Continued)
progressive
29 1920x1080/30/1:1
74.175 2200 1125 1920 80 tri 5 negative 1080 SMPTE 274M
progressive
30 1920x1080/30/PsF 74.25 2200 1125 1920 80 tri 5 negative 1080 SMPTE RP 211
31 1920x1080/29.97/1:1
74.25 2640 1125 1920 80 tri 5 negative 1080 SMPTE 274M
progressive
32 1920x1080/29.97/PsF 74.175 2200 1125 1920 80 tri 5 negative 1080 SMPTE RP 211
33 1920x1080/25/1:1
74.25 2750 1125 1920 80 tri 5 negative 1080 SMPTE 274M
progressive
34 1920x1080/25/PsF 74.25 2640 1125 1920 80 tri 5 negative 1080 SMPTE RP 211
35 1920x1080/24/1:1
74.175 2750 1125 1920 80 tri 5 negative 1080 SMPTE 274M
progressive
36 1920x1080/24/PsF 74.25 2750 1125 1920 80 tri 5 negative 1080 SMPTE RP 211
37 1920x1080/23.98/1:1
25.2 800 525 640 96 negative 2 negative 480 IBM Standard
@ 60 Hz
38 1920x1080/23.98/PsF 74.175 2750 1125 1920 80 tri 5 negative 1080 SMPTE RP 211
39 640 x 480 VGA
36 832 509 640 56 negative 3 negative 480 VESA
31.5 840 500 640 64 negative 3 negative 480 VESA
@ 75 Hz
@ 85 Hz
40 640 x 480 VGA
41 640 x 480 VGA
49.5 1056 625 800 80 positive 3 positive 600 VESA
40.00 1056 628 800 128 positive 4 positive 600 VESA
@ 60 Hz
@ 75 Hz
42 800 x 600 SVGA
43 800 x 600 SVGA
65 1344 806 1024 136 negative 6 negative 768 VESA
56.25 1048 631 800 64 positive 3 positive 600 VESA
@ 85 Hz
@ 60 Hz
44 800 x 600 SVGA
45 1024 x 768 XGA
36655 - 4 April 2007
GS4911B/GS4910B Data Sheet
Standard
Scan Format
Active
Lines /
V Sync
Polarity
Width
V Sync
H Sync
Polarity
Width
H Sync
Active
PCLKS /
Frame
(Lines)
(Clocks)
Line
VDMT75HZ
VDMTPROP
VDMTREV
VDMT75HZ
VDMTPROP
VDMTPROP
24 of 113
Frame
Total Lines /
Line
/ Total
PCLKS
– – 1250 – – negative 3 positive 1200 –
– – 1250 – – negative 3 positive 1200 –
94.5 1376 808 1024 96 negative 3 positive 768 VESA
78.75 1312 800 1024 96 positive 3 positive 768 VESA
(MHz)
Frequency
Video PCLK
System
Nomenclature
[5:0]
VID_STD
Table 1-2: Recognized Video and Graphics Standards (Continued)
@ 75 Hz
46 1024 x 768 XGA
108.00 1688 1066 1280 112 positive 3 positive 1024 VESA
@ 85 Hz
@ 60 Hz
47 1024 x 768 XGA
48 1280 x 1024 SXGA
135.00 1688 1066 1280 144 negative 3 positive 1024 VESA
@ 75 Hz
49 1280 x 1024 SXGA
162 2160 1250 1600 192 negative 3 positive 1200 VESA
157.5 1728 1072 1280 160 negative 3 positive 1024 VESA
@ 85 Hz
@ 60 Hz
@ 75 Hz
50 1280 x 1024 SXGA
51† 1600 x 1200 UXGA
52* 1600 x 1200 UXGA
– – 1589 – – negative 3 positive 1536 –
@ 85 Hz
@ 60 Hz
53* 1600 x 1200 UXGA
54* 2048 x 1536 QXGA
––––––––––
(Section 3.10 on
62 Custom format only
55 - 61 Reserved – – – – – – – – – –
––––––––––
page 75)
Standard follows Input
Standard
63 Automatic Output
36655 - 4 April 2007
* VID_STD[5:0] = 2, 52, 53, and 54 are recognized as input references only. To generate clock and timing signals for these standards use the device’s custom format capability.
† The LOCK_LOST output signal will be unstable when attempting to genlock to an input reference corresponding to VID_STD[5:0] = 51, although the device does achieve lock. To correct
this, the user can program register address 27h = 38d.
‡ When VID_STD = 4, 6, or 8, the Vblanking output pulse width is 2 lines too long for field 1 and 1 line too short for field 2 when compared to the digital timing defined in ITU-R BT.656 and
ITU-R BT.799.
GS4911B/GS4910B Data Sheet
1.5 Output Timing Signals
Table 1-3 describes the output timing signals available to the user via pins
TIMING_OUT_1 to TIMING_OUT_8. The user may output any of the signals listed
below on each pin by programming the Output_Select registers beginning at
address 43h of the host interface.
s
Table 1-3: Output Timing Signals
Signal Name Description Default Output Pin
H Sync The H Sync signal has a leading edge at the start of the horizontal sync pulse.
H Blanking The H Blanking signal is used to indicate the portion of the video line not
Its length is determined by the selected video standard (see Table 1-2), or
according to custom timing parameters programmed in the host interface (see
Section 3.10 on page 75).
The width of the H Sync output pulse is determined by the selected video
standard. Table 1-2
video and graphics standard recognized by the GS4911B/GS4910B. Custom
video timing parameters may also be programmed in the host interface to
define a unique H Sync width (see Section 3.10 on page 75).
In Genlock mode the leading edge of the output H Sync signal is nominally
simultaneous with the half amplitude point of the reference HSYNC input. This
timing may be offset using the Genlock Offset registers beginning at address
1Bh of the host interface (see Section 3.2.1.1 on page 38).
By default, after system reset, the polarity of the H Sync signal output will be
active LOW. The polarity may be selected as active HIGH by programming the
Polarity register at address 56h of the host interface (see Section 3.12.3 on
page 80).
containing active video data.
The H Blanking signal will be LOW (default polarity) for the portion of the video
line containing valid video samples. The signal will be LOW at the first valid
pixel of the line, and HIGH after the last valid pixel of the line.
The H Blanking signal remains HIGH throughout the horizontal blanking period.
The width of this signal will be determined by the selected video standard (see
Table 1-2), or according to custom timing parameters programmed in the host
interface (see Section 3.10 on page 75).
When in Genlock mode, the output H Blanking signal will be phase locked to the
reference HSYNC input. This timing may be offset using the Genlock Offset
registers beginning at address 1Bh of the host interface (see Section 3.2.1.1 on
page 38).
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see Section 3.12.3 on page 80).
lists the H Sync width (in clocks) of each pre-programmed
TIMING_OUT_1
TIMING_OUT_2
36655 - 4 April 2007 25 of 113
GS4911B/GS4910B Data Sheet
Table 1-3: Output Timing Signals (Continued)
Signal Name Description Default Output Pin
V Sync The V Sync timing signal has a leading edge at the start of the vertical sync
pulse. Its length is determined by the selected video standard (see Table 1-2),
or according to custom timing parameters programmed in the host interface
(see Section 3.10 on page 75).
The leading edge of V Sync is nominally simultaneous with the leading edge of
the first broad pulse.
When in Genlock mode, the output V Sync signal will be phase locked to the
reference VSYNC input. This timing may be offset using the Genlock Offset
registers beginning at address 1Bh of the host interface (see Section 3.2.1.1 on
page 38).
By default, after system reset, the polarity of the V Sync signal output will be
active LOW. The polarity may be selected as active HIGH by programming the
Polarity register at address 56h of the host interface (see Section 3.12.3 on
page 80).
V Blanking The V Blanking signal is used to indicate the portion of the video field/frame not
containing active video lines.
The V Blanking signal will be LOW (default polarity) for the portion of the
field/frame containing valid video data, and will be HIGH throughout the vertical
blanking period.
The width of this signal will be determined by the selected video standard (see
Table 1-2), or according to custom timing parameters programmed in the host
interface (see Section 3.10 on page 75).
When in Genlock mode, the output V Blanking signal will be phase locked to the
reference VSYNC input. This timing may be offset using the Genlock Offset
registers beginning at address 1Bh of the host interface (see Section 3.2.1.1 on
page 38).
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see Section 3.12.3 on page 80).
NOTE: When VID_STD = 4, 6, or 8, the Vblank output pulse width is 2 lines too
long for field 1 and 1 line too short for field 2 when compared to the digital timing
defined in ITU-R BT.656 and ITU-R BT.799.
F Sync The F Sync signal is used to indicate field 1 and field 2 for interlaced video
formats.
The F Sync signal will be HIGH (default polarity) for the entire period of field 1. It
will be LOW for all lines in field 2 and for all lines in progressive scan systems.
The width and timing of this signal will be determined by the V Sync parameters
of the selected video standard (see Table 1-2), or according to custom V Sync
timing parameters programmed in the host interface (see Section 3.10 on
page 75). The F Sync signal always changes state on the leading edge of V
Sync.
When in Genlock mode, the output F Sync signal will be phase locked to the
reference FSYNC input. This timing may be offset using the Genlock Offset
registers beginning at address 1Bh of the host interface (see Section 3.2.1.1 on
page 38).
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see Section 3.12.3 on page 80).
TIMING_OUT_3
TIMING_OUT_4
TIMING_OUT_5
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GS4911B/GS4910B Data Sheet
Table 1-3: Output Timing Signals (Continued)
Signal Name Description Default Output Pin
F Digital F Digital is used in digital interlaced standards to indicate field 1 and field 2.
The F Digital changes state at the leading edge of every V Blanking pulse. It will
be LOW (default polarity) for the entire period of field 1 and for all lines in
progressive scan systems. It will be HIGH for all lines in field 2 .
The width and timing of this signal will be determined by the timing parameters
of the selected video standard (see Table 1-2), or according to custom
parameters programmed in the host interface (see Section 3.10 on page 75).
When in Genlock mode, the output F Digital signal will be phase locked to the
reference FSYNC input. This timing may be offset using the Genlock Offset
registers beginning at address 1Bh of the host interface (see Section 3.2.1.1 on
page 38).
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see Section 3.12.3 on page 80).
10 Field Identification The 10 Field Identification (10FID) signal is used to indicate the 10-field
sequence for 29.97Hz, 30Hz, 59.94Hz and 60Hz video standards. It will be
LOW for output standards with other frame rates.
The sequence defines the phase relationship between film frames and video
frames, so that cadence may be maintained in mixed format environments.
The 10FID signal will be HIGH (default polarity) for one line at the start of the
10-field sequence. It will be LOW for all other lines. The signal’s rising and
falling edges will be simultaneous with the leading edge of the H Sync output
signal.
Alternatively, by setting bit 4 of the Video_Control register (see Section 3.12.3
on page 80), the 10FID output signal may be configured to go HIGH (default
polarity) on the leading edge of the H Sync output on line 1 of the first field in
the 10 field sequence, and be reset LOW on the leading edge of the H Sync
pulse of the first line of the second field in the 10 field sequence.
When in Genlock mode, the output 10FID signal will be phase locked to the
10FID reference input. If a 10FID input is not provided to the device, the user
must configure the 10FID output using register 1Ah of the host interface (see
Section 3.8.1 on page 68).
For applications involving audio, this signal may be used in place of the AFS
signal if the format selected is appropriate for a 10 field AFS repetition rate, and
the desired phase relationship of audio to video clock phasing coincides with
the desired film frame cadence.
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see Section 3.12.3 on page 80).
Please see Section 3.8.1 on page 68 for more detail on the 10FID output signal.
Display Enable The Display Enable (DE) signal is used to indicate the display enable for
graphic display interfaces.
This signal will be HIGH (default polarity) whenever pixel information is to be
displayed on the display device (i.e. whenever both H Blanking and V Blanking
are in the active video state)
The width and timing of this signal will be determined by the timing parameters
of the selected video standard (see Table 1-2), or according to custom timing
parameters programmed in the host interface (see Section 3.10 on page 75).
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see Section 3.12.3 on page 80).
TIMING_OUT_6
TIMING_OUT_7
TIMING_OUT_8
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GS4911B/GS4910B Data Sheet
Table 1-3: Output Timing Signals (Continued)
Signal Name Description Default Output Pin
Audio Frame Sync
(GS4911B only)
USER_1~4 The GS4911B/GS4910B offers four user programmable output signals. Each
The Audio Frame Sync (AFS) signal is HIGH (default polarity) for the duration of
the first line of the n’th video frame to indicate that the ACLK dividers are reset
at the start of line 1 of that frame. It is defined according to the frame rate of the
video format and the selected audio sample rate programmed via the
VID_STD[5:0] and ASR_SEL[2:0] pins or the host interface.
For example, if the video format is based on a 59.94Hz frame rate and the
audio sample rate clock is 48kHz, then n=5, and the AFS signal will be identical
to the 10FID signal.
By default, the AFS signal is reset by the 10 Field Identification (10FID)
reference input. This feature may be disabled using the Audio_Control register
at address 31h of the host interface (see Section 3.12.3 on page 80). The AFS
signal may also be reset using register 1Ah of the host interface. With no
reference, the frame divide by “n” controlling the AFS signal will free-run at an
arbitrary phase.
The default polarity of this signal may be inverted by programming the Polarity
register at address 56h of the host interface (see Section 3.12.3).
Please see Section 3.8.2 on page 69 for more detail on the AFS output signal.
USER signal is controlled by four timing registers and a polarity select bit. The
timing registers define the start and stop times in H pixels and V lines and begin
at address 57h of the host interface (see Section 3.12.3 on page 80).
Each user signal is individually programmable and the polarity, position, and
width of each output may be defined with respect to the H, V, and F output
timings of the device. Each output signal may be programmed in both the
horizontal and vertical dimensions relative to the leading edges of H and V
Sync. If desired, the pulses produced may then be combined with a logical
AND, OR, or XOR function to produce a composite signal (for example, a
horizontal back porch pulse during active lines only, or the active part of lines 15
through 20 for vertical information retrieval). Each output has selectable
polarity.
Please see Section 3.8.3 on page 70 for more detail on the USER_1~4 output
signals.
–
–
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Parameter Conditions Value/Units
GS4911B/GS4910B Data Sheet
Supply Voltage Core and Analog
(CORE_VDD, VID_PLL_VDD, AUD_PLL_VDD,
PhS_VDD, ANALOG_VDD)
Supply Voltage I/O
(IO_VDD, XTAL_VDD)
Input Voltage Range (any input) IO_VDD = +3.3V -0.3V to +5.5V
Operating Temperature – -20°C <
Storage Temperature – -50°C <
Soldering Temperature – 260°C
ESD protection on all pins – 1 kV
– -0.3V to +2.1V
– -0.3V to +3.6V
IO_VDD = +1.8V -0.3V to +3.6V
TA < 85°C
T
STG
< 125°C
2.2 DC Electrical Characteristics
Table 2-1: DC Electrical Characteristics
VDD = 1.8V, TA = 0°C to 70°C, unless otherwise specified.
Parameter Symbol Condition Min Ty p Max Units Notes
System
Operating Temperature Range T
Core power supply voltage CORE_VDD – 1.71 1.8 1.89 V –
Digital I/O Buffer Power Supply
Voltage
Video PLL Power Supply Voltage VID_PLL_VDD – 1.71 1.8 1.89 V –
Audio PLL Power Supply Voltage
(GS4911B only)
Analog Power Supply Voltage ANALOG_VDD – 1.71 1.8 1.89 V –
Crystal Buffer Power Supply Voltage XTAL_VDD 1.8V Operation 1.71 1.8 1.89 V –
Video Clock Phase Shift Supply
Voltage
A
IO_VDD 1.8V Operation 1.71 1.8 1.89 V –
IO_VDD 3.3V Operation 3.135 3.3 3.465 V –
AUD_PLL_VDD – 1.71 1.8 1.89 V –
XTAL_VDD 3.3V Operation 3.135 3.3 3.465 V –
PhS_VDD – 1.71 1.8 1.89 V –
36655 - 4 April 2007 29 of 113
– 0 25 70 °C 1
GS4911B/GS4910B Data Sheet
Table 2-1: DC Electrical Characteristics (Continued)
VDD = 1.8V, TA = 0°C to 70°C, unless otherwise specified.
Parameter Symbol Condition Min Ty p Max Units Notes
System Power P
Digital I/O
D
GS4911B
CORE_VDD = Max
––450mW–
IO_VDD = Max
o
T = 70
C
unloaded, max PCLK
frequency
P
D
GS4911B
–300–mW–
CORE_VDD = 1.8V
IO_VDD = 3.3V
o
T = 25
C
unloaded,
PCLK = 74.25MHz
P
D
GS4910B
CORE_VDD = Max
––400mW–
IO_VDD = Max
o
T = 70
C
unloaded, max PCLK
frequency
P
D
GS4910B
CORE_VDD = 1.8V
–250–mW–
IO_VDD = 3.3V
o
T = 25
C
unloaded,
PCLK = 74.25MHz
Input Voltage, Logic LOW V
Input Voltage, Logic HIGH V
Output Voltage, Logic LOW V
IL
V
IL
IH
V
IH
OL
1.8V Operation – – 0.35 x
3.3V Operation – – 0.8 V –
1.8V Operation 0.65 x
3.3V Operation 2.145 – 5.25 V –
current drive = HIGH
or LOW as selected
Output Voltage, Logic HIGH V
OH
current drive = HIGH
or LOW as selected
Digital Output Currents
Timing Output Drive Current – IO_VDD = 1.8V
current drive = LOW
– IO_VDD = 3.3V
current drive = LOW
– IO_VDD = 1.8V
– IO_VDD = 3.3V
current drive = HIGH
current drive = HIGH
V–
VDD
–3.6V –
IO_VDD
––0.4V2
0.65 x
––V 2
IO_VDD
–5–mA–
–10–mA–
–7–mA–
–14–mA–
36655 - 4 April 2007 30 of 113
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