GS1572
A Guide to Designing with the GS1572 (EB1572)
Reference Design
GS1572 A Guide to Designing with the GS1572
(EB1572)
Reference Design
46282 - 1 November 2009
www.gennum.com
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Proprietary & Confidential
Revision History
Version ECR Date Changes and/or Modifications
1 153754 November 2009 Updated to latest Gennum template.
0 146806 August 2007 New document.
Contents
Revision History ................................................................................................................................................. 2
1. Overview.......................................................................................................................................................... 3
2. Design and Layout Guide ........................................................................................................................... 4
2.1 Power Supply and Ground Isolation ..........................................................................................4
2.1.1 Isolation Methods .................................................................................................................4
2.2 Serial Digital Outputs ...................................................................................................................... 5
2.3 VCO Power ......................................................................................................................................... 6
3. Evaluation Board User’s Guide .................................................................................................................7
3.1 Power .................................................................................................................................................... 7
3.2 Inputs ....................................................................................................................................................7
3.3 Outputs ................................................................................................................................................ 8
3.4 Modes of Operation .........................................................................................................................9
3.5 External Control Interface .......................................................................................................... 10
4. Board Schematic ......................................................................................................................................... 11
5. Board Layout................................................................................................................................................ 13
6. Bill of Materials............................................................................................................................................ 15
7. Recommended Components .................................................................................................................. 17
8. References..................................................................................................................................................... 18
GS1572 A Guide to Designing with the GS1572
(EB1572)
Reference Design
46282 - 1 November 2009
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1. Overview
GO1555
(VCO)
GS1572
Parallel
Input
and
PCLK
Serial
Output
This document serves as a reference for designing with the GS1572. It uses the GS1572
evaluation board as a guide. The document is separated into two main sections:
1. Recommended PCB layout practices when designing with the GS1572.
2. A user’s guide to the GS1572 evaluation board, including information on how to use
the board, and detailed schematic and board layout information.
An example of a board design including the GS1572 is shown below. A 10-bit or 20-bit
signal at HD or SD rates must be supplied, along with a parallel clock. The serialized
output is driven by an internal cable driver. The output is fed to BNC’s.
The GS1572 also requires the external GO1555 VCO.
Figure 1-1: GS1572 Block Diagram
GS1572 A Guide to Designing with the GS1572
(EB1572)
Reference Design
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2. Design and Layout Guide
The following sections describe recommended PCB layout practices to optimize the
performance of the GS1572. All layout recommendations discussed in this section are
used on the GS1572 evaluation board. For information on the GS1572, please see
Evaluation Board User’s Guide on page 7.
2.1 Power Supply and Ground Isolation
The GS1572 requires two voltages, +3.3V and +1.8V. The +1.8V feeds the digital core,
phase detector and optionally, the digital I/O. The +3.3V feeds the on-chip regulator for
the external VCO and the SDI cable driver. Optionally, the I/O may also use the +3.3V
supply. For optimal performance, it is essential that these supplies be isolated to avoid
external noise coupling. The supplies can be broken down into four components:
1. +1.8V ANALOG - supplying power to the following pins on the GS1572:
PD_VDD/PD_GND (pins A6, B6 and C6, C7, C8)
2. +1.8V DIGITAL - supplying power to the following pins on the GS1572:
CORE_VDD/CORE_GND (pins A5, E1, G10, K8 and B5, C5, D5, E2, E5, E6, E7, F4,
F5, F6, F7, G9, J8)
3. +3.3V ANALOG - supplying power to the following pins on the GS1572:
CP_VDD/CP_GND, CD_VDD/CD_GND (pins A10 and B10, E10 and C9, D9, E9,
F9)
NOTE: Power should be removed from CD_VDD in STANDBY mode for
additional power savings.
4. +3.3V DIGITAL: - supplying power to the following pins on the GS1572:
IO_VDD/IO_GND (pins G1, H10 and G2, H9)
NOTE: Optionally, 3.3V digital can be replaced with 1.8V digital to run with 1.8V
IO.
2.1.1 Isolation Methods
Because of the noise sensitive nature of the PLL and analog components of the GS1572,
an isolation technique should be used to filter power to these sections.
Figure 2-1 shows the basic concept behind the technique used. The power plane and
ground plane are isolated from the main plane by a ‘moat.’ Power and ground
connections to the ‘islands’ are made through ferrite beads (0
decoupled on both sides. If possible, running high-speed traces across the moat should
be avoided. Also, any copper (i.e. planes or pours on other layers) which bridge the moat
should be removed.
Ω resistors) which are
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(EB1572)
Reference Design
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Figure 2-1: Power Supply Isolation Method
ISOLATED
PLANE
+
VIA TO GROUND
VIA TO POWER
GROUND PLANE
POWER PLANE
FB
FB
+
POWER PLANE
GROUND PLANE
VIA TO POWER
VIA TO GROUND
MAIN PLANE
Plane Layer,
Negative Image
Power and Ground
Plane Voids
2.2 Serial Digital Outputs
The serial digital differential outputs are designed to be SMPTE compliant for voltage
level, rise/fall time and return loss specifications. Figure 2-2 shows the recommended
SDO layout and component placement. Ground and power plane voids are placed
under the ORL matching network. The cutouts under the pull-up resistors attached to
the output pins are necessary and are used to reduce the capacitance and provide better
matching to the 75
Additional points relating to SDO layout and component placement (Figure 2-2):
1. Place the pull-up resistors close to the SDO and SDO pins of the GS1572.
2. Try to avoid running high speed traces through vias.
.
Ω transmission line.
Figure 2-2: Recommended Layout of SDO Section of PCB
GS1572 A Guide to Designing with the GS1572
(EB1572)
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2.3 VCO Power
Plane Layer,
Negative Image
Gennum’s external GO1555 VCO is required for operation of the GS1572. VCO_VCC
(pin A8) and VCO_GND (pins B8 and B9) are provided by the GS1572’s internal regulator
and supply +2.5V to the GO1555. The +2.5V is derived from the +3.3V ANALOG
connection to CP_VDD (pin A10) and CP_GND (pin B10) of the GS1572.
Figure 2-3 shows the connection to the VCO supply and Figure 2-4 shows the
recommended PCB layout and component placement. Note that isolation is complete
and the only connection to the VCO plane is through the VCO_VCC and VCO_GND pins.
NOTE: Do not externally apply voltages to the VCO_VCC and VCO_GND pins.
+3.3V
+
GND
FB
+
FB
CP_GND
Figure 2-3: Connection of GS1572 to VCO Supply
Figure 2-4: Recommended VCO Layout
CP_VCC
VOLTAGE REGULATOR
VCO_VCC
GO1555
VCO_GND
GS1572 A Guide to Designing with the GS1572
(EB1572)
Reference Design
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