GENNUM GS1531 User Manual
GS1531 HD-LINX® II
Multi-Rate Serializer with ClockCleaner™
GS1531 Data Sheet
Key Features
• SMPTE 292M and SMPTE 259M-C compliant
scrambling and NRZ → NRZI encoding (with
bypass)
• DVB-ASI sync word insertion and 8b/10b encoding
• Rejection of more than 300ps jitter on the input
PCLK
• User selectable additional processing features
including:
• CRC, ANC data checksum, and line number
calculation and insertion
• TRS and EDH packet generation and insertion
• illegal code remapping
• Internal flywheel for noise immune TRS generation
• 20-bit / 10-bit CMOS parallel input data bus
• 148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel
digital input
• Automatic standards detection and indication
• 1.8V core power supply and 3.3V charge pump
power supply
• 3.3V digital I/O supply
• JTAG test interface
• Available in a Pb-free package
• small footprint (11mm x 11mm)
Applications
• SMPTE 292M Serial Digital Interfaces
• SMPTE 259M-C Serial Digital Interfaces
• DVB-ASI Serial Digital Interfaces
Description
The GS1531 is a multi-standard serializer with an
integrated cable driver. When used in conjunction with
the GO1555/GO1525* Voltage Controlled Oscillator, a
transmit solution can be realized for HD-SDI, SD-SDI
and DVB-ASI applications.
The device features an internal PLL, which can be
configured for loop bandwidth as narrow as 100kHz.
Thus the GS1531 can tolerate in excess of 300ps jitter
on the input PCLK and still provide output jitter well
within SMPTE specification. Connect the output clocks
from Gennum’s GS4911 clock generator directly to the
GS1531’s PCLK input and configure the GS1531’s loop
bandwidth accordingly.
In addition to serializing the input, the GS1531 performs
NRZ-to-NRZI encoding and scrambling as per SMPTE
292M/259M-C when operating in SMPTE mode. When
operating in DVB-ASI mode, the device will insert K28.5
sync characters and 8b/10b encode the data prior to
serialization.
Parallel data inputs are provided for 10-bit multiplexed
or 20-bit demultiplexed formats at both HD and SD
signal rates. An appropriate parallel clock input signal is
also required.
The integrated cable driver features an output mute on
loss of parallel clock, high impedance mode, adjustable
signal swing, and automatic dual slew rate selection
depending on HD/SD operational requirements.
The GS1531 also includes a range of data processing
functions including automatic standards detection and
EDH support. The device can also insert TRS signals,
calculate and insert line numbers and CRC’s, re-map
illegal code words and insert SMPTE 352M payload
identifier packets. All processing features are optional
and may be enabled/disabled via external control pin(s)
and/or host interface programming.
*For new designs use GO1555
30573 - 7 February 2008 1 of 50
www.gennum.com
Functional Block Diagram
SDO
SDO
SDO_EN/DIS
RSET
CP_CAP
H
V
F
DIN[19:0]
IOPROC_EN/DIS
DVB_ASI
I/O
Buffer
&
demux
SMPTE
352M
generation
TRS insertion,
Line number
insertion,
CRC insertion,
data blank, code re-map and
flywheel
dvb-asi
bypass
RESET_TRST
Reset
HOST Interface /
JTAG test
CS_TMS
SCLK_TCK
SDIN_TDI
SDOUT_TDO
JTAG/HOST
LOCKED
V
CO
VCO
LF
LB_CONT
VCO_VCC
VCO_GND
SD/HD
20bit/10bit
DVB-ASI sync
word insert &
8b/10b encode
EDH
generation
& SMPTE
scramble
PCLK
BLANK
DETECT_TRS
SMPTE_BYPASS
Phase detector, charge pump,
VCO control & power supply
P -> S
sd/hd
ClockCleaner™
GS1531 Data Sheet
GS1531 Functional Block Diagram
30573 - 7 February 2008 2 of 50
GS1531 Data Sheet
Contents
Key Features.................................................................................................................1
Applications...................................................................................................................1
Description ....................................................................................................................1
Functional Block Diagram .............................................................................................2
1. Pin Out .....................................................................................................................5
1.1 Pin Assignment ...............................................................................................5
1.2 Pin Descriptions ..............................................................................................6
2. Electrical Characteristics........................................................................................13
2.1 Absolute Maximum Ratings ..........................................................................13
2.2 DC Electrical Characteristics ........................................................................13
2.3 AC Electrical Characteristics.........................................................................14
2.4 Solder Reflow Profiles...................................................................................16
3. Input/Output Circuits ..............................................................................................17
3.1 Host Interface Maps......................................................................................19
3.1.1 Host Interface Map (Read Only Registers).........................................20
3.1.2 Host Interface Map (R/W Configurable Registers) .............................21
4. Detailed Description ...............................................................................................22
4.1 Functional Overview .....................................................................................22
4.2 Parallel Data Inputs.......................................................................................22
4.2.1 Parallel Input in SMPTE Mode............................................................23
4.2.2 Parallel Input in DVB-ASI Mode..........................................................23
4.2.3 Parallel Input in Data-Through Mode ..................................................23
4.2.4 Parallel Input Clock (PCLK) ................................................................24
4.3 SMPTE Mode................................................................................................25
4.3.1 Internal Flywheel.................................................................................25
4.3.2 HVF Timing Signal Extraction.............................................................25
4.4 DVB-ASI mode..............................................................................................26
4.4.1 Control Signal Inputs ..........................................................................27
4.5 Data-Through Mode......................................................................................28
4.6 Additional Processing Functions...................................................................28
4.6.1 Input Data Blank .................................................................................28
4.6.2 Automatic Video Standard Detection..................................................28
4.6.3 Packet Generation and Insertion ........................................................30
4.7 Parallel-To-Serial Conversion .......................................................................37
4.8 Serial Digital Data PLL..................................................................................38
4.8.1 External VCO......................................................................................38
4.8.2 Lock Detect Output .............................................................................38
4.8.3 Loop Bandwidth Adjustment ...............................................................39
4.9 Serial Digital Output ......................................................................................39
4.9.1 Output Swing ......................................................................................39
30573 - 7 February 2008 3 of 50
GS1531 Data Sheet
4.9.2 Serial Digital Output Mute...................................................................40
4.10 GSPI Host Interface ....................................................................................40
4.10.1 Command Word Description.............................................................41
4.10.2 Data Read and Write Timing ............................................................42
4.10.3 Configuration and Status Registers ..................................................43
4.11 JTAG...........................................................................................................43
4.12 Device Power Up ........................................................................................45
4.13 Device Reset...............................................................................................45
5. Application Reference Design................................................................................46
5.1 Typical Application Circuit.............................................................................46
6. References & Relevant Standards.........................................................................47
7. Package & Ordering Information............................................................................48
7.1 Package Dimensions ....................................................................................48
7.2 Packaging Data.............................................................................................49
7.3 Ordering Information .....................................................................................49
8. Revision History .....................................................................................................50
30573 - 7 February 2008 4 of 50
1. Pin Out
1
32
45
6
7
8
9
10
A
B
C
D
E
F
G
H
J
K
LOCKED
PCLK
LB_
CONT
NC
DIN19
DIN18
DIN17
DIN16
DIN14
DIN12
DIN10
DIN8
DIN6
DIN4
DIN2
DIN1
DIN15
DIN13
DIN11
DIN9
DIN7
DIN5
DIN3
DIN0
SD/HD
IO_VDD
IO_VDD
IO_GND
BLANK
H
IO_VDD
CORE
_VDD
IO_GND
CORE
_VDD
CORE
_GND
CORE
_GND
DETECT
_TRS
DVB_ASI
SMPTE_
BYPASS
NC
NC
20bit/
10bit
SDIN
_TDI
SCLK
_TCK
SDOUT
_TDO
CS_
TMS
NC
NC
NC
CD_VDD
RSET
NC
NC
NC
NC
NC
NC
NC
NC
NC
CP_CAP
SDO
SD0
VCO_
VCC
VCO_
GND
LF
VCO
VCO
CP_VDD
CP_GND
PD_VDD
PD_GND
NC
NC
NC
NC
V
IO_GND
CD_GND
F
NCNC
NC
NC
NC
NC
NC
NC
NC
NC
RSV
NC
NC
NC
NC
NC
JTAG/
HOST
SDO_EN
/DIS
RESET
_TRST
IOPROC
_EN/DIS
1.1 Pin Assignment
GS1531 Data Sheet
30573 - 7 February 2008 5 of 50
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
GS1531 Data Sheet
Pin
Name Timing Type Description
Number
A1 LF Analog Output Control voltage to external voltage controlled oscillator. Nominally +1.25V
A2 VCO_VCC – Output
Power
A3 VCO_GND – Output
Power
A4, A5 VCO
A6, B5,
B6, C1,
C4, C5,
C6, C7,
C8, D1,
D2, D3,
D4, D7,
D8, E1,
E2, E3,
E7, F2,
F3, F7,
G1, G2,
G3, G7,
H1, H2,
H3, H7,
J1, J2,
J3, J4
, VCO Analog Input Differential inputs for the external VCO reference signal. For single ended
NC – – No connect.
DC.
Power supply for the external voltage controlled oscillator. Connect to pin
7 of the GO1555/GO1525*. This pin is an output.
Should be isolated from all other power supplies.
*For new designs use GO1555
Ground reference for the external voltage controlled oscillator. Connect to
pins 2, 4, 6, and 8 of the GO1555/GO1525*. This pin is an output.
Should be isolated from all other grounds.
*For new designs use GO1555
devices such as the GO1555/GO1525*, VCO
VCO_GND.
VCO is nominally 1.485GHz.
*For new designs use GO1555
should be AC coupled to
A7 PCLK – Input PARALLEL DATA BUS CLOCK
Signal levels are LVCMOS/LVTTL compatible.
HD 20-bit mode PCLK = 74.25MHz or 74.25/1.001MHz
HD 10-bit mode PCLK = 148.5MHz or 148.5/1.001MHz
SD 20-bit mode PCLK = 13.5MHz
SD 10-bit mode PCLK = 27MHz
A8, E8, K8 IO_VDD – Power Power supply connection for digital I/O buffers. Connect to +3.3V DC
30573 - 7 February 2008 6 of 50
digital.
Table 1-1: Pin Descriptions (Continued)
GS1531 Data Sheet
Pin
Number
A10, A9,
B10, B9,
C10, C9,
D10, D9,
E10, E9
Name Timing Type Description
DIN[19:10] Synchronous
with PCLK
Input PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
DIN19 is the MSB and DIN10 is the LSB.
HD 20-bit mode
SD/HD
= LOW
20bit/10bit
HD 10-bit mode
SD/HD
= LOW
20bit/10bit
SD 20-bit mode
SD/HD
= HIGH
20bit/10bit
= HIGH
= LOW
= HIGH
Luma data input in SMPTE mode
SMPTE_BYPASS
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS
DVB_ASI = LOW
Multiplexed Luma and Chroma data input
in SMPTE mode
SMPTE_BYPASS
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS
DVB_ASI = LOW
Luma data input in SMPTE mode
SMPTE_BYPASS
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS
DVB_ASI = LOW
DVB-ASI data input in DVB-ASI mode
SMPTE_BYPASS
DVB_ASI = HIGH
= HIGH
= LOW
= HIGH
= LOW
= HIGH
= LOW
= LOW
SD 10-bit mode
SD/HD
= HIGH
20bit/10bit
B1 CP_CAP Analog Input PLL lock time constant capacitor connection.
B2 CP_VDD – Power Power supply connection for the charge pump. Connect to +3.3V DC
B3 CP_GND – Power Ground connection for the charge pump. Connect to analog GND.
B4 LB_CONT Analog Input Control voltage to set the loop bandwidth of the integrated reclocker.
B7 DETECT_TRS Non
Synchronous
Input CONTROL SIGNAL INPUT
analog.
Signal levels are LVCMOS/LVTTL compatible.
Used to select the timing mode of the device.
When set HIGH, the device will lock the internal flywheel to the embedded
TRS timing signals in the parallel input data.
When set LOW, the device will lock the internal flywheel to the externally
supplied H, V, and F input signals.
= LOW
Multiplexed Luma and Chroma data input
in SMPTE mode
SMPTE_BYPASS
DVB_ASI = LOW
Data input in data through mode
SMPTE_BYPASS
DVB_ASI = LOW
DVB-ASI data input in DVB-ASI mode
SMPTE_BYPASS
DVB_ASI = HIGH
= HIGH
= LOW
= LOW
30573 - 7 February 2008 7 of 50
Table 1-1: Pin Descriptions (Continued)
GS1531 Data Sheet
Pin
Name Timing Type Description
Number
B8, F8, J8 IO_GND – Power Ground connection for digital I/O buffers. Connect to digital GND.
C2 PD_VDD – Power Power supply connection for the phase detector. Connect to +1.8V DC
analog.
C3 PD_GND – Power Ground connection for the phase detector. Connect to analog GND.
D5 DVB_ASI Non
Synchronous
D6 LOCKED Synchronous
with PCLK
E4 SD/HD
Non
Synchronous
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with SD/HD
= LOW, the device will be configured to operate in DVB-ASI mode.
When set LOW, the device will not support the encoding of received
DVB-ASI data.
Output STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED signal will be HIGH whenever the device has correctly
received and locked to SMPTE compliant data in SMPTE mode or
DVB-ASI compliant data in DVB-ASI mode, or when the device has
achieved lock in Data-Through mode.
It will be LOW otherwise.
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set LOW, the device will be configured to transmit signal rates of
1.485Gb/s or 1.485/1.001Gb/s only.
When set HIGH, the device will be configured to transmit signal rates of
270Mb/s only.
= HIGH and SMPTE_BYPASS
E5, F5 CORE_GND – Power Ground connection for the digital core logic. Connect to digital GND.
E6, F6 CORE_VDD – Power Power supply connection for the digital core logic. Connect to +1.8V DC
digital.
F1 RSV – – Connect to Analog GND.
F4 20bit/10bit
Non
Synchronous
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select the input data bus width in SMPTE or Data-Through
modes.
When set HIGH, the parallel input will be 20-bit demultiplexed data.
When set LOW, the parallel input will be 10-bit multiplexed data.
30573 - 7 February 2008 8 of 50
Table 1-1: Pin Descriptions (Continued)
GS1531 Data Sheet
Pin
Number
F10, F9,
G10, G9,
H10, H9,
J10, J9,
K10, K9
Name Timing Type Description
DIN[9:0] Synchronous
with PCLK
Input PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
DIN9 is the MSB and DIN0 is the LSB.
HD 20-bit mode
SD/HD
= LOW
20bit/10bit
HD 10-bit mode
SD/HD
20bit/10bit
SD 20-bit mode
SD/HD
20bit/10bit
SD 10-bit mode
SD/HD
20bit/10bit
= HIGH
= LOW
= LOW
= HIGH
= HIGH
= HIGH
= LOW
Chroma data input in SMPTE mode
SMPTE_BYPASS
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS
DVB_ASI = LOW
High impedance in all modes.
Chroma data input in SMPTE mode
SMPTE_BYPASS
DVB_ASI = LOW
Data input in Data-Through mode
SMPTE_BYPASS
DVB_ASI = LOW
High impedance in DVB-ASI mode
SMPTE_BYPASS
DVB_ASI = HIGH
High impedance in all modes.
=HIGH
= LOW
= HIGH
= LOW
= LOW
G4 IOPROC_EN/DIS
Non
Synchronous
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable I/O processing features.
When set HIGH, the following I/O processing features of the device are
enabled:
• EDH Packet Generation and Insertion (SD-only)
• SMPTE 352M Packet Generation and Insertion
• ANC Data Checksum Calculation and Insertion
• Line-based CRC Generation and Insertion (HD-only)
• Line Number Generation and Insertion (HD-only)
• TRS Generation and Insertion
• Illegal Code Remapping
To enable a subset of these features, keep IOPROC_EN/DIS
disable the individual feature(s) in the IOPROC_DISABLE register
accessible via the host interface.
When set LOW, the I/O processing features of the device are disabled,
regardless of whether the features are enabled in the IOPROC_DISABLE
register.
HIGH and
30573 - 7 February 2008 9 of 50
Table 1-1: Pin Descriptions (Continued)
GS1531 Data Sheet
Pin
Name Timing Type Description
Number
G5 SMPTE_BYPASS
G6 RESET_TRST
G8 BLANK
Non
Synchronous
Non
Synchronous
Synchronous
with PCLK
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with DVB_ASI = LOW, the device will be
configured to operate in SMPTE mode. All I/O processing features may be
enabled in this mode.
When set LOW, the device will not support the scrambling or encoding of
received SMPTE data. No I/O processing features will be available.
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings and to
reset the JTAG test sequence.
Host Mode (JTAG/HOST
When asserted LOW, all functional blocks will be set to default conditions
and all input and output signals become high
serial digital outputs SDO and
Must be set HIGH for normal device operation.
JTAG Test Mode (JTAG/HOST
When asserted LOW, all functional blocks will be set to default and the
JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence resumes.
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable input data blanking.
When set LOW, the luma and chroma input data is set to the appropriate
blanking levels. Horizontal and vertical ancillary spaces will also be set to
blanking levels.
When set HIGH, the luma and chroma input data pass through the device
unaltered.
= LOW)
impedance, including the
SDO.
= HIGH)
H4 CS
H5 SCLK_TCK Non
_TMS Synchronous
with
SCLK_TCK
Synchronous
30573 - 7 February 2008 10 of 50
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Chip Select / Test Mode Select
Host Mode (JTAG/HOST
CS
_TMS operates as the host interface chip select, CS, and is active
LOW.
JTAG Test Mode (JTAG/HOST
CS
_TMS operates as the JTAG test mode select, TMS, and is active
HIGH.
NOTE: If the host interface is not being used, tie this pin HIGH.
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Clock / Test Clock.
Host Mode (JTAG/HOST
SCLK_TCK operates as the host interface burst clock, SCLK. Command
and data read/write words are clocked into the device synchronously with
this clock.
JTAG Test Mode (JTAG/HOST
SCLK_TCK operates as the JTAG test clock, TCK.
NOTE: If the host interface is not being used, tie this pin HIGH.
= LOW)
= LOW)
= HIGH)
= HIGH)
Table 1-1: Pin Descriptions (Continued)
GS1531 Data Sheet
Pin
Name Timing Type Description
Number
H6 SDOUT_TDO Synchronous
SCLK_TCK
H8 H Synchronous
with PCLK
with
Output CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Output / Test Data Output
Host Mode (JTAG/HOST
SDOUT_TDO operates as the host interface serial output, SDOUT, used
to read status and configuration information from the internal registers of
the device.
JTAG Test Mode (JTAG/HOST
SDOUT_TDO operates as the JTAG test data output, TDO.
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active video data
when DETECT_TRS is set LOW. The device will set the H bit in all
outgoing TRS signals for the entire period that the H input signal is HIGH
(IOPROC_EN/DIS
H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register, accessible via the host interface.
Active Line Blanking (H_CONFIG = 0
The H signal should be set HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words, and LOW otherwise. This is the
default setting.
TRS Based Blanking (H_CONFIG = 1
The H signal should be set HIGH for the entire horizontal blanking period
as indicated by the H bit in the received TRS ID words, and LOW
otherwise.
= LOW)
must also be HIGH).
= HIGH)
h
)
)
h
J5 SDO_EN/DIS
J6 SDIN_TDI Synchronous
Non
Synchronous
with
SCLK_TCK
Input CONTROL SIGNAL INPUT
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output stage.
When set LOW, the serial digital output signals SDO and SDO
disabled and become high impedance.
When set HIGH, the serial digital output signals SDO and SDO
enabled.
Signal levels are LVCMOS/LVTTL compatible.
Serial Data In / Test Data Input
Host Mode (JTAG/HOST
SDIN_TDI operates as the host interface serial input, SDIN, used to write
address and configuration information to the internal registers of the
device.
JTAG Test Mode (JTAG/HOST
SDIN_TDI operates as the JTAG test data input, TDI.
NOTE: If the host interface is not being used, tie this pin HIGH.
= LOW)
are
are
= HIGH)
30573 - 7 February 2008 11 of 50
Table 1-1: Pin Descriptions (Continued)
GS1531 Data Sheet
Pin
Name Timing Type Description
Number
J7 V Synchronous
with PCLK
K1 RSET Analog Input Used to set the serial digital output signal amplitude. Connect to CD_VDD
K2 CD_VDD – Power Power supply connection for the serial digital cable driver. Connect to
K3, K4 SDO, SDO
K5 CD_GND – Power Ground connection for the serial digital cable driver. Connect to analog
K6 JTAG/HOST
Analog Output Serial digital output signal operating at 1.485Gb/s, 1.485/1.001Gb/s, or
Non
Synchronous
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video field / frame that is used for
vertical blanking when DETECT_TRS is set LOW. The device will set the
V bit in all outgoing TRS signals for the entire period that the V input signal
is HIGH (IOPROC_EN/DIS
The V signal should be set HIGH for the entire vertical blanking period and
should be set LOW for all lines outside of the vertical blanking interval.
The V signal is ignored when DETECT_TRS = HIGH.
through 281Ω +/- 1% for 800mV
+1.8V DC analog.
270Mb/s.
The slew rate of these outputs is automatically controlled to meet SMPTE
292M and 259M requirements according to the setting of the SD/HD
GND.
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS
configured for JTAG boundary scan testing.
When set LOW, CS
configured as GSPI pins for normal host interface operation.
_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
must also be HIGH).
single-ended output swing.
p-p
pin.
K7 F Synchronous
with PCLK
30573 - 7 February 2008 12 of 50
Input CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the ODD / EVEN field of the video signal when
DETECT_TRS is set LOW. The device will set the F bit in all outgoing TRS
signals for the entire period that the F input signal is HIGH
(IOPROC_EN/DIS
The F signal should be set HIGH for the entire period of field 2 and should
be set LOW for all lines in field 1 and for all lines in progressive scan
systems.
The F signal is ignored when DETECT_TRS = HIGH.
must also be HIGH).
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Parameter Value/Units
Supply Voltage Core -0.3V to +2.1V
Supply Voltage I/O -0.3V to +4.6V
Input Voltage Range (any input) -2.0V to + 5.25V
GS1531 Data Sheet
Ambient Operating Temperature -20°C <
Storage Temperature -40°C <
ESD Protection On All Pins (see Note 1) 1kV
NOTES:
1. HBM, per JESDA-114B.
TA < 85°C
T
< 125°C
STG
2.2 DC Electrical Characteristics
Table 2-1: DC Electrical Characteristics
TA = 0°C to 70°C, unless otherwise specified.
Parameter Symbol Conditions Min Typ Max Units Test
Level
System
Operation Temperature Range T
Digital Core Supply Voltage CORE_VDD – 1.71 1.8 1.89 V 3 1
Digital I/O Supply Voltage IO_VDD – 3.13 3.3 3.47 V 3 1
Charge Pump Supply Voltage CP_VDD – 3.13 3.3 3.47 V 3 1
Phase Detector Supply Voltage PD_VDD – 1.71 1.8 1.89 V 3 1
Input Buffer Supply Voltage BUFF_VDD – 1.71 1.8 1.89 V 3 1
Cable Driver Supply Voltage CD_VDD – 1.71 1.8 1.89 V 3 1
External VCO Supply Voltage
Output
+1.8V Supply Current I
+3.3V Supply Current I
To t a l Dev i c e P o we r P
A
VCO_VCC – 2.25 – 2.75 V 1 –
1V8
3V3
D
–0–70°C31
SDO Enabled – – 245 mA 3 3
–––45mA34
SDO Enabled – – 590 mW 3 –
Notes
30573 - 7 February 2008 13 of 50
Table 2-1: DC Electrical Characteristics (Continued)
TA = 0°C to 70°C, unless otherwise specified.
GS1531 Data Sheet
Parameter Symbol Conditions Min Typ Max Units Test
Level
Digital I/O
Input Logic LOW V
Input Logic HIGH V
Output Logic LOW V
Output Logic HIGH V
IL
IH
OL
OH
––– 0.8V4–
–2.1––V4–
+8mA – 0.2 0.4 V 4 –
-8mA IO_VDD - 0.4 – – V 4 –
Input
RSET Voltage V
RSET
RSET=281Ω 0.54 0.6 0.66 V 1 2
Output
Output Common Mode Voltage V
TEST LEVELS
1. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply
voltage with guardbands for supply and temperature ranges
using correlated test.
3. Production test at room temperature and nominal supply
voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of
similar product.
9. Indirect test.
CMOUT
75Ω load,
RSET=281Ω,
SD and HD
0.8 1.0 1.2 V 1 –
NOTES
1. All DC and AC electrical parameters within specification.
2. Set by the value of the RSET resistor.
3. Sum of all 1.8V supplies.
4. Sum of all 3.3V supplies.
Notes
2.3 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics
TA = 0°C to 70°C, unless otherwise shown
Parameter Symbol Conditions Min Typ Max Units Test
Level
System
Device Latency – 10-bit SD – 21 – PCLK 8 –
– 20-bit HD – 19 – PCLK 8 –
– DVB-ASI – 11 – PCLK 8 –
Reset Pulse Width t
reset
–1––ms81
30573 - 7 February 2008 14 of 50
Notes
Table 2-2: AC Electrical Characteristics (Continued)
TA = 0°C to 70°C, unless otherwise shown
GS1531 Data Sheet
Parameter Symbol Conditions Min Typ Max Units Test
Notes
Level
Parallel Input
Parallel Clock Frequency f
PCLK
Parallel Clock Duty Cycle DC
Input Data Setup Time t
Input Data Hold Time t
su
ih
PCLK
– 13.5 – 148.5 MHz 4 –
–40– 60%6–
–2.0––ns5–
–1.5––ns5–
Serial Digital Output
Serial Output Data Rate DR
Serial Output Swing ΔV
Serial Output Rise Time
20% ~ 80%
Serial Output Fall Time
20% ~ 80%
Serial Output Intrinsic Jitter t
tr
tr
tf
tf
IJ
t
IJ
SDO
SDD
SDO
SDO
SDO
SDO
– – 1.485 – Gb/s 1 –
– – 1.485/1.001 – Gb/s 9 –
– –270–Mb/s1–
RSET = 281Ω
650 800 950 mVp-p 1 –
75Ω load
HD signal – – 260 ps 1 –
SD signal 400 550 1500 ps 1 –
HD signal – – 260 ps 1 –
SD signal 400 550 1500 ps 1 –
Pseudorandom and
–90125ps5–
pathological HD signal
Pseudorandom and
–270350ps5 –
pathological SD signal
GSPI
GSPI Input Clock Frequency f
GSPI Input Clock Duty Cycle DC
SCLK
SCLK
GSPI Input Data Setup Time – – 0 – – ns 8 –
GSPI Input Data Hold Time – – 1.43 – – ns 8 –
GSPI Output Data Hold Time – – 2.1 – – ns 8 –
GSPI Output Data Delay
– – – – 7.27 ns 8 –
Time
TEST LEVELS
1. Production test at room temperature and nominal supply voltage
with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage
with guardbands for supply and temperature ranges using
correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of
similar product.
9. Indirect test.
–––6.6MHz8–
–40–60%8–
NOTES
1. See Device Power Up on page 45, Figure 4-12.
30573 - 7 February 2008 15 of 50
Loading...