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EB-GS2972
User Manual
22 pgs1.97 Mb0

GENNUM EB-GS2972 User Manual

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EB-GS2972
Evaluation Board User Guide
EB-GS2972 Evaluation Board User Guide 50283 - 2 May 2012
www.gennum.com
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Version ECR Date Changes and / or Modifications
2 158067 May 2012 Changed R14 value from 380Ω to 200Ω.
Also, changed mistake in 1.5.2 JTAG
Header (JP1) section.
1 151327 January 2009 Updates to Board Layout figures.
0 149901 June 2008 New document.
Contents
Overview .............................................................................................................................................................. 3
1. Board User Guide ..........................................................................................................................................5
1.1 Power (J1) ............................................................................................................................................5
1.2 Switch Settings (SW6 & SW7) ....................................................................................................... 5
1.3 Inputs .................................................................................................................................................... 7
1.3.1 Audio Input............................................................................................................................. 7
1.3.2 Parallel Video Input ............................................................................................................. 7
1.4 SDI Outputs (J3 and J4) ................................................................................................................... 7
1.5 Control and Status ............................................................................................................................8
1.5.1 GSPI Header (JP8) .................................................................................................................8
1.5.2 JTAG Header (JP1) ................................................................................................................ 8
1.5.3 Lock Status .............................................................................................................................. 8
1.6 Modes of Operation .........................................................................................................................8
2. Board Schematics ..........................................................................................................................................9
2.1 Top Level Schematic ........................................................................................................................ 9
2.2 Audio Input Schematic ................................................................................................................ 10
2.3 GS2972 Schematic ......................................................................................................................... 11
2.4 Power Schematic ........................................................................................................................... 12
3. Board Layout................................................................................................................................................ 13
4. Bill of Materials............................................................................................................................................ 19
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Overview
Together with the EB-GS2972 Evaluation Board, this document serves as a guide for evaluating the GS2972, a Gennum 3Gb/s, HD, SD SDI Transmitter. This document contains four main sections:
1. Evaluation Board User Guide.
2. Evaluation Board Schematics.
3. Evaluation Board Layout.
4. Evaluation Board Bill of Materials.
The figure below shows a block diagram of the features and the functions of the EB-GS2972.
The board includes a power supply, 2 SDI output ports, a GS2972 Transmitter, a parallel video input connector, an audio input with four BNCs for AES audio, an optional four-pin header for serial audio, an audio conditioning block, a JTAG/GSPI header, a dip switch and some status indicator LEDs.
The GS2972 can be configured in SD-SDI, HD-SDI, 3G-SDI or DVB-ASI mode. This may be selected manually through a DIP switch. The serialized video is available on the SDI output BNC connectors.
The EB-GS2972 also provides a JTAG interface and access to the GS2972’s internal registers via GSPI and USB. A GSPI dongle is included in the kit, to communicate with the GS2972 and Sample Rate Converters (SRCs) through a USB connection.The GSPI dongle has the provision to control and monitor an additional EB-GS2970 board connected to the EB-GS2972.
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Block Diagram of the EB-GS2972
GS2972
(Transmitter)
Power
SDO
SDO
3G-SDI
3G-SDI
20-bit Video
PCLK
LED’s
FVH
GSPI
7
GSPI Header
Audio
DIP Switch
AES (x4)
Serial Audio
Group 2
4
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1. Board User Guide
Figure 1-1 shows the inputs, outputs and power connections for the EB-GS2972.
Power Supply Connector (J1)
Parallel Video Input Connector (J25)
DIP Switches (SW6 & SW7)
H, V & F Timing Signals
Connector (J27)
GSPI Connector for Interface
with the GS2970 Receiver (J29)
Power Status LED (D7)
Audio Input Group One (AES 1/J13 & AES 2/J14)
Lock Status LED (U25)
1.8V/3.3V Jumper (JP7)
Audio Input Group Two (AES 2/J115 & AES 2/J16)
SDI Outputs (J3 & J4)
JTAG Header (JP1)
GSPI Header (JP8)
Serial Audio Input (Group Two)
Figure 1-1: GS2972 Evaluation Board (EB-GS2972)
1.1 Power (J1)
The EB-GS2972 requires a single +5V DC power supply. The board is powered through J1.
LED (D7) indicates the power on/off state of the board.
Through the use of JP7, the user can select the I/O voltage to be either 1.8V or 3.3V.
If the EB-GS2972 and the EB-GS2970 are connected together, one supply will power both boards. Therefore, the +5V DC power is only required on either the EB-GS2972 or the EB-GS2970.
1.2 Switch Settings (SW6 & SW7)
DIP switches (SW6 and SW7) are populated on the board with each bit labelled on the silk-screen. They are used to set the operation mode of GS2972.
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NOTE: Some signals are active LOW so that you will need to switch the bit OFF to
RATE_SEL0
Data Rate
0
0
1
0
1
X
1.485 or 1.485/1.001Gb/s
2.97 or 2.97/1.001Gb/s
270Mb/s
RATE_SEL1
activate the signal.
Refer to the GS2972 Data Sheet for definitions of each bit.
Table 1-1: SW6 and SW7 Settings
Bit Name Description
TIM861
(SW6)
SMPTE_BYPASSn
(SW6)
DVB_ASI
(SW6)
RATE_SEL0,
RATE_SEL1
(SW6)
Connected to the GS2972 TIM_861 pin. Used to select external CEA-861 timing mode.
When DETECT_TRS is LOW and TIM-861 is LOW, the device extracts all internal timing from the supplied H:V:F timing signals. When DETECT_TRS is LOW and TIM-861 is HIGH, the device extracts all internal timing from the supplied HSYNC, VSYNC, DE timing signals.
When DETECT_TRS is HIGH, the device extracts all internal timing from TRS signals embedded in the supplied video stream.
Connected to the GS2972 SMPTE_BYPASS scrambling and EDH insertion.
When set LOW, the device operates in Data Through mode (DVB_ASI= LOW), or in DVB_ASI mode (DVB_ASI = HIGH). No SMPTE scrambling takes place and none of the I/O processing features of the device are available when SMPTE_BYPASS
When set HIGH, the device carries out SMPTE scrambling and I/O processing.
Connected to the GS2972 DVB_ASI pin. Used to enable/disable the DVB-ASI data transmission.
When set HIGH, the device will carry out DVB_ASI, word-alignment, I/O processing and transmission. The SMPTE_BYPASS When SMPTE_BYPASS
Connected to the GS2972 RATE_SEL0 and RATE_SEL1 pins. Used to configure the operating data rate.
is set LOW.
pin must be set LOW.
and DVB_ASI are both set LOW, the device operates in data-through mode.
pin. Used to enable/disable all forms of encoding/decoding,
IOPROC_EN/DISn
(SW6)
20bit/10bitn
(SW6)
SDO_EN/DISn
(SW6)
DETECT_TRS
(SW7)
Connected to the GS2972 IOPROC_EN/DIS device are enabled. When IOPROC_EN/DIS applicable in SMPTE mode.
Connected to the GS2972 20bit/10bit
Connected to the GS2972 SDO_EN/DIS
When SDO_EN/DIS high-impedance.
When SDO_EN/DIS
Connected to the GS2972 DETECT_TRS pin. Used to select external HVF timing mode or TRS extraction timing mode.
When DETECT_TRS is LOW, the device extracts all internal timing from the supplied H:V:F or CEA-861 timing signals, dependent on the status of the TIM861 pin. When DETECT_TRS is HIGH, the device extracts all internal timing from TRS signals embedded in the supplied video stream.
pin. When IOPROC_EN/DIS is HIGH, the I/O processing features of the
is LOW, the I/O processing features of the device are disabled. Only
pin. Used to select the input bus width.
pin. Used to enable or disable the serial digital output stage.
is LOW, the serial digital output signals SDO and SDO are disabled and become
is HIGH, the serial digital output signals SDO and SDO are enabled.
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Table 1-1: SW6 and SW7 Settings
Bit Name Description
ANC_BLANKn
(SW7)
GRP1_EN/DISn
(SW7)
GRP2_EN/DISn
(SW7)
STANDBY
(SW7)
JTAG_HOSTn
(SW7)
Connected to the GS2972 ANC_BLANK pin.
When ANC_BLANK is LOW, the Luma and Chroma input data is set to the appropriate blanking levels during the H and V blanking intervals.
When ANC_BLANK is HIGH, the Luma and Chroma data pass through the device unaltered. Only applicable in SMPTE mode.
Connected to the GS2972 GRP1_EN/DIS
Connected to the GS2972 GRP2_EN/DIS
Connected to the GS2972 STANDBY pin. HIGH to power-down device. NOTE: Cable Driver is not powered down.
Connected to the GS2972 JTAG/HOST
When JTAG/HOST When JTAG/HOST become the JTAG port (JP1).
is HIGH, the Host Interface port is configured for JTAG test. is LOW, normal operation of the Host Interface port resumes and the separate JTAG pins
pin. Enable Input for Audio Group 1. Set HIGH to enable.
pin. Enable Input for Audio Group 2. Set HIGH to enable.
pin. Used to select JTAG test mode or Host Interface mode.
1.3 Inputs
1.3.1 Audio Input
Up to 8 channels of audio are supported by the EB-GS2972.
Group One (AES 1/J13 and AES 2/J14) goes to SRCs. Through the software, the SRC can be programmed to output AES or serial (synchronous or asynchronous) audio signals to the GS2972. The master clock for the SRCs is supplied by the GS4911B on the EB-GS2972.
Group Two can be connected directly to the GS2972 as AES (AES 3/J15 and AES 4/J16) or serial audio (Header J30). In the case where synchronous audio is required, external synchronization must be applied. This configuration is meant to allow users to have the capability of evaluating audio embedding. For SD audio, when embedding audio with both groups, the audio needs to be synchronized externally.
1.3.2 Parallel Video Input
The EB-GS2972 has a 48-pin parallel connector for the serialized video input (J25). The video input includes the 20-bit video data and pixel clock.
The related timing signals (F,V,H) are on the 10-bit parallel connector (J27).
1.4 SDI Outputs (J3 and J4)
The EB-GS2972 includes two SDI outputs on J3 and J4.
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