GENNUM EB-GS2972 User Manual

EB-GS2972

Evaluation Board User Guide

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

www.gennum.com

1 of 22

Version ECR Date Changes and / or Modifications

2 158067 May 2012 Changed R14 value from 380Ω to 200Ω.

Also, changed mistake in 1.5.2 JTAG

Header (JP1) section.

1 151327 January 2009 Updates to Board Layout figures.

0 149901 June 2008 New document.

Contents

Overview .............................................................................................................................................................. 3

1. Board User Guide ..........................................................................................................................................5

1.1 Power (J1) ............................................................................................................................................5

1.2 Switch Settings (SW6 & SW7) ....................................................................................................... 5

1.3 Inputs .................................................................................................................................................... 7

1.3.1 Audio Input............................................................................................................................. 7

1.3.2 Parallel Video Input ............................................................................................................. 7

1.4 SDI Outputs (J3 and J4) ................................................................................................................... 7

1.5 Control and Status ............................................................................................................................8

1.5.1 GSPI Header (JP8) .................................................................................................................8

1.5.2 JTAG Header (JP1) ................................................................................................................ 8

1.5.3 Lock Status .............................................................................................................................. 8

1.6 Modes of Operation .........................................................................................................................8

2. Board Schematics ..........................................................................................................................................9

2.1 Top Level Schematic ........................................................................................................................ 9

2.2 Audio Input Schematic ................................................................................................................ 10

2.3 GS2972 Schematic ......................................................................................................................... 11

2.4 Power Schematic ........................................................................................................................... 12

3. Board Layout................................................................................................................................................ 13

4. Bill of Materials............................................................................................................................................ 19

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

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Overview

Together with the EB-GS2972 Evaluation Board, this document serves as a guide for
evaluating the GS2972, a Gennum 3Gb/s, HD, SD SDI Transmitter. This document
contains four main sections:

1. Evaluation Board User Guide.

2. Evaluation Board Schematics.

3. Evaluation Board Layout.

4. Evaluation Board Bill of Materials.

The figure below shows a block diagram of the features and the functions of the
EB-GS2972.

The board includes a power supply, 2 SDI output ports, a GS2972 Transmitter, a parallel
video input connector, an audio input with four BNCs for AES audio, an optional
four-pin header for serial audio, an audio conditioning block, a JTAG/GSPI header, a dip
switch and some status indicator LEDs.

The GS2972 can be configured in SD-SDI, HD-SDI, 3G-SDI or DVB-ASI mode. This may
be selected manually through a DIP switch. The serialized video is available on the SDI
output BNC connectors.

The EB-GS2972 also provides a JTAG interface and access to the GS2972’s internal
registers via GSPI and USB. A GSPI dongle is included in the kit, to communicate with the
GS2972 and Sample Rate Converters (SRCs) through a USB connection.The GSPI dongle
has the provision to control and monitor an additional EB-GS2970 board connected to
the EB-GS2972.

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

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Block Diagram of the EB-GS2972

GS2972

(Transmitter)

Power

SDO

SDO

3G-SDI

3G-SDI

20-bit Video

PCLK

LED’s

FVH

GSPI

7

GSPI Header

Audio

DIP Switch

AES (x4)

Serial Audio

Group 2

4

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50283 - 2 May 2012

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1. Board User Guide

Figure 1-1 shows the inputs, outputs and power connections for the EB-GS2972.

Power Supply Connector (J1)

Parallel Video Input
Connector (J25)

DIP Switches (SW6 & SW7)

H, V & F Timing Signals

Connector (J27)

GSPI Connector for Interface

with the GS2970 Receiver (J29)

Power Status LED (D7)

Audio Input Group One
(AES 1/J13 & AES 2/J14)

Lock Status LED (U25)

1.8V/3.3V Jumper (JP7)

Audio Input Group Two
(AES 2/J115 & AES 2/J16)

SDI Outputs (J3 & J4)

JTAG Header (JP1)

GSPI Header (JP8)

Serial Audio Input (Group Two)

Figure 1-1: GS2972 Evaluation Board (EB-GS2972)

1.1 Power (J1)

The EB-GS2972 requires a single +5V DC power supply. The board is powered through
J1.

LED (D7) indicates the power on/off state of the board.

Through the use of JP7, the user can select the I/O voltage to be either 1.8V or 3.3V.

If the EB-GS2972 and the EB-GS2970 are connected together, one supply will power
both boards. Therefore, the +5V DC power is only required on either the EB-GS2972 or
the EB-GS2970.

1.2 Switch Settings (SW6 & SW7)

DIP switches (SW6 and SW7) are populated on the board with each bit labelled on the
silk-screen. They are used to set the operation mode of GS2972.

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

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NOTE: Some signals are active LOW so that you will need to switch the bit OFF to

RATE_SEL0

Data Rate

0

0

1

0

1

X

1.485 or 1.485/1.001Gb/s

2.97 or 2.97/1.001Gb/s

270Mb/s

RATE_SEL1

activate the signal.

Refer to the GS2972 Data Sheet for definitions of each bit.

Table 1-1: SW6 and SW7 Settings

Bit Name Description

TIM861

(SW6)

SMPTE_BYPASSn

(SW6)

DVB_ASI

(SW6)

RATE_SEL0,

RATE_SEL1

(SW6)

Connected to the GS2972 TIM_861 pin. Used to select external CEA-861 timing mode.

When DETECT_TRS is LOW and TIM-861 is LOW, the device extracts all internal timing from the supplied H:V:F
timing signals. When DETECT_TRS is LOW and TIM-861 is HIGH, the device extracts all internal timing from the
supplied HSYNC, VSYNC, DE timing signals.

When DETECT_TRS is HIGH, the device extracts all internal timing from TRS signals embedded in the supplied
video stream.

Connected to the GS2972 SMPTE_BYPASS
scrambling and EDH insertion.

When set LOW, the device operates in Data Through mode (DVB_ASI= LOW), or in DVB_ASI mode (DVB_ASI =
HIGH). No SMPTE scrambling takes place and none of the I/O processing features of the device are available
when SMPTE_BYPASS

When set HIGH, the device carries out SMPTE scrambling and I/O processing.

Connected to the GS2972 DVB_ASI pin. Used to enable/disable the DVB-ASI data transmission.

When set HIGH, the device will carry out DVB_ASI, word-alignment, I/O processing and transmission. The
SMPTE_BYPASS
When SMPTE_BYPASS

Connected to the GS2972 RATE_SEL0 and RATE_SEL1 pins. Used to configure the operating data rate.

is set LOW.

pin must be set LOW.

and DVB_ASI are both set LOW, the device operates in data-through mode.

pin. Used to enable/disable all forms of encoding/decoding,

IOPROC_EN/DISn

(SW6)

20bit/10bitn

(SW6)

SDO_EN/DISn

(SW6)

DETECT_TRS

(SW7)

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

Connected to the GS2972 IOPROC_EN/DIS
device are enabled. When IOPROC_EN/DIS
applicable in SMPTE mode.

Connected to the GS2972 20bit/10bit

Connected to the GS2972 SDO_EN/DIS

When SDO_EN/DIS
high-impedance.

When SDO_EN/DIS

Connected to the GS2972 DETECT_TRS pin. Used to select external HVF timing mode or TRS extraction timing
mode.

When DETECT_TRS is LOW, the device extracts all internal timing from the supplied H:V:F or CEA-861 timing
signals, dependent on the status of the TIM861 pin. When DETECT_TRS is HIGH, the device extracts all internal
timing from TRS signals embedded in the supplied video stream.

pin. When IOPROC_EN/DIS is HIGH, the I/O processing features of the

is LOW, the I/O processing features of the device are disabled. Only

pin. Used to select the input bus width.

pin. Used to enable or disable the serial digital output stage.

is LOW, the serial digital output signals SDO and SDO are disabled and become

is HIGH, the serial digital output signals SDO and SDO are enabled.

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Table 1-1: SW6 and SW7 Settings

Bit Name Description

ANC_BLANKn

(SW7)

GRP1_EN/DISn

(SW7)

GRP2_EN/DISn

(SW7)

STANDBY

(SW7)

JTAG_HOSTn

(SW7)

Connected to the GS2972 ANC_BLANK pin.

When ANC_BLANK is LOW, the Luma and Chroma input data is set to the appropriate blanking levels during the
H and V blanking intervals.

When ANC_BLANK is HIGH, the Luma and Chroma data pass through the device unaltered. Only applicable in
SMPTE mode.

Connected to the GS2972 GRP1_EN/DIS

Connected to the GS2972 GRP2_EN/DIS

Connected to the GS2972 STANDBY pin. HIGH to power-down device.
NOTE: Cable Driver is not powered down.

Connected to the GS2972 JTAG/HOST

When JTAG/HOST
When JTAG/HOST
become the JTAG port (JP1).

is HIGH, the Host Interface port is configured for JTAG test.
is LOW, normal operation of the Host Interface port resumes and the separate JTAG pins

pin. Enable Input for Audio Group 1. Set HIGH to enable.

pin. Enable Input for Audio Group 2. Set HIGH to enable.

pin. Used to select JTAG test mode or Host Interface mode.

1.3 Inputs

1.3.1 Audio Input

Up to 8 channels of audio are supported by the EB-GS2972.

Group One (AES 1/J13 and AES 2/J14) goes to SRCs. Through the software, the SRC can
be programmed to output AES or serial (synchronous or asynchronous) audio signals to
the GS2972. The master clock for the SRCs is supplied by the GS4911B on the
EB-GS2972.

Group Two can be connected directly to the GS2972 as AES (AES 3/J15 and AES 4/J16)
or serial audio (Header J30). In the case where synchronous audio is required, external
synchronization must be applied. This configuration is meant to allow users to have the
capability of evaluating audio embedding. For SD audio, when embedding audio with
both groups, the audio needs to be synchronized externally.

1.3.2 Parallel Video Input

The EB-GS2972 has a 48-pin parallel connector for the serialized video input (J25). The
video input includes the 20-bit video data and pixel clock.

The related timing signals (F,V,H) are on the 10-bit parallel connector (J27).

1.4 SDI Outputs (J3 and J4)

The EB-GS2972 includes two SDI outputs on J3 and J4.

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50283 - 2 May 2012

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1.5 Control and Status

1.5.1 GSPI Header (JP8)

The GS2972 contains a set of internal status and configuration registers. These registers
are available to the host via the GS2972s GSPI pins. To communicate with the GS2972
and the two SRCs, a Gennum USB to GSPI dongle must be connected to the GSPI header.

A GSPI dongle is provided for communication to the GSPI interface. If you have the
EB-GS2972 and the EB-GS2970 connected together, only one GSPI dongle is required,
and can be connected to either of the boards. On the EB-GS2972, connector J29 provides
interface with the EB-GS2970.

1.5.2 JTAG Header (JP1)

This header is used for the JTAG test of the GS2972. It can also be used to communicate
with the GSPI interface of the GS4911B to program the part. To change this header to the
GS4911B GSPI interface, populate R115 and R113 with 0
R22. However, under normal conditions, the GS4911B will not need to be programmed.

1.5.3 Lock Status

LED U25 indicates the lock status of the GS2972.

Ω, and unpopulate R114 and

1.6 Modes of Operation

The GS2972 supports four distinct modes of operation that can be set through the DIP
switch or by programming internal registers through the GSPI. These modes are: SMPTE
mode, Data-Through mode, DVB-ASI mode and Standby mode.

In SMPTE mode, the GS2972 performs all SMPTE processing features. Both SMPTE 425M
Level A and Level B formats are supported with optional conversion from Level A to
Level B for 1080p 50/60 4:2:2 10-bit.

In DVB-ASI mode, the device will perform 8b/10b encoding prior to transmission.

In Data-Through mode, all SMPTE and DVB-ASI processing is disabled. The device can
be used as a simple parallel to serial converter.

The device can also operate in a lower power Standby mode. In this mode, no signal is
generated at the output.

The DIP switches (SW6 and SW7) correspond directly to pins on the GS2972. Refer to the
GS2972 Data Sheet for a more detailed explanation of the operation of these pins in each
mode.

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

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Sch_Power

J304 HEADER

Sch_Audio_In

AES 1

J13BCJ-F PLV01

J25

246810121416182022242628303234363840424446

13579

2. Board Schematics

2.1 Top Level Schematic

Power

123

4

1

VCC_3.3V

WCLK_connGS2972_Audio5

ACLK_connGS2972_Audio4

GS2972_Audio6

PCLK_GS4911

PCLK_GS4911

AES_IN1_2

AES 2

J14 BCJ-FPLV01

R102

75R

1

2
3

PCLK_IN

GS2972_DIN2

GS2972_DIN1

GS2972_DIN0

11131517192123252729313335373941434547

10

U28

GS2972_Audio7

IOVDD_2972

GS2972_Audio7

GS2972_Audio6

S_AUDIO_0 GS2972_Audio0

GS2972_AES5_6

GS2972_AES7_8

AES_IN3_4

AES_IN5_6

AES 4

J16

R104

75R

1

2

AES 3

3

J15BCJ-F PLV01

R103

75R

1

GND

2
3

GND

GND

GND

GS2972_DIN6

GS2972_DIN5

GS2972_DIN7

GS2972_DIN4

GS2972_DIN3

GS2972_DIN8

GS2972_DIN9

GS2972_DIN11

GS2972_DIN10

GND

4

K13K2

Lock

HSMF-C165

U25

A1 green1A2 red

2

VCC_3.3V

R101

75R

GND

3

6

VCCA

A02A1

TR04TR1

GND

5

VCCB

OEb7B09B1

GND

S_AUDIO_1 GS2972_Audio1

S_AUDIO_2 GS2972_Audio2

S_AUDIO_3 GS2972_Audio3

S_AUDIO_[ 3:0]

S_AUDIO_[ 3:0]

AES_IN7_8

Audio_RST

RESET

GS2972_HVF[2: 0]

R105

75R

1

GND

2
3

GND

BCJ-FPLV01

GNDGND

GS2972_DIN17

GS2972_DIN12

GS2972_DIN15

GS2972_DIN16

GS2972_DIN18

GS2972_DIN14

GS2972_DIN13

GND

8

FXL2TD245

GS2972_Audio[7:0]

GSPI_GS4911_[3:0]

GSPI_GS4911_[3:0]

HVF_IN[2:0]

SRC4382_SPI[ 4:0]

Audio_In

GS2972_PCLK

Sch_GS2972

SRC4382_SPI[ 4:0]

SDOUT SRC4382_SPI0

SDIN SRC4382_SPI1

GS2972_DIN19

48

PCLK

R108

R109 NP

SCLK SRC4382_SPI2

CS2 SR C4382_SPI3

CS3 SR C4382_SPI4

PCLK_GS4911

PCLK_IN

V GS2972_HVF1

H GS2972_H VF0

F GS2972_H VF2

246810

J27

FEMALE: TOP-S IDE

13579

SQT-124-01-F-D-RA

GND

J3

UCBBJE20-1

+SDO

1

SDO

GS2972_Locked

GS2972_Audio[7:0]

GS2972_DIN[19:0]

GS2972_HVF[2: 0]

0R

GS2972_HVF[2: 0]

GS2972_DIN[ 19:0]

GND

SCLK

246810

J29

13579

SQT-105-01-F-D-RA

FEMALE: TOP-S IDE

GND

VCC_5V

SDI Output

C69

J4

UCBBJE20-1

GNDA_2972

GNDA_2972

-SDO

3

3

2

2

1

SDOn

JTAG[3:0]

Pin _ctrl[13: 0]

GS2972_RESETn

GS2972_GSPI[3:0]

RESET

GS2972_GSPI[3:0]

GS2972_GSPI2

GND

2

A03A14A25A3

U17

T/R b0

VCCA

1

IOVDD_2972

VCC_3.3V

CS0

SDIN

SDOUT

CS3

CS2

CS1

VCCB

16

15

GND

GND

SCLK

JP8

GSPI

CS3

JTAG/HOSTb

SQT-105-01-F-D-RA

FEMALE: TOP-S IDE

R77 10K

R78 10K

GND

IOVDD_2972

IOVDD_2972

IOVDD_2972

RESET

JTAG[3:0]

GS2972

GS2972_GSPI3

GS2972_GSPI1

GS2972_GSPI0

GND

6

7

FXL4TD245

T/R b3

GND

8

OEb

9

T/R b210B311B212B113B014T/R b1

CS1

IOVDD_2972

SDIN

R112

0R

SDOUT

CS0

12345678910

R106NP

TSW-105-07-L-D

CS2

CS1

VCC_3.3V

R80 10K

R79 10K

0.1u

GND

2

5

Vcc

U1

RESET1MR

WDI

4

R107

1.15K

RESET

RST

R22

10K

R21

10K

R20

10K

IOVDD_2972

JP1

JTAG/GSPI_GS4911

Pin _ctrl[13: 0]

TIM861 Pin _ctrl12

DVB_ASI Pin _ctrl10

RATE_SEL1 Pin _ctrl8

RATE_SEL0 Pin _ctrl9

SMPTE_BYPASSn Pin _c trl11

GND

CS1

OPEN

1

0

SW6

SW8_LOGIC_D IP_TH

IOVDD_2972

TIM861

SMPT E_BYPASSn

DVB_ AS I

RAT E_SEL 0

RAT E_SEL 1

P.O. Bo x 489, Station A

GND

MAX6823V

3

S1

B3S-1002

GND

JTAG0

JTAG2

JTAG3

JTAG1

R1140R

R115

NP

GSPI_GS4911_[3:0]

GND

TDI

TMS

TDO

TCK

GSPI_GS4911_2

1

9

7

3

5

NC

TDI

TCK

TMS

TDO

GND

VDD

NC

NC

GND

TSW-105-07-L-D

2

4

6

8

10

IOVDD_2972

STANDBY Pin _ctrl13

STANDBY

20BIT/10BITn Pin _ctrl6

SDO_EN/DISn Pin _ctrl5

DETECT_TRS Pin _ctrl4

ANC_BLANKn Pin _ctrl3

GRP1_EN_DI Sn Pin _ct rl2

GRP2_EN_DI Sn Pin _ct rl1

IOPROC_EN/DISn Pin _ctrl7

1

1

CLOSED

0

0

SW7

ANC_BLANKn

IOPROC_EN/DI Sn

20BI T/ 10 BIT n

DETECT_TRS

SDO_EN/DISn

GRP1_EN_ DISn

GRP2_EN_ DISn

ST ANDBY

GSPI_GS4911_2

GSPI_GS4911_0

GSPI_GS4911_1TMS

GSPI_GS4911_3TCK

R113NP

GND

TDO

Pin _ctrl0JTAG_HOSTn

Pin _ctrl0

1

16

2

15

3

14

500R500R

4

13

5

12

RN1

6

11

7

10

8 9

1

16
15
14
13
12
11
10

OPEN

CLOSED

0

SW6_LOGIC_DIP_TH

JTAG_HOSTn

GND

2
3
4
5

6

7
8 9

RN2

013G

00HD

SD

1RATE_SEL0

X

RATE_SEL1

Figure 2-1: Top Level Schematic

EB-GS2972

Evaluation Board User Guide

50283 - 2 May 2012

2.2 Audio Input Schematic

AES_IN3_4

Master clock for SRC

GND

Audio_RST

IO_V_SRC4382

Audio_RST

slow_48k

SRC4382_SPI0

TP16

GSPI_GS4911_3

ACLK_GS4911

Audio_RST

SRC4382_SPI1

Audio outputs and SPI

TP17

GND

SRC4382_SPI2

R86

1.15K

3V3_SRC4382

GND

GSPI_GS4911_2

SRC4382_SPI3

ACLK_GS4911

SRC4382_SPI3

AES3_4_SRC4382

C122 0. 1u

C148 0.1u

GND

GND

Gr2_AES_Ser

Part Ref erence
105R

GND

AES1_2_SRC4382

C143

0.1u

C144

0.1u

A

3

B

4

R

5

GND

2

Vcc

1

110R

U10

SN65LVDT2

VCC_3.3V

GND

GND GND

GSPI_GS4911_1

Connect pin 44 to pin 10.

Pin 10 is then connected to
the ground plane.

GND

GND

slow_48k

S_AUDIO_[3: 0]

GND

GND

SRC4382_SPI2

GSPI_GS4911_0

3V3_SRC4382

PCLK_GS4911

S_AUDIO_2

1 B1

3 B2

S6GND

2

A

4

5Vcc

U18

SN74LVC1G3157

IO_V_SRC4382

SRC4382_SPI4

SRC4382_SPI4

GND

GND

R111
105R

AES3_4_SRC4382

C146

0.1u

C145

0.1u

VCC_3.3V

GND

A

3

B

4

R

5

GND

2

Vcc

1

110R

U11

SN65LVDT2

GND GND

GND

RX1+

1

RX1-

2

RX2+

3

RX2-

4

RX3+

5

RX3-

6

RX4+

7

RX4-

8

VCC

9

AGND

10

LOCKb

11

RXCKO

12

RXCKI13MUTE14RDYb15DGND116VDD1817CPM18CSb19CCLK20CDIN21CDOUT22INTb23RSTb

24

MCLK

25

GPO1

26

GPO2

27

GPO3

28

GPO4

29

DGND2

30

TX-

31

TX+

32

VDD33

33

AESOUT

34

BLS

35

SYNC

36

BCKA

37

LRCKA

38

SDINA

39

SDOUTA

40

NC

41

VIO

42

DGND3

43

BGND

44

SDOUTB

45

SDINB

46

LRCKB

47

BCKB

48

U26

SRC4382

GND

AES_IN5_6

AES5_6

R92
105R

C126

0.1u

GND

C125

0.1u
A

3

B

4

R

5

GND

2

Vcc

1

110R

U12

SN65LVDT2

GND GND

SRC4382_SPI2

VCCA1VCCB

10

A0

2

A1

3

TR0

4

TR1

6

GND

5

OEb

7

B0

9

B1

8

U24

FXL2TD245

GND

PCLK_GS4911

GSPI_GS4911_3

RX1+

1

RX1-

2

RX2+

3

RX2-

4

RX3+

5

RX3-

6

RX4+

7

RX4-

8

VCC

9

AGND

10

LOCKb

11

RXCKO

12

RXCKI13MUTE14RDYb15DGND116VDD1817CPM18CSb19CCLK20CDIN21CDOUT22INTb23RSTb

24

MCLK

25

GPO1

26

GPO2

27

GPO3

28

GPO4

29

DGND2

30

TX-

31

TX+

32

VDD33

33

AESOUT

34

BLS

35

SYNC

36

BCKA

37

LRCKA

38

SDINA

39

SDOUTA

40

NC

41

VIO

42

DGND3

43

BGND

44

SDOUTB

45

SDINB

46

LRCKB

47

BCKB

48

U27

SRC4382

AES_IN7_8

GND

S_AUDIO_0

AES7_8

R93
105R

C128

0.1u

C127

0.1u

VCC_3.3V

GND

A

3

B

4

R

5

GND

2

Vcc

1

110R

U13

SN65LVDT2

GND GND

GND

SRC4382_SPI1

GND

1V8_SRC4382

S_AUDIO_1

GS2972_AES5_6

AES_IN1_2

S_AUDIO_2

GS2972_AES7_8

AES7_8

AES5_6

R88

1.15K

1V8_SRC4382

S_AUDIO_3

GSPI_GS4911_[3:0]

GS2972_AES5_6

GS4911_genlockb

HVF_IN[2:0]

SRC4382_SPI1

GS2972_AES5_6
GS2972_AES7_8

GS2972_AES7_8

1V8_SRC4382

SRC4382_SPI0

VCC_3.3V

S_AUDIO_0

Connect pin 44 to pin 10.
Pin 10 is then connected to
the ground plane.

GSPI_GS4911_0

GSPI_GS4911_[3:0]

GSPI_GS4911_1

TP21

GND

IOVDD_2972

GSPI_GS4911_2

SRC4382_SPI[4: 0]

S_AUDIO_0

SRC4382_SPI0

1V8_SRC4382

S_AUDIO_1

IO_V_SRC4382

SRC4382_SPI[4: 0]

AES1_2_SRC4382

C116 0. 1u

SRC A

C147 0. 1u

GND

1V8_Core_GS4911

Audio_RST

3V3_PLL_SRC4382_A

SRC B

GND

GND

GND

S_AUDIO_1

GND

R95
10K

HVF_IN1
HVF_IN2

ACLK_GS4911

V_STD_Sel

HVF_IN0

IO_V_GS4911

HVF_IN[2:0]

PCLK_GS4911

1V8_GS4911

IO_V_GS4911

1V8_GS4911

1V8_Core_GS4911

1V8_GS4911

GS4911_genlockb

IO_V_GS4911

1V8_GS4911

1V8_GS4911

IO_V_GS4911

IO_V_GS4911

V_STD_Sel

1V8_GS4911

V_STD_Sel

Audio_RST

VID_PLL_GND

4

VID_PLL_VDD

3

XTAL_VDD

5

X1

6

X2

7

XTAL_GND

8

CORE_GND

9

PHS_GND

55

PHS_VDD

54

ANALOG_VDD

10

NC

11

ANALOG_GND

12

AUD_PLL_GND

13

AUD_PLL_VDD

14

10FID

15

HSYNC

16

VSYNC17IO_VDD18FSYNC19NC20VID_STD021VID_STD122VID_STD223VID_STD324VID_STD425VID_STD527ACLK128ACLK229ACLK330IO_VDD31CORE_VDD26ASR_SEL2

32

ASR_SEL1

33

ASR_SEL0

34

TIMIN G_OUT1

35

TIMIN G_OUT2

36

IO_VDD

38

TIMIN G_OUT4

39

TIMIN G_OUT3

37

TIMIN G_OUT5

40

LVDS/PCLK3_VDD

45

PCLK3

46

LVDS/PCLK3_GND

48

PCLK3

47

PCLK2

49

PCLK1&2_GND

52

PCLK1

51

IO_VDD

50

TIMIN G_OUT6

41

TIMIN G_OUT7

42

TIMIN G_OUT8

43

PCLK1&2_VDD

53

LOCK_LOST

1

REF_LOST

2

GENLOCK

64

CORE_VDD

44

JTAG/HOST56SCLK_TCLK

57

SDIN_TDI

58

SDOUT_TDO

59

CS_TMS

60

RESET

61

IO_VDD

62

NC

63

GND_PAD

65

U20

GS4911

AES inputs 1_2 and 3_4 with SRCs

1V8_GS4911

Y2

27.000MHZ

VDD_XTAL_GS4911

R99
10K

C120

24p

C119

38p

R98
22R

R97
1M

IO_V_GS4911

TP23

TP22

GND

GND

S_AUDIO_[3: 0]

3V3_PLL_SRC4382_B

GND

Gr2_AES_Ser

AES inputs 5_6 and 7_8

S_AUDIO_3

1 B1

3 B2

S6GND

2

A

4

5Vcc

U22

SN74LVC1G3157

IO_V_SRC4382

VCC_3.3V

Figure 2-2: Audio Input Schematics

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

10 of 22

11 of 22

+1.2VA_2972

CDVDD _2972

GNDA_2972

R26 75R

SDOn

SDOn

C41 4u7

C40 10n

(SUBJECT TO CHANGE)

R27 75R

R28 75R

L4 5n6

SDO

SDO

C39 4u7

Pin _ctrl[13: 0]

R24 75R

L3 5n6

Return Loss compensation Network

JTAG[3:0]

Pin _ctrl13STANDBY

GS2972_Locked

GND

R65

D5

F7

RSV

RSV

AVDD

A10

IO_VDD

H10

IO_VDD

G1

CORE_VDD

G10

CORE_VDD

K8

CORE_VDD

E1

CORE_VDD

A5

+1.2V

CDVDD _2972

+1.2VA_2972 IOVDD_2972 +3.3VA_2972

C18

10u

R7

105R

GNDA_2972

CD_VDD

E10

PLL_VDD

B6

PLL_VDD

A6

VCO_VDD

B7

TIM861 Pin _ct rl12

DVB_ASI Pin _ctrl10

TP11

TP8

TP10

TP9

NP

D7

F4

RSVD6RSV

RSV

VBG

LF

A8

A7

RATE_SEL0 Pin _ctrl9

RATE_SEL1 Pin _ctrl8

20BIT/10BITn Pin _ctrl6

SMPTE_BYPASSn Pin _ctrl11

IOPROC_EN /DISn Pin _ctrl7

G4

G7

G6

G5

G3

A9

D8

D3

E3

E4

RSV

RSV

TIM_8 61

DVB_ASI

STANDBY

RATE_SEL0

RATE_SEL1

SMPTE_BYPASS

IOPROC_EN/DIS

PCLK

DIN18A2DIN19

DIN17

DIN16

B4

B3

A1

B2

B1

TP12

CDVDD _2972

R23

750R

JTAG_HOSTn Pin _ctrl0

SDO_EN/D ISn Pin _ctrl5

DETECT_TR S Pi n _ctrl4

ANC_BLANKn Pin _ctrl3

GRP2_EN_DI Sn Pin _ctrl1

GRP1_EN_DI Sn Pin _ctrl2

GS2972_Locked

H6

H5

H3

D4

H8

H4

H7

F3

LOCKED

20BIT/10BIT

DIN14C2DIN15

AUDIO_INT

JTAG/H OST

ANC_BLANK

SDO_EN/D IS

DETECT_TR S

GRP1_EN/D IS

GRP2_EN/D IS

DIN12C3DIN13

DIN10D2DIN11

DIN8F2DIN9

DIN6H2DIN7

J1

F1

C1

D1

H1

GS2972_SDI_SDOn

GS2972_SDI_SDO

GS2972_TCK2 J TAG3

GS2972_TDO2 JTAG2

D10

C10

F8

J8

F10

TCK

SDO

SDO

RSET

U5

GS2972

ACLK1K7WCLK1J7AIN_1/2

DIN4J2DIN5

H/HSYNC

V/VSYN C

DIN2K2DIN3

F/DE

DIN0K3DIN1

J3

A4

K1

A3

C4

GS2972_GSPI[3:0]

GS2972_TDI2 JTAG0

GS2972_TMS2 JTAG1

GS2972_SDO GS2972_GSPI 0

GS2972_SDI GS2972_GSPI 1

GS2972_SCK GS2972_GSPI2

GS2972_CSn GS2972_GSPI3

J10

K9

E8

E7

K10

J9

TDI

TMS

TDO

CS_TMS

SDIN_TDI

SCLK_TCK

AIN_3/4

ACLK2

WCLK2

J6

J5

J4

K6

K5

K4

IO_GND

GND

H9

IO_GND

G2

CORE_GND

SDOUT_TDO

AIN_7/8

G9

CORE_GND

F6

CORE_GND

F5

CORE_GND

E6

CORE_GND

E5

CORE_GND

E2

CORE_GND

C5

CORE_GND

B5

CD_GND

F9

CD_GND

E9

CD_GND

D9

CD_GND

C9

VCO_GND

B8

AGND

B10

AGND

B9

PLL_GND

C8

PLL_GND

C7

PLL_GND

C6

RESETG8AIN_5/6

GNDA_2972

Close to

GS2972.

C10

10n

IOVDD_2972

Pins G1,H10

C9

10n

C8

1u

R1

0R

C7

10u

IO_V

3.3V or 1.8V

2.3 GS2972 Schematic

Power Decoupling & Filtering

GS2972_HGS2972_HVF0

GS2972_VGS2972_HVF1

GS2972_DIN14

GS2972_DIN16

GS2972_DIN15

GS2972_DIN19

GS2972_DIN18

C37 1u

R14 200R

C35 100p

C36 10u

GNDA_2972

Close to GS2972.

C34

Pin A10

+3.3VA_2972

1u

C33

R9

0R

GND

C19

C25

VCC_3.3V

GS2972_DIN17

C38

DNP

R17

DNP

GS2972_PCLK

GS2972_PCLK

10n

Pin E10

GNDA_2972

CDVDD _2972

0R

R6

0R

R81

10n

1u

GND

VCC_3.3V

GS2972_DIN6

GS2972_DIN7

GS2972_DIN11

GS2972_DIN10

GS2972_DIN9

GS2972_DIN8

GS2972_DIN13

GS2972_DIN12

GND

C17

10n

GNDA_2972

1u

C16

0R

R82

C15

1u

C14

10n

+1.2V

GND

GS2972_FGS2972_H VF2

GS2972_DIN2

GS2972_DIN1

GS2972_DIN5

GS2972_DIN0

GS2972_DIN4

GS2972_DIN3

C6

C5

C4

Pins A5,E1,K8,G10

C3

GS2972_ACLK1GS2972_Audio0

GS2972_HVF[2: 0]

GS2972_DIN[ 19:0]

Pins A6,B6

+1.2VA_2972

10n

10n

R11

0R

10n

10n

GND

+1.2V

GS2972_AIN7_8GS2972_Audio7

GS2972_ACLK2GS2972_Audio4

GS2972_AIN3_4GS2972_Audio3

GS2972_AIN1_2GS2972_Audio2

GS2972_AIN5_6GS2972_Audio6

GS2972_WCLK1GS2972_Audio1

GS2972_WCLK2GS2972_Audio5

GS2972_RESETn

GS2972_RESETn

GS2972_Audio[7:0]

C24

10n

GNDA_2972

C32

10n

1u

C31

R13

0R

C30

1u

C29

10n

GND

Figure 2-3: GS2972 Schematic

EB-GS2972

Evaluation Board User Guide

50283 - 2 May 2012

2.4 Power Schematic

POWER SUPPLIES

5V

VCC_5V

J1

5V Input

GND

SRC4382 power decoupling

VCC_3.3V

10u

GND

VCC_1.8V

GND

Between pins 33 and 30
SRC-A

R75 0R

C130

Between pins 16 and 17
SRC-A

R76 0R

C134

10u

C20
EEV-FK1C221XP

IO_V

GND

3V3_SRC4382

C131
10u

C135
10u

C129

10u

C108

0.1u

1V8_SRC4382

C137

0.1u

C86
1u

PWRGD_3V3

Between pins 43 and 42
SRC-A

R690R

Between pins 33 and 30
SRC-B

C110

C109

10u

0.1u

Between pins 16 and 17
SRC-B

C136

C138

10u

0.1u

R66

49.9K

VCC_5V

C95
10u

PWRGD_3V3

C87
22u

GND

3V3_SRC4382

TPS74201_RGW

SN74LVC1T45DBVR

IO_V_SRC4382

C92

0.1u

GND

R72 2R

5

IN

6

IN

7

IN

8

IN

10

BIAS

11

EN

9

PG

U15

1

VCCA

2

GND

A3B

Between pins 43 and 42
SRC-B

C93

10u

3V3_PLL_SRC4382_A

C139

10u

Between pins 9 and 10
SRC-A

GND

U14

NC2NC3NC4Pad

VCCB

DIR

TP2

1

OUT

20

OUT

19

OUT

18

OUT

17

NC

16

FB

15

SS

GND12NC13NC

14

21

VCC_3.3V

6

VCC_5V

5

R32

4

240R

LNJ311G8P

VCC_3.3VVCC_5V

R2

3.57K

C12

C88

10n

D7

GND

22u

R4

1.15K

GND

GNDGND

PWR

VCC_3.3V

VCC_3.3V

C70
1u

C90
1u

U4
LT3021ES8-1.2

8

IN

OUT

5

SHDN

6

4

U16
LT3021ES8-1.8

8

IN

5

SHDN

6

PGND

4

AGND

PGND
AGND

Hea t s ink
on copper

Hea t s ink
on copper

SENSE

SENSE

OUT

NC
NC

NC
NC

C26

0.1u

GND

C84

0.1u

GND

500mA

+1.2V

+1.2V

2
3

C27

22u

1
7

GND

500mA

TP3

VCC_1.8V

+1.8V

2
3

C85

22u

1
7

GND

IO V

1.8V 3.3V

VCC_3.3V

VCC_1.8V

JP7

()

123

IO_V

C91
22u

GND

GS4911 decoupling

DECOUPLING @ PINS 3,10,14,45,53,54

1V8_GS4911VCC_1.8V

C94

0.1u

3V3_SRC4382

C140

0.1u

R73 2R

3V3_PLL_SRC4382_B

Between pins 9 and 10
SRC-B

GND

C142

C141

0.1u

10u

R67

0R

C80

C73

C72

10u

10u

0.1u

GND

IO_V

R68

0R

C96

C105

0.1u

10u

GND

C81

0.1u

IO_V_GS4911

C104
10u

C82
10n

DECOUPLING @ PINS18,31,38,50,62

C97

C75

C74

0.1u

10n

10n

C99

C100

C98

C83

10n

10n

C76
10n

C101

10n

10n

10n

C78

C77

10n

C111

10n

0.1u

GND

VDD_XTAL_GS4911VCC_3.3V

DECOUPLING

R70

@ PIN 5

0R

C106

C115

10u

0.1u

GND

1V8_Core_GS4911VCC_1.8V

R71

0R

C113

C112

10u

10u

C102

C107

10n

10u

DECOUPLING @
PINS 26,44

C114

C118

C117

0.1u

10n

10n

Figure 2-4: Power Schematic

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

12 of 22

3. Board Layout

Figure 3-1: Layer 1 (Top Layer)

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

13 of 22

Figure 3-2: Layer 2 (Ground)

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

14 of 22

Figure 3-3: Layer 3 (Power)

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

15 of 22

Figure 3-4: Layer 4 (Signal 1)

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

16 of 22

Figure 3-5: Layer 5 (Signal 2)

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

17 of 22

Figure 3-6: Layer 6 (Bottom Layer)

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

18 of 22

4. Bill of Materials

Table 4-1: Bill of Materials

Quantity Reference Part

14 C3, C4, C5, C6, C9, C10, C14, C17, C19, C24,

C29, C32, C34, C40

22 C7, C18, C36, C73, C80, C93, C95, C104, C105,

C106, C107, C110, C112, C113, C129, C130,
C131, C134, C135, C136, C139, C141

8 C8, C15, C16, C25, C30, C31, C33, C37 1μF Capacitor (0603)

5 C12, C27, C85, C87, C91 22μF Capacitor (0805)

1 C20 EEV-FK1C221XP Capacitor

30 C26, C69, C72, C81, C84, C92, C94, C96, C97,

C108, C109, C111, C114, C115, C116, C122,
C125, C126, C127, C128, C137, C138, C140,
C142, C143, C144, C145, C146, C147, C148

1 C35 100pF Capacitor (0402)

2 C39, C41 4.7μF Capacitor (0603)

2 C43, C44 16pF Capacitor (0603)

3 C70, C86, C90 1μF Capacitor (0402)

15 C74, C75, C76, C77, C78, C82, C83, C88, C98,

C99, C100, C101, C102, C117, C118

1 C119 38pF Capacitor (0402)

10nF Capacitor (402)

10μF Capacitor (0603)

(CT-CAP/PANA_FK_D8)

0.1μF Capacitor (0603)

10nF Capacitor (0402)

1 C120 24pF Capacitor (0402)

1 D7 LNJ311G8P (1206_LED)

2 JP1, JP8 TSW-105-07-L-D

1JP7 BLKCON

.100/VH/TM1SQ/W.100/3

1 J1 5V Input

(CON_WEID5MM_2_PWR)

2 J3, J4 UCBBJE20-1 (BNC_EDGEMNT

_GHZ-POUR-2LYR-ER3.8)

4 J13, J14, J15, J16 BCJ-FPLV01

1J25 SQT-124-01-F-D-RA (HEADER

2MM_48_2X24_INVERSE)

2 J27, J29 SQT-105-01-F-D-RA (HEADER

2MM_10_2X5_INVERSE)

1 J30 4 HEADER (header_4_1x4)

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

19 of 22

Table 4-1: Bill of Materials

Quantity Reference Part

2 L3, L4 5.6nH Inductor (0402)

16 R1, R6, R9, R11, R13, R67, R68, R69, R70, R71,

R75, R76, R81, R82, R112, R114

1 R2 3.57kΩ Resistor (0603)

3 R4, R86, R88 1.15kΩ Resistor (0603)

6 R7, R92, R93, R107, R110, R111 105Ω Resistor (0603)

1 R14 200Ω Resistor (0603)

9 R20, R21, R22, R77, R78, R79, R80, R95, R99 10kΩ Resistor (0603)

1 R23 750Ω Resistor (0402)

9 R24, R26, R27, R28, R101, R102, R103, R104,

R105

1 R32 240Ω Resistor (0603)

1 R66 49.9kΩ Resistor (0603)

2R72, R73 2Ω Resistor (0805)

1 R97 1MΩ Resistor (0402)

1 R98 22Ω Resistor (0603)

1R108 0Ω Resistor (0402)

2 RN1, RN2 500Ω Resistor Network

1 SW6 SW8_LOGIC_DIP_TH

0Ω Resistor (0603)

75Ω Resistor (0402)

1 SW7 SW6_LOGIC_DIP_TH

1 S1B3S-1002

12 TP2, TP3, TP8, TP9, TP10, TP11, TP12, TP16,

TP17, TP21, TP22, TP23

1 U1 MAX6823V (SOT23)

1 U4 LT3021ES8-1.2 (CT-SOIC_8)

1U5 GS2972

4 U10, U11, U12, U13 SN65LVDT2 (SOT23-5)

1 U14 TPS74201_RGW

1U15 SN74LVC1T45DBVR (sot23-6)

1 U16 LT3021ES8-1.8 (CT-SOIC_8)

1 U17 FXL4TD245 (mlp16e)

2 U18, U22 SN74LVC1G3157 (S

1U20 GS4911B (64QFN-9X9-P65)

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

Via (CT-TP)

(CT-BGA_100_11X11_1.00)

(20QFN-5X5(MOD))

OT23-6)

20 of 22

Table 4-1: Bill of Materials

Quantity Reference Part

2 U24, U28 FXL2TD245 (mac010a)

1U25 HSMF-C165

2 U26, U27 SRC4382 (48-TQFP)

1Y2 CS10-27.000M

(SM/XTAL_6.0X3.5/2)

Parts Not To Be Populated

1 R17 DNP (0603)

2 R65, R106 DNP (0603)

1 R109 DNP (0402)

2 R113, R115 DNP (0603)

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

21 of 22

DOCUMENT IDENTIFICATION

USER GUIDE

Information relating to this product and the application or design described
herein is believed to be reliable, however such information is provided as a
guide only and Gennum assumes no liability for any errors in this document, or
for the application or design described herein. Gennum reserves the right to
make changes to the product or this document at any time without notice.

GENNUM CORPORATION

Mailing Address: P.O. Box 489, Station A, Burlington, Ontario L7R 3Y3 Canada

Street Addresses: 4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada

Phone: [phone] Fax: [phone]

Email: [e-mail] www.gennum.com

CAUTION

ELECTROSTATIC SENSITIVE DEVICES

DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A
STATIC-FREE WORKSTATION

OTTAWA DESIGN CENTRE

232 Herzberg Road, Suite 101
Kanata, Ontario K2K 2A1
Canada

Phone: [phone]

Fax: [phone]

UNITED KINGDOM DESIGN CENTRE

North Building, Walden Court
Parsonage Lane,
Bishop’s Stortford Hertfordshire, CM23 6DB
Great Britain

Phone: [phone]

Fax: [phone]

JAPAN KK

Shinjuku Green Tower Building 27F
6-14-1, Nishi Shinjuku
Shinjuku-ku, Tokyo, 160-0023
Japan

Phone: [phone]

Fax: [phone]

Email: [e-mail]

Web Site: http://www.gennum.co.jp

Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of
the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent
infringement.

All other trademarks mentioned are the properties of their respective owners.

GENNUM and the Gennum logo are registered trademarks of Gennum Corporation.

© Copyright 2008 Gennum Corporation. All rights reserved. Printed in Canada.

www.gennum.com

SNOWBUSH IP - A DIVISION OF GENNUM

439 University Ave. Suite 1700
Toronto, Ontario M5G 1Y8
Canada

Phone: [phone]

Fax: [phone]

Web Site: http://www.snowbush.com

AGUASCALLIENTES PHYSICAL DESIGN
CENTER

Venustiano Carranza 122 Int. 1
Centro, Aguascalientes
Mexico CP 20000

Phone: [phone]

GERMANY

Niederlassung Deutschland
Stefan-George-Ring 29
81929 München, Germany

Phone: [phone]

Fax: [phone]

Email: [e-mail]

UNITED STATES - WESTERN REGION

Bayshore Plaza
2107 N 1st Street, Suite #300
San Jose, CA 95131
United States

Phone: [phone]

Fax: [phone]

UNITED STATES - EASTERN REGION

4281 Harvester Road
Burlington, Ontario L7L 5M4
Canada

Phone: [phone]

Fax: [phone]

TA IW A N

6F-4, No.51, Sec.2, Keelung Rd.
Sinyi District, Taipei City 11502

Taiwan R.O.C.

Phone: [phone]

Fax: [phone]

KOREA

8F, Jinnex Lakeview Bldg.
65-2, Bangidong, Songpagu
Seoul, Korea 138-828

Phone: [phone]

Fax: [phone]

EB-GS2972
Evaluation Board User Guide
50283 - 2 May 2012

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