Page 1
NI 5421 Specifications
NI PXI/PCI-5421 16-Bit 100 MS/s Arbitrary Waveform Generator
Unless otherwise noted, the following conditions were used for each
specification:
• Analog Filter enabled.
• Interpolation set to maximum allowed factor for a given sample rate.
• Signals terminated with 50 Ω.
• Direct Path set to 1 V
and High-Gain Amplifier Path set to 12 V
• Sample clock set to 100 MS/s.
Typical values are representative of an average unit operating at room
temperature. Specifications are subject to change without notice. For the
most recent NI 5421 specifications, visit
To access all the NI 5421 documentation, including the NI Signal
Generators Getting Started Guide, which contains functional descriptions
of the NI 5421 signals, navigate to Start»Programs»National
Instruments»NI-FGEN»Documentation.
Hot Surface If the NI 5421 has been in use, it may exceed safe handling temperatures and
cause burns. Allow the NI 5421 to cool before removing it from the chassis.
Contents
, Low-Gain Amplifier Path set to 2 V
pk-pk
.
pk-pk
ni.com/manuals.
pk-pk
,
CH 0 ........................................................................................................ 2
Sample Clock .......................................................................................... 14
Onboard Clock ........................................................................................ 17
Phase-Locked Loop (PLL) Reference Clock .......................................... 18
CLK IN ................................................................................................... 19
PFI 0 and PFI 1 ....................................................................................... 20
DIGITAL DATA & CONTROL (DDC) ................................................ 22
Start Trigger ............................................................................................ 24
Markers ................................................................................................... 26
Waveform and Instruction Memory Utilization...................................... 27
Calibration............................................................................................... 29
Power ...................................................................................................... 29
Software .................................................................................................. 30
Environment............................................................................................ 31
Safety, Electromagnetic Compatibility, and CE Compliance................. 33
Physical ...................................................................................................34
Where to Go for Support......................................................................... 36
Page 2
CH 0
(Channel 0 Analog Output, Front Panel Connector)
Table 1.
Specification Val ue Comments
Number of
1 —
Channels
Connector SMB (jack) —
Output Voltage Characteristics
Output Paths 1. The software-selectable Main Output Path setting
provides full-scale voltages from 12.00 V
5.64 mV
into a 50 Ω load. NI-FGEN uses either the
pk-pk
pk-pk
to
—
Low-Gain Amplifier or the High-Gain Amplifier when
the Main Output Path is selected, depending on the Gain
attribute.
2. The software-selectable Direct Path is optimized for
IF applications and provides full-scale voltages from
DAC
1.000 V
16 bits —
to 0.707 V
pk-pk
pk-pk
.
Resolution
NI 5421 Specifications 2 ni.com
Page 3
Table 1. (Continued)
Specification Val ue Comments
Amplitude and Offset
Amplitude
Amplitude (V
) 1. Amplitude
pk-pk
Range
Path Load
Minimum Value Maximum Value
Direct 50 Ω 0.707 1.00
1 kΩ 1.35 1.91
Open 1.41 2.00
Low-
50 Ω 0.00564 2.00
Gain
Amplifier
1 kΩ 0.0107 3.81
Open 0.0113 4.00
High-
50 Ω 0.0338 12.0
Gain
Amplifier
1 kΩ 0.0644 22.9
Open 0.0676 24.0
Amplitude
3 digits —
Resolution
Offset Range Span of ±25% of Amplitude Range with increments
<0.0014% of Amplitude Range.
values assume
the full scale
of the DAC is
utilized. If an
amplitude
smaller than
the minimum
value is
desired, then
waveforms less
than full scale
of the DAC can
be used.
2. NI-FGEN
compensates
for userspecified
resistive loads.
Not available on
the Direct Path.
© National Instruments Corporation 3 NI 5421 Specifications
Page 4
Table 1. (Continued)
Specification Val ue Comments
Maximum Output Voltage
Maximum
Path Load Maximum Output Voltage (V
Output
Vo l t a g e
Direct 50 Ω ±0.500
1 kΩ ±0.953
Open ±1.000
LowGain
Amplifier
50 Ω ±1.000
1 kΩ ±1.905
Open ±2.000
High-
Gain
Amplifier
50 Ω ±6.000
1 kΩ ±11.43
Open ±12.00
Accuracy
DC Accuracy For the Low-Gain or High-Gain Amplifier Path:
±0.2% of Amplitude ± 0.05% of Offset ±500 µV
(within ±10 °C of self-calibration temperature)
±0.4% of Amplitude ± 0.05% of Offset ±1 mV
(0 °C to 55 °C)
For the Direct Path:
Gain Accuracy: ±0.2% (within ±10 °C of self-calibration
temperature)
Gain Accuracy: ±0.4% (0 °C to 55 °C)
DC Offset Error: ±30 mV (0 °C to 55 °C)
) The Maximum
pk-pk
Output Voltage
of the NI 5421 is
determined by
the Amplitude
Range and the
Offset Range.
All paths are
calibrated for
amplitude and
gain errors. The
Low-Gain and
High-Gain
Amplifier Paths
also are
calibrated for
offset errors.
Specifications
valid only for
high impedance.
AC Amplitude
Accuracy
±1.0% of Amplitude ±1 mV 50 kHz sine
wave.
Output Characteristics
Output
50 Ω nominal or 75 Ω nominal, software-selectable. —
Impedance
Load
Impedance
Output amplitude is compensated for user-specified load
impedances.
—
Compensation
NI 5421 Specifications 4 ni.com
Page 5
Table 1. (Continued)
Specification Val ue Comments
Output
DC —
Coupling
Output
Enable
Software-selectable. When disabled, CH 0 out is terminated
with a 1 W resistor with a value equal to the selected output
—
impedance.
Maximum
Output
Overload
The CH 0 output can be connected to a 50 Ω, ±12 V
(±8 V for the Direct Path) source without sustaining any
damage. No damage occurs if the CH 0 output is shorted to
—
ground indefinitely.
Waveform
Summing
The CH 0 output supports waveform summing among
similar paths—specifically, the outputs of multiple NI 5421
—
signal generators can be connected together.
Frequency and Transient Response
Bandwidth 43 MHz Measured at
–3 dB.
Digital
Interpolation
Software-selectable Finite Impulse Response (FIR) filter.
Available interpolation factors are 2, 4, or 8.
—
Filter
Analog
Filter
Software-selectable 7-pole elliptical filter. Available on
Low-Gain
Amplifier and
High-Gain
Amplifier Paths.
Passband
Flatness
Pulse
Response
Direct
+0.6 dB to –0.4 dB
100 Hz to 40 MHz
Direct
+0.5 dB to –1.0 dB
100 Hz to 20 MHz
Path —
Low-Gain
Amplifiers
High-Gain
Amplifiers
+0.5 dB to –1.2 dB
100 Hz to 20 MHz
Path Analog Filter
Low-Gain
Amplifier
High-Gain
Amplifier
and Digital
Interpolation
Filter disabled.
Rise/Fall Time <5 ns <8 ns <10 ns
Aberration <10% <5% <5%
© National Instruments Corporation 5 NI 5421 Specifications
Page 6
2.0
1.0
0.0
–1.0
–2.0
–3.0
–4.0
dB
–5.0
–6.0
–7.0
–8.0
–9.0
–10.0
1.0M 10.0M 48.0M
Guaranteed Specification
Typical
Frequency (Hz)
+0.3 dB
–0.4 dB
+0.4 dB
–0.4 dB
–0.4 dB
Figure 1. Normalized Passband Flatness, Direct Path
2.0
+0.6 dB
1.6
1.2
0.8
0.4
0.0
Amplitude (V)
–0.4
–0.8
–1.2
–1.6
–2.0
0.0 20.0n 40.0n 60.0n 80.0n 100.0n
Time (s)
Figure 2. Pulse Response, Low-Gain Amplifier Path 50
Ω Load
NI 5421 Specifications 6 ni.com
Page 7
Table 1. (Continued)
Specification Val ue Comments
Suggested Maximum Frequencies for Common Functions
Function Path Disable the
Analog Filter
and the Digital
Interpolation
Filter for Square,
Direct
Low-Gain
Amplifier
High-Gain
Amplifier
Sine 43 MHz 43 MHz 43 MHz
Ramp, and
Square Not Recommended 25 MHz 12.5 MHz
Triangle.
Ramp Not Recommended 5 MHz 5 MHz
Triangle Not Recommended 5 MHz 5 MHz
Spectral Characteristics
Signal to
Path Amplitude
Noise and
Distortion
(SINAD)
Direct
Low-Gain
Amplifier
1 MHz 64 dB 66 dB 63 dB
10 MHz 61 dB 60 dB 47 dB
20 MHz 57 dB 56 dB 42 dB
30 MHz 60 dB 62 dB 62 dB
40 MHz 60 dB 62 dB 62 dB
43 MHz 58 dB 60 dB 55 dB
High-Gain
Amplifier
–1 dBFS.
Measured from
DC to 50 MHz.
SINAD at low
amplitudes is
limited by a
–148 dBm/Hz
noise floor.
© National Instruments Corporation 7 NI 5421 Specifications
Page 8
Table 1. (Continued)
Specification Val ue Comments
Spectral Characteristics (Continued)
Spurious-Free
Path Amplitude
Dynamic
Range
(SFDR) with
Harmonics
Direct
Low-Gain
Amplifier
1 MHz –76 dBc –71 dBc –58 dBc
10 MHz –68 dBc –64 dBc –47 dBc
20 MHz –60 dBc –57 dBc –42 dBc
30 MHz –73 dBc –73 dBc –74 dBc
40 MHz –76 dBc –73 dBc –74 dBc
43 MHz –78 dBc –75 dBc –59 dBc
Spurious-Free
Path Amplitude
Dynamic
Range
(SFDR)
without
Harmonics
Direct
Low-Gain
Amplifier
1 MHz –88 dBFS –91 dBFS –91 dBFS
10 MHz –87 dBFS –89 dBFS –91 dBFS
20 MHz –80 dBFS –89 dBFS –89 dBFS
30 MHz –73 dBFS –73 dBFS –74 dBFS
40 MHz –76 dBFS –73 dBFS –74 dBFS
High-Gain
Amplifier
High-Gain
Amplifier
–1 dBFS.
Measured from
DC to 50 MHz.
Also called
harmonic
distortion.
SFDR with
harmonics at low
amplitudes is
limited by a
–148 dBm/Hz
noise floor.
All values are
typical and
include aliased
harmonics.
–1 dBFS.
Measured from
DC to 50 MHz.
SFDR without
harmonics at low
amplitudes is
limited by a
–148 dBm/Hz
noise floor.
All values are
typical and
include aliased
harmonics.
43 MHz –78 dBFS –75 dBFS –60 dBFS
NI 5421 Specifications 8 ni.com
Page 9
Table 1. (Continued)
Specification Val ue Comments
Spectral Characteristics (Continued)
0 ºC to 40 ºC
Path Amplitude
Total
Harmonic
Distortion
(THD)
Direct
Low-Gain
Amplifier
–77 dBc
20 kHz –77 dBc (typical)
(typical)
–70 dBc
1 MHz –75 dBc (typical)
(typical)
5 MHz –68 dBc –68 dBc –55 dBc
10 MHz –65 dBc –61 dBc –46 dBc
20 MHz –55 dBc –53 dBc —
30 MHz –50 dBc –48 dBc —
40 MHz –48 dBc –46 dBc —
43 MHz –47 dBc –45 dBc —
0 ºC to 55 ºC
Path Amplitude
Total
Harmonic
Distortion
(THD)
Direct
Low-Gain
Amplifier
High-Gain
Amplifier
–77 dBc (typical)
–62 dBc (typical)
High-Gain
Amplifier
–1 dBFS.
Includes the 2
through the 6
harmonic.
–1 dBFS.
Includes the 2
through the 6
harmonic.
nd
th
nd
th
–76 dBc
20 kHz –76 dBc (typical)
(typical)
–76 dBc (typical)
–69 dBc
1 MHz –74 dBc (typical)
(typical)
–61 dBc (typical)
5 MHz –67 dBc –67 dBc –54 dBc
10 MHz –63 dBc –60 dBc –45 dBc
20 MHz –54 dBc –52 dBc —
30 MHz –48 dBc –46 dBc —
40 MHz –46 dBc –41 dBc —
43 MHz –45 dBc –41 dBc —
© National Instruments Corporation 9 NI 5421 Specifications
Page 10
Table 1. (Continued)
Specification Val ue Comments
Average Noise
Density
Intermodulation
Distortion (IMD)
10.2 MHz and
11.2 MHz
Amplitude
Path
V
pk-pk
Range
dBm dBm/Hz
Average Noise Density
nV
-----------
Hz
dBFS/
Hz
Direct 1 4.0 18 –142 –146.0
Low Gain 0.06 –20.4 9 –148 –127.6
Low Gain 0.1 –16.0 9 –148 –132.0
Low Gain 0.4 –4.0 13 –145 –141.0
Low Gain 1 4.0 18 –142 –146.0
Low Gain 2 10.0 35 –136 –146.0
High Gain 4 16.0 71 –130 –146.0
High Gain 12 25.6 213 –120 –145.6
Path Each tone is
Direct
Low-Gain
Amplifier
High-Gain
Amplifier
–81 dBc –80 dBc – 62 dBc
Average Noise
Density at small
amplitudes is
limited by a
–148 dBm/Hz
noise floor.
–7 dBFS.
All values
are typical.
10.6 MHz and
–81 dBc –79 dBc – 61 dBc
10.8 MHz
19.5 MHz and
–78 dBc –66 dBc –54 dBc
20.5 MHz
19.9 MHz and
–78 dBc –65 dBc –50 dBc
20.1 MHz
34.0MHz and
–75 dBc –58 dBc –51 dBc
35.0 MHz
34.8 MHz and
–75 dBc –58 dBc –51 dBc
35.0 MHz
42.0 MHz and
–75 dBc –55 dBc –51 dBc
43.0 MHz
42.8 MHz and
–75 dBc –55 dBc –50 dBc
43.0 MHz
NI 5421 Specifications 10 ni.com
Page 11
10.0
0.0
–10.0
–20.0
–30.0
–40.0
dBm
–50.0
–60.0
–70.0
–80.0
–90.0
0.0 25.0M 50.0M 75.0M 100.0M 125.0M 158.0M 175.0M 200.0M
Frequency (Hz)
Figure 3. 10 MHz Single-Tone Spectrum, Direct Path, 100 MS/s,
Interpolation Factor Set to 4
Note The noise floor in Figure 3 is limited by the measurement device. Refer to the
Average Noise Density specification.
© National Instruments Corporation 11 NI 5421 Specifications
Page 12
20.0
10.0
0.0
–10.0
–20.0
–30.0
dBm
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
0.0 25.0M 50.0M 75.0M 100.0M 125.0M 150.0M 175.0M 200.0M
Frequency (Hz)
Figure 4. 10 MHz Single-Tone Spectrum, Low-Gain Amplifier Path, 100 MS/s,
Interpolation Factor Set to 4
Note The noise floor in Figure 4 is limited by the measurement device. Refer to the
Average Noise Density specification.
NI 5421 Specifications 12 ni.com
Page 13
10.0
0.0
–10.0
–20.0
–30.0
–40.0
dBm
–50.0
–60.0
–70.0
–80.0
–90.0
0.0 25.0M 50.0M 75.0M 100.0M 125.0M 150.0M 175.0M 200.0M
Frequency (Hz)
Figure 5. Direct Path, 2-Tone Spectrum (Typical)
Note
The noise floor in Figure 5 is limited by the measurement device. Refer to the
Average Noise Density specification.
© National Instruments Corporation 13 NI 5421 Specifications
Page 14
Sample Clock
Table 2.
Specification Val ue Comments
Sources 1. Internal, Divide-by-N (N ≥ 1)
2. Internal, DDS-based, High-Resolution
3. External, CLK IN (SMB front panel connector)
4. External, DDC CLK IN (DIGITAL DATA &
CONTROL front panel connector)
5. NI PXI-5421: External, PXI Star trigger
(backplane connector)
6. NI PXI-5421: External, PXI_Trig<0..7>
(backplane connector)
NI PCI-5421: External, RTSI<0..7>
Sample Rate Range and Resolution
Sample Clock
Source
Divide-by-N 23.84 S/s to 100 MS/s Settable to (100 MS/s) / N
High
Resolution
CLK IN 200 kS/s to 105 MS/s Resolution determined by
DDC CLK IN 10 S/s to 105 MS/s
NI PXI-5421
PXI Star
Trigger
Sample Rate Range Sample Rate Resolution
(1 ≤ N ≤ 4,194,304)
10 S/s to 100 MS/s 1.06 µHz
external clock source.
10 S/s to 105 MS/s
External Sample Clock duty
cycle tolerance 40% to 60%.
Refer to the
Onboard Clock
section for more
information
about Internal
Clock Sources.
—
NI PXI-5421
PXI_Trig<0..7>
NI PCI-5421
RTSI<0..7>
NI 5421 Specifications 14 ni.com
10 S/s to 20 MS/s
10 S/s to 20 MS/s
Page 15
Table 2. (Continued)
Specification Val ue Comments
Effective Sample Rate
Sample Rate
(MS/s)
10 S/s to
105 MS/s
12.5 MS/s to
105 MS/s
10 MS/s to
100 MS/s
10 MS/s to
50 MS/s
Interpolation
Effective Sample
Factor
1 (Off) 10 S/s to
105 MS/s
2 25 MS/s to
210 MS/s
4 40 MS/s to
400 MS/s
8 80 MS/s to
400 MS/s
Sample Clock Delay Range and Resolution
Sample Clock
Source
Delay Adjustment
Range
Delay Adjustment
Resolution
Divide-by-N ±1 sample clock period <10 ps
HighResolution
±1 sample clock period Sample Clock
Period/16,384
External (all) 0 ns to 7.6 ns <15 ps
Rate
Effective Sample
Rate =
(Interpolation
Factor) * (Sample
Rate)
—
© National Instruments Corporation 15 NI 5421 Specifications
Page 16
Table 2. (Continued)
Specification Val ue Comments
System Phase Noise and Jitter (10 MHz Carrier)
Sample Clock
Source
NI PXI-5421
Divide-by-N
NI PCI-5421
Divide-by-N
HighResolution
1
NI PXI-5421
CLK IN
NI PCI-5421
CLK IN
NI PXI-5421
PXI Star
2
Trigger
External
Sample Clock
Input Jitter
Tolerance
System Phase Noise
Density
(dBc/Hz) Offset
100 Hz 1 kHz 10 kHz
System Output Jitter
(Integrated from
100 Hz to 100 kHz)
–107 –121 –137 <1.2 ps rms
–110 –127 –137 <2.0 ps rms
–109 –121 –123 <4.2 ps rms
–111 –122 –135 <1.2 ps rms
–113 –125 –135 <2.0 ps rms
–115 –118 –130 <3.0 ps rms
Cycle-Cycle Jitter ±300 ps
Period Jitter ±1 ns
1. HighResolution
specifications
increase as the
Sample Rate is
decreased.
2. NI PXI-5421
PXI Star
trigger
specification is
valid when the
Sample Clock
Source is
locked to
PXI_CLK10.
—
NI 5421 Specifications 16 ni.com
Page 17
Table 2. (Continued)
Specification Val ue Comments
Sample Clock Exporting
Exported
Sample Clock
Destinations
Exported
Sample Clock
Destinations
PFI<0..1> 105 MHz PFI 0: 6 ps rms
DDC CLK
OUT
NI PXI-5421
PXI_Trig<0..7>
NI PCI-5421
RTSI<0..7>
1. PFI<0..1> (SMB front panel connectors)
2. DDC CLK OUT (DIGITAL DATA & CONTROL front
panel connector)
3. NI PXI-5421—PXI_Trig<0..7> (backplane connector)
NI PCI-5421—RTSI<0..7>
Maximum
Frequency
105 MHz 40 ps rms 40% to 60%
20 MHz — —
20 MHz — —
Jitter (Typical) Duty Cycle
PFI 1: 12 ps rms
Onboard Clock
(Internal VCXO)
Exported Sample
Clocks can be
divided by integer
K (1 ≤ K ≤
4,194,304).
—
25% to 65%
Table 3.
Specification Val ue Comments
Clock Source Internal sample clocks can either be locked to a Reference
Clock using a phase-locked loop or be derived from the
onboard VCXO frequency reference.
Frequency
Accuracy
© National Instruments Corporation 17 NI 5421 Specifications
±25 ppm —
—
Page 18
Phase-Locked Loop (PLL) Reference Clock
Table 4.
Specification Val ue Comments
Sources 1. NI PXI-5421—PXI_CLK10 (backplane connector)
NI PCI-5421—RTSI_7 (RTSI_CLK)
2. CLK IN (SMB front panel connector)
Frequency
Accuracy
Lock Time Typical: 70 ms.
Frequency
Range
Duty Cycle
Range
Exported PLL
Reference
Clock
Destinations
When using the PLL, the Frequency Accuracy of the
NI 5421 is solely dependent on the Frequency Accuracy
of the PLL Reference Clock Source.
Maximum: 200 ms.
5 MHz to 20 MHz in increments of 1 MHz.
Default of 10 MHz.
The PLL Reference Clock Frequency has to be accurate
to ±50 ppm.
40% to 60% —
1. PFI<0..1> (SMB front panel connectors)
2. NI PXI-5421—PXI_Trig<0..7> (backplane connector)
NI PCI-5421—RTSI<0..7>
The PLL
Reference Clock
provides the
reference
frequency for the
phase-locked
loop.
—
—
—
—
NI 5421 Specifications 18 ni.com
Page 19
CLK IN
(Sample Clock and Reference Clock Input, Front Panel Connector)
Table 5.
Specification Val ue Comments
Connector SMB (jack) —
Direction Input —
Destinations 1. Sample Clock
—
2. PLL Reference Clock
Frequency
Range
1 MHz to 105 MHz (Sample Clock destination and
sine waves)
—
200 kHz to 105 MHz (Sample Clock destination and
square waves)
5 MHz to 20 MHz (PLL Reference Clock destination)
Input Voltage
Range
Maximum
Sine wave: 0.65 V
pk-pk
to 2.8 V
into 50 Ω
pk-pk
—
(0 dBm to +13 dBm)
Square wave: 0.2 V
pk-pk
to 2.8 V
into 50 Ω
pk-pk
±10 V —
Input Overload
Input
50 Ω —
Impedance
Input Coupling AC —
© National Instruments Corporation 19 NI 5421 Specifications
Page 20
PFI 0 and PFI 1
(Programmable Function Interface, Front Panel Connectors)
Table 6.
Specification Val ue Comments
Connectors Two SMB (jack) —
Direction Bi-directional —
Frequency
Range
As an Input (Trigger)
Destinations Start Trigger —
Maximum
Input Overload
V
IH
V
IL
Input
Impedance
As an Output (Event)
Sources 1. Sample Clock divided by integer K (1 ≤ K ≤ 4,194,304)
DC to 105 MHz —
–2 V to +7 V —
2.0 V
0.8 V
1 kΩ
—
2. Sample Clock Timebase (100 MHz) divided by integer
M (2 ≤ M ≤ 4,194,304)
3. PLL Reference Clock
4. Marker
5. Exported Start Trigger (Out Start Trigger)
Output
Impedance
Maximum
Output
Overload
NI 5421 Specifications 20 ni.com
50 Ω —
–2 V to +7 V —
Page 21
Table 6. (Continued)
Specification Val ue Comments
V
OH
V
OL
Rise/Fall Time
(20% to 80%)
Minimum: 2.9 V (open load), 1.4 V (50 Ω load) Output drivers are
+3.3 V TTL
compatible.
Measured with a
Maximum: 0.2 V (open load), 0.2 V (50 Ω load)
1 m cable.
≤ 2.0 ns Load of 10 pF.
© National Instruments Corporation 21 NI 5421 Specifications
Page 22
DIGITAL DATA & CONTROL (DDC)
Optional Front Panel Connector
Table 7.
Specification Val ue Comments
Connector
Type
Number of
Data Output
Signals
Control
Signals
Ground 23 pins —
Output Signal Characteristics (Includes Data Outputs, DDC CLK OUT, and PFI<4..5>)
Signal Type LVDS (Low-Voltage Differential Signal) —
Signal
Characteristics
V
OH
V
OL
Differential
Output Voltage
Output
Common-Mode
Vo l t a g e
Rise/Fall Time — 0.8 ns 1.6 ns
68-pin VHDCI female receptacle —
16 —
1. DDC CLK OUT (clock output)
2. DDC CLK IN (clock input)
3. PFI 2 (input)
4. PFI 3 (input)
5. PFI 4 (output)
6. PFI 5 (output)
Minimum Typical Maximum
— 1.3 V 1.7 V
0.8 V 1.0 V —
0.25 V — 0.45 V
1.125 V — 1.375 V
1. Tested with
2. Measured at
3. Load
4. Driver and
—
100 Ω
differential
load.
the front panel.
capacitance
<10 pF.
receiver
comply with
ANSI/TIA/
EIA-644.
5. Rise time is
20% to 80%.
NI 5421 Specifications 22 ni.com
Page 23
Table 7. (Continued)
Specification Val ue Comments
Output Signal Characteristics (Continued)
Output Skew Typical: 1 ns, maximum 2 ns. Skew between any
—
two outputs on the DIGITAL DATA & CONTROL
front panel connector.
Output
Enable/Disable
Controlled through the software on all Data Output Signals
and Control Signals collectively. When disabled, the outputs
—
go to a high-impedance state.
Maximum
–0.3 V to +3.9 V —
Output
Overload
Input Signal Characteristics (Includes DDC CLK IN and PFI<2..3>)
Signal Type LVDS (Low-Voltage Differential Signal) —
Input
100 Ω —
Differential
Impedance
Maximum
–0.3 V to +3.9 V —
Output
Overload
Signal
Characteristics
Differential
Minimum Maximum
0.1 V 0.5 V
—
Input Voltage
Input Common
0.2 V 2.2 V
Mode Voltage
DDC CLK OUT
Clocking
Format
Frequency
Data outputs and markers change on the falling edge of
—
DDC CLK OUT.
Refer to the Sample Clock section for more information. —
Range
Duty Cycle 40% to 60% —
Jitter 40 ps rms —
© National Instruments Corporation 23 NI 5421 Specifications
Page 24
Table 7. (Continued)
Specification Val ue Comments
DDC CLK IN
Clocking
Format
Frequency
Range
Input Duty
Cycle
Tolerance
Input Jitter
Tolerances
DDC Data Output signals change on the rising edge of
DDC CLK IN.
10 Hz to 105 MHz —
40% to 60% —
300 ps pk-pk of Cycle-Cycle Jitter, and 1 ns rms of
Period Jitter.
—
—
Start Trigger
Table 8.
Specification Val ue Comments
Sources 1. PFI<0..1> (SMB front panel connectors)
2. PFI<2..3> (DIGITAL DATA & CONTROL front panel
connector)
3. NI PXI-5421—PXI_Trig<0..7> (backplane connector)
NI PCI-5421—RTSI<0..7>
—
4. NI PXI-5421—PXI Star trigger (backplane connector)
5. Software (use function call)
6. Immediate (does not wait for a trigger). Default.
Modes 1. Single
2. Continuous
3. Stepped
4. Burst
Edge Detection Rising —
Minimum
Pulse Width
NI 5421 Specifications 24 ni.com
25 ns. Refer to ts1 at NI Signal Generators Help»Devices»
NI 5421»NI <bus>-5421»Triggering»Trigger Timing.
—
—
Page 25
Table 8. (Continued)
Specification Val ue Comments
Delay from
Start Trigger to
CH 0 Analog
Output
Delay from
Start Trigger to
Digital Data
Output
Trigger Exporting
Exported
Trigger
Destinations
Exported
Trigger Delay
Interpolation Factor Typical Delay Refer to ts2 at
Digital Interpolation Filter
disabled.
2 57 Sample Clock
43 Sample Clock
Periods + 110 ns
Periods + 110 ns
NI Signal
Generators
Help»Devices»
NI 5421»
NI <bus>-5421»
Triggering»
4 63 Sample Clock
Trigger Timing.
Periods + 110 ns
8 64 Sample Clock
Periods + 110 ns
40 Sample Clock periods + 110 ns. —
A signal used as a trigger can be routed out to any
—
destination listed in the Destinations specification
of Table 9.
65 ns (typical). Refer to ts3 at NI Signal Generators Help»
—
Devices»NI 5421»NI <bus>-5421»Triggering»Trigger
Timing.
Exported
Trigger Pulse
Width
© National Instruments Corporation 25 NI 5421 Specifications
>150 ns. Refer to ts4 at NI Signal Generators Help»
Devices»NI 5421»NI <bus>-5421»Triggering»Trigger
Timing.
—
Page 26
Markers
Table 9.
Specification Val ue Comments
Destinations 1. PFI<0..1> (SMB front panel connectors)
2. PFI<4..5> (DIGITAL DATA & CONTROL front panel
connector)
3. NI PXI-5421—PXI_Trig<0..6> (backplane connector)
NI PCI-5421—RTSI<0..7>
Quantity One Marker per Segment. —
Quantum Marker position must be placed at an integer multiple of
four samples.
Width >150 ns. Refer to tm2 at NI Signal Generators Help»
Devices»NI 5421»NI <bus>-5421»Waveform
Generation»Marker Events.
Skew
With Respect to
Destination
PFI<0..1> ±2 Sample Clock
PFI<4..5> N/A <2 ns
NI PXI-5421
PXI_Trig<0..6>
Analog Output
Periods
±2 Sample Clock
Periods
With Respect to
Digital Data
Output
N/A
N/A
Refer to tm1 at
NI Signal
Generators
Help»Devices»
NI 5421»
NI <bus>-5421»
Waveform
Generation»
Marker Events.
—
—
—
NI PCI-5421
RTSI<0..6>
Jitter 20 ps rms —
NI 5421 Specifications 26 ni.com
Page 27
Waveform and Instruction Memory Utilization
Table 10.
Specification Val ue Comments
Memory Usage The NI 5421 uses the Synchronization and Memory Core
(SMC) technology in which waveforms and instructions
share onboard memory. Parameters, such as number of
segments in sequence list, maximum number of waveforms
in memory, and number of samples available for waveform
storage, are flexible and user defined.
Onboard
Memory Size
Output Modes Arbitrary Waveform mode and Arbitrary Sequence mode —
Arbitrary
Waveform
Mode
Arbitrary
Sequence
Mode
8 MB standard:
8,388,608 bytes
In Arbitrary Waveform mode, a single waveform is selected
from the set of waveforms stored in onboard memory and
generated.
In Arbitrary Sequence mode, a sequence directs the NI 5421
to generate a set of waveforms in a specific order. Elements
of the sequence are referred to as segments. Each segment is
associated with a set of instructions. The instructions
identify which waveform is selected from the set of
waveforms in memory, how many loops (iterations) of the
waveform are generated, and at which sample in the
waveform a marker output signal is sent.
32 MB option:
33,554,432 bytes
256 MB option:
268,435,456 bytes
For more
information,
refer to NI Signal
Generators
Help»
Programming»
NI-TClk
Synchronization
Help.
—
—
—
Minimum
Waveform Size
(Samples)
© National Instruments Corporation 27 NI 5421 Specifications
Trigger Mode
Single 16 16
Continuous 16 96 @ > 50 MS/s
Stepped 32 96 @ >50 MS/s
Burst 16 512 @ >50 MS/s
Arbitrary
Waveform Mode
Arbitrary
Sequence Mode
32 @ ≤50 MS/s
32 @ ≤50 MS/s
256 @ ≤ 50 MS/s
The Minimum
Waveform Size
is sample rate
dependent in
Arbitrary
Sequence Mode.
Page 28
Table 10. (Continued)
Specification Val ue Comments
Loop Count 1 to 16,777,215.
—
Burst trigger: Unlimited
Quantum Waveform size must be an integer multiple of four samples. —
Memory Limits
8 MB Standard 32 MB Option 256 MB Option All trigger modes
Arbitrary
Waveform
4,194,176
Samples
16,777,088
Samples
134,217,600
Samples
except where
noted.
Mode,
Maximum
Waveform
Memory
Arbitrary
Sequence
Mode,
4,194,120
Samples
16,777,008
Samples
134,217,520
Samples
Condition: One
or two segments
in a sequence.
Maximum
Waveform
Memory
Arbitrary
Sequence
Mode,
65,000
Burst trigger:
8,000
262,000
Burst trigger:
32,000
2,097,000
Burst trigger:
262,000
Condition: One
or two segments
in a sequence.
Maximum
Waveforms
Arbitrary
Sequence
Mode,
Maximum
104,000
Burst trigger:
65,000
418,000
Burst trigger:
262,000
3,354,000
Burst trigger:
2,090,000
Condition:
Wav efo rm
memory is
<4,000 samples.
Segments in a
Sequence
NI 5421 Specifications 28 ni.com
Page 29
Calibration
Table 11.
Specification Val ue Comments
Self-Calibration An onboard, 24-bit ADC and precision voltage reference are
used to calibrate the DC gain and offset. The self-calibration
is initiated by the user through the software and takes
approximately 75 seconds to complete.
External
Calibration
Calibration
Interval
Warm-up Time 15 minutes —
The External Calibration calibrates the VCXO, voltage
reference, DC gain, and offset. Appropriate constants are
stored in nonvolatile memory.
Specifications valid within 2 years of External Calibration. —
—
—
Power
Table 12.
Specification Typical Operation Overload Operation Comments
+3.3 VDC 1.9 A 2.7 A Typical.
+5 VDC 2.0 A 2.2 A
+12 VDC 0.46 A 0.5 A
–12 VDC 0.01 A 0.01 A
Total Power 21.9 W 26.0 W
Overload
operation occurs
when CH 0 is
shorted to
ground.
© National Instruments Corporation 29 NI 5421 Specifications
Page 30
Software
Table 13.
Specification Val ue Comments
Driver
Software
Application
Software
Soft Front
Panel/
Interactive
Configuration
NI-FGEN 2.0 or later version. NI-FGEN is an
IVI-compliant driver that allows you to configure, control,
and calibrate the NI 5421. NI-FGEN provides application
programming interfaces for many development
environments.
NI-FGEN provides programming interfaces for the
following application development environments:
•LabVIEW
™
• LabWindows
/CVI
™
• Measurement Studio
• Microsoft Visual C/C++
• Microsoft Visual Basic
• Borland C/C++
The FGEN Soft Front Panel 1.3 or later supports interactive
control of the NI 5421. The FGEN Soft Front Panel is
included on the NI-FGEN driver CD.
Measurement & Automation Explorer (MAX) also provides
interactive configuration and test tools for the NI 5421.
MAX is also included on the NI-FGEN CD.
—
—
—
NI 5421 Specifications 30 ni.com
Page 31
Environment
NI PXI-5421 Environment
Note To ensure that the NI PXI-5421 cools effectively, follow the guidelines in the
Maintain Forced-Air Cooling Note to Users included in the NI 5421 kit. The NI PXI-5421
is intended for indoor use only.
Table 14.
Specifications Val ue Comments
Operating
Temperature
Storage
Temperature
Operating
Relative
Humidity
Storage
Relative
Humidity
Operating
Shock
Storage
Shock
Operating
Vibration
0 ºC to +55 ºC in all NI PXI chassis except the following:
0 ºC to +45 ºC when installed in an NI PXI-101x or
NI PXI-1000B chassis.
Meets IEC-60068-2-1 and IEC-60068-2-2.
–25 ºC to +85 ºC. Meets IEC-60068-2-1 and
IEC-60068-2-2.
10% to 90%, noncondensing. Meets IEC-60068-2-56. —
5% to 95%, noncondensing. Meets IEC-60068-2-56. —
30 g, half-sine, 11 ms pulse. Meets IEC-60068-2-27. Test
profile developed in accordance with MIL-PRF-28800F.
50 g, half-sine, 11 ms pulse. Meets IEC-60068-2-27. Test
profile developed in accordance with MIL-PRF-28800F.
5 Hz to 500 Hz, 0.31 g
. Meets IEC-60068-2-64. Spectral and jitter
rms
Spectral and jitter
specifications
could degrade.
specifications
could degrade.
—
—
—
Storage
Vibration
Altitude 2,000 m maximum (at 25 °C ambient temperature) —
Pollution
Degree
© National Instruments Corporation 31 NI 5421 Specifications
5 Hz to 500 Hz, 2.46 g
profile exceeds requirements of MIL-PRF-28800F, Class B.
2 —
. Meets IEC-60068-2-64. Test
rms
—
Page 32
NI PCI-5421 Environment
Note To ensure that the NI PCI-5421 cools effectively, follow the guidelines in the
Maintain Forced-Air Cooling Note to Users included in the NI 5421 kit. Also, to maximize
airflow and extend the life of the device, leave any adjacent PCI slots empty. The
NI PCI-5421 is intended for indoor use only.
Table 15.
Specifications Val ue Comments
Operating
0 ºC to +45 ºC. Meets IEC-60068-2-1 and IEC-60068-2-2. —
Temperature
Storage
Temperature
Operating
–25 ºC to +85 ºC. Meets IEC-60068-2-1 and
—
IEC-60068-2-2.
10% to 90%, noncondensing. Meets IEC-60068-2-56. —
Relative
Humidity
Storage
5% to 95%, noncondensing. Meets IEC-60068-2-56. —
Relative
Humidity
Storage
Shock
Storage
Vibration
50 g, half-sine, 11 ms pulse. Meets IEC-60068-2-27. Test
profile developed in accordance with MIL-PRF-28800F.
5 Hz to 500 Hz, 2.46 g
. Meets IEC-60068-2-64. Test
rms
profile exceeds requirements of MIL-PRF-28800F, Class B.
—
—
Altitude 2,000 m maximum (at 25 °C ambient temperature) —
Pollution
2 —
Degree
NI 5421 Specifications 32 ni.com
Page 33
Safety, Electromagnetic Compatibility, and CE Compliance
Table 16.
Specification Val ue Comments
Safety
Note: For UL and other safety certifications, refer to the product label or visit ni.com/
certification
Certification column.
Emissions EN 55011 Class A at 10 m
Immunity EN 61326:1997 + A2:2001, Table 1 —
EMC/EMI CE, C-Tick, and FCC Part 15 (Class A) Compliant
The NI 5421 is designed to meet the requirements of the
following standards of safety for electrical equipment
for measurement, control, and laboratory use:
IEC 61010-1, EN 61010-1
UL 61010-1
CAN/CSA-C22.2 No. 61010-1
, search by model number or product line, and click the appropriate link in the
FCC Part 15A above 1 GHz
Notes:
1. This device is not intended for, and is restricted
from, use in residential areas.
2. For EMC compliance, operate this device with
shielded cabling.
3. When connected to other test objects, this product
may cause radio interference. If this occurs, you
may be required to take adequate measures to
reduce the interference.
—
—
—
This product meets the essential requirements of applicable European Directives as amended for
CE marking, as follows:
Low-Voltage
Directive (safety)
Electromagnetic
Compatibility
Directive (EMC)
Note: Refer to the Declaration of Conformity (DoC) for this product for any additional regulatory
compliance information. To obtain the DoC for this product, visit
search by model number or product line, and click the appropriate link in the Certification column.
© National Instruments Corporation 33 NI 5421 Specifications
73/23/EEC —
89/336/EEC —
ni.com/certification,
Page 34
Physical
Table 17.
Specification Val ue Comments
NI PXI-5421 NI PCI-5421
Dimensions
Weigh t 345 g (12.1 oz) 419 g (14.8 oz) —
Front Panel Connectors
Label Function(s) Connector Type —
CH 0 Analog Output SMB (jack)
CLK IN Sample clock input and PLL
PFI 0 Marker output, trigger input,
PFI 1 Marker output, trigger input,
DIGITAL
DATA &
CONTROL
3U, One Slot,
PXI/cPCI Module
2.0 × 13.0 × 21.6 cm
(0.8 × 5.1 × 8.5 inches)
reference clock input.
sample clock output,
exported trigger output, and
PLL reference clock output.
sample clock output,
exported trigger output, and
PLL reference clock output.
Digital data output, trigger
input, exported trigger
output, markers, external
sample clock input, and
sample clock output.
34.07 × 10.67 × 2.03 cm
(13.4 × 4.20 × 0.8 inches)
SMB (jack)
SMB (jack)
SMB (jack)
68-pin VHDCI female
receptacle
—
NI 5421 Specifications 34 ni.com
Page 35
Table 17. (Continued)
Specification Val ue Comments
NI PXI-5421 Only—Front Panel LED Indicators
Label Function For more
ACCESS LED The ACCESS LED indicates the status of the PCI bus and
the interface from the NI 5421 to the controller.
information, refer
to the NI Signal
Generators Help.
ACTIVE LED The ACTIVE LED indicates the status of the onboard
generation hardware of the NI 5421.
Included Cable
1 (NI part number 763541-01), 50 Ω, BNC Male to
SMB Plug, RG223/U, Double Shielded, 1 m cable.
—
© National Instruments Corporation 35 NI 5421 Specifications
Page 36
Where to Go for Support
The National Instruments Web site is your complete resource for technical
support. At
troubleshooting and application development self-help resources to email
and phone assistance from NI Application Engineers.
A Declaration of Conformity (DoC) is our claim of compliance with the
Council of the European Communities using the manufacturer’s
declaration of conformity. This system affords the user protection for
electronic compatibility (EMC) and product safety. You can obtain the DoC
for your product by visiting
supports calibration, you can obtain the calibration certificate for your
product at
National Instruments corporate headquarters is located at
11500 North Mopac Expressway, Austin, Texas, 78759-3504.
National Instruments also has offices located around the world to help
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