Genesis gmZAN3T, gmZAN3L Datasheet

Genesis Microchip Publication

PRELIMINARY DATA SHEET

gmZAN3

XGA Analog Interface

LCD Monitor Controller

GENESIS MICROCHIP

CONFIDENTIAL

Publication Number: C0523-DAT-01G

Publication Date: July 2003

Genesis Microchip Inc.

165 Commerce Valley Dr. West • Thornhill • ON • Canada • L3T 7V8 • Tel: (905) 889-5400 • Fax: (905) 889-5422

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www.genesis-microchip.com / info@genesis-microchip.com

.com

The following are trademarks or registered trademarks of Genesis Microchip, Inc.:

GenesisTM, Genesis Display PerfectionTM, ESMTM, RealColorTM, Ultra-Reliable DVITM, Real RecoveryTM, SageTM, JagASMTM,

SureSync

, Adaptive Backlight Control™, FaroudjaTM, DCDiTM, TrueLifeTM, IntelliCombTM

Other brand or product names are trademarks of their respective holders.

Genesis Microchip Inc. reserves the right to change or modify the information contained herein without notice. It is the customer’s responsibility to obtain the most recent revision of the document. Genesis Microchip Inc. makes no warranty for the use of its products and bears no responsibility for any errors or omissions that may appear in this document.

gmZAN3 Preliminary Data Sheet

Table Of Contents

1 Overview ........................................................................................................................................8

1.1 gmZAN3 System Design Examples......................................................................................8

1.2 gmZAN3 Features .................................................................................................................9

2 gmZAN3 Pinout ...........................................................................................................................10

3 gmZAN3 Pin List .........................................................................................................................12

4 Functional Description .................................................................................................................19

4.1 Clock Generation.................................................................................................................19

4.1.1 Using the Internal Oscillator with External Crystal ........................................................19

4.1.2 Using an External Clock Oscillator.................................................................................22

4.1.3 Clock Synthesis...............................................................................................................23

4.2 Hardware Reset ...................................................................................................................24

4.3 Analog to Digital Converter ................................................................................................26

4.3.1 ADC Pin Connection.......................................................................................................26

4.3.2 ADC Characteristics........................................................................................................28

4.3.3 Clock Recovery Circuit...................................................................................................28

4.3.4 Sampling Phase Adjustment............................................................................................29

4.3.5 Integrated Schmitt Trigger for Horizontal and Vertical Sync input................................29

4.3.6 SOG and CSYNC support...............................................................................................30

4.3.7 ADC Capture Window ....................................................................................................31

4.4 Test Pattern Generator (TPG)..............................................................................................32

4.5 Input Format Measurement .................................................................................................33

4.5.1 Horizontal and Vertical Measurement ............................................................................33

4.5.2 Format Change Detection................................................................................................33

4.5.3 Watchdog ........................................................................................................................34

4.5.4 Internal Odd/Even Field Detection (For Interlaced Inputs to ADC Only) ......................34

4.5.5 Input Pixel Measurement ................................................................................................34

4.5.6 Image Phase Measurement..............................................................................................34

4.5.7 Image Boundary Detection..............................................................................................34

4.5.8 Image Auto Balance ........................................................................................................34

4.6 High-Quality Scaling...........................................................................................................35

4.6.1 Variable Zoom Scaling....................................................................................................35

4.6.2 Horizontal & Vertical Shrink ..........................................................................................35

4.7 Gamma LUT........................................................................................................................35

4.8 Display Output Interface .....................................................................................................35

4.8.1 Display Synchronization .................................................................................................35

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4.8.2 Programming the Display Timing...................................................................................36

4.8.3 Panel Power Sequencing (PPWR, PBIAS) .....................................................................37

4.8.4 Output Dithering .............................................................................................................38

4.9 Four Channel LVDS Transmitter (for gmZAN3L Only) ....................................................38

4.10 Flexible TTL Outputs (gmZAN3T Only)............................................................................39

4.11 Energy Spectrum Management (ESM)................................................................................39

4.12 OSD .....................................................................................................................................39

4.12.1 On-Chip OSD SRAM .................................................................................................40

4.12.2 Color Look-up Table (LUT) .......................................................................................41

4.13 General Purpose Inputs and Outputs (GPIO’s) ...................................................................41

4.14 Bootstrap Configuration Pins ..............................................................................................41

4.15 Host Interface ......................................................................................................................41

4.15.1 Host Interface Command Format – for 2 or 6-wire ....................................................42

4.15.2 2-wire Serial Protocol .................................................................................................42

4.15.3 8-bit Parallel Interface ................................................................................................44

4.16 Miscellaneous Functions .....................................................................................................45

4.16.1 Low Power State.........................................................................................................45

4.16.2 Pulse Width Modulation (PWM) Back Light Control................................................45

5 Electrical Specifications ...............................................................................................................46

5.1 Preliminary DC Characteristics...........................................................................................46

5.2 Preliminary AC Characteristics...........................................................................................49

6 Ordering Information ...................................................................................................................52

7 Mechanical Specifications............................................................................................................53

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gmZAN3 Preliminary Data Sheet

List Of Tables

Table 1. Analog Input Port (Common to gmZAN3T and gmZAN3L) .............................................12

Table 2. Clock Pins (Common to gmZAN3T and gmZAN3L).........................................................12

Table 3. System Interface and GPIO Signals (gmZAN3T)...............................................................13

Table 4. System Interface and GPIO Signals (gmZAN3L)...............................................................14

Table 5. Display Output Port for (gmZAN3L)..................................................................................15

Table 6. Display Output Port for (gmZAN3T)..................................................................................16

Table 7. Reserved Pins for gmZAN3L..............................................................................................17

Table 8. Reserve Pins for gmZAN3T................................................................................................17

Table 9. I/O Power and Ground Pins for gmZAN3L ........................................................................17

Table 10. Power and Ground Pins for LVDS Transmitter for gmZAN3L......................................18

Table 11. I/O Power and Ground pins for gmZAN3T ....................................................................18

Table 12. TCLK Specification ........................................................................................................22

Table 13. Temperature and Voltage variations for T

RESETn

..........................................................26

Table 14. Pin Connection for RGB Input with HSYNC/VSYNC...................................................26

Table 15. ADC Characteristics........................................................................................................28

Table 16. Temperature and Voltage Variation for Schmitt Trigger................................................30

Table 17. Supported LVDS 24-bit Panel Data Mappings ...............................................................39

Table 18. Supported LVDS 18-bit Panel Data Mapping.................................................................39

Table 19. Bootstrap Signals.............................................................................................................41

Table 20. Instruction Byte Map.......................................................................................................42

Table 21. Absolute Maximum Ratings............................................................................................46

Table 22. gmZAN3L DC Characteristics........................................................................................47

Table 23. gmZAN3T DC Characteristics........................................................................................48

Table 24. Maximum Speed of Operation ........................................................................................49

Table 25. Display Timing and DCLK Adjustments........................................................................49

Table 26. 2-Wire Host Interface Port Timing .................................................................................49

Table 27. Microcontroller Interface Timing (Muxed Address/Data) for Register Read/Write.......50

Table 28. Microcontroller Interface Timing (Muxed Address/Data) for OSD Memory Read/Write51

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gmZAN3 Preliminary Data Sheet

List Of Figures

Figure 1. gmZAN3 System Design Examples..................................................................................8

Figure 2. gmZAN3T Pin Out Diagram...........................................................................................10

Figure 3. gmZAN3L Pin out Diagram............................................................................................11

Figure 4. gmZAN3 Functional Block Diagram ..............................................................................19

Figure 5. Using the Internal Oscillator with External Crystal ........................................................20

Figure 6. Internal Oscillator Output................................................................................................21

Figure 7. Sources of Parasitic Capacitance.....................................................................................22

Figure 8. Using an External Single-ended Clock Oscillator...........................................................22

Figure 9. Internally Synthesized Clocks .........................................................................................23

Figure 10. gmZAN3 Re-setting External MCU................................................................................25

Figure 11. External MCU Re-setting gmZAN3................................................................................25

Figure 12. Reset Signal Timing (T

RESETn

).......................................................................................25

Figure 13. Example ADC Signal Terminations................................................................................27

Figure 14. gmZAN3 Clock Recovery...............................................................................................29

Figure 15. Schmitt Trigger Timing Diagram....................................................................................30

Figure 16. Supported SOG and CSYNC signals ..............................................................................31

Figure 17. ADC Capture Window ....................................................................................................32

Figure 18. Some of gmZAN3 built-in test patterns ..........................................................................32

Figure 19. Factory Calibration and Test Environment .....................................................................33

Figure 20. ODD/EVEN Field Detection...........................................................................................34

Figure 21. Display Windows and Timing.........................................................................................36

Figure 22. Single Pixel Width Display Data.....................................................................................37

Figure 23. Double Pixel Wide Display Data ....................................................................................37

Figure 24. Panel Power Sequencing .................................................................................................38

Figure 25. OSD Cell Map .................................................................................................................40

Figure 26. 2-Wire Protocol Data Transfer ........................................................................................43

Figure 27. 2-Wire Write Operations (0x1x and 0x2x)......................................................................43

Figure 28. 2-Wire Read Operation (0x9x and 0xAx) .......................................................................44

Figure 29. 8-bit Parallel Interface .....................................................................................................44

Figure 30. Microcontroller Register Write Cycle .............................................................................50

Figure 31. Microcontroller Register Read Cycle ..............................................................................51

Figure 32. Microcontroller OSD CCF Write Cycle..........................................................................52

Figure 33. Microcontroller OSD CCF Read Cycle...........................................................................52

Figure 34. gmZAN3 128-pin PQFP Mechanical Drawing ...............................................................53

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gmZAN3 Preliminary Data Sheet

Revision History

Document Description Date

C0523-DAT-01A

C0523-DAT-01B

C0523-DAT-01C

C0523-DAT-01D

C0523-DAT-01E

C0523-DAT-01F

C0523-DAT-01G

• Initial Release

• Changed the LVDS pin names to allow simple board layout. See Figure 3 and Table 5.

• Fixed typo in Table 19 V

• Updated Table 20 with correct 1.8V voltage min and max

• Updated the minimum and maximum operating conditions in Section 5.2 Preliminary

AC Characteristics.

• Removed Dual- edge clocking from section 4.11

• Updated Table 19 with Theta Jc and Theta Ja values

• Updated Table 20 with measured Power consumption for gmZAN3L

• Added Table 21 with gmZAN3T DC characteristics with measured Power Consumption

• Added information on the integrated Reset Circuit

• Figure 10 gmZAN3 Re-setting external MCU

• Figure 11 External MCU re-setting gmZAN3

• Figure 12 Reset Signal Timing

• Table 13 Temperature & Voltage Variation on the Reset Circuit

• Added Section 4.3.5 on the Schimtt Trigger

• Figure 15 Schmitt Trigger Timing

• Table 16 Temperature & Voltage Variation on the Schimtt Trigger

• Changed Figure 14 drawing with more clarification

• Pin corrections (documentation error):

• gmZAN3L – corrected pins: 40, 43, 52,53, 60, 63 (GPIO[8:13] to GPO[8:13])

• gmZAN3T – corrected pins: 40, 43, 52, 53, 60, 63

• Part Number change: removed hyphen from chip name throughout document

• Updated frequency in TCLK specification table.

• Corrected storage temperature in Preliminary DC Characteristics

• Updated Table 16 Temperature and Voltage variation of the Schmitt trigger

VDD_1.85

>> V

VDD_1.8

Feb. 2003

Mar. 2003

Apr. 2003

May 2003

July 2003

C0523-DAT-01G 7 July 2003

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gmZAN3 Preliminary Data Sheet

1 Overview

The gmZAN3 is a graphics processing IC for Liquid Crystal Display (LCD) monitors at XGA resolution. It provides all key IC functions required for the highest quality LCD monitors. On-chip functions include a high-speed triple-ADC and PLL, a high quality zoom and shrink scaling engine, an on-screen display (OSD) controller and digital color controls.

The gmZAN3 is provided with two versions;

• gmZAN3T with 48-bit TTL output and

• gmZAN3L with industry standard single four channel LVDS transmitter for direct connect to LCD

panels with LVDS interface.

With this level of integration, the gmZAN3 devices simplify and reduce the cost of LCD monitors while maintaining a high-degree of flexibility and quality.

1.1 gmZAN3 System Design Examples

Figure 1 below shows a typical analog interface LCD monitor system based on the gmZAN3. The gmZAN3 reduces system cost, simplifies hardware and firmware design and increased reliability because only a minimal number of components are required in the system.

Analog

RGB

gmZAN3T/L

Direct

Connect to

LVDS IF

for Panels

TTL IF to

Panels

LCD Module

Back-light

Micro

Figure 1. gmZAN3 System Design Examples

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1.2 gmZAN3 Features

gmZAN3 Preliminary Data Sheet

FEATURE OVERVIEW

• Zoom (from VGA) and shrink (from SXGA) scaling

• Integrated 8-bit triple-channel ADC / PLL

• Csync and SOG support

• On-chip versatile OSD engine

• All system clocks synthesized from a single

external crystal

• On-chip reset circuit

• Programmable gamma correction (CLUT)

• PWM back light intensity control

• 5-Volt tolerant inputs – up to 13 GPIO pins

• Low EMI and power saving features

High-Quality Advanced Scaling

• Fully programmable zoom ratios

• Shrink capability from SXGA resolution

• Real Recovery function provides full color

recovery image for refresh rates higher than those supported by the LCD panel

Analog RGB Input Port

• Supports up to SXGA input

• On-chip high-performance PLLs (only a single

reference crystal required)

Auto-Configuration / Auto-Detection

• Automatic input format detection

• Robust phase and image positioning

On-Chip OSD Controller

• On-chip RAM for downloadable menus

• 1 and 2-bit per pixel character cells

• Horizontal and vertical stretch of OSD menus

• Blinking and transparency

• Proportional font support

• 90 degree rotation of fonts for Portrait Display

support

Built in Test Pattern Generator

• Simplifies manufacturing and testing

Highly Integrated Solution to Provide Low System Cost

• Two layer PCB support

• On-chip reset feature to eliminate

external reset component

• Output slew rate control

• Integrated Schmitt trigger for Vsync

and Hsync

OUTPUT INTERFACE

gmZAN3T

• Support for 8 or 6-bit panels (with high-quality dithering)

• Swap red and green channels

• Ability to reverse bit order of each

R, G, B output

• Single or double pixel clock

• Support up to XGA 85Hz

Built in Flexible LVDS Transmitter for gmZAN3L

• Four channel 6/8-bit LVDS transmitter (with high-quality dithering)

• Programmable channel swapping and polarity

• Support up to XGA 85Hz output

PACKAGE

• 128-pin PQFP

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gmZAN3 Preliminary Data Sheet

2 gmZAN3 Pinout

These devices are available in a 128-pin Plastic Quad Flat Pack (PQFP) package. Figure 2 provides the pin locations for all signals.

HDATA0/AD0/HP0

HDATA1/AD1/HP1

HDATA2/AD2/OSC_SEL

HDATA3/AD3

HFS/AD4

GPIO7/AD5

GPIO6/AD6

GPIO5/AD7

RDn

WRn

HCLK/ALE

GPIO4/MEM_REG

GPIO3/IRQn

CRVSS

CVDD_1.8

CRVSS

RVDD_3.3

TCLK

XTAL

AVDD_RPLL_3.3

AVSS_RPLL

VBUFS_RPLL

VDD_RPLL_1.8

VSS_RPLL

VDD_ADC_1.8

GND_ADC

RESETn

RESET_OUT

VCO_LV

AVDD_3.3

AVSS PD0/ER0 PD1/ER1 PD2/ER2 PD3/ER3 PD4/ER4 PD5/ER5 PD6/ER6 PD7/ER7

PD8/EG0 PD9/EG1

AVSS

AVDD_3.3

AVSS

AVDD_3.3 CVDD_1.8

CRVSS

RVDD_3.3

CRVSS PD10/EG2 PD11/EG3 PD12/EG4 PD13/EG5 PD14/EG6 PD15/EG7

PD16/EB0 PD17/EB1 PD18/EB2 PD19/EB3 PD20/EB4

CVDD_1.8

CRVSS

PD21/EB5 PD22/EB6

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

2 3 4 5 6 7 8

gmZAN3T

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

39404142434445464748495051525354555657585960616263

109

108

107

106

105

104

103

102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

AGND_ADC ADC_TEST AVDD_ADC_3.3 AGND_RED REDRED+ AVDD_RED_3.3 AGND_GREEN GREENGREEN+ SOG_MCSS AVDD_GREEN_3.3 AGND_BLUE BLUEBLUE+ AVDD_BLUE_3.3 VSYNC HSYNC STI_TM2 STI_TM1 CRVSS CVDD_1.8 GPIO0/PWM0 GPIO1/PWM1 GPIO2 PBIAS CRVSS RVDD_3.3 PPWR DCLK DVS DHS DEN PD47/OB7 PD46/OB6 PD45/OB5 PD44/OB4 PD43/OB3

CRVSS

PD23/EB7

RVDD_3.3

PD26/OR2

PD27/OR3

PD25/OR1/GPO13

PD24/OR0/GPO12

CRVSS

CVDD_1.8

PD28/OR4

PD31/OR7

PD29/OR5

PD30/OR6

PD32/OG0/GPO10

PD33/OG1/GPO11

PD34/OG2

PD35/OG3

PD36/OG4

PD37/OG5

PD38/OG6

PD39/OG7

PD40/OB0/GPO8

RVDD_3.3

CRVSS

PD42/OB2

PD41/OB1/GPO9

Figure 2. gmZAN3T Pin Out Diagram

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gmZAN3 Preliminary Data Sheet

HDATA0/AD0/HP0

HDATA1/AD1/HP1

HDATA2/AD2/OSC_SEL

HDATA3/AD3

HFS/AD4

GPIO7/AD5

GPIO6/AD6

GPIO5/AD7

RDn

WRn

HCLK/ALE

GPIO4/MEM_REG

GPIO3/IRQn

CRVSS

CVDD_1.8

CRVSS

RVDD_3.3

TCLK

XTAL

AVDD_RPLL_3.3

AVSS_RPLL

VBUFS_RPLL

VDD_RPLL_1.8

VSS_RPLL

VDD_ADC_1.8

GND_ADC

RESETn

RESET_OUT

AVDD_OUT_LV_3.3

VCO_LV

AVSS_OUT_LV

CH3P_LV CH3N_LV CLKP_LV CLKN_LV CH2P_LV CH2N_LV CH1P_LV CH1N_LV CH0P_LV CH0N_LV

AVSS_OUT_LV

AVSS_LV

AVDD_LV_3.3

CVDD_1.8

CRVSS RVDD_3.3

CRVSS

RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

CVDD_1.8

CRVSS

RESERVED RESERVED

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

2 3 4 5 6 7 8

gmZAN3L

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

39404142434445464748495051525354555657585960616263

109

108

107

106

105

104

103

102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

GPO8

GPO12

RVDD_3.3

RESERVED

GPO13

CRVSS

RESERVED

CVDD_1.8

RESERVED

CRVSS

RESERVED

GPO10

GPO11

RESERVED

RVDD_3.3

RESERVED

GPO9

CRVSS

RESERVED

Figure 3. gmZAN3L Pin out Diagram

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gmZAN3 Preliminary Data Sheet

3 gmZAN3 Pin List

I/O Legend: A = Analog, I = Input, O = Output, P = Power, G = Ground, I-PU = Input with pull-up,

I-PD = Input with pull down, IO-PD = Bidirectional with pull down

Table 1.

Analog Input Port (Common to gmZAN3T and gmZAN3L)

Pin Name No. I/O Description

AVDD_RED_3.3 96 AP Analog power (3.3V) for the red channel. Must be bypassed with decoupling capacitor

RED+ 97 AI Positive analog input for Red channel. RED- 98 AI Negative analog input for Red channel. AGND_RED 99 AG Analog ground for the red channel.

AVDD_GREEN_3.3 91 AP Analog power (3.3V) for the green channel. Must be bypassed with decoupling capacitor

SOG_MCSS 92 AI Dedicated Sync-on-Green pin GREEN+ 93 AI Positive analog input for Green channel. GREEN- 94 AI Negative analog input for Green channel. AGND_GREEN 95 AG Analog ground for the green channel.

AVDD_BLUE_3.3 87 AP Analog power (3.3V) for the blue channel. Must be bypassed with decoupling capacitor

BLUE+ 88 AI Positive analog input for Blue channel. BLUE- 89 AI Negative analog input for Blue channel. AGND_BLUE 90 AG Analog ground for the blue channel.

AVDD_ADC_3.3 100 AP Analog power (3.3V) for ADC analog blocks that are shared by all three channels. Includes

ADC_TEST 101 AO Analog test output for ADC. Do not connect. AGND_ADC 102 AG Analog ground for ADC analog blocks that are shared by all three channels. Includes band

GND_ADC 103 AG Digital ground for ADC clocking circuit.

VDD_ADC_1.8 104 P Digital power (1.8V) for ADC encoding logic. Must be bypassed with decoupling capacitor

HSYNC 85 I ADC input horizontal sync input. The input hysteresis can be set to 0.5V or 1.5V

VSYNC 86 I ADC input vertical sync input. The input hysteresis can be set to 0.5V or 1.5V

(0.1µF) to AGND_RED pin on system board (as close as possible to the pin).

Must be directly connected to the system ground plane.

(0.1µF) to AGND_GREEN pin on system board (as close as possible to the pin).

Must be directly connected to the system ground plane.

(0.1µF) to AGND_BLUE pin on system board (as close as possible to the pin).

Must be directly connected to the system ground plane.

band gap reference, master biasing and full-scale adjust. Must be bypassed with decoupling capacitor (0.1µF) to AGND_ADC pin on system board (as close as possible to the pin).

gap reference, master biasing and full-scale adjust. Must be directly connected to system ground plane.

Must be directly connected to the system ground plane.

(0.1µF) to GND_ADC pin on system board (as close as possible to the pin).

[Input, Schmitt trigger, 5V-tolerant]

[Input, Schmitt triggered, 5V-tolerant]

Table 2. Clock Pins (Common to gmZAN3T and gmZAN3L)

Pin Name No I/O Description

TCLK 111 AI Reference clock (TCLK) from the 14.3MHz crystal oscillator (see Figure 5), or from single-

XTAL 110 AO Crystal oscillator output. VBUFS_RPLL 107 AO Reserved. For test purposes only. Do not connect AVSS_RPLL 108 G Analog ground for the reference DDS PLL. Must be directly connected to the system ground

VSS_RPLL 105 G Digital ground for the RCLK and clock generator. Must be directly connected to the system

VDD_RPLL_1.8 106 P Digital power for the RCLK and clock generators. Connect to 1.8V supply. Must be bypassed

AVDD_RPLL_3.3 109 P Analog power for the reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a

C0523-DAT-01G 12 July 2003

ended CMOS/TTL clock oscillator (see Figure 8). This is a 5V-tolerant input. See Table 14.

plane.

ground plane.

with a 0.1µFcapacitor to pin AVSS_RPLL

0.1µFcapacitor to pin VSS_RPLL

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gmZAN3 Preliminary Data Sheet

Table 3. System Interface and GPIO Signals (gmZAN3T)

Pin Name No I/O Description

RESETn 1 IO Active-low hardware reset signal. The reset signal is held low for at least 150ms on the

RESET_OUT 2 O Active-high hardware reset signal. The reset signal is held high for at least 150ms on the

GPIO0/PWM0 80 IO General-purpose input/output signal or PWM0. Open drain option via register setting.

GPIO1/PWM1 79 IO General-purpose input/output signal or PWM1. Open drain option via register setting.

GPIO2 78 IO General-purpose input/output signal. Open drain option via register setting.

GPIO3/IRQn 116 IO General-purpose input/output signal. This is also active-low interrupt input external micro-

GPIO4/MEM_REG 117 IO-PD General-purpose input/output signal. Open drain option via register setting. For 8-bit A/D

GPIO5/AD7 121 IO General-purpose input/output signal or Adddress/data[7] for 8-bit A/D host interface. Open

GPIO6/AD6 122 IO General-purpose input/output signal or Adddress/data[6] for 8-bit A/D host interface.

GPIO7/AD5 123 IO General-purpose input/output signal or Adddress/data[5] for 8-bit A/D host interface.

GPO8/PD40/OB0 60 O General-purpose output signal. GPO or TTL 48-bit panel data/Odd Blue0. GPO9/PD41/OB1 63 O General-purpose output signal. GPO or TTL 48-bit panel data/Odd Blue1. GPO10/PD32/OG0 52 O General-purpose output signal. GPO or TTL 48-bit panel data/Odd Green0. GPO11/PD33/OG1 53 O General-purpose output signal. GPO or TTL 48-bit panel data/Odd Green1. GPO12/PD24/OR0 40 O General-purpose output signal. GPO or TTL 48-bit panel data/Odd Red0. GPO13/PD25/OR1 43 O General-purpose output signal. GPO or TTL 48-bit panel data/Odd Red1. HDATA0/ADO/HP0 HDATA1/AD1/HP1

HDATA2/AD2/OSC_SEL

HDATA3/AD3 125 IO-PD If using 6-wire protocol the HDATA[3] determines the upper A/D3 bits of the host data. For

HFS/AD4 124 IO

HCLK/ALE 118 I

WRn 119 I-PU RDn 120 I-PU

128

IO-PD Host data for 6-wire serial protocol.

127

126 IO-PD If using 6-wire protocol the HDATA[2] determines bit 2 of the host data. For 8-bit A/D host

chip power up. It has an internal 60KΩl pull-up resistor which can be used for re-setting other system devices. See section 4.2 [Bi-directional (open drain), 5V-tolerant]

chip power up. It can be used for re-setting other system devices[Output, open-drain 5Vtolerant]

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

controller. [Bi-directional, Active low open drain, 5V-tolerant]

host interface, this selects between OSD memory (high) and register access (low). [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60K pull- down]

drain option via register setting. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

For 8-bit A/D host interface determines A/D0 and A/D1 bit. Note: See Table 19, Boostrap Signals [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60KΩ pulldown]

interface determines A/D2 bit. Note: See Table 19, Boostrap Signals [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60KΩ pulldown]

8-bit A/D host interface determines address/data bit. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60KΩ pulldown] Host Frame Sync. Frames the packet on the serial channel 6-wire interface. For 8-bit A/D host interface determines A/D4 bit. [Bi-directional, Schmitt trigger (400mV typical hysteresis), slew rate limited, 5V-tolerant]

Clock signal input for the 6-wire interface and 2-wire modes.

For 8-bit A/D host interface it becomes the Address Latch Enable. [Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

For 8-bit A/D host interface write strobe input. Internal 60K pull-up.

For 8-bit A/D host interface read strobe input. Internal 60K pull-up

C0523-DAT-01G 13 July 2003

Genesis Microchip Confidential

http://www.genesis-microchip.com

gmZAN3 Preliminary Data Sheet

Table 4. System Interface and GPIO Signals (gmZAN3L)