Genesis gm2125, gm2115 Datasheet

PRELIMINARY DATA SHEET

gm2115/25

Analog Interface XGA/SXGA OnPanel

LCD Panel Controller

*** Genesis Microchip Confidential ***

C2115-DAT-01B

June 2002

2150 Gold Street, Alviso, P.O. Box 2150, CA USA 95002 Tel: [phone] Fax: [phone]

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2-9-5 Higashigotanda, Shinagawa-ku, Tokyo, 141-0022, Japan, Tel [phone], Fax [phone]

www.genesis-microchip.com / [e-mail]

Genesis Microchip Inc.

*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

•

Revision History

Document Description Date

C2115-DAT-01A Initial release. August 2001

D2115-DAT-01B

• Pins 143 ~ 146: changed xxx_SDDS or xxxx_SDDS to xxx_DDDS or xxxx_DDDS
respectively

• Pins 138 ~ 141: changed xxx_DDDS or xxxx_DDDS to xxx_SDDS or xxxx_SDDS
respectively

Pins 147 ~ 148: changed xxx_DPLL to xxx_RPLL

June 2002

Trademarks: RealColor and Real Recovery are trademarks of Genesis Microchip Inc.

© Copyright 2001, Genesis Microchip Inc. All Rights Reserved.

Genesis Microchip Inc. reserves the right to change or modify the information contained herein without
notice. Please obtain the most recent revision of this document. Genesis Microchip Inc. makes no warranty
for the use of its products and bears no responsibility for any errors or omissions that may appear.

*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Table Of Contents

1. Overview ............................................................................................................................................ 5

1.1 gm2115/25 System Design Example ........................................................................................... 5

1.2 gm2115/25 Features..................................................................................................................... 6

2. gm2115/25 Pinout ..............................................................................................................................7

3. gm2115/25 Pin List ............................................................................................................................ 8

4. Functional Description ..................................................................................................................... 14

4.1 Clock Generation ....................................................................................................................... 14

4.1.1 Using the Internal Oscillator with External Crystal............................................................ 15

4.1.2 Using an External Clock Oscillator ....................................................................................17

4.1.3 Clock Synthesis................................................................................................................... 18

4.2 Hardware Reset.......................................................................................................................... 20

4.3 Analog to Digital Converter (ADC)........................................................................................... 20

4.3.1 ADC Pin Connection .......................................................................................................... 21

4.3.2 ADC Characteristics ........................................................................................................... 21

4.3.3 Clock Recovery Circuit ...................................................................................................... 22

4.3.4 Sampling Phase Adjustment ............................................................................................... 23

4.3.5 ADC Capture Window........................................................................................................ 23

4.4 Test Pattern Generator (TPG) .................................................................................................... 24

4.5 Input Format Measurement (IFM) ............................................................................................. 24

4.5.1 HSYNC / VSYNC Delay.................................................................................................... 24

4.5.2 Horizontal and Vertical Measurement ................................................................................ 25

4.5.3 Format Change Detection ................................................................................................... 26

4.5.4 Watchdog............................................................................................................................ 26

4.5.5 Internal Odd/Even Field Detection ..................................................................................... 26

4.5.6 Input Pixel Measurement .................................................................................................... 27

4.5.7 Image Phase Measurement ................................................................................................. 27

4.5.8 Image Boundary Detection ................................................................................................. 27

4.5.9 Image Auto Balance............................................................................................................ 27

4.6 RealColor Digital Color Controls .............................................................................................. 27

4.6.1 RealColor Flesh tone Adjustment....................................................................................... 28

4.6.2 Color Standardization and sRGB Support .......................................................................... 28

4.7 High-Quality Scaling ................................................................................................................. 28

4.7.1 Variable Zoom Scaling ....................................................................................................... 28

4.7.2 Horizontal and Vertical Shrink ........................................................................................... 29

4.7.3 Moiré Cancellation ............................................................................................................. 29

4.8 Bypass Options ..........................................................................................................................29

4.9 Gamma Look-Up-Table (LUT) ................................................................................................. 29

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

4.10 Display Output Interface.......................................................................................................... 29

4.10.1 Display Synchronization................................................................................................... 30

4.10.2 Programming the Display Timing .................................................................................... 30

4.10.3 Panel Power Sequencing (PPWR, PBIAS)....................................................................... 32

4.10.4 Output Dithering............................................................................................................... 32

4.11 Timing Controller (TCON)...................................................................................................... 33

4.11.1 Programmable Column Driver Interface .......................................................................... 33

4.11.2 Programmable Row Driver Interface................................................................................ 36

4.11.3 Reduced EMI .................................................................................................................... 36

4.12 OSD.......................................................................................................................................... 38

4.12.1 On-Chip OSD SRAM ....................................................................................................... 38

4.12.2 Color Look-up Table (LUT) ............................................................................................. 39

4.12.3 OSD Position .................................................................................................................... 39

4.12.4 OSD Stretch ...................................................................................................................... 39

4.12.5 Blending............................................................................................................................ 39

4.13 On-Chip Microcontroller (OCM)............................................................................................. 40

4.13.1 Standalone Configuration ................................................................................................. 40

4.13.2 Full-Custom Configuration............................................................................................... 41

4.13.3 General Purpose Inputs and Outputs (GPIO).................................................................... 42

4.14 Bootstrap Configuration Pins................................................................................................... 43

4.15 Host Interface........................................................................................................................... 44

4.15.1 Host Interface Command Format...................................................................................... 44

4.15.2 2-wire Serial Protocol ....................................................................................................... 45

4.16 Miscellaneous Functions.......................................................................................................... 47

4.16.1 Power Down Operation .................................................................................................... 47

4.16.2 Pulse Width Modulation (PWM) Back Light Control...................................................... 47

5. Electrical Specifications ................................................................................................................... 48

5.1 Preliminary DC Characteristics ................................................................................................. 48

5.2 Preliminary AC Characteristics ................................................................................................. 49

6. Ordering Information ....................................................................................................................... 51

7. Mechanical Specifications................................................................................................................ 52

June 2002 C2115-DAT-01B

2

*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

List Of Tables

Table 1. Analog Input Port.......................................................................................................8

Table 2. RCLK PLL Pins.........................................................................................................8

Table 3. System Interface and GPIO Signals...........................................................................9

Table 4. Display Output Port .................................................................................................10

Table 5. Parallel ROM Interface Port ....................................................................................11

Table 6. TCON Output Port...................................................................................................11

Table 7. Reserved Pins...........................................................................................................11

Table 8. Power Pins for ADC Sampling Clock DDS ............................................................13

Table 9. Power Pins for Display Clock DDS.........................................................................13

Table 10. I/O Power and Ground Pins .....................................................................................13

Table 11. Core Power and Ground Pins...................................................................................13

Table 12. TCLK Specification.................................................................................................18

Table 13. Pin Connection for RGB Input with HSYNC/VSYNC ...........................................21

Table 14. ADC Characteristics ................................................................................................22

Table 15. gm2115/25 GPIOs and Alternate Functions............................................................43

Table 16. Bootstrap Signals .....................................................................................................43

Table 17. Instruction Byte Map ...............................................................................................45

Table 18. Absolute Maximum Ratings ....................................................................................48

Table 19. DC Characteristics ...................................................................................................49

Table 20. Maximum Speed of Operation.................................................................................50

Table 21. Display Timing and DCLK Adjustments ................................................................50

Table 22. 2-Wire Host Interface Port Timing..........................................................................50

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

List Of Figures

Figure 1. gm2115/25 System Design Example.........................................................................5

Figure 2. gm2115/25 Pin Out Diagram.....................................................................................7

Figure 3. gm2115/25 Functional Block Diagram....................................................................14

Figure 4. Using the Internal Oscillator with External Crystal.................................................15

Figure 5. Internal Oscillator Output ........................................................................................16

Figure 6. Sources of Parasitic Capacitance .............................................................................17

Figure 7. Using an External Single-ended Clock Oscillator ...................................................18

Figure 8. Internally Synthesized Clocks .................................................................................19

Figure 9. On-chip Clock Domains ..........................................................................................20

Figure 10. Example ADC Signal Terminations ....................................................................21

Figure 11. gm2115/25 Clock Recovery ................................................................................22

Figure 12. ADC Capture Window.........................................................................................23

Figure 13. Some of gm2115/25 built-in test patterns............................................................24

Figure 14. HSYNC Delay .....................................................................................................25

Figure 15. Active Data Crosses HSYNC Boundary..............................................................25

Figure 16. ODD/EVEN Field Detection ...............................................................................26

Figure 17. RealColor Digital Color Controls ........................................................................27

Figure 18. Display Windows and Timing .............................................................................31

Figure 19. Single Pixel Width Display Data .........................................................................31

Figure 20. Double Pixel Wide Display Data.........................................................................32

Figure 21. Panel Power Sequencing......................................................................................32

Figure 22. Column Driver Interface Timing .........................................................................35

Figure 23. Row Driver Interface Timing...............................................................................37

Figure 24. OSD Cell Map......................................................................................................38

Figure 25. OCM Full-Custom and Standalone Configurations.............................................40

Figure 26. Programming OCM in Standalone Configuration ...............................................41

Figure 27. Programming the OCM in Full-Custom Configuration.......................................42

Figure 28. Factory Calibration and Test Environment..........................................................44

Figure 29. 2-Wire Protocol Data Transfer.............................................................................45

Figure 30. 2-Wire Write Operations (0x1x & 0x2x).............................................................46

Figure 31. 2-Wire Read Operation (0xAx) ...........................................................................46

Figure 32. gm2115/25 208-pin PQFP Mechanical Drawing................................................52

June 2002 C2115-DAT-01B

4

*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

1. OVERVIEW

The gm2115/25 is a graphics processing IC for Liquid Crystal Display (LCD) monitors at
XGA/SXGA resolution. The gm2115/25 are pin compatible and firmware compatible to
gm5115/25 and gm3115/25. It provides all key IC functions required for image capture,
processing and timing control for direct interface to the row and column drivers of the LCD
panel. On-chip functions include a high-speed triple-ADC and PLL, a high quality zoom and
shrink scaling engine, an on-screen display (OSD) controller, an on-chip microcontroller
(OCM), and a programmable panel timing controller (TCON). With all these functions
integrated onto a single device, the gm2115/25 eliminates the need for a separate LCD
monitor controller printed circuit board (PCB) from the system along with the associated
connectors and cables. Therefore, the gm2115/25 simplifies the design and reduces the cost
of LCD monitors while maintaining a high-degree of flexibility and quality.

11..11 ggmm22111155//2255 SSyysstteemm DDeessiiggnn EExxaammppllee

Figure 1 below shows a typical dual interface LCD monitor system based on the gm2115/25.
Designs based on the gm2115/25 have reduced system cost, simplified hardware and
firmware design and increased reliability because only a minimal number of components are
required in the system.

Analog

RGB

gm2115/25

Row

Driver

ICs

Column

Driver

ICs

LCD

Panel

Back-light

NVRAM

ROM

(optional)

Figure 1. gm2115/25 System Design Example

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

11..22 ggmm22111155//2255 FFeeaattuurreess

FEATURES

• Zoom (from VGA) and shrink (from UXGA) scaling

• Integrated 8-bit triple-channel ADC / PLL

• On-chip programmable OnPanel timing controller

• Embedded microcontroller with parallel ROM interface

• On-chip versatile OSD engine

• All system clocks synthesized from a single external crystal

• Programmable gamma correction (CLUT)

• RealColor™ controls provide sRGB compliance

• PWM back light intensity control

• 5 Volt tolerant inputs

• Low EMI and power saving features

• High-Quality Advanced Scaling

• Fully programmable zoom ratios

• High-quality shrink capability from UXGA resolution

• Real Recovery™ function provides full color recovery

image for refresh rates higher than those supported by
the LCD panel

• Moire cancellation

• Analog RGB Input Port

• Supports up to 162.5MHz (SXGA 75Hz / UXGA 60Hz)

• On-chip high-performance PLLs

(only a single reference crystal required)

• Auto-Configuration / Auto-Detection

• Input format detection

• Phase and image positioning

• RealColor Technology

• Digital brightness and contrast controls

• TV color controls including hue and saturation controls

• Flesh-tone adjustment

• Full color matrix allows end-users to experience the

same colors as viewed on CRTs and other displays
(e.g. sRGB compliance)

• On-chip OSD Controller

• On-chip RAM for downloadable menus

• 1, 2 and 4-bit per pixel character cells

• Horizontal and vertical stretch of OSD menus

• Blinking, transparency and blending

• On-chip Microcontroller

• Requires no external micro-controller

• External parallel ROM interface allows firmware customization

with little additional cost

• 23 general-purpose inputs/outputs (GPIOs) available for
managing system devices (keypad, back-light, NVRAM, etc)

• Industry-standard firmware embedded on-chip, requires no
external ROM (configuration settings stored in NVRAM)

• Built-in OnPanel Timing Controller

• Eliminates the need for an external panel timing controller

(TCON) device, thereby reducing system cost

• Direct connect to commercial row/column driver ICs (supports
dual-bus / dual-port and dual-bus / single-port)

• Low EMI and power saving features include frame, line and in-line
inversion, blanking, data staggering and slew rate control.

• Programmable Output Format

• Single / double wide up to XGA/SXGA 75Hz output

• Pin swap, odd / even swap and red / blue group swap of

RGB outputs for flexibility in board layout

• Support for 8 or 6-bit panels (with high-quality dithering)

• Highly Integrated System-on-a-Chip

Reduces Component Count for Highly Cost

Effective Solution

• Standalone operation requires no external

ROM and no firmware development for Fast

Time to Market

• Pin and register compatible OnPanel Family:

- gm5115/gm5125 Dual-Interface XGA/SXGA

- gm3115/gm3125 Digital-Interface XGA/SXGA

- gm2115/gm2125 Analog-Interface XGA/SXGA

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

2. GM2115/25 PINOUT

The gm2115/25 is available in a 208-pin Plastic Quad Flat Pack (PQFP) package. Figure 2
provides the pin locations for all signals.

GPIO18

GPIO19

GPIO20

GPIO16/HFSn

GPIO22/HCLK

CVDD_2.5

CVSS

CLKOUT

N/C

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

AVDD_RED

RED+

RED-

AGND_RED

AVDD_GREEN

GREEN+

GREEN-

AGND_GREEN

AVDD_BLUE

BLUE+

BLUE-

AGND_BLUE

AVDD_ADC

ADC_TEST

AGND_ADC

RVDD
RVSS

RVDD
RVSS

CVSS

RVDD
RVSS

1

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

5354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899

gm2115/25

167

166

165

164

163

162

161

100

160

101

159

102

158

103

GPIO17

GPIO21/IRQn

RESETn
GPIO14/DDC_SCL
GPIO15/DDC_SDA

ROM_ADDR15
ROM_ADDR14
ROM_ADDR13
ROM_ADDR12
ROM_ADDR11
ROM_ADDR10

ROM_ADDR9
ROM_ADDR8
ROM_ADDR7
ROM_ADDR6
ROM_ADDR5
ROM_ADDR4

ROM_ADDR3
ROM_ADDR2
ROM_ADDR1
ROM_ADDR0

CVDD_2.5

ROM_DATA7
ROM_DATA6
ROM_DATA5
ROM_DATA4
ROM_DATA3
ROM_DATA2
ROM_DATA1
ROM_DATA0

ROM_Oen

GPIO8/IRQINn

GPIO0/PWM0
GPIO1/PWM1
GPIO2/PWM2

GPIO3/TIMER1
GPIO4/UART_D1
GPIO5/UART_D0

GPIO6/TCON_SHC

GPIO7/TCON_TDIV

GPIO9/TCON_ROE2

GPIO10/TCON_ROE3

GPIO11/ROM_WEn
GPIO12/NVRAM_SDA
GPIO13/NVRAM_SCL

SGND_ADC

157

104

156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105

GND1_ADC
VDD1_ADC_2.5
GND2_ADC
VDD2_ADC_2.5
TCLK
XTAL
AVDD_RPLL
AVSS_RPLL
VDD_RPLL
VSS_RPLL
AVDD_DDDS
AVSS_DDDS
VDD_DDDS
VSS_DDDS
N/C
AVDD_SDDS
AVSS_SDDS
VDD_SDDS
VSS_SDDS
HSYNC
VSYNC
CVSS
CVDD_2.5
CVSS
Reserved
Reserved
RVSS
RVDD
TCON_ROE
TCON_RCLK
TCON_RSP3
TCON_RSP2
TCON_EINV
TCON_EPOL
TCON_ESP
TCON_OINV
TCON_OPOL
TCON_OSP
DCLK/TCON_OCLK
DVS/TCON_FSYNC
DHS/TCON_LP
DEN/TCON_ECLK
PBIAS
PPWR
RVSS
RVDD
PD47/OB7
PD46/OB6
PD45/OB5
PD44/OB4
PD43/OB3
PD42/OB2

RVSS

RVDD

PD0/ER0

PD1/ER1

PD2/ER2

PD3/ER3

PD4/ER4

PD5/ER5

PD6/ER6

PD7/ER7

PD8/EG0

RVSS

RVDD

PD9/EG1

PD10/EG2

PD11/EG3

PD16/EB0

PD17/EB1

PD18/EB2

PD19/EB3

PD12/EG4

PD13/EG5

PD14/EG6

PD15/EG7

PD20/EB4

PD21/EB5

PD22/EB6

PD23/EB7

RVSS

RVDD

CVSS

PD24/OR0

CVDD_2.5

PD25/OR1

PD26/OR2

PD27/OR3

PD28/OR4

PD29/OR5

PD30/OR6

PD31/OR7

PD32/OG0

PD33/OG1

PD34/OG2

PD35/OG3

RVSS

RVDD

PD36/OG4

PD37/OG5

PD38/OG6

PD39/OG7

PD40/OB0

PD41/OB1

Figure 2. gm2115/25 Pin Out Diagram

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

3. GM2115/25 PIN LIST

I/O Legend: A = Analog, I = Input, O = Output, P = Power, G= Ground

Table 1. Analog Input Port

Pin Name No. I/O Description

AVDD_RED 172 AP Analog power (3.3V) for the red channel. Must be bypassed with decoupling capacitor to

RED+ 171 AI Positive analog input for Red channel.
RED- 170 AI Negative analog input for Red channel.
AGND_RED 169 AG Analog ground for the red channel.

AVDD_GREEN 168 AP Analog power (3.3V) for the green channel. Must be bypassed with decoupling capacitor to

GREEN+ 167 AI Positive analog input for Green channel.
GREEN- 166 AI Negative analog input for Green channel.
AGND_GREEN 165 AG Analog ground for the green channel.

AVDD_BLUE 164 AP Analog power (3.3V) for the blue channel. Must be bypassed with decoupling capacitor to

BLUE+ 163 AI Positive analog input for Blue channel.
BLUE- 162 AI Negative analog input for Blue channel.
AGND_BLUE 161 AG Analog ground for the blue channel.

AVDD_ADC 160 AP Analog power (3.3V) for ADC analog blocks that are shared by all three channels. Includes

ADC_TEST 159 AO Analog test output for ADC Do not connect.
AGND_ADC 158 AG Analog ground for ADC analog blocks that are shared by all three channels. Includes band

SGND_ADC 157 AG Dedicated pad for substrate guard ring that protects the ADC reference system.

GND1_ADC 156 G Digital GND for ADC clocking circuit.

VDD1_ADC_2.5 155 P Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to

GND2_ADC 154 G Digital GND for ADC clocking circuit.

VDD2_ADC_2.5 153 P Digital power (2.5V) for ADC encoding logic. Must be bypassed with decoupling capacitor to

HSYNC 137 I ADC input horizontal sync input.

VSYNC 136 I ADC input vertical sync input.

AGND_RED pin on system board (as close as possible to the pin).

Must be directly connected to the analog system ground plane.

AGND_GREEN pin on system board (as close as possible to the pin).

Must be directly connected to the analog system ground plane.

AGND_BLUE pin on system board (as close as possible to the pin).

Must be directly connected to the analog system ground plane.

band gap reference, master biasing and full-scale adjust. Must be bypassed with
decoupling capacitor to AGND_ADC pin on system board (as close as possible to the pin).

gap reference, master biasing and full-scale adjust.
Must be directly connected to analog system ground plane.

Must be directly connected to the analog system ground plane.

Must be directly connected to the digital system ground plane

GND1_ADC pin on system board (as close as possible to the pin).

Must be directly connected to the digital system ground plane.

GND2_ADC pin on system board (as close as possible to the pin).

[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

Table 2. RCLK PLL Pins

Pin Name No I/O Description

AVDD_RPLL 150 AP Analog power for the Reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a

AVSS_RPLL 149 AG Analog ground for the Reference DDS PLL.

TCLK 152 AI Reference clock (TCLK) from the 14.3MHz crystal oscillator (see Figure 4), or from single-

XTAL 151 AO Crystal oscillator output.
VDD_RPLL 148 P Digital power for RCLK PLL. Connect to 3.3V supply.
VSS_RPLL 147 G Digital ground for RCLK PLL.

June 2002 C2115-DAT-01B

0.1uF capacitor to pin AVSS_RPLL (as close to the pin as possible).

Must be directly connected to the analog system ground plane.

ended CMOS/TTL clock oscillator (see Figure 7). This is a 5V-tolerant input. See Table 13.

8

*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Table 3. System Interface and GPIO Signals

Pin Name No I/O Description

RESETn 5 I

GPIO0/PWM0 40 IO General-purpose input/output signal or PWM0. Open drain option via register setting.

GPIO1/PWM1 41 IO General-purpose input/output signal or PWM1. Open drain option via register setting.

GPIO2/PWM2 42 IO General-purpose input/output signal or PWM2. Open drain option via register setting.

GPIO3/TIMER1 43 IO General-purpose input/output signal. Open drain option via register setting. This pin is also

GPIO4/UART_DI 44 IO General-purpose input/output signal. Open drain option via register setting. This pin is also

GPIO5/UART_DO 45 IO General-purpose input/output signal. Open drain option via register setting. This pin is also

GPIO6/TCON_SHC 46 IO General-purpose input/output signal.

GPIO7/TCON_TDIV 47 IO General-purpose input/output signal.

GPIO8/IRQINn 39 IO General-purpose input/output signal. This is also active-low interrupt input to OCM and is

GPIO9/TCON_ROE2 48 IO General-purpose input/output signal. Open drain option via register setting. This pin can

GPIO10/TCON_ROE3 49 IO General-purpose input/output signal. Open drain option via register setting. This pin can

GPIO11/ROM_WEn 50 IO General-purpose input/output signal, or ROM write enable if a programmable FLASH

GPIO12/NVRAM_SDA
GPIO13/NVRAM_SCL

GPIO14/DDC_SCL
GPIO15/DDC_SDA

GPIO16/HFSn 205 IO General-purpose input/output signal when host port is disabled, or data signal for 2-wire

GPIO17
GPIO18
GPIO19
GPIO20
GPIO21/IRQn 4 IO General-purpose input/output signal when host port is disabled, or active-low and open-

GPIO22/HCLK 204 IO General-purpose input/output signal when host port is disabled, or clock for 2-wire serial

51
52

6 7 IO General-purpose input/output signals, or 2-wire master serial interface to NVRAM in

1
208
207
206

Active-low hardware reset signal. The reset signal must be held low for at least 1µS.
[Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

connected to Timer 1 clock input of the OCM.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

connected to the OCM UART data input signal by programming an OCM register.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

connected to the OCM UART data output signal by programming an OCM register.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

directly wired to OCM int_0n.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

also function as TCON signal ROE2.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

also function as TCON signal ROE3.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

device is used. Open drain option via register setting.
[Bi-directional Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

IO

General-purpose input/output signals, or 2-wire master serial interface to NVRAM in
standalone mode. Open drain option via register setting.

IO

[Bi-directional Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

standalone mode. Open drain option via register setting.
[Bi-directional Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

serial host interface.
[Bi-directional, Schmitt trigger (400mV typical hysteresis), slew rate limited, 5V tolerant]

IO

General-purpose input/output signals.

IO

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]
IO
IO

drain interrupt output pin.

[Bi-directional, 5V-tolerant]

host interface.

[Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant]

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Table 4. Display Output Port

Pin Name No I/O Description

DCLK/TCON_OCLK 118 O Panel output clock or TCON Odd Column Driver Bus Clock.

DVS/TCON_FSYNC 117 O Panel Vertical Sync or TCON Frame Synchronization.

DHS/TCON_LP 116 O Panel Horizontal Sync or TCON Load Pulse.

DEN/TCON_ECLK 115 O Panel Display Enable, which frames the output background window, or TCON Even Column

PBIAS 114 O Panel Bias Control (back light enable)

PPWR 113 O Panel Power Control

PD47
PD46
PD45
PD44
PD43
PD42
PD41
PD40
PD39
PD38
PD37
PD36
PD35
PD34
PD33
PD32
PD31
PD30
PD29
PD28
PD27
PD26
PD25
PD24
PD23
PD22
PD21
PD20
PD19
PD18
PD17
PD16
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0

110
109
108
107
106
105
104
103
102
101
100

99
96
95
94
93
92
91
90
87
86
85
84
83
80
79
78
77
76
75
74
73
72
71
70
69
66
65
64
63
62
61
60
59
58
57
56
55

[Tri-state output, Programmable Drive]

[Tri-state output, Programmable Drive]

[Tri-state output, Programmable Drive]

Driver Bus Clock.
[Tri-state output, Programmable Drive]

[Tri-state output, Programmable Drive]

[Tri-state output, Programmable Drive]

O

Panel or TCON output data.

O

[Tri-state output, Programmable Drive]
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Table 5. Parallel ROM Interface Port

Pin Name No I/O Description

ROM_ADDR15
ROM_ADDR14
ROM_ADDR13
ROM_ADDR12
ROM_ADDR11
ROM_ADDR10
ROM_ADDR9
ROM_ADDR8
ROM_ADDR7
ROM_ADDR6
ROM_ADDR5
ROM_ADDR4
ROM_ADDR3
ROM_ADDR2
ROM_ADDR1
ROM_ADDR0
ROM_DATA7
ROM_DATA6
ROM_DATA5
ROM_DATA4
ROM_DATA3
ROM_DATA2
ROM_DATA1
ROM_DATA0
ROM_Oen 36 O External PROM data Output Enable

8

9
10
11
12
13
14
15
16
17
18
19
22
23
24
25
28
29
30
31
32
33
34
35

IO

ROM address output. These pins also serve as 5V-tolerant bootstrap inputs on power up.
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO

I

5V-tolerant external PROM data input

I
I
I
I
I
I
I

Table 6. TCON Output Port

Pin Name No I/O Description

TCON_OSP 119 O Odd Starting Pulse
TCON_OPOL 120 O Odd Polarity
TCON_OINV 121 O Odd Data Transmission Inversion
TCON_ESP 122 O Even Starting Pulse
TCON_EPOL 123 O Even Polarity
TCON_EINV 124 O Even Data Transmission Inversion
TCON_RSP2 125 O Row Starting Pulse for 2-Voltage Row Driver
TCON_RSP3 126 O Row Starting Pulse for 3-Voltage Row Driver
TCON_RCLK 127 O Row Shift Clock
TCON_ROE 128 O Row Output Enable

Table 7. Reserved Pins

Pin Name No I/O Description

Reserved 131 I Tie to GND.
Reserved 132 I Tie to GND.
N/C 142 O No connect.
Reserved 173 N/C No connect.
Reserved 174 N/C No connect.
Reserved 175 N/C No connect.
Reserved 176 N/C No connect.
Reserved 177 N/C No connect.
Reserved 178 N/C No connect.
Reserved 179 N/C No connect.
Reserved 180 N/C No connect.
Reserved 181 N/C No connect.
Reserved 182 N/C No connect.
Reserved 183 N/C No connect.
Reserved 184 N/C No connect.
Reserved 185 N/C No connect.
Reserved 186 N/C No connect.
Reserved 187 N/C No connect.

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Reserved 188 N/C No connect.
Reserved 189 N/C No connect.
Reserved 190 N/C No connect.
Reserved 191 N/C No connect.
Reserved 192 N/C No connect.
Reserved 193 N/C No connect.
Reserved 194 N/C No connect.
Reserved 195 N/C No connect.
Reserved 196 N/C No connect.
Reserved 197 N/C No connect.
Reserved 198 N/C No connect.
Reserved 199 N/C No connect.
N/C 200 O No connect.
CLKOUT 201 AO For test purposes only. Do not connect.

Note: For PCB compatibility with gm5115/25 and gm3115/25 input pins 173-199 should be
connected as described in the gm5115 data sheet C5115-DAT-01.

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

Note that VDD pins having "_2.5" in their names should be connected to 2.5V power supplies. All

other VDD pins should be connected to 3.3V power supplies.

Table 8. Power Pins for ADC Sampling Clock DDS

Pin Name No I/O Description

AVDD_DDDS 146 AP Analog power for the Destination DDS. Connect to 3.3V supply.

AVSS_DDDS 145 AG Analog ground for the Destination DDS.

VDD_DDDS 144 P Digital power for the Destination DDS. Connect to 3.3V supply.
VSS_DDDS 143 G Digital ground for the Destination DDS.

Must be bypassed with a 0.1uF capacitor to AVSS_DDDS pin
(as close to the pin as possible).

Must be directly connected to the analog system ground.

Table 9. Power Pins for Display Clock DDS

Pin Name No I/O Description

AVDD_SDDS 141 AP Analog power for Source DDS. Connect to 3.3V supply.

AVSS_SDDS 140 AG Analog ground for Source DDS.

VDD_SDDS 139 P Digital power for the Source DDS. Connect to 3.3V supply.
VSS_SDDS 138 G Digital ground for the Source DDS.

Must be bypassed with a 0.1uF capacitor to AVSS_SDDS pin
(as close to the pin as possible).

Must be directly connected to the analog system ground plane.

Table 10. I/O Power and Ground Pins

Pin Name No I/O Description

RVDD 2

111
129

RVSS 3

112
130

20
37
53
67
81
97

21
38
54
68
82
98

P

Connect to 3.3V supply.

P

Must be bypassed with a 0.1uF capacitor to RVSS (as close to the pin as possible).
P
P
P
P
P
P
P

G

Connect to digital ground.

G
G
G
G
G
G
G
G

Table 11. Core Power and Ground Pins

Pin Name No I/O Description

CVDD_2.5 26

134
203

CVSS 27

133
135
202

Note, “AP” indicates a power supply that is analog in nature and does not have large switching

currents. These should be isolated from other digital supplies that do have large switching currents.

88

89

P

Connect to 2.5V supply.
P

Must be bypassed with a 0.1uF capacitor to CVSS (as close to the pin as possible).
P
P

G

Connect to digital ground.

G
G
G
G

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

4. FUNCTIONAL DESCRIPTION

A functional block diagram is illustrated below. Each of the functional units shown is
described in the following sections.

Analog RGB

Input

NVRAM

Serial I/F

Serial Host I/F

Parallel
ROM IF

Crystal

Reference

Host

Interface

8051-style

Micro-

controller

MCU

RAM

External
ROM I/F

Internal

ROM

Triple ADC

and PLL

Test Pattern

Generator

Image
Capture /
Measure-

ment

Brightness /

Contrast /
Hue / Sat /

RealColor /

Moire

Zoom /

Shrink /

Filter

Controller

OSD

OSD

RAMs

Gamma
Control

Clock

Generation

Panel

Timing

Controller

Output

Data
Path

Timing
Control
Signals

Panel Data

Figure 3. gm2115/25 Functional Block Diagram

44..11 CClloocckk GGeenneerraattiioonn

The gm2115/25 features two clock inputs. All additional clocks are internal clocks derived
from one or both of these:

1. Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal
oscillator and corresponding logic. A 14.3 MHz TV crystal is recommended. Other
crystal frequencies may be used, but require custom programming. This is illustrated in
Figure 4 below. Alternatively, a single-ended TTL/CMOS clock oscillator can be driven
into the TCLK pin (leave XTAL as N/C in this case). This is illustrated in Figure 7
below. This option is selected by connecting a 10KΩ pull-up to ROM_ADDR13 (refer to
Table 16). See also Table 13.

June 2002 C2115-DAT-01B

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*** Genesis Microchip Confidential *** gm2115/25 Preliminary Data Sheet

2. Host Interface Transfer Clock (HCLK)

The gm2115 TCLK oscillator circuitry is a custom designed circuit to support the use of an
external oscillator or a crystal resonator to generate a reference frequency source for the
gm2115 device.

4.1.1 Using the Internal Oscillator with External Crystal

The first option for providing a clock reference is to use the internal oscillator with an
external crystal. The oscillator circuit is designed to provide a very low jitter and very low
harmonic clock to the internal circuitry of the gm2115. An Automatic Gain Control (AGC) is
used to insure startup and operation over a wide range of conditions. The oscillator circuit
also minimizes the overdrive of the crystal, which reduces the aging of the crystal.

When the gm2115/25 is in reset, the state of the ROM_ADDR13 pin (pin number 10) is
sampled. If the pin is left unconnected (internal pull-down) then internal oscillator is enabled.
In this mode a crystal resonator is connected between TCLK (pin 152) and the XTAL (pin

151) with the appropriately sized loading capacitors CL1 and CL2. The size of CL1 and CL2 are

determined from the crystal manufacturer’s specification and by compensating for the
parasitic capacitance of the gm2115/25 device and the printed circuit board traces. The
loading capacitors are terminated to the analog VDD power supply. This connection
increases the power supply rejection ratio when compared to terminating the loading
capacitors to ground.

Vdda

CL1

152

TCLK

gm2115/25

Vdd

Vdda

CL2

151

XTAL

100 K

180 uA

OSC_OUT

TCLK Distribution

N/C

ROM_ADDR13

10

Reset State Logic

Internal Pull Down

Resistor

~ 60K

Internal Oscillator Enable

Figure 4. Using the Internal Oscillator with External Crystal

June 2002 C2115-DAT-01B

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