Gemalto M2M ALAS66A-W manual revised

Cinterion® ALAS66A

Hardware Interface Description
Version: 01.000b

DocId: ALAS66A_HID_v01.000b

 GEMALTO.COM/M2M

Cinterion® ALAS66A Hardware Interface Description

2

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Document Name:
Version:

Date:
DocId:
Status

Cinterion

®

ALAS66A Hardware Interface Description

01.000b
2019-02-06
ALAS66A_HID_v01.000b
Confidential / Preliminary

GENERAL NOTE

THE USE OF THE PRODUCT INCLUDING THE SOFTWARE AND DOCUMENTATION (THE "PROD­UCT") IS SUBJECT TO THE RELEASE NOTE PROVIDED TOGETHER WITH PRODUCT. IN ANY
EVENT THE PROVISIONS OF THE RELEASE NOTE SHALL PREVAIL. THIS DOCUMENT CONTAINS
INFORMATION ON GEMALTO M2M PRODUCTS. THE SPECIFICATIONS IN THIS DOCUMENT ARE
SUBJECT TO CHANGE AT GEMALTO M2M'S DISCRETION. GEMALTO M2M GMBH GRANTS A NON­EXCLUSIVE RIGHT TO USE THE PRODUCT. THE RECIPIENT SHALL NOT TRANSFER, COPY,
MODIFY, TRANSLATE, REVERSE ENGINEER, CREATE DERIVATIVE WORKS; DISASSEMBLE OR
DECOMPILE THE PRODUCT OR OTHERWISE USE THE PRODUCT EXCEPT AS SPECIFICALLY
AUTHORIZED. THE PRODUCT AND THIS DOCUMENT ARE PROVIDED ON AN "AS IS" BASIS ONLY
AND MAY CONTAIN DEFICIENCIES OR INADEQUACIES. TO THE MAXIMUM EXTENT PERMITTED
BY APPLICABLE LAW, GEMALTO M2M GMBH DISCLAIMS ALL WARRANTIES AND LIABILITIES.
THE RECIPIENT UNDERTAKES FOR AN UNLIMITED PERIOD OF TIME TO OBSERVE SECRECY
REGARDING ANY INFORMATION AND DATA PROVIDED TO HIM IN THE CONTEXT OF THE DELIV­ERY OF THE PRODUCT. THIS GENERAL NOTE SHALL BE GOVERNED AND CONSTRUED
ACCORDING TO GERMAN LAW.

Copyright

Transmittal, reproduction, dissemination and/or editing of this document as well as utilization of its con­tents and communication thereof to others without ex press autho rization are prohib ited. Offenders will be
held liable for payment of damages. All rights created by patent grant or registration of a utility model or
design patent are reserved.

Copyright © 2019, Gemalto M2M GmbH, a Gemalto Company

Trademark Notice

Gemalto, the Gemalto logo, are trademarks and service marks of Gemalto and are registered in certain
countries. Microsoft and Win dows are e ither regis tered trademarks or trademarks of Microsoft Corpora­tion in the United States and/or other countries. All other register ed trademarks or trademarks mention ed
in this document are property of their respective owners.

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Contents

1 Introduction.................................................................................................................8

1.1 Product Variants ................................................................................................8

1.2 Key Features at a Glance..................................................................................9

1.2.1 Supported Frequency Bands.............................................................. 13

1.2.2 Supported CA Configurations............................................................. 14

1.3 System Overview.............................................................................................18

1.4 Circuit Concept ................................................................................................19

2 Interface Characteristics ..........................................................................................20

2.1 Application Interface ........................................................................................20

2.1.1 Pad Assignment..................................................................................20

2.1.2 Signal Properties.................................................................................24

2.1.2.1 Absolute Maximum Ratings ................................................31

2.1.3 USB Interface......................................................................................32

2.1.4 Serial Interface ASC0 .........................................................................33

2.1.5 Serial Interface ASC1 .........................................................................34

2.1.6 I

2.1.7 UICC/SIM/USIM Interface...................................................................36

2.1.8 Digital Audio Interface.........................................................................39

2.1.9 Analog-to-Digital Converter (ADC)......................................................40

2.1.10 RTC Backup........................................................................................40

2.1.11 GPIO Interface....................................................................................40

2.1.12 Control Signals....................................................................................42

2.1.13 JTAG Interface....................................................................................42

2.1.14 eMMC Interface ..................................................................................43

2.2 GSM/UMTS/LTE Antenna Interface.................................................................44

2.2.1 Antenna Interface Specifications ........................................................45

2.2.2 Antenna Installation ............................................................................50

2.2.3 RF Line Routing Design......................................................................51

2.2.4 RF Antenna Diagnostic.......................................................................54

2.3 GNSS Antenna Interface .................................................................................57

2.3.1 GNSS Antenna Diagnostic..................................................................58

2.4 Sample Application..................... ........... .......... ........... ........... ..........................59

2.4.1 Prevent Back Powering.......................................................................60

2.4.2 Sample Level Conversion Circuit........................................................61

2.4.3 Sample Circuit for Antenna Detection.................................................62

2

C Interface........................................................................................35

2.1.7.1 Enhanced ESD Protection for SIM Interfaces.....................38

2.1.8.1 Inter IC Sound Interface (I

2

S)..............................................39

2.1.11.1 External Antenna Switch Interface......................................41

2.1.12.1 PWR_IND Signal.................................................................42

2.1.12.2 Heartbeat Signal .................................................................42

2.1.14.1 eMMC Power Supply ..........................................................43

2.2.3.1 Line Arrangement Instructions ............................................51

2.2.3.2 Routing Examples...............................................................53

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3 GNSS Interface..........................................................................................................65

3.1 GNSS Interface Characteristics.......................................................................66

4 Operating Characteristics........................................................................................67

4.1 Operating Modes .............................................................................................67

4.2 Power Up/Power Down Scenarios...................................................................68

4.2.1 Turn on ALAS66A...............................................................................68

4.2.2 Signal States after First Startup..........................................................69

4.2.3 Turn off or Restart ALAS66A..............................................................72

4.2.3.1 Switch off ALAS66A Using Shutdown Command................72

4.2.3.2 Restart ALAS66A Using Restart Command........................ 73

4.2.3.3 Turn off ALAS66A Using IGT Line.......................................74

4.2.3.4 Turn off or Restart ALAS66A in Case of Emergency...........75

4.2.3.5 Overall Shutdown Sequence...............................................76

4.2.4 Automatic Shutdown...........................................................................77

4.2.4.1 Thermal Shutdown..............................................................78

4.2.4.2 Deferred Shutdown at Extreme Temperature Conditions.... 79

4.2.4.3 Undervoltage Shutdown......................................................80

4.2.4.4 Overvoltage Shutdown........................................................80

4.3 Power Saving...................................................................................................81

4.3.1 Power Saving while Attached to GSM Networks................................81

4.3.2 Power Saving while Attached to WCDMA Networks ..........................82

4.3.3 Power Saving while Attached to LTE Networks..................................83

4.4 Power Supply...................................................................................................84

4.4.1 Power Supply Ratings.........................................................................85

4.4.2 Minimizing Power Losses ...................................................................92

4.4.3 Monitoring Power Supply by Configuration Setting.............................92

4.5 Operating Temperatures..................................................................................93

4.6 Electrostatic Discharge....................................................................................94

4.7 Reliability Characteristics.................................................................................94

5 Mechanical Dimensions and Mounting...................................................................95

5.1 Mechanical Dimensions of ALAS66A ..............................................................95

5.2 Mounting ALAS66A onto the Application Platform...........................................97

5.2.1 SMT PCB Assembly ...........................................................................97

5.2.1.1 Land Pattern and Stencil.....................................................97

5.2.1.2 Board Level Characterization..............................................98

5.2.2 Moisture Sensitivity Level ...................................................................99

5.2.3 Soldering Conditions and Temperature.............................................. 99

5.2.3.1 Reflow Profile......................................................................99

5.2.3.2 Maximum Temperature and Duration................................ 100

5.2.4 Durability and Mechanical Handling..................................................101

5.2.4.1 Storage Conditions............................................................101

5.2.4.2 Processing Life..................................................................101

5.2.4.3 Baking...............................................................................102

5.2.4.4 Electrostatic Discharge .....................................................102

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5.3 Packaging......................................................................................................103

5.3.1 Trays.................................................................................................103

5.3.2 Shipping Materials ............................................................................103

5.3.2.1 Moisture Barrier Bag.........................................................103

5.3.2.2 Transportation Boxes........................................................105

6 Regulatory and Type Approval Information ......................................................... 106

6.1 Directives and Standards...............................................................................106

6.2 SAR requirements specific to portable mobiles............................................. 109

6.3 Reference Equipment for Type Approval.......................................................110

6.4 Compliance with FCC Rules and Regulations...............................................111

7 Document Information............................................................................................113

7.1 Revision History.............................................................................................113

7.2 Related Documents .......................................................................................117

7.3 Terms and Abbreviations...............................................................................117

7.4 Safety Precaution Notes................................................................................120

8 Appendix..................................................................................................................121

8.1 List of Parts and Accessories.........................................................................121

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Tables

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Tables

Table 1: Supported frequency bands for each ALAS66A variant................................. 13

Table 2: Supported CA configurations......................................................................... 14

Table 3: Overview: Pad assignments........................................................................... 21

Table 4: Signal description........................................................................................... 24

Table 5: Absolute maximum ratings............................................................................. 31

Table 6: DCE-DTE wiring of ASC0 .............................................................................. 34

Table 7: Signals of the SIM interface (SMT application interface)............................... 36

Table 8: Overview of I

Table 9: GPIO lines and possible alternative assignment............................................ 40

Table 10: GPIO lines and fixed alternative assignment................................................. 41

Table 11: Return loss in the active band........................................................................ 44

Table 12: RF Antenna interface GSM/UMTS/LTE (at operating temperature range) -

TBD................................................................................................................ 45

Table 13: Possible GPIOx signal states if used for antenna diagnosis.......................... 55

Table 14: Assured antenna diagnostic states................................................................ 56

Table 15: GSM/UMTS/LTE antenna diagnostic decision threshold............................... 56

Table 16: Sample ranges of the GNSS antenna diagnostic measurements and

their possible meaning................................................................................... 58

Table 17: Antenna detection reference circuit - parts list............................................... 64

Table 18: GNSS properties (TBD.) ................................................................................ 66

Table 19: Power supply for active GNSS antenna......................................................... 66

Table 20: Overview of operating modes ........................................................................ 67

Table 21: Signal states................................................................................................... 69

Table 22: Board temperature warning and switch off level............................................ 78

Table 23: Voltage supply ratings.................................................................................... 85

Table 24: Current consumption ratings (to be continued).............................................. 86

Table 25: Board temperature......................................................................................... 93

Table 26: Electrostatic values........................................................................................ 94

Table 27: Reflow temperature recommendations........................................................ 100

Table 28: Storage conditions ....................................................................................... 101

Table 29: Directives ..................................................................................................... 106

Table 30: Standards of North American type approval................................................ 106

Table 31: Standards of European type approval.......................................................... 106

Table 32: Requirements of quality ............................................................................... 107

Table 33: Standards of the Ministry of Information Industry of the

People’s Republic of China.......................................................................... 107

Table 34: Toxic or hazardous substances or elements with defined concentration

limits............................................................................................................. 108

Table 35: Antenna gain limits for FCC......................................................................... 111

Table 36: List of parts and accessories........................................................................ 121

Table 37: Molex sales contacts (subject to change).................................................... 122

Table 38: Hirose sales contacts (subject to change)................................................... 122

2

S pin functions......................................................................... 39

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Figures

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Figures

Figure 1: ALAS66A system overview............................................................................ 18

Figure 2: ALAS66A block diagram................................................................................ 19

Figure 3: ALAS66A bottom view: Pad assignments...................................................... 22

Figure 4: ALAS66A top view: Pad assignments............................................................ 23

Figure 5: USB circuit ..................................................................................................... 32

Figure 6: Serial interface ASC0..................................................................................... 33

Figure 7: Serial interface ASC1..................................................................................... 34

Figure 8: I

Figure 9: First UICC/SIM/USIM interface...................................................................... 37

Figure 10: SIM interfaces - enhanced ESD protection.................................................... 38

Figure 11: I

Figure 12: PWR_IND signal............................................................................................ 42

Figure 13: eMMC power supply ...................................................................................... 43

Figure 14: Antenna pads (top view)................................................................................ 50

Figure 15: Embedded Stripline line arrangement............................................................ 51

Figure 16: Micro-Stripline line arrangement samples...................................................... 52

Figure 17: Routing to application‘s RF connector ........................................................... 53

Figure 18: Routing detail................................................................................................. 53

Figure 19: Resistor measurement used for antenna detection....................................... 54

Figure 20: Basic circuit for antenna detection................................................................. 55

Figure 21: Supply voltage for active GNSS antenna....................................................... 57

Figure 22: ESD protection for passive GNSS antenna................................................... 58

Figure 23: ALAS66A sample application......................................................................... 60

Figure 24: Sample level conversion circuits.................................................................... 61

Figure 25: Antenna detection circuit sample - overview.................................................. 62

Figure 26: Antenna detection circuit sample - schematic................................................ 63

Figure 27: Power-on with IGT ......................................................................................... 68

Figure 28: Signal states during turn-off procedure.......................................................... 73

Figure 29: Timing of IGT if used as ON/OFF switch ....................................................... 74

Figure 30: Shutdown by EMERG_OFF signal................................................................. 75

Figure 31: Restart by EMERG_OFF signal..................................................................... 75

Figure 32: Overall shutdown sequence........................................................................... 76

Figure 33: Power saving and paging in GSM networks .................................................. 81

Figure 34: Power saving and paging in WCDMA networks............................................. 82

Figure 35: Power saving and paging in LTE networks.................................................... 83

Figure 36: Decoupling capacitor(s) for BATT+................................................................ 84

Figure 37: Power supply limits during transmit burst....................................................... 92

Figure 38: Board and ambient temperature differences.................................................. 93

Figure 39: ALAS66A – top and bottom view ................................................................... 95

Figure 40: Dimensions of ALAS66A (all dimensions in mm)........................................... 96

Figure 41: Land pattern (top layer).................................................................................. 97

Figure 42: Recommended design for 110 micron thick stencil (top layer)...................... 98

Figure 43: Reflow Profile................................................................................................. 99

Figure 44: Shipping tray dimensions............................................................................. 103

Figure 45: Moisture Sensitivity Label ............................................................................ 104

Figure 46: Humidity Indicator Card - HIC...................................................................... 105

Figure 47: Reference equipment for type approval....................................................... 110

2

C interface connected to VEXT ................................................................... 35

2

S timing (master mode) ............................................................................... 39

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1 Introduction

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1 Introduction

This document1 describes the hardware of the Cinterion® ALAS66A products listed in Section

1.1. It helps you quickly retrieve interface specifications, electrical and mechanical details and

information on the requirements to be considered for integrating further components.

1.1 Product Variants

This document applies to the following Gemalto M2M modules:

•Cinterion

•Cinterion

•Cinterion

•Cinterion

•Cinterion

•Cinterion

®

ALAS66A-W

®

ALAS66A-CN

®

ALAS66A-E

®

ALAS66A-US

®

ALAS66A-J

®

ALAS66A-K

Where necessary a note is made to differentiate between the various product variants and re­leases.

1. The document is effective only if listed in the appropriate Release Notes as part of the technical docu­mentation delivered with your Gemalto M2M product.

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1.2 Key Features at a Glance

Feature Implementation

General
Frequency bands Note: Not all of the frequency bands (and 3GPP technologies) me ntioned

throughout this document are supported by every ALAS66A products vari­ant. Please refer to Section 1.2.1 for an overview of the frequency bands
supported by each ALAS66A product variant.

GSM class Small MS

Output power
(according to Release 99)

Output power
(according to Release 4)

Output power
(according to Release 8)

Power supply 3.3V <
Operating temperature

(board temperature)
Physical Dimensions: 48mm x 36mm x 3mm

RoHS All hardware components fully compliant with EU RoHS Directive

GSM/GPRS/UMTS:
Class 4 (+33dBm ±2dB) for EGSM850 and EGSM900
Class 1 (+30dBm ±2dB) for GSM1800 and GSM1900
Class E2 (+27dBm ± 3dB) for GSM 850 8-PSK and GSM 900 8-PSK
Class E2 (+26dBm +3 /-4dB) for GSM 1800 8-PSK and GSM 1900 8-PSK
Class 3 (+24dBm +1/-3dB) for all supported WCDMA FDD bands

TD-SCDMA:
Class 2 (+24dBm +1/-3dB) for TD-SCDMA 1900, TD-SCDMA Bd39 and
TD-SCDMA 2000, TD-SCDMA Bd34

LTE (FDD):
Class 3 (+23dBm +-2dB) for all supported LTE FDD bands

LTE (TDD):
Class 3 (+23dBm +-2dB) for all supported LTE TDD bands

V

Normal operation: -30°C to +85°C
Restricted operation: -40°C to +95°C

Weight: approx. 10.5g

BATT+

< 4.2V

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Feature Implementation

LTE features
3GPP Release 13 Downlink carrier aggregation (CA) to increase bandwidth, and thereby

increase bitrate:

• Maximum aggregated bandwidth: 80MHz

• Maximum number of component carriers: 3

• Inter-band FDD, TDD

• Intra-band FDD, TDD, contiguous, non-contiguous

• Supported inter- and intra-band CA configurations: See Section 1.2.2.
If 4x4 MIMO is supported by the mobile network:

• Downlink:
Up to 1Gbps CAT 16 with 4x4 MIMO 2 CA DL + 4(2)x2 MIMO 1 CA DL
or up to 800Mbps CAT 15 with 4x4 MIMO 2 CA DL

• Uplink:
Up to 150Mbps CAT 13 with 2 CA UL

If 4(2)x2 MIMO is supported by the mobile network:

• Downlink:
Up to 800Mbps CAT 15 with 4 CA DL

• Uplink:
Up to 150Mbps CAT 13 with 2 CA UL

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HSPA features
3GPP Release 8 UE CAT. 14, 24

DC-HSPA+ – DL 42Mbps
HSUPA – UL 5.76Mbps

Compressed mode (CM) supported according to 3GPP TS25.212
UMTS features
3GPP Release 8 PS data rate – 384 kbps DL / 384 kbps UL
TD-SCDMA features
3GPP Release 4 2.8 Mbps DL / 2.2Mbps UL
GSM / GPRS / EGPRS features
Data transfer GPRS:

• Multislot Class 12

• Mobile Station Class B

• Coding Scheme 1 – 4

EGPRS:

• Multislot Class 12

• EDGE E2 power class for 8 PSK

• Downlink coding schemes – CS 1-4, MCS 1-9

• Uplink coding schemes – CS 1-4, MCS 1-9

• SRB loopback and test mode B

• 8-bit, 11-bit RACH

• 1 phase/2 phase access procedures

• Link adaptation and IR

• NACC, extended UL TBF

• Mobile Station Class B

SMS Point-to-point MT and MO, Cell broadcast,

Text and PDU mode

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1.2 Key Features at a Glance

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Feature Implementation

Software
Embedded Linux platform Embedded Linux with API (ARC, RIL).

Memory space available for Linux applications is 4GB in the flash file sys-

tem, and 2GB RAM.
SIM Application Toolkit SAT Release 99, letter classes b, c, e with BIP and RunAT support
Firmware update Linux controlled firmware update.

GNSS Features

Protocol NMEA
Modes Standalone GNSS (GPS, GLONASS, Beidou, Galileo)

Integrated gpsOne 9HT support (GPS, GLONASS, Beidou, Galileo)

QZSS and SBAS support
General Power saving modes

DC feed bridge and control of power supply for active antenna via GPIO
Interfaces
Module interface Surface mount device with solderable connection pads (SMT application

interface).

Land grid array (LGA) technology ensures high solder joint reliability and

provides the possibility to use an optional module mounting socket.

For more information on how to integrate SMT modules see also [3]. This

application note comprises chapters on module mounting and app lication

layout issues as well as on additional SMT application development equip-

ment.
Antenna 50. 2 GSM/UMTS/LTE main antennas, 2 LTE Diversity/MIMO antennas,

(active/passive) GNSS antenna
USB USB 2.0 High Speed (480Mbit/s) device interface or

USB 3.0 Super Speed (5Gbit/s) device interface for debugging purposes
Serial interface Linux controlled:

ASC0:

• 4-wire (8-wire prepared) (plus GND line) interface unbalanced, asyn­chronous

• Fixed baud rates from 115,200 to 921,600bps

• Supports RTS0/CTS0 hardware flow control

ASC1:

• 4-wire, unbalanced asynchronous interface

• Fixed baud rates: 115,200bps to 921,60bps

• Supports RTS1/CTS1 hardware flow control

ASC2:

• 2-wire, unbalanced asynchronous interface at GPIO9 (RXD2) and
GPIO10 (TXD2) lines used for debugging purposes (optional)

UICC interface Supported chip cards: UICC/SIM/USIM 2.85V, 1.8V

2

I

C interfaces Linux controlled:

Audio 1 digital interface (I

2

2 I

C interfaces

2

S)
Power on/off, Reset
Power on/off Switch-on by hardware signal IGT

Automatic switch-off in case of critical temperature or voltage conditions

Emergency-off Emergency-off by hardware signal EMERG_OFF

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Feature Implementation

Special Features
Antenna SAIC (Single Antenna Interference Cancellation) / DARP (Downlink

Advanced Receiver Performance)
Rx Diversity (receiver type 3i - 64-QAM) / MIMO
HORxD (Higher Order Receive Diversity) with up to 4 antennas

GPIO Linux controlled:

18 I/O pins of the application interface programmable as GPIO.

External antenna switch 3 GPIOs permanently configured as optional external antenna switch inter-

face.

Emergency call handling EU eCall 3GPP Release 10 compliant (modem and GNSS)

ERA compliant (modem and GNSS)

ADC inputs Linux controlled:

Analog-to-Digital Converter with unbalanced analo g inputs for example for
(external) antenna diagnosis

JTAG JTAG interface for debug purposes

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eMMC Linux controlled:

Embedded Multi-Media Card interface

PCIe Linux controlled:

PCIe interface
Evaluation kit
Evaluation module ALAS66A module soldered onto a dedicated PCB.

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1.2.1 Supported Frequency Bands

The following table lists the supported frequency bands for each of the ALAS66A product vari­ants mentioned in Section 1.1.

Table 1: Supported frequency bands for each ALAS66A variant

Band -W -CN -E -US -J -K
GSM/GPRS/EDGE

850MHz x x x x
900MHz
1800MHz
1900MHz

UMTS/HSPA

Bd.I (2100MHz) x x x x x
Bd.II (1900MHz)
Bd.III (1800MHz)
Bd.IV (1700MHz)
Bd.V (850MHz)
Bd.VI (850MHz)
Bd.VIII (900MHz)
Bd.XIX (850MHz)

TD-SCDMA

Bd.34 (2000MHz) x
Bd.39 (1900MHz)

LTE-FDD

Bd.1 (2100MHz) x x x x x

x x x x x x
x x x x x x
x x x x

x

x x x x x

x
x x x x
x x x
x x x x x
x x x

x

Bd.2 (1900MHz)
Bd.3 (1800MHz)
Bd.4 (1700MHz)
Bd.5 (850MHz)
Bd.7 (2600MHz)
Bd.8 (900MHz)
Bd.12 (700MHz)
Bd.13 (700MHz)
Bd.18 (850MHz)
Bd.19 (850MHz)
Bd.20 (800MHz)
Bd.26 (850MHz)
Bd.28 (700MHz)

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x x x x
x x x x x x
x x x x x

x x x
x x x
x x x x
x x x
x x x x x

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x

Cinterion® ALAS66A Hardware Interface Description

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1.2 Key Features at a Glance

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Table 1: Supported frequency bands for each ALAS66A variant

Band -W -CN -E -US -J -K

Bd.29 (700MHz)

x

<supplementary
downlink>

Bd.30 (2300MHz)

1

x

<supplementary
downlink only acc.
FCC regulation>

Bd.32 (1500MHz)

x x x x

<supplementary
downlink>

Bd.66 (1700MHz)

x

LTE-TDD

Bd.34 (2000MHz) x x x x
Bd.38 (2600MHz)
Bd.39 (1900MHz)
Bd.40 (2300MHz)
Bd.41 (2600MHz)

1. Currently disabled by means of software because of AT&T regulation.

2. Note: Currently disabled for by means of software for the ALAS66A-W and ALAS66A-K variants. Also,
out of the 3GPP-specified frequency range for the LTE TDD Band 41 only the 110MHz frequency band
from 2545MHz to 2655MHz is supported by ALAS66A.

2

x x x x x
x x x x
x x x x
x x x x

1.2.2 Supported CA Configurations

The following table lists the supported CA configurations for each of the ALAS66A product vari­ants mentioned in Section 1.1.

Table 2: Supported CA configurations

Downlink CA Uplink CA Bandwidth

combination set

Intra-band continuous

CA_1C - 0,1 E, W, CN, J, K
CA_2C - 0 US
CA_3C CA_3C 0 E, W, CN, J, K
CA_5B - 0,1 US, W, J, K
CA_7B - 0 E, US, W, CN, J, K
CA_7C CA_7C 0, 1, 2 E, US, W, CN, J, K
CA_8B - 0 E, W, CN, J, K
CA_12B - 0 US
CA_38C CA_38C 0 E, W, CN, J, K
CA_40C CA_40C 0, 1 W, CN, J, K
CA_40D - 0,1 W, CN, J, K

Product variants
(ALAS66A-...)

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Table 2: Supported CA configurations

Downlink CA Uplink CA Bandwidth

combination set

CA_41C CA_41C 0,1,2,3 CN, J
CA_41D CA_41C 0 CN, J
CA_66B - 0 US
CA_66C - 0 US

Intra-band non-continuous

CA_2A-2A - 0 US
CA_4A-4A - 0,1 US
CA_66A-66A - 0 US

Inter-band (two bands)

CA_1A-3A - 0,1 E, W, CN, J, K
CA_1A-3C CA_3C 0 E, W, CN, J, K
CA_1A-5A CA_1A-5A 0, 1 W
CA_1A-7A - 0 E, W, CN, J, K
CA_1A-8A CA_1A-8A 0, 1, 2 E, W, CN, J, K
CA_1A-18A CA_1A-18A 0, 1 W, J, K
CA_1A-19A - 0 W, J, K
CA_1A-20A - 0 E, W, J, K
CA_1A-26A CA_1A-26A 0, 1 W, J, K
CA_1A-28A CA_1A-28A 0, 1 E, W, J, K
CA_2A-2A-4A - 0 US
CA_2A-2A-4A-4A - 0 US
CA_2A-2A-5A - 0 US
CA_2A-2A-12A - 0 US
CA_2A-2A-13A - 0 US
CA_2A-2A-66A - 0 US
CA_2A-4A - 0, 1, 2 US
CA_2A-4A-4A - 0 US
CA_2A-5A - 0, 1 US
CA_2A-12A - 0, 1, 2 US
CA_2A-12B - 0 US
CA_2A-13A - 0, 1 US
CA_2A-28A - 0 US
CA_2A-29A - 0, 1, 2 US
CA_2A-66A - 0,1,2 US
CA_2A-66A-66A - 0 US
CA_2C-5A - 0 US
CA_2C-12A - 0 US
CA_2C-29A - 0 US
CA_3A-3A-8A CA_7C 0, 1 E, W, CN, J, K
CA_3A-5A CA_3A-8A 0, 1, 2, 3,4 W, J, K
CA_3A-7A - 0, 1 E, W, CN, J, K
CA_3A-7B CA_3A-20A 0 E, W, CN, J, K

Product variants
(ALAS66A-...)

Page 15 of 123

 ALAS66A_HID_v01.000b 2019-02-06

Confidential / Preliminary

Cinterion® ALAS66A Hardware Interface Description

1.2 Key Features at a Glance

19

Table 2: Supported CA configurations

Downlink CA Uplink CA Bandwidth

combination set

CA_3A-7C - 0, 1 E, W, CN, J, K
CA_3A-8A - 0, 1, 2, 3 E, W, CN, J, K
CA_3A-19A - 0 W, J, K
CA_3A-20A CA_3C 0, 1 E, W, J, K
CA_3A-26A - 0, 1 W, J, K
CA_3A-28A CA_3A-20A 0,1 E, W, J, K
CA_3C-5A - 0 W, J, K
CA_3C-7A - 0 E, W, CN, J, K
CA_3C-7C - 0,1 E, W, J, K
CA_3C-8A CA_3C-8A, CA_3C 0 W, J, K
CA_3C-20A - 0 E, W, J, K
CA_3C-28A - 0 E, W, J, K
CA_4A-4A-5A - 0 US
CA_4A-4A-7A - 0, 1 US
CA_4A-4A-12A - 0 US
CA_4A-4A-13A - 0 US
CA_4A-5A - 0, 1 US
CA_4A-7A - 0, 1 US
CA_4A-12A - 0,1,2,3,4,5 US
CA_4A-12B - 0 US
CA_4A-13A - 0, 1 US
CA_4A-28A - 0 US
CA_4A-29A - 0, 1, 2 US
CA_5A-7A CA_5A-7A 0, 1 US, W, J, K
CA_5A-12A - 0 US
CA_5A-66A - 0 US
CA_5A-66A-66A - 0 US
CA_7A-8A - 0, 1,2 E, W, CN, J, K
CA_7A-12A - 0 US
CA_7A-20A CA_7A-20A 0, 1 E, W, J, K
CA_7A-28A - 0, 1 E, US, W, J, K
CA_7B-28A - 0 E, US, W, J, K
CA_7C-28A CA_7C 0 E, US, W, J, K
CA_8A-20A - 0, 1 E, W, J, K
CA_12A-66A - 0,1,2,3,4,5 US
CA_12A-66A-66A - 0 US
CA_13A-66A - 0 US
CA_13A-66A-66A - 0 US
CA_18A-28A - 0 W, J, K
CA_20A-32A - 0,1 E, W, J, K
CA_39A-41A - 0 CN
CA_39A-41C CA_41C 0 CN

Product variants
(ALAS66A-...)

Page 16 of 123

 ALAS66A_HID_v01.000b 2019-02-06

Confidential / Preliminary

Cinterion® ALAS66A Hardware Interface Description

1.2 Key Features at a Glance

19

Table 2: Supported CA configurations

Downlink CA Uplink CA Bandwidth

combination set

CA_39C-41A CA_39C 0 CN

Inter-band (three bands)

CA_1A-3A-5A CA_1A-5A, CA_3A-5A 0, 1 E, W, J, K
CA_1A-3A-8A CA_1A-8A, CA_3A-8A 0,1,2,3 E, W, CN, J, K
CA_1A-3A-19A - 0 W, J, K
CA_1A-3A-20A CA_3A-20A 0 E, W, J, K
CA_1A-3A-26A - 0 W, J, K
CA_1A-3A-28A - 0 E, W, J, K
CA_1A-5A-7A CA_1A-5A, CA_5A-7A 0, 1 E, W, J, K
CA_1A-7A-8A - 0 E, W, CN, J, K
CA_1A-7A-20A - 0,1 E, W, J, K
CA_1A-7A-28A - 0,1,2 E, W, J, K
CA_1A-18A-28A - 0, 1 W, J, K
CA_1A-19A-28A - 0 W, J, K
CA_2A-2A-4A-12A - 0 US
CA_2A-2A-12A-66A - 0 US
CA_2A-4A-4A-12A - 0 US
CA_2A-4A-5A - 0 US
CA_2A-4A-12A - 0 US
CA_2A-4A-13A - 0 US
CA_2A-4A-29A - 0 US
CA_2A-5A-66A - 0 US
CA_2A-12A-66A - 0 US
CA_2A-12A-66A-66A - 0 US
CA_2A-13A-66A - 0 US
CA_3A-7A-8A CA_3A-8A 0, 1,2 E, W, CN, J, K
CA_3A-7A-28A - 0 E, W, J, K
CA_3A-7C-28A - 0 E, W, J, K
CA_4A-7A-12A - 0, 1 US

Product variants
(ALAS66A-...)

Page 17 of 123

 ALAS66A_HID_v01.000b 2019-02-06

Confidential / Preliminary

Cinterion® ALAS66A Hardware Interface Description

Power

Supply

IGT

EMERG_OFF

Application

Interfaces

ALAS66A

Application

VEXT

PWR_IND

Serial Interface

Digital
Audio

GNSS

Application

USIM

SIM

Card

Codec

GSM/UMTS/LTE

GPIO

Antenna-

diagnostic

4 x

ADC

I2S

I2C

I2C

Serial Interface

I2C

USB

2.0/3.0

ASC0

ASC1

I2C

Digital

Audio

GPIO

I2S

USB

Antenna-

diagnostic

External Antenna

Switch (optiona l)

TRX1 TRX2 RX3 RX4GNSS

GPIO

Power

Supply

eMMC

eMMC Interface

Power
Supply

PCIe

PCIe

3 x

ANT_SW

1.3 System Overview

19

1.3 System Overview

Page 18 of 123

Figure 1: ALAS66A system overview

 ALAS66A_HID_v01.000b 2019-02-06

Confidential / Preliminary

Cinterion® ALAS66A Hardware Interface Description

DDR2SDRAM

4GBi t

NANDFlash

8GBi t

38.4MHz

Powermanagement

Basebandcontroller

RFpart

Clocks

LDO

LDO

LDO

LDO

LDO

S1

S2

S3

S4

S5

PMU

PMU

MB/HB

PA

LB
PA

GSM

PA

Filter

&

Switches

QLINK RFFE

EBI 1

EBI 2

GRFC

BATT+

ANT_ TRX1

ANT_ TRX2

ANT_RX3

ANT_RX4

ANT_GNSS
GNSS_EN
ANT_GNSS_

C

LGAPads

IGT

EMERG _O FF

PWR_IND

USB 3.0
USB 2.0

ASC0
ASC1

2xI2C

I2S2

eMMC

SIM
GPIO
PCIe

4xADC_IN

ADC

BATT +_RF

GND

ALAS66A‐W

Page 19 of 123

1.4 Circuit Concept

19

1.4 Circuit Concept

Figure 2 shows a block diagram of the ALAS66A module and illustrates the major functional

components:
Baseband block:

• GSM/UMTS/LTE controller/transceiver/power supply

• NAND/LPDDR2 memory devices

• A pplication interface (SMT with connecting pads)
RF section:

• RF transceiver

• RF power amplifier/frontend

• RF filter

• GNSS receiver/Front end

• Antenna pad

 ALAS66A_HID_v01.000b 2019-02-06

Figure 2: ALAS66A block diagram

Confidential / Preliminary

D

Cinterion® ALAS66A Hardware Interface Description

2 Interface Characteristics

66

Page 20 of 123

2 Interface Characteristics

ALAS66A is equipped with an SMT application interface that connects to the external applica­tion. The SMT application interface incorporates the various application interfaces as well as
the RF antenna interface.

2.1 Application Interface

2.1.1 Pad Assignment

The SMT application interface on the ALAS66A provides connecting pads to integrate the mod­ule into external applications. Table 3 lists the pads’ assignments. Figure 3 (bottom view) and

Figure 4 (top view) show the connecting pads’ numbering plan.

Please note that a number of connecting pads are marked as reserved for future use (rfu) and
further qualified as either (<name>), (dnu), (GND) or (nc):

• Pads marked as “rfu“ and qualified as “<name>“ (signal name) may be soldered and could
be connected to an external application compliant to the signals’ electrical characteristics
as described in Table 4.

• Pads marked "rfu" and qualified as "dnu" (do not use) may be soldered but should not be
connected to an external application.

• Pads marked "rfu" and qualified as "GND" (ground) are assigned to ground with ALAS66A
modules, but may have different assignments with future Gemalto M2M p roducts using the
same pad layout.

• P ads marked "rfu" and qualified as "nc" (not connected) are internally not connected with
ALAS66A modules, but may be soldered and arbitrarily be connected to external ground.

Also note that some pads are marked with a circle ( ). These pads have a round shape for
improved impedance control.

Gemalto strongly recommends to solder all connecting pads for mechanical stability and heat
dissipation.

Also, Gemalto strongly recommends to provide test points for certain signal lines to and from
the module while developing SMT applications – for debug and/or test purposes during the
manufacturing process. In this way it is possible to detect soldering problems. Please refer to

[2] for more information on test points and how to implement them. The signal lines for which

test points should be provided for are marked as “Test point required” or “Test point recom­mended“ in Section 2.1.2: Table 4 describing signal characteristics.

 ALAS66A_HID_v01.000b 2019-02-06

Confidential / Preliminary

Cinterion® ALAS66A Hardware Interface Description

Page 21 of 123

2.1 Application Interface

66

Table 3: Overview: Pad assignments

Pad No. Signal Name Pad No. Signal Name Pad No. Signal Name

A1 GND E15 rfu (dnu) M8 JTAG_WD_DISABLE
A2 GND E16 rfu (dnu) M9 I2CDAT1
A5 GND E17 rfu (dnu) M10 I2CCLK1
A6 GND E18 VEXT M11 I2CDAT2
A7 ANT_RX3 E19 rfu (dnu) M12 I2CCLK2
A8 GND E20 BATT+ M13 EMMC_D6
A9 GND E21 GND M14 EMMC_D1
A10 GND F2 ANT_TRX2 M15 GPIO22 (Interrupt)
A11 ANT_RX4 F3 GND M16 USB_DP
A12 GND F4 GND M17 USB_DN
A13 GND F5 GND M18 rfu (dnu)
A14 GND F6 rfu (dnu) M19 CCCLK
A15 ANT_GNSS F7 rfu (dnu) M20 GPIO8 (Interrupt)
A16 GND F8 rfu (nc) M21 GND
A17 ANT_GNSS_DC F14 rfu (nc) N3 GND
A20 GND F15 GND

A21

B4
B5
B6
B7 GND F20 BATT+ N9 DIN2
B8
B9
B10 GND G4 GND N12 EMMC_D4
B11
B12
B13 GND G16 GND N15 EMMC_D0
B14 GND G17 GND N16 GND
B15 GND G18 GPIO20 / DCD0 / Download N17 GND
B16 GND G19 CTS0 N18 rfu (dnu)
B17 GND G20 RTS0 N19 CCIN
B18 rfu (dnu) H2 GND P1 GND
C1 GND H3 GND P2 GND
C2 GND H4 GND P4 BATT+_RF
C4 GND H5 GND P5 BATT+_RF
C5 GND H6 GND P6 GPIO5 (Interrupt)
C6 GND H16 USB_SSTX_P P7 rfu (DIN1)
C7 GND H17 USB_SSTX_N P8 rfu (DOUT1)
C8 GND H18 GPIO6 P9 rfu (BCLK1)
C9 GND H19 TXD0 P10 rfu (FSC1)
C10 GND H20 rfu (BATT_ID) P11 rfu (MCLK)
C11 GND J2 GND P12 EMMC_D7
C12 GND J3 GND P13 EMMC_CMD
C13 GND J4 GND P14 EMMC_D3
C14 GND J5 GND P15 EMMC_CLK
C15 GND J6 rfu (dnu) P16 PCIE_CLK_P
C16 GND J16 GND P17 PCIE_CLK_N
C17 HEART_BEAT J17 GND P18 VUSB_IN
C18 JTAG_TCK J18 rfu (dnu) P20 GND
C20 GND J19 CCIO P21 GND
C21 GND J20 GPIO19 / RING0 R5 PWR_IND
D3 GND K2 GND R6 RTS1
D4 GND K3 GND R7 CTS1
D5 GND K4 GND R8 TXD1
D6
D7
D8 ADC4_IN K16 USB_SSRX_P R11 PCIE_HOST_RST
D9
D10
D11
D12
D13 GNSS_EN L2 ANT_TRX1 R16 GND
D14 JTAG_TMS L3 GND R17 GPIO16 (Interrupt)
D15 JTAG_TRST L4 GND T1 GND
D16 JTAG_TDI L5 GND T2 GND
D17 JTAG_SRST L6 rfu (dnu) T5 rfu (dnu)
D18 JTAG_TDO L7 EMMC_DETECT T6 rfu (dnu)
D19 IGT L8 rfu (nc) T7 GPIO2 / FwSwap (Interrupt)
E1 GND L14 rfu (nc) T8 GPIO10 / TXD2 (Interrupt)
E2 GND L15 EMMC_PWR T9 GPIO15 / WLAN_EN
E3 GND L16 GND T10 GPIO9 / RXD2
E4 GND L17 GND T11 GND
E5 GND L18 rfu (dnu) T12 PCIE_RX_P
E6 GND L19 CCRST T13 PCIE_RX_N
E7 rfu (dnu) L20 GPIO4 T14 GND
E8 GPIO1/ DR_SYNC M1 GND T15 PCIE_TX_P
E9 GPIO7 (Interrupt) M2 GND T16 PCIE_TX_N
E10 ANT_SW3 M3 GND T17 GND
E11 ANT_SW2 M4 GND T20 GND
E12 ANT_SW1 M5 GND T21 GND
E13 JTAG_PS_HOLD M6 GND
E14 rfu (dnu) M7 GPIO17 / BT_EN

GND F16 EMERG_OFF

rfu (dnu) F17 GPIO18 / DSR0 N6 GND
GND F18 RXD0 N7 FSC2
GND F19 GPIO21 / DTR0 N8 DOUT2

GND G2 GND N10 BCLK2
GND G3 GND N11 GND

GND G5 GND N13 EMMC_D5
GND G6 rfu (dnu) N14 EMMC_D2

GND K5 GND R9 RXD1
rfu (dnu) K6 rfu (dnu) R10 PCIE_HOST_WAKE

ADC5_IN K17 USB_SSRX_N R12 GND
ADC1_IN K18 rfu (dnu) R13 GND
ADC2_IN K19 CCVCC R14 PCIE_CLK_REQ
GPIO11 K20 rfu (dnu) R15 GND

N4 GND

N5 GND

 ALAS66A_HID_v01.000b 2019-02-06

Confidential / Preliminary

Cinterion® ALAS66A Hardware Interface Description

1 2 3 4 5 6 7 8 9 101112131415161718192021

T

GND GND rfu

(dnu)

rfu

(dnu)

GPIO2 /
FwSWAP
(Interrupt)

GPIO10 /

TXD2

(Interrupt)

GPIO15 /
WLAN_E

N

GPIO9 /

RXD2

GND PCIE_

RX_P

PCIE_
RX_N

GND PCIE_

TX_P

PCIE_

TX_N

GND GND GND

R

PWR_

IND

RTS1 CTS1 TXD1 RXD1 PCIE_

HOST_

WAKE

PCIE_

HOST_

RST

GND GND PCIE_

CLK_

REQ

GND GND GPIO16

(Interrupt)

GND

P

GND GND BATT+_RFBATT+_RFGPIO5

(Inter-

rupt)

rfu

(DIN1)

rfu

(DOUT1)

rfu

(BCLK1)

rfu

(FSC1)

rfu

(MCLK)

EMMC_D7EMMC_

CMD

EMMC_D3EMMC_

CLK

PCIE_­CLK_P

PCIE_

CLK_N

VUSB_

IN

GND GND

N

GND GND GND GND FSC2 DOUT2 DIN2 BCLK2 GND

EMMC_D4EMMC_D5EMMC_D2EMMC_

D0

GND GND rfu

(dnu)

CCIN GND

M

GND GND GND GND GND GND GPIO17 /

BT_EN

JTAG_

WD_

DISABLE

I2CDAT1 I2CCLK1I2CDAT2I2CCLK

2

EMMC_D6EMMC_

D1

GPIO22

(Inter-

rupt)

USB_DP USB_DN rfu

(dnu)

CCCLK GPIO8

(Interrupt)

GND

L

ANT_
TRX1

GND GND GND rfu

(dnu)

EMMC_

DETECT

rfu

(nc)

rfu

(nc)

EMMC_

PWR

GND GND rfu

(dnu)

CCRST GPIO4

K

GND GND GND GND rfu

(dnu)

USB_

SSRX_P

USB_

SSRX_N

rfu

(dnu)

CCVCC rfu

(dnu)

GND

J

GND GND GND GND rfu

(dnu)

GND GND rfu

(dnu)

CCIO GPIO19 /

RING0

GND

H

GND GND GND GND GND

USB_

SSTX_P

USB_

SSTX_N

GPIO6 TXD0 rfu

(BATT_

ID)

GND

G

GND GND GND GND rfu

(dnu)

GND GND GPIO20 /

DCD0 /

Down-

load

CTS0 RTS0 GND

F

ANT_
TRX2

GND GND GND rfu

(dnu)

rfu

(dnu)

rfu

(nc)

rfu

(nc)

GND EMERG

_OFF

GPIO18 /

DSR0

RXD0 GPIO21 /

DTR0

BATT+

E

GND GND GND GND GND GND rfu

(dnu)

GPIO1 /

DR_SYNC

GPIO7

(Inter-

rupt)

ANT_

SW3

ANT_

SW2

ANT_

SW1

JTAG_

PS_

HOLD

rfu

(dnu)

rfu

(dnu)

rfu

(dnu)

rfu

(dnu)

VEXT rfu

(dnu)

BATT+ GND

D

GND GND GND GND rfu

(dnu)

ADC4_IN ADC5_IN ADC1_INADC2_INGPIO11 GNSS_ENJTAG_

TMS

JTAG_

TRST

JTAG_

TDI

JTAG_

SRST

JTAG_

TDO

IGT

C

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND HEART_

BEAT

JTAG_

TCK

GND GND

B

rfu

(dnu)

GND GND GND GND GND GND GND GND GND GND GND GND GND

rfu

(dnu)

GND

A

GND GND GND GND

ANT_

RX3

GND GND GND

ANT_

RX4

GND GND GND

ANT_

GNSS

GND ANT_

GNSS_

DC

GND GND

rfu: Reserved for future use (may be connected to external application
(nc): Internally not connected (may be arbitrarily connected to external GND)

(dnu): Do not use (should not be connected to external application)

Circle marks round shaped pads designed for improved impedance.

Orange: Keep out areas on external application’s PCB.

Rectangular shaped: GND pads should be soldered, but no further tracks
on PCB’s 1

st

layer, as well as a solid ground plane on PCB’s 2nd layer.
Round shaped: No solder pads, should therefore not be soldered. No fur­ther tracks on PCB’s first layer.

2.1 Application Interface

66

Page 22 of 123

 ALAS66A_HID_v01.000b 2019-02-06

Figure 3: ALAS66A bottom view: Pad assignments

Confidential / Preliminary

Cinterion® ALAS66A Hardware Interface Description

21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

T

GND GND GND

PCIE_

TX_N

PCIE_
TX_P

GND

PCIE_

RX_N

PCIE_

RX_P

GND GPIO9 /

RXD2

GPIO15 /
WLAN_E

N

GPIO10 /

TXD2

(Interrupt)

GPIO2 /
FwSwap

(Interrupt)

rfu

(dnu)

rfu

(dnu)

GND GND

R

GND GPIO16

(Interrupt)

GND GND PCIE_

CLK_
REQ

GND GND PCIE_

HOST_

RST

PCIE_

HOST_

WAKE

RXD1 TXD1 CTS1 RTS1 PWR_

IND

P

GND GND VUSB_INPCIE_

CLK_N

PCIE_­CLK_P

EMMC_

CLK

EMMC_D3EMMC_

CMD

EMMC_

D7

rfu

(MCLK)

rfu

(FSC1)

rfu

(BCLK1)

rfu

(DOUT1)

rfu

(DIN1)

GPIO5

(Inter-

rupt)

BATT+_RFBATT+_

RF

GND GND

N

GND CCIN rfu

(dnu)

GND GND

EMMC_D0EMMC_D2EMMC_D5EMMC_

D4

GND BCLK2 DIN2 DOUT2 FSC2 GND GND GND GND

M

GND GPIO8

(Interrupt)

CCCLK rfu

(dnu)

USB_DN USB_DP GPIO22

(Inter-

rupt)

EMMC_D1EMMC_

D6

I2CCLK2I2CDAT2I2CCLK1I2CDAT1 JTAG_

WD_

DISABLE

GPIO17 /

BT_EN

GND GND GND GND GND GND

L

GPIO4 CCRST rfu

(dnu)

GND GND EMMC_

PWR

rfu

(nc)

rfu

(nc)

EMMC_

DETECT

rfu

(dnu)

GND GND GND

ANT_
TRX1

K

GND rfu

(dnu)

CCVCC rfu

(dnu)

USB_

SSRX_N

USB_

SSRX_P

rfu

(dnu)

GND GND GND GND

J

GND GPIO19 /

RING0

CCIO rfu

(dnu)

GND GND rfu

(dnu)

GND GND GND GND

H

GND rfu

(BATT_

ID)

TXD0 GPIO6

USB_

SSTX_N

USB_

SSTX_P

GND GND GND GND GND

G

GND RTS0 CTS0 GPIO20 /

DCD0 /

Down-

load

GND GND rfu

(dnu)

GND GND GND GND

F

BATT+ GPIO21 /

DTR0

RXD0 GPIO18 /

DSR0

EMERG

_OFF

GND

rfu

(nc)

rfu

(nc)

rfu

(dnu)

rfu

(dnu)

GND GND GND

ANT_
TRX2

E

GND BATT+ rfu

(dnu)

VEXT rfu

(dnu)

rfu

(dnu)

rfu

(dnu)

rfu

(dnu)

JTAG_

PS_

HOLD

ANT_

SW1

ANT_

SW2

ANT_

SW3

GPIO7

(Inter-

rupt)

GPIO1 /

DR_SYNC

rfu

(dnu)

GND GND GND GND GND GND

D

IGT JTAG_

TDO

JTAG_

SRST

JTAG_

TDI

JTAG_

TRST

JTAG_

TMS

GNSS_ENGPIO11 ADC2_INADC1_INADC5_IN ADC4_IN rfu

(dnu)

GND GND GND GND

C

GND GND JTAG_

TCK

HEART_

BEAT

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

B

GND

rfu

(dnu)

GND GND GND GND GND GND GND GND GND GND GND GND GND

rfu

(dnu)

A

GND GND ANT_

GNSS_

DC

GND

ANT_
GNSS

GND GND GND

ANT_

RX4

GND GND GND

ANT_

RX3

GND GND GND GND

rfu: Reserved for future use (may be connected to external application
(nc): Internally not connected (may be arbitrarily connected to external GND)

(dnu): Do not use (should not be connected to external application)

Circle marks round shaped pads designed for improved impedance.

Orange: Keep out areas on external application’s PCB.

Rectangular shaped: GND pads should be soldered, but no further tracks
on PCB’s 1

st

layer, as well as a solid ground plane on PCB’s 2nd layer.
Round shaped: No solder pads, should therefore not be soldered. No fur­ther tracks on PCB’s first layer.

2.1 Application Interface

66

Page 23 of 123

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Figure 4: ALAS66A top view: Pad assig n me n ts

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Cinterion® ALAS66A Hardware Interface Description

Page 24 of 123

2.1 Application Interface

66

2.1.2 Signal Properties

Please note that the reference voltages listed in Table 4 are the values measured directly on
the ALAS66A module. They do not apply to the accessories connected.

Table 4: Signal description

Function Signal name IO Signal form and level Comment

Power sup­ply

External
supply volt­age

BATT+
BATT+_RF

IV

max = 4.2V

I

V

min = 3.3V (on board)

I

Supply voltage lines for gen­eral power management and
the RF power amplifier.

GSM during Tx burst

Lines of BATT+/BATT+_RF
and GND respectively must

n Tx = n x 577µs peak current every

4.615ms
Imax = see Table 24

be connected in parallel for
supply purposes because
higher peak currents may
occur.

WCDMA TX continuous current
Imax = see Table 24

Minimum voltage must not
fall below 3.3V including

LTE TX continuous current

drop, ripple, spikes.

Imax = see Table 24
GND Ground Application Ground
VEXT O C

max = 1µF

L

VEXT may be used for appli­cation circuits.

V

= 1.80V -2.4%, +2%

O

If unused keep line open.
Normal operation:
I

max = -50mA

O

Test point recommended.

The external digital logic
SLEEP mode operation:
I

max = -1mA

O

must not cause any spikes

or glitches on voltage VEXT.

Supply volt­age for
active
GNSS
antenna
(input)

External
GNSS sup­ply voltage
enable
(output)

ANT_GNSS_DCIV

max = 5V

I

Imax = 50mA

GNSS_EN O V

max = 0.45V at I = 2mA

OL

V

nom = 0.1V at I = 100µA

OL

V

OH

V

OH

V

OH

min = 1.30V at I = -2mA
nom = 1.65V at I = -100µA
max = 1.84V

Do not exceed I

max in any

O

operation mode.

If unused connect to GND.

The input current must be

limited to 50mA (antenna

short circuit protection).

Enable signal for an external

voltage regulator (intended

for active GNSS antenna,

high=active)

No external pull-up allowed

during startup until the mod-

ule has been secured in fac-

tory.

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2.1 Application Interface

66

Table 4: Signal description

Function Signal name IO Signal form and level Comment

Page 25 of 123

Ignition IGT I R

Emer­gency off

SIM card

EMERG_

IR

OFF

CCIN I R

detection

 200k

PU

V

max = 1.84V

OH

V

max =2.00V

IH

V

min = 1.30V

IH

V

max = 0.50V

IL

Low impulse width > 100ms

 40k

PU

V

max = 1.84V

OH

V

max = 2.00V

IH

V

min = 1.30V

IH

V

max = 0.50V

IL

¯¯|___|¯¯
low pulse width up to 2000ms
(as long as PWR_IND stays low

 24kto VEXT

PU

V

max=1.84V

OH

V

min = 1.25V at -25µA

IH

V

max= 2.0V

IH

V

max = 0.35V at -60µA

IL

This signal switches the

module on.

It is required to drive this line

low by an open drain or open

collector driver connected to

GND.

Test point recommended.

It is required to drive this line

low by an open drain or open

collector driver connected to

GND until the module finally

switches off.

If unused keep line open.

Test point recommended.

Note that a low impulse of

more than 2000ms will reset

the module’s RTC.

CCIN = Low means SIM

card inserted.

If SIM card holder does not

support CCIN, connect to

GND.

2.85V SIM
card inter­faces

CCRST O V
CCCLK

CCIO I/O R

CCVCC O V

max = 0.4V at I = 2mA

OL

V

nom = 0.1V at I = 100µA

OL

V

min = 2.2V at I = -2mA

OH

V

nom = 2.65V at I = -100µA

OH

V

max = 2.91V

OH

 6.7..8.5k

PU

V

max = 0.55V

IL

V

min = 2.35V

IH

V

max = 3.05V

IH

V

max = 0.4V at I = 2mA

OL

V

nom = 0.1V at I = 100µA

OL

V

min = 2.35V at I > -45µA

OH

V

max = 2.91V

OH

min = 2.75V

O

V

typ =2.85V

O

V

max = 2.91V

O

I

max = -50mA

O

Maximum cable length or

copper track should be not

longer than 100mm to SIM

card holder.

If unused keep lines open.

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2.1 Application Interface

66

Table 4: Signal description

Function Signal name IO Signal form and level Comment

Page 26 of 123

1.8V SIM
card inter­face

SIM inter­face shut­down

Serial
Interface
ASC0

CCRST O V
CCCLK

CCIO I/O R

CCVCC O V

max = 0.4V at I = 2mA

OL

V

nom = 0.1V at I = 100µA

OL

V

min = 1.40V at I = -2mA

OH

V

min = 1.65V at I = -100µA

OH

V

max = 1.84V

OH

 6.7..8.5k

PU

V

max = 0.30V

IL

V

min = 1.30V

IH

V

max = 1.84V

IH

V

max = 0.4V at I = 2mA

OL

V

nom = 0.1V at I = 100µA

OL

V

min = 1.40V at I > -50µA

OH

V

max = 1.84V

OH

min = 1.74V

O

V

typ = 1.80V

O

V

max = 1.84V

O

I

max = -50mA

O

BATT_ID I External pull up to VEXT and pull

down resistor within battery case
required.
R

= 100k

PU

R

= 10k

PD

RXD0 O V
CTS0 O
DSR0 O
RING0 O

max = 0.45V at I = 2mA

OL

V

nom = 0.1V at I = 100µA

OL

V

min = 1.30V at I = -2mA

OH

V

nom = 1.65V at I = -100µA

OH

V

max = 1.84V

OH

DCD0 I/O
TXD0 I V
RTS0 I
DTR0 I

max = 0.50V

IL

V

min = 1.30V

IH

V

max = 2.0V

IH

I

= 27.5µA…97.5µA

IHPD

I

= -27.5µA…-97.5µA

ILPU

I

High-Z max

= +-1µA

Maximum cable length or

copper track should be not

longer than 100mm to SIM

card holder.

If unused keep lines open.

Reserved for future use.

Connect line to GND.

Test points recommended

for TXD0, RXD0, DCD0,

RTS0, and CTS0.

If DCD0 is driven low during

startup-phase, module

enters Download Mode (see

Section 4.2.2)

If unused keep line open.

DSR0, DCD0, DTR0, and

RING0 are not yet imple-

mented, and are only avail-

able as GPIOs.

Serial
Interface
ASC1

RXD1 O V
CTS1 O

TXD1 I V
RTS1 I

max = 0.45V at I = 2mA

OL

V

nom = 0.1V at I = 100µA

OL

V

min = 1.30V at I = -2mA

OH

V

nom = 1.65V at I = -100µA

OH

V

max = 1.84V

OH

max = 0.50V

IL

V

min = 1.30V

IH

V

max = 2.0V

IH

I

= 27.5µA…97.5µA

IHPD

= -27.5µA…-97.5µA

I

ILPU

I

High-Z max

= +-1µA

Test points recommended

for RXD1, TXD1, CTS1, and

RTS1.

If unused keep line open.

 ALAS66A_HID_v01.000b 2019-02-06

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Cinterion® ALAS66A Hardware Interface Description

2.1 Application Interface

66

Table 4: Signal description

Function Signal name IO Signal form and level Comment

Page 27 of 123

Power indi-

PWR_IND O V

cator

USB VUSB_IN I V

max = 5.5V

IH

V

max = 0.45V at Imax = 2mA

OL

min = 3.0V

IN

V

max = 5.75V

IN

I

max = 100µA

I

Cin=1µF

PWR_IND (Power Indicator)

notifies the module’s on/off

state.

PWR_IND is an open collec-

tor that needs to be con-

nected to an external pull-up

resistor. Low state of the

open collector indicates that

the module is on. Vice versa,

high level notifies the Power

Down mode.

Therefore, the signal may be

used to enable external vol-

tage regulators that supply

an external logic for commu-

nication with the module,

e.g. level converters.

Test point recommended.

USB detection.

Test point recommended.

Digital
audio inter­face

2

(I

S)

USB_DN I/O Full and High speed signal (differen­USB_DP I/O

USB_
SSRX_N

USB_

tial) characteristics according to USB

2.0 specification.

I Super Speed signal (differential) Rx

characteristics according USB 3.0
specification.

I

SSRX_P
USB_

SSTX_N
USB_

O Super Speed signal (differential) Tx

characteristics according USB 3.0
specification.

O

SSTX_P
DIN2 I V
BCLK2 I/O
FSC2 I/O
DOUT2 O

max = 0.45V at I = 2mA

OL

V

nom = 0.1V at I = 100µA

OL

V

min = 1.30V at I = -2mA

OH

V

nom = 1.65V at I = -100µA

OH

V

max = 1.84V

OH

V

max = 0.50V

IL

V

min = 1.30V

IH

V

max = 2.0V

IH

= 27.5µA…97.5µA

I

IHPD

I

= -27.5µA…-97.5µA

ILPU

I

High-Z max

= +-1µA

If unused keep lines open.

Test point recommended.

USB High Speed mode

operation requires a differ-

ential impedance of 90

If unused keep lines open.

USB Super Speed mode

operation requires a differ-

ential impedance of 90

Digital audio interface con-

figurable as I

2

S interface.

If unused keep lines open.

 ALAS66A_HID_v01.000b 2019-02-06

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Cinterion® ALAS66A Hardware Interface Description

MUX,

ADC

module

1k

10n

ADCx_IN

2.1 Application Interface

66

Table 4: Signal description

Function Signal name IO Signal form and level Comment

Page 28 of 123

GPIO
interface

GPIO1...22 I/O V

max = 0.45V at I = 2mA

OL

V

nom = 0.1V at I = 100µA

OL

V

min = 1.30V at I = -2mA

OH

V

nom = 1.65V at I = -100µA

OH

V

max = 1.84V

OH

V

max = 0.50V

IL

V

min = 1.30V

IH

V

max = 2.0V

IH

I

= 27.5µA…97.5µA

IHPD

I

= -27.5µA…-97.5µA

ILPU

I

High-Z max

= +-1µA

GPIO2...GPIO5, GPIO7,

GPIO8, GPIO10, GPIO16,

and GPIO20...GPIO22 are

interrupt enabled. They can

be used to for instance wake

up the module (see Section

2.1.11).

GPIO12-14 are not imple-

mented, and only available

as external antenna switch

interface (see Section

2.1.11.1).

GPIO18-21 cannot be con-

figured as DSR0, DCD0,

DTR0, and RING0, because

this functionality is not yet

implemented.

No external pull-up / pull-

down resistors allowed for

GPIO9 and GPIO10.

There is a 2.2k decoupling

resistor between GPIO17

and JTAG_WD_DISABLE.

Heartbeat HEART_

BEAT

ADC
interface

ADC1_IN,
ADC2_IN,
ADC4_IN,
ADC5_IN

O

H --> L with 0.1Hz frequency, i.e.,
5s (+/- 1,5s) each for high and low

I Full specification compliance range

V

>=0.10V

Imin

V

<=1.70V

Imax

R

10M

I

Resolution: 14 Bit
Accuracy: <+-2mV
ADC conversion time t (max) = 550µs
at 4.8MHz sample clock

Test points recommended at

GPIO1, required at GPIO2,

GPIO9, and GPIO10.

If unused keep lines open.

However, GPIO7 and

GPIO17 must be low during

module startup until the

module has been secured in

factory.

Heartbeat signal, e.g., for

external watchdog.

If unused keep line open.

Prepared for general pur-

pose and antenna diagnos-

tic use.

 ALAS66A_HID_v01.000b 2019-02-06

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Cinterion® ALAS66A Hardware Interface Description

2.1 Application Interface

66

Table 4: Signal description

Function Signal name IO Signal form and level Comment

PCIe PCIE_RX_N I According to PCI Express Specifica-

PCIE_RX_P
PCIE_TX_N O
PCIE_TX_P
PCIE_CLK_N I/O
PCIE_CLK_P

tion, Revision 2.0/2.1 (one lane, 5
GBit/s)

Page 29 of 123

2

I

C inter-

face

JTAG inter­face

PCIE_-

IO V

CLK_REQ
PCIE_HOST_

O

RST
PCIE_HOST_

I

WAKE

I2CDAT1

I/O VILmax = 0.50V

I2CDAT2
I2CCLK1

O

I2CCLK2

JTAG_SRST I V
JTAG_TCK
JTAG_TDI
JTAG_TMS
JTAG_TRST
JTAG_TDO O

JTAG_WD_

IV

DISABLE

max = 0.45V at I = 2mA

OL

V

nom = 0.1V at I = 100µA

OL

V

min = 1.30V at I = -2mA

OH

V

nom = 1.65V at I = -100µA

OH

V

max = 1.84V

OH

V

max = 0.50V

IL

V

min = 1.30V

IH

V

max = 2.0V

IH

I

= 27.5µA…97.5µA

IHPD

I

= -27.5µA…-97.5µA

ILPU

I

High-Z max

V
V

V
V
I

ILPU

V
V
V
V

V
V
V
I

IHPD

I

ILPU

I

High-Z max

V
V

= +-1µA

min = 1.30V

IH

max = 2.0V

IH

max = 0.3V at I = 3mA

OL

max = 1.84V

OH

= -27.5µA…-97.5µA

max = 0.45V at I = 2mA

OL

nom = 0.1V at I = 100µA

OL

min = 1.30V at I = -2mA

OH

nom = 1.65V at I = -100µA

OH

max = 1.84V

OH

max = 0.50V

IL

min = 1.30V

IH

max = 2.0V

IH

= 27.5µA…97.5µA

= -27.5µA…-97.5µA

= +-1µA

max = 0.3V at -100µA

IL

min = 1.50V at 100µA

IH

max = 2.0V

IH

Additional PCIe control sig-

nals

Open Drain Output (internal

pull up)

External pull up resistors

required.

Maximum load 510Ohm.

Debug interface.

Test point recommended for

all JTAG lines.

High during reset and start-

up does disable the watch-

dog timer. (Jumper to VEXT)

There is a 2.2k decoupling

resistor between JTAG_

WD_DISABLE and GPIO17.

JTAG_
PS_HOLD

IV

min = 1.65V at 680µA

IH

V

max = 0.20V at 680µA

IL

High holds the power supply

during debugging

(Jumper to VEXT)
V

max = 1.84V

OH

V

min = 1.30V at 150µA

OH

max = 0.5V at -200µA

V

OL

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Cinterion® ALAS66A Hardware Interface Description

2.1 Application Interface

66

Table 4: Signal description

Function Signal name IO Signal form and level Comment

Page 30 of 123

eMMC
interface

1.8V
eMMC

2.95V
eMMC

EMMC_

IV

DETECT

EMMC_PWR O V

EMMC_CLK O V
EMMC_CMD O
EMMC_D[0...7]I/O

EMMC_CLK O V
EMMC_CMD O
EMMC_D[0...7]I/O

max = 0.45V at I = 2mA

OL

V

nom = 0.1V at I = 100µA

OL

V

min = 1.30V at I = -2mA

OH

V

nom = 1.65V at I = -100µA

OH

V

max = 1.84V

OH

V

max = 0.50V

IL

V

min = 1.30V

IH

V

max = 2.0V

IH

I

= 27.5µA…97.5µA

IHPD

I

= -27.5µA…-97.5µA

ILPU

I

High-Z max

I

OUT (max)

V
V

V
V
V
I

High-Z max

V
V
V
V
V
I

High-Z max

= +-1µA

OUT (nom)

= 2.95V / 1.8V

= 150mA

max = 0.45V at rated drive strength

OL

min = 1.40V at rated drive strength

OH

max = 1.84V

OH

max = 0.58V at rated drive strength

IL

min = 1.27V at rated drive strength

IH

max = 2.0V

IH

= +-5µA

max = 0.36V at rated drive strength

OL

min = 2.05V at rated drive strength

OH

max = 2.91V

OH

max = 0.68V at rated drive strength

IL

min = 1.82V at rated drive strength

IH

max = 3.05V

IH

= +-10µA

eMMC

 ALAS66A_HID_v01.000b 2019-02-06

Confidential / Preliminary