Gemalto M2M ALAS5V W User Manual

Download

Cinterion® ALAS5V

Hardware Interface Description Version: 00.030a

DocId: ALAS5V_HID_v00.030a

 GEMALTO.COM/M2M

Cinterion® ALAS5V Hardware Interface Description

Page 2 of 124

Document Name: Version:

Date: DocId: Status

Cinterion® ALAS5V Hardware Interface Description

00.030a 2019-03-20 ALAS5V_HID_v00.030a Confidential / Preliminary

GENERAL NOTE

THE USE OF THE PRODUCT INCLUDING THE SOFTWARE AND DOCUMENTATION (THE "PRODUCT") IS SUBJECT TO THE RELEASE NOTE PROVIDED TOGETHER WITH PRODUCT. IN ANY EVENT THE PROVISIONS OF THE RELEASE NOTE SHALL PREVAIL. THIS DOCUMENT CONTAINS INFORMATION ON GEMALTO M2M PRODUCTS. THE SPECIFICATIONS IN THIS DOCUMENT ARE SUBJECT TO CHANGE AT GEMALTO M2M'S DISCRETION. GEMALTO M2M GMBH GRANTS A NONEXCLUSIVE RIGHT TO USE THE PRODUCT. THE RECIPIENT SHALL NOT TRANSFER, COPY, MODIFY, TRANSLATE, REVERSE ENGINEER, CREATE DERIVATIVE WORKS; DISASSEMBLE OR DECOMPILE THE PRODUCT OR OTHERWISE USE THE PRODUCT EXCEPT AS SPECIFICALLY AUTHORIZED. THE PRODUCT AND THIS DOCUMENT ARE PROVIDED ON AN "AS IS" BASIS ONLY AND MAY CONTAIN DEFICIENCIES OR INADEQUACIES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, GEMALTO M2M GMBH DISCLAIMS ALL WARRANTIES AND LIABILITIES. THE RECIPIENT UNDERTAKES FOR AN UNLIMITED PERIOD OF TIME TO OBSERVE SECRECY REGARDING ANY INFORMATION AND DATA PROVIDED TO HIM IN THE CONTEXT OF THE DELIVERY OF THE PRODUCT. THIS GENERAL NOTE SHALL BE GOVERNED AND CONSTRUED ACCORDING TO GERMAN LAW.

Transmittal, reproduction, dissemination and/or editing of this document as well as utilization of its contents and communication thereof to others without ex press autho rization are prohib ited. Offenders will be held liable for payment of damages. All rights created by patent grant or registration of a utility model or design patent are reserved.

Trademark Notice

Gemalto, the Gemalto logo, are trademarks and service marks of Gemalto and are registered in certain countries. Microsoft and Win dows are e ither regis tered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. All other register ed trademarks or trademarks mention ed in this document are property of their respective owners.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

124

Page 3 of 124

Contents

1 Introduction.................................................................................................................8

1.1 Product Variants ................................................................................................8

1.2 Key Features at a Glance..................................................................................9

1.2.1 Supported Frequency Bands.............................................................. 12

1.2.2 Supported CA Configurations............................................................. 13

1.3 ALAS5V System Overview ..............................................................................15

1.4 Circuit Concept ................................................................................................16

2 Interface Characteristics.......................................................................................... 17

2.1 Application Interface ........................................................................................17

2.1.1 Pad Assignment..................................................................................17

2.1.2 Signal Properties.................................................................................21

2.1.2.1 Absolute Maximum Ratings ................................................29

2.1.3 USB Interface......................................................................................30

2.1.4 Serial Interface ASC0 ......................................................................... 31

2.1.5 Serial Interface ASC1 ......................................................................... 32

2.1.6 Inter-Integrated Circuit Interface......................................................... 33

2.1.7 UICC/SIM/USIM Interface...................................................................34

2.1.8 Enhanced ESD Protection for SIM Interfaces.....................................36

2.1.9 Digital Audio Interface.........................................................................37

2.1.9.1 Pulse Code Modulation Interface (PCM).............................37

2.1.9.2 Inter-IC Sound Interface......................................................38

2.1.10 Analog-to-Digital Converter (ADC)......................................................39

2.1.11 RTC Backup........................................................................................39

2.1.12 GPIO Interface....................................................................................39

2.1.13 Control Signals....................................................................................40

2.1.13.1 PWR_IND Signal.................................................................40

2.1.13.2 Remote Wakeup..................................................................41

2.1.13.3 Firmware Swap...................................................................41

2.1.14 JTAG Interface....................................................................................41

2.1.15 eMMC Interface ..................................................................................42

2.1.15.1 eMMC Power Supply .......................................... ........... .....42

2.2 GSM/UMTS/LTE Antenna Interface.................................................................43

2.2.1 Antenna Interface Specifications ........................................................44

2.2.2 Antenna Installation ............................................................................49

2.2.3 RF Line Routing Design......................................................................50

2.2.3.1 Line Arrangement Instructions ............................................50

2.2.3.2 Routing Examples...............................................................52

2.2.4 RF Antenna Diagnostic.......................................................................53

2.3 GNSS Antenna Interface .................................................................................56

2.3.1 GNSS Antenna Diagnostic..................................................................57

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Contents

124

Page 4 of 124

2.4 Sample Application..........................................................................................58

2.4.1 Prevent Back Powering.......................................................................60

2.4.2 Sample Level Conversion Circuit........................................................61

2.4.3 Sample Circuit for Antenna Detection.................................................62

3 GNSS Interface..........................................................................................................65

3.1 GNSS Interface Characteristics.......................................................................66

4 Operating Characteristics........................................................................................68

4.1 Operating Modes .............................................................................................68

4.2 Power Up/Power Down Scenarios...................................................................69

4.2.1 Turn on ALAS5V.................................................................................69

4.2.2 Signal States after First Startup..........................................................70

4.2.3 Turn off or Restart ALAS5V................................................................73

4.2.3.1 Switch off ALAS5V Using AT Shutdown Command ............ 73

4.2.3.2 Restart ALAS5V Using AT Command ................................. 74

4.2.3.3 Turn off ALAS5V Using IGT Line......................................... 75

4.2.3.4 Turn off or Restart ALAS5V in Case of Emergency ............ 76

4.2.3.5 Overall Shutdown Sequence...............................................77

4.2.4 Automatic Shutdown...........................................................................78

4.2.4.1 Thermal Shutdown..............................................................79

4.2.4.2 Deferred Shutdown at Extreme Temperature Conditions.... 80

4.2.4.3 Undervoltage Shutdown......................................................81

4.2.4.4 Overvoltage Shutdown........................................................81

4.3 Power Saving...................................................................................................82

4.3.1 Power Saving while Attached to GSM Networks................................82

4.3.2 Power Saving while Attached to WCDMA Networks ..........................84

4.3.3 Power Saving while Attached to LTE Networks..................................85

4.4 Power Supply...................................................................................................86

4.4.1 Power Supply Ratings.........................................................................87

4.4.2 Minimizing Power Losses ...................................................................94

4.4.3 Monitoring Power Supply by AT Command........................................94

4.5 Operating Temperatures..................................................................................95

4.6 Electrostatic Discharge....................................................................................96

4.7 Reliability Characteristics.................................................................................96

5 Mechanical Dimensions and Mounting...................................................................97

5.1 Mechanical Dimensions of ALAS5V ................................................................ 97

5.2 Mounting ALAS5V onto the Application Platform.............................................99

5.2.1 SMT PCB Assembly ........................................................................... 99

5.2.1.1 Land Pattern and Stencil.....................................................99

5.2.1.2 Board Level Characterization............................................100

5.2.2 Moisture Sensitivity Level .................................................................101

5.2.3 Soldering Conditions and Temperature............................................ 101

5.2.3.1 Reflow Profile....................................................................101

5.2.3.2 Maximum Temperature and Duration................................ 102

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Contents

124

Page 5 of 124

5.2.4 Durability and Mechanical Handling..................................................103

5.2.4.1 Storage Conditions............................................................103

5.2.4.2 Processing Life..................................................................103

5.2.4.3 Baking...............................................................................104

5.2.4.4 Electrostatic Discharge ..................................................... 104

5.3 Packaging......................................................................................................105

5.3.1 Trays.................................................................................................105

5.3.2 Shipping Materials ............................................................................105

5.3.2.1 Moisture Barrier Bag.........................................................105

5.3.2.2 Transportation Boxes........................................................107

6 Regulatory and Type Approval Information......................................................... 108

6.1 Directives and Standards...............................................................................108

6.2 SAR requirements specific to portable mobiles............................................. 111

6.3 Reference Equipment for Type Approval.......................................................112

6.4 Compliance with FCC and ISED Rules and Regulations...............................113

7 Document Information............................................................................................116

7.1 Revision History.............................................................................................116

7.2 Related Documents .......................................................................................118

7.3 Terms and Abbreviations...............................................................................118

7.4 Safety Precaution Notes................................................................................121

8 Appendix..................................................................................................................122

8.1 List of Parts and Accessories.........................................................................122

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Tables

124

Page 6 of 124

Tables

Table 1: Supported frequency bands for each product variant.................................... 12

Table 2: Supported CA configurations......................................................................... 13

Table 3: Overview: Pad assignments........................................................................... 18

Table 4: Signal description........................................................................................... 21

Table 5: Absolute maximum ratings (TBD.)................................................................. 29

Table 6: DCE-DTE wiring of ASC0 .............................................................................. 32

Table 7: Signals of the SIM interface (SMT application interface)............................... 34

Table 8: Overview of PCM pin functions...................................................................... 37

Table 9: Overview of I

Table 10: GPIO lines and possible alternative assignment............................................ 39

Table 11: Remote wakeup lines..................................................................................... 41

Table 12: Return loss in the active band........................................................................ 43

Table 13: RF Antenna interface GSM/UMTS/LTE (at operating temperature range).... 44

Table 14: Possible GPIOx signal states if used for antenna diagnosis.......................... 54

Table 15: Assured antenna diagnostic states................................................................ 55

Table 16: GSM/UMTS/LTE antenna diagnostic decision threshold............................... 55

Table 17: Sample ranges of the GNSS antenna diagnostic measurements and

their possible meaning................................................................................... 57

Table 18: Antenna detection reference circuit - parts list............................................... 64

Table 19: GNSS properties............................................................................................ 66

Table 20: Power supply for active GNSS antenna......................................................... 67

Table 21: Overview of operating modes ........................................................................ 68

Table 22: Signal states................................................................................................... 70

Table 23: Board temperature warning and switch off level............................................ 79

Table 24: Voltage supply ratings.................................................................................... 87

Table 25: Current consumption ratings.......................................................................... 88

Table 26: Board temperature......................................................................................... 95

Table 27: Electrostatic values........................................................................................ 96

Table 28: Reflow temperature recommendations........................................................ 102

Table 29: Storage conditions ....................................................................................... 103

Table 30: Directives ..................................................................................................... 108

Table 31: Standards of North American type approval................................................ 108

Table 32: Standards of European type approval.......................................................... 109

Table 33: Requirements of quality ............................................................................... 109

Table 34: Standards of the Ministry of Information Industry of the

People’s Republic of China.......................................................................... 110

Table 35: Toxic or hazardous substances or elements with defined concentration

limits............................................................................................................. 110

Table 36: Antenna gain limits for FCC for ALAS5V-W (TBD.)..................................... 113

Table 37: Antenna gain limits for FCC and ISED for ALAS5V-US (TBD.)................... 114

Table 38: List of parts and accessories........................................................................ 122

Table 39: Molex sales contacts (subject to change).................................................... 123

Table 40: Hirose sales contacts (subject to change)................................................... 123

S pin functions......................................................................... 38

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Figures

124

Page 7 of 124

Figures

Figure 1: ALAS5V system overview.............................................................................. 15

Figure 2: ALAS5V block diagram.................................................................................. 16

Figure 3: ALAS5V bottom view: Pad assignments........................................................ 19

Figure 4: ALAS5V top view: Pad assignments.............................................................. 20

Figure 5: USB circuit ..................................................................................................... 30

Figure 6: Serial interface ASC0..................................................................................... 31

Figure 7: Serial interface ASC1..................................................................................... 32

Figure 8: I

Figure 9: First UICC/SIM/USIM interface...................................................................... 35

Figure 10: Second UICC/SIM/USIM interface................................................................. 35

Figure 11: SIM interfaces - enhanced ESD protection.................................................... 36

Figure 12: PCM timing short frame (master, 4096KHz, 16kHz sample rate).................. 37

Figure 13: I

Figure 14: PWR_IND signal............................................................................................ 40

Figure 15: eMMC power supply ...................................................................................... 42

Figure 16: Antenna pads (top view)................................................................................ 49

Figure 17: Embedded Stripline line arrangement............................................................ 50

Figure 18: Micro-Stripline line arrangement samples...................................................... 51

Figure 19: Routing to application‘s RF connector ........................................................... 52

Figure 20: Resistor measurement used for antenna detection....................................... 53

Figure 21: Basic circuit for antenna detection................................................................. 54

Figure 22: Supply voltage for active GNSS antenna....................................................... 56

Figure 23: ESD protection for passive GNSS antenna................................................... 57

Figure 24: ALAS5V sample application........................................................................... 59

Figure 25: Sample level conversion circuits.................................................................... 61

Figure 26: Antenna detection circuit sample - Overview................................................. 62

Figure 27: Antenna detection circuit sample - Schematic............................................... 63

Figure 28: Power-on with IGT ......................................................................................... 69

Figure 29: Signal states during turn-off procedure.......................................................... 74

Figure 30: Timing of IGT if used as ON/OFF switch ....................................................... 75

Figure 31: Shutdown by EMERG_OFF signal................................................................. 76

Figure 32: Restart by EMERG_OFF signal..................................................................... 76

Figure 33: Overall shutdown sequence........................................................................... 77

Figure 34: Power saving and paging in GSM networks .................................................. 83

Figure 35: Power saving and paging in WCDMA networks............................................. 84

Figure 36: Power saving and paging in LTE networks.................................................... 85

Figure 37: Decoupling capacitor(s) for BATT+................................................................ 86

Figure 38: Power supply limits during transmit burst....................................................... 94

Figure 39: Board and ambient temperature differences.................................................. 95

Figure 40: ALAS5V – top and bottom view ..................................................................... 97

Figure 41: Dimensions of ALAS5V (all dimensions in mm)............................................. 98

Figure 42: Land pattern (top layer).................................................................................. 99

Figure 43: Recommended design for 110 micron thick stencil (top layer).................... 100

Figure 44: Reflow Profile............................................................................................... 101

Figure 45: Shipping tray dimensions............................................................................. 105

Figure 46: Moisture Sensitivity Label ............................................................................ 106

Figure 47: Humidity Indicator Card - HIC...................................................................... 107

Figure 48: Reference equipment for type approval....................................................... 112

C interface connected to VEXT ................................................................... 33

S timing (master mode) ............................................................................... 38

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

1 Introduction

Page 8 of 124

1 Introduction

This document1 describes the hardware of the Cinterion® ALAS5V module. It helps you quickly retrieve interface specifications, electrical and mechanical details and information on the requirements to be considered for integrating further components.

1.1 Product Variants

This document applies to the following Gemalto M2M modules:

•Cinterion

interion

•C

interion

•C

interion

re necessary a note is made to differentiate between the various product variants and re-

Whe

ALAS5V-W

ALAS5V-CN

ALAS5V-E

ALAS5V-US

leases.

1. The document is effective only if listed in the appropriate Release Notes as part of the technical documentation delivered with your Gemalto M2M product.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

1.2 Key Features at a Glance

Page 9 of 124

1.2 Key Features at a Glance

Feature Implementation

General Frequency bands Note: Not all of the frequency bands (and 3GPP technologie s) mentio ned

throughout this document are supported by every ant. Please refer to Section 1.2.1 for an overview of the frequency bands supported by each

GSM class Small MS

ALAS5V product variant.

ALAS5V product vari-

Output power (according to Release 99)

Output power (according to Release 4)

Output power (according to Release 8)

Power supply 3.3V < Operating temperature

(board temperature)

Physical Dimensions: 40mm x 36mm x 3mm

RoHS All hardware components fully compliant with EU RoHS Directive LTE features

GSM/GPRS/UMTS: Class 4 (+33dBm ±2dB) for EGSM850 and EGSM900 Class 1 (+30dBm ±2dB) for GSM1800 and GSM1900 Class E2 (+27dBm ± 3dB) for GSM 850 8-PSK and GSM 900 8-PSK Class E2 (+26dBm +3 /-4dB) for GSM 1800 8-PSK and GSM 1900 8-PSK Class 3 (+24dBm +1/-3dB) for all supported WCDMA FDD bands

TD-SCDMA: Class 2 (+24dBm +1/-3dB) for TD-SCDMA 1900 (Bd39) and TD-SCDMA 2000 (Bd34)

LTE (FDD): Class 3 (+23dBm ±2dB) for all supported LTE FDD bands

LTE (TDD): Class 3 (+23dBm ±2dB) for all supported LTE TDD bands

Normal operation: -30°C to +85°C Restricted operation: -40°C to +95°C

Weight: 8.8g

BATT+

< 4.2V

3GPP Release 13 Down- and Uplink carrier aggregation (CA) to increase bandwidth, and

thereby increase bitrate:

• Maximum aggregated bandwidth: 80MHz

• Maximum number of component carriers: 2

• Inter-band FDD

• Intra-band FDD, TDD, contiguous, non-contiguous

• Supported inter- and intra-band CA configurations: See Section 1.2.2 CAT 6 supported

DL 300Mbps, UL 50Mbps

2x2 MIMO in DL direction HSPA features 3GPP Release 8 UE CAT. 14, 24

DC-HSPA+ – DL 42Mbps

HSUPA – UL 5.76Mbps

Compressed mode (CM) supported according to 3GPP TS25.212

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

1.2 Key Features at a Glance

Feature Implementation

UMTS features 3GPP Release 8 PS data rate – 384 kbps DL / 384 kbps UL

TD-SCDMA features 3GPP Release 4 2.8 Mbps DL / 2.2Mbps UL GSM / GPRS / EGPRS features Data transfer GPRS:

• Multislot Class 12

• Mobile Station Class B

• Coding Scheme 1 – 4

EGPRS:

• Multislot Class 12

• EDGE E2 power class for 8 PSK

• Downlink coding schemes – CS 1-4, MCS 1-9

• Uplink coding schemes – CS 1-4, MCS 1-9

• SRB loopback and test mode B

• 8-bit, 11-bit RACH

• 1 phase/2 phase access procedures

• Link adaptation and IR

• NACC, extended UL TBF

• Mobile Station Class B

Page 10 of 124

SMS Point-to-point MT and MO, Cell broadcast,

Text and PDU mode

Software AT commands Hayes, 3GPP TS 27.007 and 27.005, and proprietary Gemalto M2M com-

mands SIM Application Toolkit SAT Release 99, letter classes b, c, e with BIP and RunAT support Firmware update Firmware update supported

GNSS Features

Protocol NMEA Modes Standalone GNSS (GPS, GLONASS, Beidou, Galileo)

Integrated gpsOne 9HT support (GPS, GLONASS, Beidou, Galileo)

QZSS and SBAS support General Power saving modes

DC feed bridge and control of power supply for active antenna via GPIO

Interfaces Module interface Surface mount device with solderable connection pads (SMT application

interface).

Land grid array (LGA) technology ensures high solder joint reliability and

provides the possibility to use an optional module mounting socket.

For more information on how to integrate SMT modules see also [3]. This

application note comprises chapters on module mounting and app lication

layout issues as well as on additional SMT application development equip-

ment.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Page 11 of 124

1.2 Key Features at a Glance

Feature Implementation

Antenna 50. GSM/UMTS/LTE main antenna, LTE Diversity/MIMO antenna,

(active/passive) GNSS antenna USB USB 2.0 High Speed (480Mbit/s) device interface or

USB 3.0 Super Speed (5Gbit/s) device interface Serial interface ASC0:

• 8-wire (plus GND line) interface unbalanced, asynchronous

• Fixed baud rates from 115,200 to 921,600bps

• Supports RTS0/CTS0 hardware flow control

Linux controlled only:

ASC1:

• 4-wire, unbalanced asynchronous interface

• Fixed baud rates: 115,200bps to 921,60bps

• Supports RTS1/CTS1 hardware flow control

ASC2:

2-wire, unbalanced asynchronous interface at RXD2 and T XD2 lines used

for tracing and debugging purposes (optional) UICC interface 2 UICC interfaces (switchable)

Supported chip cards: UICC/SIM/USIM 2.85V, 1.8V

C interface 1 I2C interface

Audio 2 digital interfaces (I

S) - first DAI reserved for future use Power on/off, Reset Power on/off Switch-on by hardware signal IGT

Switch-off by AT command (AT^SMSO) or IGT (option)

Automatic switch-off in case of critical temperature or voltage conditions Reset Orderly shutdown and reset by AT command Emergency-off Emergency-off by hardware signal EMERG_OFF Special Features Antenna SAIC (Single Antenna Interference Cancellation) / DARP (Downlink

Advanced Receiver Performance)

Rx Diversity (receiver type 3i - 64-QAM) / MIMO GPIO 15 I/O pins of the application interface programmable as GPIO.

GPIO1 can be configured as dead reckoning synchronization signal.

Programming can be done via AT commands. Emergency call handling

(not for -US variant)

EU eCall 3GPP Release 10 compliant (modem)

ERA compliant (modem and GNSS) ADC inputs Analog-to-Digital Converter with four unbalanced analog inputs for (exter-

nal) antenna diagnosis JTAG JTAG interface for debug purposes eMMC Linux controlled:

Embedded Multi-Media Card interface PCIe Linux controlled:

PCIe interface Evaluation kit Evaluation module ALAS5V module soldered onto a dedicated PCB.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

1.2 Key Features at a Glance

Page 12 of 124

1.2.1 Supported Frequency Bands

The following table lists the supported frequency bands for each of the ALAS5V product variants mentioned in Section 1.1. Supported CA configurations can be found in Section 1.2.2.

Table 1: Supported frequency bands for each product variant

Band ALAS5V-W ALAS5V-CN ALAS5V-E ALAS5V-US GSM/GPRS/EDGE

850MHz x x 900MHz 1800MHz 1900MHz

UMTS/HSPA

Bd.I (2100MHz) x x x Bd.II (1900MHz) Bd.III (1800MHz) Bd.IV (1700MHz) Bd.V (850MHz) Bd.VI (850MHz) Bd.VIII (900MHz) Bd.XIX (850MHz)

TD-SCDMA

Bd.34 (2000MHz) x Bd.39 (1900MHz)

LTE-FDD

Bd.1 (2100MHz) x x x

x x x x x x x x x x

x x x

x x x x x x x

Bd.2 (1900MHz) Bd.3 (1800MHz) Bd.4 (1700MHz) Bd.5 (850MHz) Bd.7 (2600MHz) Bd.8 (900MHz) Bd.12 (700MHz) Bd.18 (850MHz) Bd.19 (850MHz) Bd.20 (800MHz) Bd.26 (850MHz) Bd.28 (700MHz) Bd.66 (1700MHz)

 ALAS5V_HID_v00.030a 2019-03-20

x x x

x x x x x x x x

x x x x x x x

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Page 13 of 124

1.2 Key Features at a Glance

Table 1: Supported frequency bands for each product variant

Band ALAS5V-W ALAS5V-CN ALAS5V-E ALAS5V-US LTE-TDD

Bd.38 (2600MHz) x x Bd.39 (1900MHz) Bd.40 (2300MHz) Bd.41 (2600MHz)

1. Note: Out of the 3GPP specified frequency range for LTE Band 41, only that part which is used in China and apan (2545MHz to 2655MHz) is supported by ALAS5V. For the US market LTE Band 41 is disabled by

software.

x x x x x x

1.2.2 Supported CA Configurations

The following table lists the supported CA configurations (aka supported band combinations) for each of the ALAS5V product variants mentioned in Section 1.1.

Table 2: Supported CA configurations

Downlink CA Bandwidth

combination set

Intra-band continuous

CA_1C 0, 1 E, W, CN CA_2C 0 US CA_3C 0 E, W, CN CA_5B 0, 1 US, W CA_7B 0 E, US, W, CN CA_7C 0, 1, 2 E, US, W, CN CA_8B 0 W CA_12B 0 US CA_38C 0 W, CN CA_39C 0 W, CN CA_40C 0, 1 W, CN CA_41C 0, 1, 2, 3 CN CA_66B 0 US CA_66C 0 US

Intra-band non-continuous

CA_2A-2A 0 US CA_3A-3A 0, 1, 2 E, W, CN CA_4A-4A 0, 1 US CA_7A-7A 0, 1, 2, 3 E, US, W, CN CA_40A-40A 0, 1 W, CN CA_41A-41A 0, 1 CN CA_66A-66A 0 US CA_66A-66B 0 US

Product variant (ALAS5V-...)

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

1.2 Key Features at a Glance

Table 2: Supported CA configurations

Downlink CA Bandwidth

combination set

Inter-band (two bands)

CA_1A-5A 0, 1 W CA_1A-8A 0, 1, 2 E, W, CN CA_1A-18A 0, 1 W CA_1A-19A 0 W CA_1A-20A 0 E, W CA_1A-26A 0, 1 W CA_1A-28A 0, 1 E, W CA_2A-5A 0, 1 US CA_2A-5B 0 US CA_2A-12A 0, 1, 2 US CA_2A-12B 0 US CA_2A-28A 0 US CA_2A-29A 0, 1, 2 US CA_3A-5A 0, 1, 2, 3,4 W CA_3A-8A 0, 1, 2, 3 E, W, CN CA_3A-19A 0 W CA_3A-20A 0, 1 E, W CA_3A-26A 0, 1 W CA_3A-28A 0, 1 E, W CA_3C-8A 0 CN CA_4A-5A 0, 1 US CA_4A-12A 0, 1, 2, 3, 4, 5 US CA_4A-12B 0 US CA_4A-28A 0 US CA_4A-29A 0, 1, 2 US CA_5A-7A 0, 1 US, W CA_5A-30A 0 US CA_5A-40A 0, 1 W CA_5B-30A 0 US CA_5A-66A 0 US CA_5A-66B 0 US CA_5B-66A 0 US CA_7A-8A 0, 1, 2 E, W, CN CA_7A-12A 0 US CA_7A-20A 0, 1 E, W CA_7A-28A 0, 1 E, US, W CA_7B-28A 0 E, US, W CA_8A-40A 0, 1 W, CN CA_8A-41A 0, 1 CN CA_12A-30A 0 US CA_12A-66A 0, 1, 2, 3, 4, 5 US

Product variant (ALAS5V-...)

Page 14 of 124

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Power

Supply

IGT

EMERG_OFF

Application Interfaces

ALAS5

Application

VEXT

PWR_IND

GNSS

Application

UICC

SIM

Card

GSM/UMTS/LTE

GPIO

Antenna-

diagnostic

2 x

ADC

I2C

USB

2.0/3.0

I2C

Digital

Audio

GPIO

PCM/I2S

USB

Antenna-

diagnostic

ANT_MAIN ANT_DRX_MIMOGNSS

GPIO

Power

Supply

eMMC

eMMC Interface

Power Supply

PCIe

Serial Interface

ASC0

Serial Interface

ASC1

SIM

Card

1.3 ALAS5V System Overview

Table 2: Supported CA configurations

Downlink CA Bandwidth

combination set

CA_20A-38A 0 W CA_20A-40A 0 W CA_28A-40A 0 W CA_29A-66A 0 US

Product variant (ALAS5V-...)

1.3 ALAS5V System Overview

Page 15 of 124

Figure 1: ALAS5V system overview

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

LPDDR2SDRAM

2GBit

NANDFlash

4GBit

38.4MHz

PowerManagement

Basebandcontroller

RFpart

Clocks

LDO

PMU

LB/MB /HB

GSM

Filter

Switches

QLINK RFFE

EBI 1

EBI 2

GRFC

BATT+

LGAPads

IGT

EMERGO FF

PWR_IND

USB 3.0 USB 2.0

ASC0 ASC1

I2C

2xPCM/I2S

I2S_MCLK

eMMC 2xSIM

GPIO PCIe

4xADC

ADC

BATT+ _RF

GND

ALAS5

ANT_MAIN

ANT_DRX_

MIMO

ANT_GNSS

GNSS_EN

ANT_GNSS_DC

Page 16 of 124

1.4 Circuit Concept

Figure 2 shows a block diagram of the ALAS5V module and illustrates the major functional

components: Baseband block:

• GSM/UMTS/LTE controller/transceiver/power supply

• NAND/LPDDR2 memory devices

• Application interface (SMT with connecting pads) RF section:

• RF transceiver

• RF power amplifier/frontend

• RF filter

• GNSS receiver/Front end

• Antenna pad

 ALAS5V_HID_v00.030a 2019-03-20

Figure 2: ALAS5V block diagram

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2 Interface Characteristics

Page 17 of 124

2 Interface Characteristics

ALAS5V is equipped with an SMT application interface that connects to the external application. The SMT application interface incorporates the various application interfaces as well as the RF antenna interface.

2.1 Application Interface

2.1.1 Pad Assignment

The SMT application interface on the ALAS5V provides connecting pads to integrate the module into external applications. Table 3 lists the pads’ assignments. Figure 3 (bottom view) and

Figure 4 (top view) show the connecting pads’ numbering plan.

Please note that a number of connecting pads are marked as reserved for future use (rfu) and further qualified as either (<name>), (dnu), (GND) or (nc):

• Pads marked as “rfu“ and q ualified as “<name>“ (signal name) may be soldered and could be connected to an external application compliant to the signals’ electrical characteristics as described in Table 4.

• Pads marked "rfu" and qualified as "dnu" (do not use) may be soldered but should not be connected to an external application.

• Pads marked "rfu" and qualified as "GND" (ground) are assigned to ground with ALAS5V modules, but may have different assignments with future Gemalto M2M p roducts using the same pad layout.

• Pads marked "rfu" and qualified as "nc" (not connected) are internally not connected with ALAS5V modules, but may be soldered and arbitrarily be connected to external ground.

Also note that some pads are marked with a circle ( ). These pads have a round shape for improved impedance control.

Gemalto strongly recommends to solder all connecting pads for mechanical stability and heat dissipation.

Also, Gemalto strongly recommends to provide test points for certain signal lines to and from the module while developing SMT applications – for debug and/or test purposes during the manufacturing process. In this way it is possible to detect soldering problems. Please refer to

[3] for more information on test points and how to implement them. The signal lines for which

test points should be provided for are marked as “Test point required” or “Test point recommended“ in Section 2.1.2: Table 4 describing signal characteristics.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Page 18 of 124

2.1 Application Interface

Table 3: Overview: Pad assignments

Pad No. Signal Name Pad No. Signal Name Pad No. Signal Name

A2 GND E15 rfu (dnu) M5 GND A5 GND E16 rfu (dnu) M6 GND A6 GND E17 rfu (dnu) M7 GPIO17 A7 rfu (dnu) E18 VEXT M8 JTAG_WD_DISABLE A8 GND E19 rfu (dnu) M9 I2CDAT1 A9 GND E20 BATT+ M10 I2CCLK1 A10 GND F2 ANT_DRX_MIMO M11 rfu (d nu ) A11 rfu (dnu) F3 GND M12 rfu (dnu) A12 GND F4 GND M13 EMMC_D6 A13 GND F5 GND M14 EMMC_D1 A14 GND F6 rfu (dnu) M15 GPIO22 A15 ANT_GNSS F7 rfu (dnu) M16 USB_DP A16 GND F8 rfu (nc) M17 USB_DN A17 ANT_GNSS_DC F14 rfu (nc) M18 CCCLK2 A20 GND F15 GND M19 CCCLK1 B4 rfu (dnu) B5 B6 B7 GND F19 DTR0 N5 GND B8 B9 GND G2 GND N7 FSC2 B10 B11 B12 GND G5 GND N10 BCLK2 B13 B14 B15 GND G17 GND N13 EMMC_D5 B16 GND G18 DCD0 / Download N14 EMMC_D2 B17 GND G19 CTS0 N15 EMMC_D0 B18 rfu (dnu) G20 RTS0 N16 GND C2 GND H2 GND N17 GND C4 GND H3 GND N18 CCIN2 C5 GND H4 GND N19 CCIN1 C6 GND H5 GND P2 GND C7 GND H6 GND P4 BATT+_RF C8 GND H16 USB_SSTX_P P5 BATT+_RF C9 GND H17 USB_SSTX_N P6 GPIO5 (Interrupt) C10 GND H18 GPIO6 (Interrupt) P7 rfu (DIN1) C11 GND H19 TXD0 P8 rfu (DOUT1) C12 GND H20 rfu (BATT_ID) P9 rfu (BCLK1) C13 GND J2 GND P10 rfu (FSC1) C14 GND J3 GND P11 MCLK C15 GND J4 GND P12 EMMC_D7 C16 GND J5 GND P13 EMMC_CMD C17 GPIO3 (Interrupt) J6 rfu (dnu) P14 EMMC_D3 C18 JTAG_TCK J16 GND P15 EMMC_CLK C20 GND J17 GND P16 PCIE_CLK_P D3 GND J18 CCIO2 P17 PCIE_CLK_N D4 GND J19 CCIO1 P18 VUSB_IN D5 GND J20 RING0 P20 GND D6 GND K2 GND R5 PWR_IND D7 D8 D9 ADC5_IN K5 GND R8 TXD1 D10 D11 D12 GPIO11 K17 USB_SSRX_N R11 PCIE_HOST_RST D13 D14 D15 D16 D17 JTAG_SRST L3 GND R16 GND D18 JTAG_TDO L4 GND R17 GPIO16 (Interrupt) D19 IGT L5 GND T2 GND E2 GND L6 rfu (dnu) T5 rfu (dnu) E3 GND L7 EMMC_DETECT T6 rfu (dnu) E4 GND L8 rfu (nc) T7 FwSwap E5 GND L14 rfu (nc) T8 TXD2 E6 GND L15 EMMC_PWR T9 GPIO15 E7 rfu (dnu) L16 GND T10 RXD2 E8 GPIO1/ DR_SYNC L17 GND T11 GND E9 GPIO7 (Interrupt) L18 CCVCC2 T12 PCIE_RX_P E10 GPIO14 L19 CCRST1 T13 PCIE_RX_N E11 GPIO13 L20 GPIO4 T14 GND E12 GPIO12 M2 GND T15 PCIE_TX_P E13 JTAG_PS_HOLD M3 GND T16 PCIE_TX_N E14 rfu (dnu) M4 GND T17 GND

GND F17 DSR0 N3 GND GND F18 RXD0

GND F20 BATT+ N6 GND GND G3 GND N8 DOUT2

GND G4 GND N9 DIN2 GND G6 rfu (dnu) N11 GND

GND G16 GND N12 EMMC_D4

rfu (dnu) K3 GND R6 RTS1 ADC4_IN K4 GND R7 CTS1

ADC1_IN K6 rfu (dnu) R9 RXD1 ADC2_IN K16 USB_SSRX_P R10 PCIE_HOST_WAKE

GNSS_EN K18 CCRST2 R12 GND JTAG_TMS K19 CCVCC1 R13 GND JTAG_TRST K20 rfu (dnu) R14 PCIE_CLK_REQ JTAG_TDI L2 ANT_MAIN R15 GND

F16 EMERG_OFF

M20 GPIO8 (Interrupt)

N4 GND

T20 GND

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

GND rfu

(dnu)

rfu

(dnu)

FwSwap TXD2 GPIO15 RXD2 GND

PCIE_

RX_P

PCIE_ RX_N

GND

PCIE_

TX_P

PCIE_

TX_N

GND GND

PWR_

IND

RTS1 CTS1 TXD1 RXD1 PCIE_

HOST_

WAKE

PCIE_

HOST_

RST

GND GND PCIE_

CLK_

REQ

GND GND GPIO16

(Interrupt)

GND BATT+_RFBATT+_RFGPIO5

(Inter-

rupt)

rfu

(DIN1)

rfu

(DOUT1)

rfu

(BCLK1)

rfu

(FSC1)

MCLK

EMMC_D7EMMC_

CMD

EMMC_D3EMMC_

CLK

PCIE_CLK_P

PCIE_

CLK_N

VUSB_

GND

GND GND GND GND FSC2 DOUT2 DIN2 BCLK2 GND

EMMC_D4EMMC_

EMMC_D2EMMC_

GND GND CCIN2 CCIN1 GND

GND GND GND GND GND GPIO17 JTAG_

WD_

DISABLE

I2CDAT1 I2CCLK1 rfu

(dnu)

rfu

(dnu)

EMMC_D6EMMC_

GPIO22 USB_DP USB_DN CCCLK2 CCCLK1 GPIO8

(Interrupt)

ANT_ MAIN

GND GND GND rfu

(dnu)

EMMC_

DETECT

rfu

(nc)

rfu

(nc)

EMMC_

PWR

GND GND CCVCC2 CCRST1 GPIO4

GND GND GND GND rfu

(dnu)

USB_

SSRX_P

USB_

SSRX_N

CCRST2 CCVCC1 rfu

(dnu)

GND GND GND GND rfu

(dnu)

GND GND CCIO2 CCIO1 RING0

GND GND GND GND GND

USB_

SSTX_P

USB_

SSTX_N

GPIO6

(Inter-

rupt)

TXD0 rfu

(BATT_

ID)

GND GND GND GND rfu

(dnu)

GND GND DCD0 /

Down-

load

CTS0 RTS0

ANT_ DRX_ MIMO

GND GND GND rfu

(dnu)

rfu

(dnu)

rfu

(nc)

rfu

(nc)

GND EMERG

_OFF

DSR0 RXD0 DTR0 BATT+

GND GND GND GND GND rfu

(dnu)

GPIO1 /

DR_SYNC

GPIO7

(Inter-

rupt)

GPIO14 GPIO13 GPIO12 JTAG_

PS_

HOLD

rfu

(dnu)

rfu

(dnu)

rfu

(dnu)

rfu

(dnu)

VEXT rfu

(dnu)

BATT+

GND GND GND GND rfu

(dnu)

ADC4_IN ADC5_IN ADC1_INADC2_INGPIO11 GNSS_ENJTAG_

TMS

JTAG_

TRST

JTAG_

TDI

JTAG_

SRST

JTAG_

TDO

IGT

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GPIO3

(Interrupt)

JTAG_

TCK

GND

rfu

(dnu)

GND GND GND GND GND GND GND GND GND GND GND GND GND

rfu

(dnu)

GND GND GND

rfu

(dnu)

GND GND GND

rfu

(dnu)

GND GND GND

ANT_

GNSS

GND ANT_

GNSS_

GND

rfu: Reserved for future use (may be connected to external application (nc): Internally not connected (may be arbitrarily connected to external GND)

(dnu): Do not use (should not be connected to external application)

Circle marks round shaped pads designed for improved impedance.

Orange: Keep out areas on external application’s PCB.

Round shaped: No solder pads, should therefore not be soldered. No further tracks on PCB’s first layer.

2.1 Application Interface

Page 19 of 124

 ALAS5V_HID_v00.030a 2019-03-20

Figure 3: ALAS5V bottom view: Pad assignments

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

GND GND

PCIE_

TX_N

PCIE_

TX_P

GND

PCIE_ RX_N

PCIE_

RX_P

GND RXD2 GPIO15 TXD2 FwSwap rfu

(dnu)

rfu

(dnu)

GND

GPIO16

(Interrupt)

GND GND PCIE_

CLK_

REQ

GND GND PCIE_

HOST_

RST

PCIE_

HOST_

WAKE

RXD1 TXD1 CTS1 RTS1 PWR_

IND

GND VUSB_INPCIE_

CLK_N

PCIE_CLK_P

EMMC_

CLK

EMMC_D3EMMC_

CMD

EMMC_

MCLK rfu

(FSC1)

rfu

(BCLK1)

rfu

(DOUT1)

rfu

(DIN1)

GPIO5

(Inter-

rupt)

BATT+_RFBATT+_

GND

GND CCIN1 CCIN2 GND GND

EMMC_D0EMMC_D2EMMC_D5EMMC_

GND BCLK2 DIN2 DOUT2 FSC2 GND GND GND GND

GPIO8

(Interrupt)

CCCLK1 CCCLK2 USB_DN USB_DP GPIO22

EMMC_D1EMMC_

rfu

(dnu)

rfu

(dnu)

I2CCLK1 I2CDAT1 JTAG_

WD_

DISABLE

GPIO17 GND GND GND GND GND

GPIO4 CCRST1 CCVCC2 GND GND EMMC_

PWR

rfu

(nc)

rfu

(nc)

EMMC_

DETECT

rfu

(dnu)

GND GND GND

ANT_ MAIN

rfu

(dnu)

CCVCC1 CCRST2

USB_

SSRX_N

USB_

SSRX_P

rfu

(dnu)

GND GND GND GND

RING0 CCIO1 CCIO2 GND GND rfu

(dnu)

GND GND GND GND

rfu

(BATT_

ID)

TXD0 GPIO6

(Inter-

rupt)

USB_

SSTX_N

USB_

SSTX_P

GND GND GND GND GND

RTS0 CTS0 DCD0 /

Down-

load

GND GND rfu

(dnu)

GND GND GND GND

BATT+ DTR0 RXD0 DSR0 EMERG

_OFF

GND

rfu

(nc)

rfu

(nc)

rfu

(dnu)

rfu

(dnu)

GND GND GND

ANT_ DRX_ MIMO

BATT+ rfu

(dnu)

VEXT rfu

(dnu)

rfu

(dnu)

rfu

(dnu)

rfu

(dnu)

JTAG_

PS_

HOLD

GPIO12 GPIO13 GPIO14 GPIO7

(Inter-

rupt)

GPIO1 /

DR_SYNC

rfu

(dnu)

GND GND GND GND GND

IGT JTAG_

TDO

JTAG_

SRST

JTAG_

TDI

JTAG_

TRST

JTAG_

TMS

GNSS_ENGPIO11 ADC2_INADC1_INADC5_IN ADC4_IN rfu

(nc)

GND GND GND GND

GND JTAG_

TCK

GPIO3

(Interrupt)

GND GND GND GND GND GND GND GND GND GND GND GND GND GND

rfu

(dnu)

GND GND GND GND GND GND GND GND GND GND GND GND GND

rfu

(dnu)

GND ANT_

GNSS_

GND

ANT_

GNSS

GND GND GND

rfu

(nc)

GND GND GND

rfu

(nc)

GND GND GND

rfu: Reserved for future use (may be connected to external application (nc): Internally not connected (may be arbitrarily connected to external GND)

(dnu): Do not use (should not be connected to external application)

Circle marks round shaped pads designed for improved impedance.

Orange: Keep out areas on external application’s PCB.

Round shaped: No solder pads, should therefore not be soldered. No further tracks on PCB’s first layer.

2.1 Application Interface

Page 20 of 124

 ALAS5V_HID_v00.030a 2019-03-20

Figure 4: ALAS5V top view: Pad assignments

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Page 21 of 124

2.1 Application Interface

2.1.2 Signal Properties

Please note that the reference voltages listed in Table 4 are the values measured directly on the ALAS5V module. They do not apply to the accessories connected.

Table 4: Signal description

Function Signal name IO Signal form and level Comment

Power supply

External supply voltage

BATT+ BATT+_RF

max = 4.2V

min = 3.3V (on board)

Supply voltage lines for general power management and the RF power amplifier.

Lines of BATT+/BATT+_RF

n Tx = n x 577µs peak current every

4.615ms Imax = see Table 25

WCDMA TX continuous current Imax = see Table 25

LTE TX continuous current Imax = see Table 25

and GND respectively must be connected in parallel for supply purposes because higher peak currents may occur.

Minimum voltage must not fall below 3.3V including drop, ripple, spikes.

GND Ground Application Ground VEXT O C

max = 1µF

VEXT may be used for application circuits.

= 1.80V -2.4%, +2%

If unused keep line open. Normal operation: I

max = -50mA

Test point recommended.

The external digital logic SLEEP mode operation: I

max = -1mA

must not cause any spikes

or glitches on voltage VEXT.

Supply voltage for active GNSS antenna (Input)

External GNSS supply voltage enable (output)

ANT_GNSS_DCIV

max = 5V

Imax = 50mA

GNSS_EN O V

max = 0.45V at I = 2mA

nom = 0.1V at I = 100µA

min = 1.30V at I = -2mA nom = 1.65V at I = -100µA max = 1.84V

Do not exceed I

max in any

operation mode.

If unused connect to GND.

The input current must be

limited to 50mA (antenna

short circuit protection).

Enable signal for an external

voltage regulator (intended

for active GNSS antenna,

high=active).

No external pull-up allowed

during startup until the mod-

ule has been secured in fac-

tory.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.1 Application Interface

Table 4: Signal description

Function Signal name IO Signal form and level Comment

Page 22 of 124

Ignition IGT I R

Emergency off

Firmware

EMERG_

OFF

FwSwap I V

switch

 200k

max = 1.84V

max =2.00V

min = 1.30V

max = 0.50V

Low impulse width > 100ms

 40k

max = 1.84V

max = 2.00V

min = 1.30V

max = 0.50V

~~|___|~~ low impulse width up to 2000ms (as long as PWR_IND stays low)

max = 0.50V

min = 1.30V

max = 2.0V

= 27.5µA…97.5µA

IHPD

= -27.5µA…-97.5µA

ILPU

High-Z max

= ±1µA

This signal switches the

module on.

It is required to drive this line

low by an open drain or open

collector driver connected to

GND.

Test point recommended.

It is required to drive this line

low by an open drain or open

collector driver connected to

GND until the module finally

switches off.

If unused keep line open.

Test point recommended.

Note that a low impulse of

more than 2000ms will reset

the module’s RTC.

Input during the startup

phase:

If FwSwap's state is High, a

switch to the possible other,

and currently not active firm-

ware image is triggered.

SIM card detection

CCIN1 I R

V V V V

CCIN2 I V

V V I

 24kto VEXT

max=1.84V

min = 1.25V at -25µA

max= 2.0V

max = 0.35V at -60µA

(max) = 0.5V

(min) = 1.30V

(max) = 2.0V

(max) = ±1µA

High-Z

Test point required.

CCIN = Low means SIM

card inserted.

If SIM card holder does not

support CCINx, connect to

GND.

CCIN2: External pull-up

required - for details please

refer to Section 2.1.7.

If 2

SIM interface not used,

keep line open.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.1 Application Interface

Table 4: Signal description

Function Signal name IO Signal form and level Comment

Page 23 of 124

2.85V SIM card interfaces

1.8V SIM card interface

CCRST1 CCRST2

CCCLK1 CCCLK2

CCIO1 CCIO2

CCVCC1 CCVCC2

CCRST1 CCRST2

CCCLK1 CCCLK2

CCIO1 CCIO2

I/O R

max = -50mA

I/O R

max = 0.4V at I = 2mA nom = 0.1V at I = 100µA

min = 2.2V at I = -2mA nom = 2.65V at I = -100µA max = 2.91V

 6.7..8.5k

max = 0.55V

min = 2.35V max = 3.05V

max = 0.4V at I = 2mA nom = 0.1V at I = 100µA

min = 2.35V at I > -45µA max = 2.91V

min = 2.75V typ =2.85V max = 2.91V

max = 0.4V at I = 2mA nom = 0.1V at I = 100µA

min = 1.40V at I = -2mA min = 1.65V at I = -100µA max = 1.84V

 6.7..8.5k

max = 0.30V

min = 1.30V max = 1.84V

Maximum cable length or

copper track should be not

longer than 100mm to SIM

card holder.

CCIO2: External 10kW pull-

up required - for details

please refer to Section 2.1.7.

If unused keep lines open.

Maximum cable length or

copper track should be not

longer than 100mm to SIM

card holder.

CCIO2: External 10kW pull-

up required - for details

please refer to Section 2.1.7.

If unused keep lines open.

SIM interface shutdown

Serial Modem Interface ASC0

max = 0.4V at I = 2mA

nom = 0.1V at I = 100µA

min = 1.40V at I > -50µA

max = 1.84V

CCVCC1 CCVCC2

max = -50mA

min = 1.74V typ = 1.80V max = 1.84V

BATT_ID I External pull up to VEXT and pull

down resistor within battery case

RXD0 O V CTS0 O DSR0 O RING0 O

required. R

max = 0.45V at I = 2mA

nom = 0.1V at I = 100µA

min = 1.30V at I = -2mA

nom = 1.65V at I = -100µA

max = 1.84V

= 100kRPD = 10k

DCD0 I/O TXD0 I V RTS0 I DTR0 I

max = 0.50V

min = 1.30V

max = 2.0V

= 27.5µA…97.5µA

IHPD

= -27.5µA…-97.5µA

ILPU

High-Z max

= ±1µA

Reserved for future use.

Connect line to GND.

Test points recommended

for TXD0, RXD0, DCD0,

RTS0, and CTS0.

If DCD0 is driven low during

startup-phase, module

enters Download Mode (see

Section 4.2.2)

If unused keep line open.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.1 Application Interface

Table 4: Signal description

Function Signal name IO Signal form and level Comment

Page 24 of 124

Serial Modem Interface ASC1

Serial Debug Interface ASC2 (Gemalto internal)

Power indicator

RXD1 O V CTS1 O

TXD1 I V RTS1 I

RXD2 O V

TXD2 I V

PWR_IND O V

max = 0.45V at I = 2mA

nom = 0.1V at I = 100µA

min = 1.30V at I = -2mA

nom = 1.65V at I = -100µA

max = 1.84V

max = 0.50V

min = 1.30V

max = 2.0V

= 27.5µA…97.5µA

IHPD

= -27.5µA…-97.5µA

ILPU

High-Z max

V V V V

V V I

IHPD

ILPU

High-Z max

= ±1µA

max = 0.45V at I = 2mA

nom = 0.1V at I = 100µA

min = 1.30V at I = -2mA

nom = 1.65V at I = -100µA

max = 1.84V

max = 0.50V

min = 1.30V

max = 2.0V

= 27.5µA…97.5µA

= -27.5µA…-97.5µA

= ±1µA

max = 5.5V

max = 0.45V at Imax = 2mA

Test points recommended

for RXD1, TXD1, CTS1,

RTS1.

If unused keep line open.

No external pull-up / pull-

down resistors allowed.

Test points required.

If unused keep line open.

PWR_IND (Power Indicator)

notifies the module’s on/off

state.

PWR_IND is an open collec-

tor that needs to be con-

nected to an external pull-up

resistor. Low state of the

open collector indicates that

the module is on. Vice versa,

high level notifies the Power

Down mode.

Therefore, the signal may be

used to enable external vol-

tage regulators that supply

an external logic for commu-

nication with the module,

e.g. level converters.

Test point recommended.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.1 Application Interface

Table 4: Signal description

Function Signal name IO Signal form and level Comment

Page 25 of 124

USB VUSB_IN I V

USB_DN I/O Full and High speed signal (differenUSB_DP I/O

USB_

I Super Speed signal (differential) Rx

SSRX_N USB_

SSRX_P USB_

O Super Speed signal (differential) Tx

SSTX_N USB_

SSTX_P

Digital audio interface (PCM/I

DIN2 I V BCLK2 I/O

FSC2 I/O DOUT2 O

MCLK O V

min = 3.0V

max = 5.75V

max = 100µA

Cin=1µF

tial) characteristics according to USB

2.0 specification.

characteristics according USB 3.0 specification.

max = 0.45V at I = 2mA

nom = 0.1V at I = 100µA

min = 1.30V at I = -2mA

nom = 1.65V at I = -100µA

max = 1.84V

max = 0.50V

min = 1.30V

max = 2.0V

= 27.5µA…97.5µA

IHPD

= -27.5µA…-97.5µA

ILPU

High-Z max

V V V V

= ±1µA

max = 0.45V at I = 2mA

nom = 0.1V at I = 100µA

min = 1.30V at I = -2mA

nom = 1.65V at I = -100µA

max = 1.84V

fo = TBD. MHz

USB detection.

Test point recommended.

If unused keep lines open.

Test point recommended.

USB High Speed mode

operation requires a differ-

ential impedance of 90

If unused keep lines open.

USB Super Speed mode

operation requires a differ-

ential impedance of 90

Digital audio interface con-

figurable as PCM or I

interface.

If unused keep lines open.

First digital audio interface

(DIN1, BCLK1, FSC1, and

DOUT1) reserved for future

use.

For I

S: Master clock output

Test point recommended in

case I

S interface is not

used.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

MUX,

ADC

module

10n

ADCx_IN

2.1 Application Interface

Table 4: Signal description

Function Signal name IO Signal form and level Comment

Page 26 of 124

GPIO interface

GPIO1, GPIO3...8, GPIO11...17, GPIO22

I/O V

max = 0.45V at I = 2mA

nom = 0.1V at I = 100µA

min = 1.30V at I = -2mA

nom = 1.65V at I = -100µA

max = 1.84V

max = 0.50V

min = 1.30V

max = 2.0V

= 27.5µA…97.5µA

IHPD

= -27.5µA…-97.5µA

ILPU

High-Z max

= ±1µA

GPIO3, GPIO5...GPIO7,

GPIO8, and GPIO16 are

interrupt enabled. They can

be used to for instance wake

up the module (see Section

2.1.12).

Following functions can be

configured for GPIOs using

AT commands:

GPIO1 --> DR_SYNC

There is a 2.2k decoupling

resistor between GPIO17

and JTAG_WD_DISABLE.

Test points recommended

for GPIO1, GPIO3.

If unused keep lines open.

However, GPIO7 and

GPIO17, must be low during

module startup until the

module has been secured in

factory.

1PPS interface

ADC interface

GPIO1 (DR_SYNC)

ADC1_IN, ADC2_IN, ADC4_IN, ADC5_IN

O Clock signal with 1 pulse per second,

frequency 1Hz, accuracy +/- 5ms

I Full specification compliance range

>=0.10V

Imin

<=1.70V

Imax

10M

Resolution: 14 Bit Accuracy: < ±2mV ADC conversion time t (max) = 550µs at 4.8MHz sample clock

If the feature is enabled (see

Chapter 3).

If unused keep line open.

Prepared for general pur-

pose and antenna diagnos-

tic use.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.1 Application Interface

Table 4: Signal description

Function Signal name IO Signal form and level Comment

PCIe PCIE_RX_N I According to PCI Express Specifica-

PCIE_RX_P PCIE_TX_N O PCIE_TX_P PCIE_CLK_N I/O PCIE_CLK_P

tion, Revision 2.0/2.1 (one lane, 5 GBit/s)

Page 27 of 124

C inter-

face

JTAG interface

PCIE_CLK_REQ

PCIE_HOST_ RST

PCIE_HOST_ WAKE

IO V

max = 0.45V at I = 2mA

nom = 0.1V at I = 100µA

min = 1.30V at I = -2mA

nom = 1.65V at I = -100µA

max = 1.84V

max = 0.50V

min = 1.30V

max = 2.0V

= 27.5µA…97.5µA

IHPD

= -27.5µA…-97.5µA

ILPU

High-Z max

= ±1µA

I2CDAT1 I/O VILmax = 1.30V

min = 0.50V

I2CCLK1 O

JTAG_SRST I V JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TRST JTAG_TDO O

JTAG_WD_DISABLE

max = 2.0V

max = 0.3V at I = 3mA

ILPU

max = 0.45V at I = 2mA

nom = 0.1V at I = 100µA

max = 0.50V

min = 1.30V

max = 2.0V

IHPD

ILPU

High-Z max

max = 0.3V at -100µA

min = 1.50V at 100µA

max = 2.0V

max = 1.84V = -27.5µA…-97.5µA

min = 1.30V at I = -2mA nom = 1.65V at I = -100µA max = 1.84V

= 27.5µA…97.5µA

= -27.5µA…-97.5µA

= ±1µA

Additional PCIe control sig-

nals

Open Drain Output (internal

pull up)

External pull up resistors

required.

Maximum load 510 Ohm.

Debug interface.

Test point recommended for

all JTAG lines.

High during reset and start-

up does disable the watch-

dog timer (jumper to VEXT).

There is a 2k2Ohm decou-

pling resistor between

JTAG_WD_DISABLE and

GPIO17.

JTAG_ PS_HOLD

min = 1.65V at 680µA

max = 0.20V at 680µA

High holds the power supply

during debugging (jumper to

VEXT). V

max = 1.84V

min = 1.30V at 150µA

max = 0.5V at -200µA

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.1 Application Interface

Table 4: Signal description

Function Signal name IO Signal form and level Comment

Page 28 of 124

eMMC interface

1.8V eMMC

2.95V eMMC

EMMC_

DETECT

EMMC_PWR O V

EMMC_CLK O V EMMC_CMD O EMMC_D[0...7]I/O

max = 0.45V at I = 2mA

nom = 0.1V at I = 100µA

min = 1.30V at I = -2mA

nom = 1.65V at I = -100µA

max = 1.84V

max = 0.50V

min = 1.30V

max = 2.0V

= 27.5µA…97.5µA

IHPD

= -27.5µA…-97.5µA

ILPU

High-Z max

OUT (max)

V V

V V V I

High-Z max

V V V V V I

High-Z max

= ±1µA

OUT (nom)

= 2.95V / 1.8V

= 150mA

max = 0.45V at rated drive strength

min = 1.40V at rated drive strength

max = 1.84V

max = 0.58V at rated drive strength

min = 1.27V at rated drive strength

max = 2.0V

= ±5µA

max = 0.36V at rated drive strength

min = 2.05V at rated drive strength

max = 2.91V

max = 0.68V at rated drive strength

min = 1.82V at rated drive strength

max = 3.05V

= ±10µA

eMMC

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.1 Application Interface

Page 29 of 124

2.1.2.1 Absolute Maximum Ratings

The absolute maximum ratings stated in Table 5 are stress ratings under any conditions. Stresses beyond any of these limits will cause permanent damage to ALAS5V.

Table 5: Absolute maximum ratings (TBD.)

Parameter Min Max Unit

Supply voltage BATT+ -0.3 +5.5 V Voltage at all digital lines in Power Down mode (except VEXT) -0.3 +0.5 V Voltage at VEXT in Power Down mode -0.3 +0.3 V Voltage at digital lines in normal operation -0.3 +2.3 V Voltage at UICC interface, CCVCC 1.8V in normal operation -0.3 +2.3 V Voltage at UICC interface, CCVCC 3.0V in normal operation -0.3 +3.4 V Voltage at ADC lines if the module is powered by BATT+ -0.5 V Voltage at ADC lines if the module is not powered -0.5 +0.5 V VEXT maximum current shorted to GND -600 mA VUSB_IN -0.3 5.75 V USB 3.0 data lines -0.3 +1.4 V USB 2.0 data lines -0.3 +3.6 V PCIe data and clock lines -0.3 +1.4 V PCIe control lines -0.3 2.1 V Voltage at PWR_IND line -0.5 5.5 V PWR_IND input current if PWR_IND= low 2 mA Voltage at following signals:

IGT, EMERG_OFF

-0.3 2.1 V

BATT+

+0.5V V

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

BATT+

USB_DP

lin. reg.

GND

Module

Detection only

VUSB_IN

USBpart

All ser ial (including RS) and pull-up resistors for data lines are implemented .

USB_DN

If the USB interface is opera te d with super or high speeds, it is recommende d to take special care routing the data

lines. Application layout should implement a differential impedance of 90 ohms for proper signal integrity .

VBUS

1µF

Since VUSB_IN is used for detection only it is recommended not to add any further blocking capacitors on

the VUSB_IN line.

USB_SSRX_N

USB_SSRX_P

USB_SSTX_N

USB_SSTX_P

USB_SS

_PHY

USB_HS

_PHY

USB 2.0

Controller

USB 3.0

Controller

2.0

3.0

100nF

SMT

Page 30 of 124

2.1 Application Interface

2.1.3 USB Interface

ALAS5V supports a USB 3.0 Super Speed (5Gbps) device interface, and alternatively a USB

2.0 device interface that is High Speed compatible. The USB interface is primarily intended f or use as command and data interface, and for downloading firmware.

The USB host is responsible for supplying the VUSB_IN line. This line is for voltage detection only. The USB part (driver and transceiver) is supplied by means of BATT+. This is because ALAS5V is designed as a self-powered device compliant with the “Universal Serial Bus Specification Revision 3.0”

Figure 5: USB circuit

To properly connect the module's USB interface to the external application, a USB 3.0 or 2.0 compatible connector and cable or hardware design is required. For further guidelines on implementing the external application’s USB 3.0 or 2.0 interface see [4] and [5]. For more information on the USB related signals see Table 4. Furthermore, the USB modem driver distributed with ALAS5V needs to be installed.

While a USB connection is active, the module will never switch into SLEEP mode. Only if the USB interface is in Suspended state or Detached (i.e., VUSB_IN = 0) is the module able to switch into SLEEP mode thereby saving power

1. The specification is ready for download on http://www.usb.org/developers/docs/

2. Please note that if the USB interface is employed, and a USB cable is connected, there should also be a terminal program linked to the USB port in order to receive and process the initial SYSSTART URC after module startup. Otherwise, the SYSSTART URC remains pending in the USB driver's output buffer and this unprocessed data prevents the module from power saving.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.1 Application Interface

Page 31 of 124

2.1.4 Serial Interface ASC0

ALAS5V offers an 8-wire (plus GND) unbalanced, asynchronous modem interface ASC0 conforming to ITU-T V.24 protocol DCE signaling. The electrical characteristics do not comply with ITU-T V.28. The significant levels are 0V (for low data bit or active state) and 1.8V (for high data bit or inactive state). For electrical characteristics please refer to Table 4.

ALAS5V is designed for use as a DCE. Based on the conventions for DCE-DTE connections it communicates with the customer application (DTE) using the following signals:

• Port TXD @ application sends data to the module’s TXD0 signal line

• Port RXD @ application receives data from the module’s RXD0 signal line

Figure 6: Serial interface ASC0

Features:

• Includes the data lines TXD0 and RXD0, the status lines RTS0 and CTS0, and the modem control lines DTR0, DSR0, DCD0 and RING0.

• Configured for 8 data bits, no parity and 1 stop bit.

• ASC0 can be operated at fixed bit rates from 115,200 to 921,600bps.

• Supports RTS0/CTS0 hardware flow control.

Note: If the ASC0 serial interface is the application’s only interface, it is suggested to connect test points on the USB signal lines as a potential tracing possibility.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.1 Application Interface

Table 6: DCE-DTE wiring of ASC0

V.24 circuit DCE DTE

Line function Signal direction Line function Signal direction

103 TXD0 Input TXD Output 104 RXD0 Output RXD Input 105 RTS0 Input RTS Output 106 CTS0 Output CTS Input 108/2 DTR0 Input DTR Output 107 DSR0 Output DSR Input 109 DCD0 Output DCD Input 125 RI NG0 Output RING Input

Page 32 of 124

2.1.5 Serial Interface ASC1

ALAS5V provides a 4-wire unbalanced, asynchronous modem interface ASC1 conforming to ITU-T V.24 protocol DCE signaling. The electrical characteristics do not comply with ITU-T V.28. The significant levels are 0V (for low data bit or active state) and 1.8V (for high data bit or inactive state). For electrical characteristics please refer to Table 3.

ALAS5V is designed for use as a DCE. Based on the conventions for DCE-DTE connections it communicates with the customer application (DTE) using the following signals:

• Port TXD @ application sends data to module’s TXD1 signal line

• Port RXD @ application receives data from the module’s RXD1 signal line

Figure 7: Serial interface ASC1

Features

• Includes only the data lines TXD1 and RXD1 plus RTS1 and CTS1 for hardware handshake.

• On ASC1 no RING line is available.

• Configured for 8 data bits, no parity and 1 or 2 stop bits.

• ASC1 can be operated at fixed bit rates from 115,200 bps to 921,600 bps.

• Supports RTS1/CTS1 hardware flow.

• Linux controlled only.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

I2CCLK

I2CDAT

GND

I2CCLK

I2CDAT

GND

Module Application

VEXT

R pull up

Page 33 of 124

2.1 Application Interface

2.1.6 Inter-Integrated Circuit Interface

ALAS5V provides an Inter-Integrated Circuit (I2C) interface. I2C is a serial, 8-bit oriented data transfer bus for bit rates up to 400kbps in Fast mode. It consists of two lines, the serial data line I2CDAT and the serial clock line I2CCLK. The module acts as a single master device, e.g. the clock I2CCLK is driven by the module. I2CDAT is a bi-directional line. Each device connected to the bus is software addressable by a unique 7-bit address, and simple master/slave relationships exist at all times. The module operates as master-transmitter or as master-receiver. The customer application transmits or receives data only on request of the module.

The applications’ I the VEXT line, the I

C interface can be powered via the VEXT line of ALAS5V. If connected to

C interface will properly shut down when the module enters the Power

Down mode. In the application I2CDAT and I2CCLK lines need to be connected to a positive su pply voltage

(e.g., VEXT) via a pull-up resistor. For electrical characteristics please refer to Table 4.

Figure 8: I2C interface connected to VEXT

Note: Good care should be taken when creating the PCB layout of the host application: The traces of I2CCLK and I2CDAT should be equal in length and as short as possible.

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.1 Application Interface

Page 34 of 124

2.1.7 UICC/SIM/USIM Interface

ALAS5V has two UICC/SIM/USIM interfaces compatible with the 3GPP 31.102 and ETSI 102

221. These are wired to the host interface in order to be connected to an external SIM card

holder. Five pads on the SMT application interface are reserved for each of the two SIM interfaces.

The UICC/SIM/USIM interface supports 2.85V and 1.8V SIM cards. Please refer to Table 4 for electrical specifications of the UICC/SIM/USIM interface lines depending on whether a 2.85V or 1.8V SIM card is used.

The CCINx signal serves to detect whether a tray (with SIM card) is present in the card holder. Using the CCINx signal is mandatory for compliance with the GSM 11.11 recommendation if the mechanical design of the host application allows the user to remove the SIM card during operation. To take advantage of this feature, an appropriate SIM card detect switch is required on the card holder. For example, this is true for the model supplied by Molex, which has been tested to operate with ALAS5V and is part of the Gemalto M2M reference equipment submitted for type approval. See Chapter 8 for Molex ordering numbers.

Table 7: Signals of the SIM interface (SMT application interface)

Signal Description

GND Ground connection for SIM interfaces. Optionally a separate SIM ground line may be used

to improve EMC.

CCCLK1 CCCLK2

CCVCC1 CCVCC2

CCIO1 CCIO2

CCRST1 CCRST2

CCIN1 CCIN2

and 2

Chipcard clock line for 1

SIM supply voltage line for 1

Serial data line for 1

Chipcard reset line for 1

Input on the baseband processor for detecting a SIM card tray in the holder. If the SIM is removed during operation the SIM interface is shut down immediately to prevent destruction of the SIM. The CCINx signal is active low. The CCINx signal is mandatory for applications that allow the user to remove the SIM card during operation. The CCINx signal is solely intended for use with a SIM card. It must not be used for any other purposes. Failure to comply with this requirement may inva lidate the type approval of ALAS5V.

and 2

SIM interface.

and 2

SIM interface, input and output.

SIM interface.

Note: No guarantee can be given, nor any liability accepted, if loss of data is encountered after removing the SIM card during operation. Also, no guarantee can be given for properly initializing any SIM card that the user inserts after having removed the SIM card during operation. In this case, the application must restart ALAS5V.

By default, only the 1

SIM interface is available and can be used. Using the AT command AT^SCFG=”SIM/CS” it is possible to switch between the two SIM interfaces. Command settings are non-volatile - for details see [1].

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Module

open: Card removed closed : C ar d insert ed

CCRST1

CCVCC1

CCIO1

CCCLK 1

CCIN1

SIM / UICC

220n

SMT applicat ion interface

GND

Module

Open: Card removed Closed: Card inserted

CCRST2

CCVCC2

CCIO2

CCCLK2

CCIN2

SIM /

UICC

1nF

220nF

SMT application interface

GND

VEXT

100pF

22k

2k2

10k

2.1 Application Interface

Figure 9: First UICC/SIM/USIM interface

Page 35 of 124

The total cable length between the SMT application interface pads on ALAS5V and the pads of the external SIM card holder must not exceed 100mm in order to meet the specifications of 3GPP TS 51.010-1 and to satisfy the requirements of EMC compliance.

To avoid possible cross-talk from the CCCLKx signal to the CCIOx signal be careful that both lines are not placed closely next to each other. A useful approach is using the GND line to shield the CCIOx line from the CCCLKx line.

An example for an optimized ESD protection for the SIM interface is shown in Section 2.1.8. Note: Figure 9 shows how to connect a SIM card holder to the first SIM interface . With the sec-

ond SIM interface some internally integrated components on the SIM circuit will have to be externally integrated as shown for the second SIM interface in Figure 10. The external components at CCIN2 should be populated as close as possible to the signal‘s SMT pad

 ALAS5V_HID_v00.030a 2019-03-20

Figure 10: Second UICC/SIM/USIM interface

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

CCRSTx

CCCLKx

CCIOx

CCVCCx

CCINx

51R

123

654

SIM_RST

SIM_CLK

SIM_IO

SIM_VCC

SIM_DET

Module

GND SIM_GND

5-line transient voltage supressor array, e.g., NU P4114 series

Page 36 of 124

2.1 Application Interface

2.1.8 Enhanced ESD Protection for SIM Interfaces

To optimize ESD protection for the SIM interfaces it is possible to add ESD diodes to the interface lines of the first and second SIM interface as shown in the example given in Figure 11.

The example was designed to meet ESD protection according ETSI EN 301 489-1/ 7: Contact discharge: ± 4kV, air discharge: ± 8kV.

Figure 11: SIM interfaces - enhanced ESD protection

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

MSB

LSB

14 13

MSB

62.5 µs

BCLK2

FSC2

DOUT2 DIN2

2.1 Application Interface

2.1.9 Digital Audio Interface

Page 37 of 124

ALAS5V has two digital audio interfaces (DAIs) that can be employed as inter pulse code modulation (PCM) or Inter-IC Sound (I

S) interface. Default setting is pulse code modulation.

Please note that the first DAI is reserved for future use.

2.1.9.1 Pulse Code Modulation Interface (PCM)

ALAS5V's PCM interface can be used to connect audio devices capable of pulse code modulation. The PCM functionality is limited to the use of wideband codecs with 16kHz sample rat e only. The PCM interface runs at 16 kHz sample rate (62.5µs frame length), while the signal processing maintains this rate in a wideband AMR call or samples automatically down to 8kHz in a narrowband call. Therefore, the PCM sample rate is independent of the audio bandwidth of the call.

The PCM interface has the following implementation:

• Master mode

• Short frame synchronization

• 16kHz/8kHz sample rate

• 4096/1024/512/256 kHz bit clock at 16kHz sample rate

• 2048/512/256/128 kHz bit clock at 8kHz sample rate

Table 8 lists the available PCM interface signals.

Table 8: Overview of PCM pin functions

Signal name Signal

Description direction: Master

DOUT2 O PCM Data from ALAS5V to external codec DIN2 I PCM Data from external codec to ALAS5V FSC2 O Fra m e syn ch ro n izat ion si gn al to exte rnal co de c BCLK2 O Bit clock to external codec. Note: If the BCLK2 signal is permanently

provided (AT^SAIC parameter <clk_mode> = 0), the module will no

longer enter its power save (SLEEP) state.

Note: PCM data is always formatted as 16-bit uncompressed two’s complement. Also, all PCM data and frame synchronization signals are written to the PCM bus on the rising clock edge and read on the falling edge.

The timing of a PCM short frame is shown in Figure 12.

 ALAS5V_HID_v00.030a 2019-03-20

Figure 12: PCM timing short frame (master, 4096KHz, 16kHz sample rate)

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

BCLK2

DOUT2

DIN2

FSC2

MSB

LSB

14 13

MSB

125 µs

Page 38 of 124

2.1 Application Interface

2.1.9.2 Inter-IC Sound Interface

The Inter-IC Sound Interface is a standardized bidirectional I2S based digital audio interface for transmission of mono voice signals for telephony services.

An activation of the I

S line is possible only out of call and out of tone presentation. The I2S properties and capabilities comply with the requirements layed out in the Phillips I2S Bus Specifications, revised June 5, 1996.

The I

S interface has the following characteristics:

• Bit clock mode: Master, optional master clock output

• Sampling rate: 8KHz (narrowband), 16KHz (wideband)

• 256kHz bit clock at 8kHz sample rate

• 512kHz bit clock at 16kHz sample rate

• Frame length: 32 bit stereo voice signal (16 bit word length)

• Optional Master clock: 2048KHz (8KHz sample rate) or 4096KHz (16KHz sample rate)

Table 9 lists the available I

Table 9: Overview of I

Signal name on SMT application interface

DOUT2 PD O I DIN2 PD I I FSC2 PD O Frame synchro n izat ion s ign al to /fr om ext erna l

BCLK2 PD O Bit clock to external codec. Note: If the BCLK2 sig-

MCLK PD O I

S pin functions

Signal configuration inactive

S interface signals, Figure 13 shows the I2S timing.

Signal

Description direction: Master

S data from ALAS5V to external codec

S data from external codec to ALAS5V

codec Word alignment (WS)

nal is permanently provided (AT^SAIC parameter

<clk_mode> = 0), the module will no longer enter its

power save (SLEEP) state.

S Master to supply external codecs without PLL.

Figure 13: I2S timing (master mode)

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.1 Application Interface

Page 39 of 124

2.1.10 Analog-to-Digital Converter (ADC)

ALAS5V provides four unbalanced ADC input lines: ADC[1-2...4-5]_IN. They can be used to measure four independent, externally connected DC voltages in the range of 0.1V to 1.7V. As described in Section 2.2.4 and Section 5.2 they can be used especially for antenna diagnosing.

The AT^SRADC command can be employed to select the ADC line, set the measurement mode and read out the measurement results.

2.1.11 RTC Backup

The internal Real Time Clock of ALAS5V is supplied from a separate voltage regulator in the power supply component which is also active when ALAS5V is in Power Down mode and BATT+ is available.

An alarm function is provided that allows to wake up ALAS5V. When the alarm time is reached the module wakes up into normal operating mode (default), or to the functionality level that was valid before power down. For example, if the module was in Airplane mode before power down, the module will wake up without logging on to the GSM/UMTS/LTE network.

2.1.12 GPIO Interface

ALAS5V has 15 GPIOs for external hardware devices. Each GPIO can be configured for use as input or output. All settings are AT command controlled.

The IO port driver has to be opened before using and configuring GPIOs. Before changing the configuration of a GPIO pin (e.g. input to output) the pin has to be closed. If the GPIO pins are not configured or the pins/driver were closed, the GPIO pins are high-Z with pull down resistor. If a GPIO is configured to input, the pin has high-Z without pull resistor.

If ALAS5V is in power save (SLEEP) mode a level state transition at GPIO3, GPIO5, GPIO6, GPIO7, GPIO8, or GPIO16 will wake up the module, if such a GPIO was configured as input using AT^SCPIN. To query the level state the AT^SCPOL command may be used. For details on the mentioned AT commands please see [1].

Table 10 shows GPIO lines with possible alternative functionalities, and comments on these

optional assignments.

Table 10: GPIO lines and possible alternative assignment

GPIOs / Alternative signal names

Description of possible alternative signals

GPIO1 / DR_SYNC

 ALAS5V_HID_v00.030a 2019-03-20

DR_SYNC. GPIO1 can also be configured as DR_SYNC line, i.e., a one pulse per second (1PPS) output for external dead reckoning applications. For more information see Chapter 3.

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Power supply

On/Off

PWR_IND

For example:

VCC µC or

BATT+

Module

SMT interface

(open

collector)

Pull-up

2.1 Application Interface

Page 40 of 124

2.1.13 Control Signals

2.1.13.1 PWR_IND Signal

PWR_IND notifies the on/off state of the module. High state of PWR_IND indicates that the module is switched off. The state of PWR_IND immediately changes to low when IGT is pulled low. For state detection an external pull-up resistor is required.

Figure 14: PWR_IND signal

 ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.1 Application Interface

Page 41 of 124

2.1.13.2 Remote Wakeup

If no call, data or message transfer is in progress, the external host application may shut down its own module interfaces or other components in order to save power. If a call, data, or other request (URC) arrives, the external application can be notified of this event and be woken up again by a state transition of a configurable remote wakeup line. Available as remote wakeup lines are some GPIO signals (recommended is GPIO4). Please refer to [1]: AT^SCFG: "RemoteWakeUp/..." for details on how to configure these lines for defined wakeup events on specified device interfaces. Possible states are listed in Table 11.

If no line is specifically configured as remote wakeup signal, the remote USB suspend and resume mechanism as specified in the “Universal Serial Bus Specification Revision 2.0” applies for the USB interface (see Section 2.1.3). Possible states for the remote wakeup GPIO lines are listed in Table 11.

Table 11: Remote wakeup lines

Signal I/O/P Description

GPIOx O Inactive to active high transition:

0 = No wake up request 1 = The host shall wake up

2.1.13.3 Firmware Swap

The firmware swap signal FwSwap allows to toggle between two firmware images that may be available on the module. Setting the FwSwap line to high during the module’s startup phase triggers the firmware swap. The signal may for instance be used as a fallback or backup solution in case a possible firmware update is not successful.

Please connect this signal to the external application and implement a test point.

2.1.14 JTAG Interface

For test purposes, e.g., 8D reporting without re-soldering the module from the external application.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

ALAS66A‐W

EMMC_PWR

(2V95 / 1V8)

BATT+

Vin Vout

eMMC

2V9

CCQ

Voltage

Regulator

BATT+

Page 42 of 124

2.1 Application Interface

2.1.15 eMMC Interface

ALAS5V has an eMMC interface that can be used for development and test purposes, e.g., to write crash dumps from the module’s FFS to eMMC. To connect an eMMC a separate, additional power supply is required as described in Section 2.1.15.1.

2.1.15.1 eMMC Power Supply

An eMMC requires two separate power supplies normally named VCC (3V3) and VCCQ (3V3 / 1V8). ALAS5V however, provides only a single power supply pad for eMMC, i.e., the EMMC_PWR pad. Therefore, an additional external power supply for the eMMC is necessary, and can for instance be provided through a voltage regulator enabled with the EMMC_PWR line.

A sample connecting circuit is shown in Figure 15. Note that with ALAS5V the EMMC_PWR line switches from 2.95V to 1.8V during eMMC operation.



Figure 15: eMMC power supply

ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.2 GSM/UMTS/LTE Antenna Interface

Page 43 of 124

The ALAS5V GSM/UMTS/LTE antenna interface comprises a GSM/UMTS/LTEmain antenna as well as a UMTS/LTE Rx diversity/MIMO antenna to improve signal reliability and quality The interface has an impedance of 50

. ALAS5V is capable of sustaining a total mismatch at

. the antenna interface without any damage, even when transmitting at maximum RF power. The external antennas must be matched properly to achieve best performance regarding radi-

ated power, modulation accuracy and harmonic suppression. Matching networks are not included on the ALAS5V PCB and should be placed in the host application, if the antenna does not have an impedance of 50

.

Regarding the return loss ALAS5V provides the following values in the active band:

Table 12: Return loss in the active band

State of module Return loss of module Recommended return loss of application

Receive > 8dB > 12dB Transmit Undefined mismatch >

12dB

1. By delivery default the UMTS/LTE Rx diversity/MIMO antenna is configured as available for the module since its usage is mandatory for LTE. Please refer to [1] for details on how to configure antenna settings.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.2 GSM/UMTS/LTE Antenna Interface

Page 44 of 124

2.2.1 Antenna Interface Specifications

Table 13: RF Antenna interface GSM/UMTS/LTE (at operating temperature range1)

Parameter Conditions Min. Typical Max. Unit

LTE connectivity Band 1, 2, 3, 4, 5, 7, 8, 12, 18, 19, 20, 26, 28, 38, 39, 40, 41, 66

Receiver Input Sensitivity @ ARP (ch. bandwidth 5MHz; 4 antenna combined, TRX1, TRX2, RX3, RX4))

LTE 2100 Band 1 -102 -107 dBm LTE 1900 Band 2 -100 -106 dBm LTE 1800 Band 3 -99 -107 dBm LTE 1700 Band 4 -102 -107 dBm LTE 850 Band 5 -97.3 -108 dBm LTE 2600 Band 7 -100 -106 dBm LTE 900 Band 8 -96.3 -107 dBm LTE 700 Band 12 -96.3 -10 6 dBm LTE 850 Band 18 -96.8 -10 8 dBm LTE 850 Band 19 -96.8 -10 8 dBm LTE 800 Band 20 -99 -108 dBm LTE 850 Band 26 -96.8 -10 8 dBm LTE 700 Band 28 -97.8 -10 8 dBm LTE 2600 Band 38 -99.3 -106 dBm LTE 1900 Band 39 -102 -108 dBm LTE 2300 Band 40 -102 -105 dBm LTE 2300 Band 41 -100 -107 dBm

RF Power @ ARP

Load

with 50

LTE 2600 Band 66 -101.5 -107 dBm LTE 2100 Band 1 +21 +23 +25 dBm LTE 1900 Band 2 +21 +23 +25 dBm LTE 1800 Band 3 +21 +23 +25 dBm LTE 1700 Band 4 +21 +23 +25 dBm LTE 850 Band 5 +21 +23 +25 dBm LTE 2600 Band 7 +21 +23 +25 dBm LTE 900 Band 8 +21 +23 +25 dBm LTE 700 Band 12 +21 +23 +25 dBm LTE 850 Band 18 +21 +23 +25 dBm LTE 850 Band 19 +21 +23 +25 dBm LTE 800 Band 20 +21 +23 +25 dBm LTE 850 Band 26 +21 +23 +25 dBm LTE 700 Band 28 +21 +23 +25 dBm LTE 2600 Band 38 +21 +23 +25 dBm



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Page 45 of 124

2.2 GSM/UMTS/LTE Antenna Interface

Table 13: RF Antenna interface GSM/UMTS/LTE (at operating temperature range1)

Parameter Conditions Min. Typical Max. Unit

RF Power @ ARP

Load

with 50

LTE 1900 Band 39 +21 +23 +25 dBm

LTE 2300 Band 40 +21 +23 +25 dBm LTE 2300 Band 41 +21 +23 +25 dBm

LTE 2600 Band 66 +21 +23 +25 dBm UMTS/HSPA connectivity Band I, II, III, IV, V, VI, VIII, XIX Receiver Input Sensitivity @

ARP Main path (TRX1)

UMTS 2100 Band I -106 -110 dBm

UMTS 1900 Band II -104 -109 dBm

UMTS 1800 Band III -103 -111 dBm

UMTS 1700 Band IV -106 -111 dBm

UMTS 900 Band VIII -103 -112 dBm

UMTS 850 Band V -104 -111 dBm

UMTS 850 Band VI -104 -111 dBm

UMTS 850 Band XIX -104 -111 dBm Receiver Input Sensitivity @

ARP Diversity path (TRX2)

UMTS 2100 Band I -106 -112 dBm

UMTS 1900 Band II -104 -111 dBm

UMTS 1800 Band III -103 -111 dBm

UMTS 1700 Band IV -106 -112 dBm

UMTS 900 Band VIII -103 -112 dBm

UMTS 850 Band V -104 -113 dBm

UMTS 850 Band VI -104 -113 dBm

UMTS 850 Band XIX -104 -113 dBm RF Power @ ARP

Load

with 50

UMTS 2100 Band I +21 +24 +25 dBm

UMTS 1900 Band II +21 +24 +25 dBm

UMTS 1800 Band III +21 +24 +25 dBm

UMTS 1700 Band IV +21 +24 +25 dBm

UMTS 900 Band VIII +21 +24 +25 dBm

UMTS 850 Band V +21 +24 +25 dBm

UMTS 850 Band VI +21 +24 +25 dBm

UMTS 850 Band XIX +21 +24 +25 dBm GPRS coding schemes Class 12, CS1 to CS4

EGPRS Class 12, MCS1 to MCS9 GSM Class Small MS Static Receiver input Sensi-

tivity @ ARP

GSM 850 /E-GSM 900 -102 -110 dBm

GSM 1800 / GSM 1900 -102 -109 dBm RF Power @ ARP

with 50

 Load GSM



GSM 850 /E-GSM 900 31 33 35 dBm

GSM 1800 / GSM 1900 28 30 32 dBm

ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.2 GSM/UMTS/LTE Antenna Interface

Table 13: RF Antenna interface GSM/UMTS/LTE (at operating temperature range1)

Parameter Conditions Min. Typical Max. Unit

Page 46 of 124

RF Power @ ARP with 50 Load ( i.e., no reduction)

RF Power @ ARP with 50 Load (



ROPR=4,



ROPR=5)

GPRS, 1 TX GSM 850 /E-GSM 900 33 dBm

GSM 1800 / GSM 1900 30 dBm

EDGE, 1 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 2 TX GSM 850 /E-GSM 900 33 dBm

GSM 1800 / GSM 1900 30 dBm

EDGE, 2 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 3 TX GSM 850 /E-GSM 900 33 dBm

GSM 1800 / GSM 1900 30 dBm

EDGE, 3 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 4 TX GSM 850 /E-GSM 900 33 dBm

GSM 1800 / GSM 1900 30 dBm

EDGE, 4 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 1 TX GSM 850 /E-GSM 900 33 dBm

GSM 1800 / GSM 1900 30 dBm

EDGE, 1 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 2 TX GSM 850 /E-GSM 900 33 dBm

GSM 1800 / GSM 1900 30 dBm

EDGE, 2 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 3 TX GSM 850 /E-GSM 900 32.2 dBm

GSM 1800 / GSM 1900 29.2 dBm

EDGE, 3 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 4 TX GSM 850 /E-GSM 900 31 dBm

GSM 1800 / GSM 1900 28 dBm

EDGE, 4 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.2 GSM/UMTS/LTE Antenna Interface

Table 13: RF Antenna interface GSM/UMTS/LTE (at operating temperature range1)

Parameter Conditions Min. Typical Max. Unit

Page 47 of 124

RF Power @ ARP with 50 Load (



ROPR=6)



ROPR=7)

GPRS, 1 TX GSM 850 /E-GSM 900 33 dBm

GSM 1800 / GSM 1900 30 dBm

EDGE, 1 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 2 TX GSM 850 /E-GSM 900 31 dBm

GSM 1800 / GSM 1900 28 dBm

EDGE, 2 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 3 TX GSM 850 /E-GSM 900 30.2 dBm

GSM 1800 / GSM 1900 27.2 dBm

EDGE, 3 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 4 TX GSM 850 /E-GSM 900 29 dBm

GSM 1800 / GSM 1900 26 dBm

EDGE, 4 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 1 TX GSM 850 /E-GSM 900 33 dBm

GSM 1800 / GSM 1900 30 dBm

EDGE, 1 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 2 TX GSM 850 /E-GSM 900 30 dBm

GSM 1800 / GSM 1900 27 dBm

EDGE, 2 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 3 TX GSM 850 /E-GSM 900 28.2 dBm

GSM 1800 / GSM 1900 25.2 dBm

EDGE, 3 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 4 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 24 dBm

EDGE, 4 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Page 48 of 124

2.2 GSM/UMTS/LTE Antenna Interface

Table 13: RF Antenna interface GSM/UMTS/LTE (at operating temperature range1)

Parameter Conditions Min. Typical Max. Unit

RF Power @ ARP with 50



Load

ROPR=8,

( i.e., max. reduction)

GPRS, 1 TX GSM 850 /E-GSM 900 33 dBm

GSM 1800 / GSM 1900 30 dBm

EDGE, 1 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 26 dBm

GPRS, 2 TX GSM 850 /E-GSM 900 30 dBm

GSM 1800 / GSM 1900 27 dBm

EDGE, 2 TX GSM 850 /E-GSM 900 24 dBm

GSM 1800 / GSM 1900 23 dBm

GPRS, 3 TX GSM 850 /E-GSM 900 28.2 dBm

GSM 1800 / GSM 1900 25.2 dBm

EDGE, 3 TX GSM 850 /E-GSM 900 22.2 d Bm

GSM 1800 / GSM 1900 21.2 dBm

GPRS, 4 TX GSM 850 /E-GSM 900 27 dBm

GSM 1800 / GSM 1900 24 dBm

EDGE, 4 TX GSM 850 /E-GSM 900 21 dBm

GSM 1800 / GSM 1900 20 dBm

1. At restricted temperature range no active power reduction is implemented - any deviations are hardware related.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2

T R P N M

GND GND

GND ANT_

MAIN

GND GND

J H G

GND GND

GND ANT_

DRX_ MAIN

GND GND

D C B

GND GND GND

GND ANT_

GNSS

GND

Page 49 of 124

2.2 GSM/UMTS/LTE Antenna Interface

2.2.2 Antenna Installation

The antennas are connected by soldering the antenna pads (ANT_MAIN, ANT_DRX_MIMO, ANT_GNSS) and their neighboring ground pads directly to the application’s PCB.

Figure 16: Antenna pads (top view)

The distance between the antenna pads and their neighboring GND pads has been optimized for best possible impedance. To prevent mismatch, special attention should be paid to these pads on the application’ PCB.The wiring of the antenna connection, starting from the antenna pad to the application’s antenna must result in a 50

 line impedance. Line width and distance

to the GND plane need to be optimized with regard to the PCB’s layer stack. To prevent receiver desensitization due to interferences generated by fast transients like high

speed clocks on the external application PCB, it is recommended to realize the antenna connection line using embedded Stripline rather than Micro-Stripline technology.

For type approval purposes (i.e., FCC KDB 996369 related to modular approval requirements), an external application must connect the RF signal in one of the following ways:

•Via 50

 coaxial antenna connector (common connectors are U-FL or SMA) placed as close

as possible to the module's antenna pad.

• By soldering the antenna to the antenna connection line on the application’s PCB (without the use of any connector) as close as possible to the module’s antenna pad.

• By routing the application PCB’s antenna to the module’s antenna pad in the shortest possible way.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.2 GSM/UMTS/LTE Antenna Interface

Page 50 of 124

2.2.3 RF Line Routing Design

2.2.3.1 Line Arrangement Instructions

Several dedicated tools are available to calculate line arrangements for specific applications and PCB materials - for example from http://www.polarinstruments.com/ (commercial software) or from http://web.awrcorp.com/Usa/Products/Optional-Products/TX-Line/ (free software).

Embedded Stripline

This below figure shows line arrangement examples for embedded stripline.



Figure 17: Embedded Stripline line arrangement

ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.2 GSM/UMTS/LTE Antenna Interface

Micro-Stripline

This section gives two line arrangement examples for micro-stripline.

Page 51 of 124



Figure 18: Micro-Stripline line arrangement samples

ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

e.g. ANT_ MAIN

G N D

Edge of module PCB

Stripl i ne ( 50 ohms) on top

layer of evaluation board from

antenna pad to module edge

Width = 0.40 mm

E.g., U.FL antenna

connector

50 ohms micro str i p lin e

G N D G N D

Ground connection

Page 52 of 124

2.2 GSM/UMTS/LTE Antenna Interface

2.2.3.2 Routing Examples

Interface to RF Connector

Figure 19 shows a sample connection of a module‘s antenna pad at the bottom layer of the

module PCB with an application PCB‘s coaxial antenna connector. Line impedance depends on line width, but also on other PCB characteristics like dielectric, height and layer gap. The sample stripline width of 0.40mm is recommended for an application with a PCB layer stack resembling the one of the ALAS5V evaluation board. For different layer stacks the stripline width will have to follow stripline routing rules, avoiding 90 degree corners and using the shortest distance to the PCB’s coaxial antenna connector.



Figure 19: Routing to application‘s RF connector

ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Antenna

SC1 SC2

8...36V

-0.8V...+0.8V

0...5kHz

1.6Vpp

Ri=5Ohm

6k...12k

ANT

Page 53 of 124

2.2 GSM/UMTS/LTE Antenna Interface

2.2.4 RF Antenna Diagnostic

RF antenna (GSM/UMTS/LTE) diagnosis requires the implementation of an external antenna detection circuit. An example for such a circuit is illustrated in Figure 21. It allows to check the presence and the connection status of RF antennas.

To properly detect the antenna and verify its connection status the antenna feed point must have a DC resistance R

of 9k (±3k).

ANT

A positive or negative voltage drop (referred to as V

) on the ground line may occur without

disturb

having any impact on the measuring procedure and the measuring result. A peak deviation (V V

) of < 0.8V from ground is acceptable.

disturb

(peak) = ± 0.8V (maximum); f

disturb

= 0Hz … 5kHz

disturb

Waveform: DC, sinus, square-pulse, peak-pulse (width = 100µs) R

= 5

disturb

To make sure that the antenna detection operates reliably, the capacitance at the module’s antenna pad (i.e., the cable capacitance plus the antenna capacitance (C

)) should not be

ANT

greater than 1000pF. Some types of antennas (for example "inverted F antenna" or "half loop antenna") need an RF short circuit between the antenna structure and g round to work properly. In this case the RF short circuit has to be realized via a capacitance (C

) . For C

ANT

we rec-

ANT

ommend a capacitance lower than 100pF (see Figure 20).



Figure 20: Resistor measurement used for antenna detection

ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Antenna1..2

Ant

SC1 SC2

8..36V

-0.8V..+0.8V

0..5 kHz

1.6 Vpp

= 5 Ohm

6k..12k

ADC1..2_IN

L1 S1

ADC

GPIOx

BATT+

appr.

0.7V + V

BATT+

ANT_MAIN .. ANT_DRX_MIMO

Module

ANT1..2

Page 54 of 124

2.2 GSM/UMTS/LTE Antenna Interface

Figure 21 shows the basic principles of an antenna detection circuit that is able to detect an-

tennas and verify their connection status. The GPIO pads can be employed to enable the antenna detection, the ADCx_IN pads can be used to measure the voltage of external devices connected to these ADC input pads - thus determining R

values. The AT^SRADC write com-

ANT

mand configures the parameters required for ADC measurement and returns the measurement result(s) - for command details see [1].

Figure 21: Basic circuit for antenna detection

The following Table 14 lists possible signal states for the GPIOx signal lines in case these lines are configured and used for antenna detection. For GPIO configuration and control commands see [1].

Table 14: Possible GPIOx signal states if used for antenna diagnosis

Signal state Meaning

GPIOx:

Input Pull down or Output low Output high

Antenna detection control (S1 in above figure):

Off (diagnostic measurement is off) On (diagnostic measurement is on)



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.2 GSM/UMTS/LTE Antenna Interface

Page 55 of 124

Table 15 lists assured antenna diagnostic states depending on the measured R

that the R

ranges not mentioned in the below table, i.e., 1k...6k and 12k...40k are tol-

ANT

values. Note

ANT

erance ranges. Within these tolerance ranges a decision threshold for a diagnostic app lication may be located. For more details on the sample antenna detection circuit please refer to Sec-

tion 2.3.1.

Table 15: Assured antenna diagnostic states

Antenna state R

Normal operation, antenna connected (resistance at feed

range

ANT

= 6k…12k

ANT

point as required) Antenna pad short-circuited to GND R Antenna not properly connected, or resistance at antenna

= 0…1k

ANT

= 40k…

ANT

feed point wrong or not present Antenna pad is short-circuited to the supply voltage of the

max. 36V host application, for example the vehicle’s on-board power supply voltage

Measuring procedure for the basic circuit given in Figure 21:

The battery current flows through R1 and RA. The voltage drop on RA is divided by R3/(R3+R2) and measured by the ADCx_IN input. For the ADCx_IN voltage V AT^SRADC) and the BATT+ supply voltage V

(monitored using AT^SBV) several measur-

BATT+

ing samples should be taken for averaging. The measured and averaged value V

(monitored using

ADCx

will then

ADCx

be compared to three decision thresholds. The decision thresholds depend on BATT+:

Table 16: GSM/UMTS/LTE antenna diagnostic decision threshold

Decision threshold

Short to GND Appr. 0,176*V

No antenna Appr. 0,337*V

Short to power 0.146+0.405*V

1. The decision thresholds depends on BATT+ and has to be calculated separately for each decision (the BATT+ voltage level V

(580mV…738mV)

(1111mV…1414mV)

(1482mV…1888mV)

is known to the system: 3.3V < V

BATT+

ADCx

Result

 Short-circuited to ground  Antenna connected



> Antenna nor properly connected < > Short-circuited to power

< 4.2V).

BATT+



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

GNSS

Active GNSS

Antenna

Current Sensor

FAN4010

(3.2V)

ADC5_IN

GNSS

Receiver

Antenna

Matching

ANT_GNSS_DC

ANT_GNSS

Module

Application:

3k3

10k

ESD

Protection

LNA

100

1R0

LDO

BATT+

IN OUT

GNSS_EN

LP3985IM5-3.2

10k

Si1023X_1

Si1023X_2

Page 56 of 124

2.3 GNSS Antenna Interface

In addition to the RF antenna interface ALAS5V also has a GNSS antenna interface. See Sec-

tion 2.1.1 to find out where the GNSS antenna pad is located. The GNSS pad’s shape is the

same as for the RF antenna interface (see Section 2.2.2). It is possible to connect active or passive GNSS antennas. In either case they must have 50

impedance. The simultaneous operation of GSM/UMTS/LTE and GNSS is implemented. For electrical characteristics see Section 2.2.

ALAS5V provides the signal GNSS_EN to enable an active GNSS antenna power supply. Fig-

ure 22 shows the flexibility in realizing the power supply for an active GNSS antenna by g iving

a sample circuit realizing the supply voltage for an active GNSS antenna.



Figure 22: Supply voltage for active GNSS antenna

ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

GNSS_EN

ANT_GNSS

Passive

GNSS

antenna

10nH

100nF

To GNSS

receive r

Module

SMT in t erf ac e

ANT_GNSS_DC

(Optional)

ESD

protection

Not used

Page 57 of 124

2.3 GNSS Antenna Interface

Figure 23 shows a sample circuit realizing ESD protection for a passive GNSS antenna. Con-

necting the input ANT_GNSS_DC to GND prevents ESD from coupling into the module.

Figure 23: ESD protection for passive GNSS antenna

2.3.1 GNSS Antenna Diagnostic

GNSS antenna diagnosis does require an external detection circuit. The antenna DC supply current can be measured via ADC5_IN. The ADC5_IN input voltage (Ug) may be generated by a sample circuit shown in Figure 22. The circuit allows to check the presence and the connection status of an active GNSS antenna. Passive GNSS antennas cannot be detected. Therefore, GNSS antenna detection is only available in active GNSS antenna mode.

Having enabled the active GNSS antenna mode the presence and connection status of a n active GNSS antenna can be checked. The following table lists sample current ranges for possible antenna states as well as sample voltage ranges as possible decision thresholds to distinguish between the antenna connection states.

Table 17: Sample ranges of the GNSS antenna diagnostic measurements and their possible meaning

Antenna connection status Current ranges (IS)

Antenna not connected <1.4mA

Decision threshold 59mV ±20%

Antenna connected 2.2mA...20mA

Decision threshold 825mV ±20%

Antenna short circuited to ground >30mA

Voltage ranges (UG)

GNSS antenna detection is not possible because GNSS antenna power supply is switched off.

1. Please note that the mA ranges 1.4mA...2.2mA and 20mA...30mAare tolerance ranges. The decision threshold should be defined within these ranges.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.4 Sample Application

Page 58 of 124

2.4 Sample Application

Figure 24 shows a typical example of how to integrate an ALAS5V module with an applica tion.

The PWR_IND line is an open collector that needs an external pull-up resistor which connects to the voltage supply VCC µC of the microcontroller. Low state of the open collector pulls the PWR_IND signal low and indicates that the ALAS5V module is active, high level notifies the Power Down mode.

If the module is in Power Down mode avoid current flowing from any other source into the module circuit, for example reverse current from high state external control lines. Therefore, the controlling application must be designed to prevent reverse flow.

While developing SMT applications it is strongly recommended to provide test points for certain signals, i.e., lines to and from the module - for debug and/or test purposes. The SMT application should allow for an easy access to these signals. For details on how to implement test points see [3].

The EMC measures are best practice recommendations. In fact, an adequate EMC strategy for an individual application is very much determined by the overall layout and, especially, the position of components.

Some LGA pads are connected to clocks or high speed data streams that might interfere with the module’s antenna. The RF receiver would then be blocked at certain frequencies (self interference). The external application’s PCB tracks connected to these pads should therefore be well shielded or kept away from the antenna. This applies especially to the USB and UICC/ SIM interfaces.

Depending on the micro controller used by an external application ALAS5V‘s digital input and output lines may require level conversion. Section 2.4.2 shows a possible sample level conversion circuit.

The analog-to-digital converter (ADCx_IN lines) can be used for antenna diagnosis. A sample antenna detection circuit can be found in Figure 26 and Figure 27.

Disclaimer: No warranty, either stated or implied, is provided on the sample schematic diagram shown in

Figure 24 and the information detailed in this section. As functionality and compliance with na-

tional regulations depend to a great amount on the used electronic components and the individual application layout manufacturers are required to ensure adequate design and operating safeguards for their products using ALAS5V modules.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

USB_DP, USB_DN

CCVCC CCRST

CCCLK

CCIN

CCIO

SIM

220nF

1nF

GND

ANT_MAIN

BATT+

Main antenna

(GSM/UMTS/LTE)

Module

All SIM components should be close to card holder. Keep SIM wires low capacitive.

BATT+_RF

USB_SS...

47µF Ultra low ESR

GND

ANT_DRX_MIMO

Diversity antenna

(LTE)

EMERG _OFF

47k

IGT

47k

4 x 47µF

Ultra low ES R

NTC

Rechargeable

Lithium battery

Optional low

capacitance ESD

protection**

VUSB_IN

USB 2.0 HS

Mode

USB 3.0 SS

Mode

PCM2_...

PCM interface lines

Level

Controller

VDD (1.8V)

VCC µC

CCA

CCB

VEXT ( 1. 8V )

PWR_IND

100k

VCC µC

** See Section 2.1.8 for details on enhanced ESD protection

2.4 Sample Application

Page 59 of 124

Figure 24: ALAS5V sample application



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.4 Sample Application

Page 60 of 124

2.4.1 Prevent Back Powering

Because of the very low power consumption design, current flowing from any other source into the module circuit must be avoided in any case, for example reverse current from high state external control lines while the module is powered down. Therefore, the external application must be designed to prevent reverse current flow. Otherwise there is the risk of undefined states of the module during startup and shutdown or even of damaging the module. A simple solution preventing back powering is the usage of VEXT for level shifters, as Figure 25 shows. If level shifters are not really required, it is also possible to employ buffers.

While the module is in power down mode, VEXT must have a level lower than 0.3V after a certain time. If this is not the case the module is fed back by the application interface - recognizing such a fault state is possible by VEXT.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

5V tolerarant

Low level input

VCC

5V tolerant

VCC

E.g., 74VHC1GT50 74LV1T34

E.g.,

74LVC2G34

NC7WZ16

External application

Micro controller

VLOGIC

(3.0V...3.6V)

Input lines,

e.g., µRXD, µCTS

Output lines,

e.g., µTXD, µRTS

VEXT (1.8V)

Digital output lines, e.g., RXD0, CTS0

Wireless module

Digital input lines, e.g., TXD0, RTS0

VCCA

Wirel ess module

1DIR 2DIR

1A1 1A2 2A1 2A2

GND1 GND2

2B2

2B1

1B2

1B1

2OE

1OE

VCCB

E.g., 74AVC4T245

GNDGND

External A ppl i cation

CTS0D

RXD0D

RTS0D

TXD0D TXD0

RTS0 RXD0 CTS0

+3.0V VEXT (1.8V)

PWR_IND

GND

2 3

4 5 6 7

100k

+3.0V

Page 61 of 124

2.4 Sample Application

2.4.2 Sample Level Conversion Circuit

Depending on the micro controller used by an external application ALAS5V‘s digital input and output lines (i.e., ASC0 lines) may require level conversion. The following Figure 25 shows sample circuits with recommended level shifters for an external application‘s micro controller (with VLOGIC between 3.0V...3.6V). The level shifters can be used for digital input and output lines with V able for back powering protection.

max=1.85V or VIHmax =1.85V. The circuits recommend below would also be suit-



Figure 25: Sample level conversion circuits

ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

BATT+

ADC1_IN

ADC2_IN

BATT+

GND

BATT+ BATT+

ADC2_IN

GPIOx

ADC1_IN

ANT_MA IN

ANT1

Module

Antenna Detection Circuit

GPIOx

ANT_GNSS

Main antenna

GNSS Antenna

Separate single GND pin which is not used for module’s power supply

GNSS antenna pad

MAIN antenna pad

LGA

ADC5_IN

DRX_MIMO antenna pad

ANT_DRX_MIMO

ANT3

ANT2

RX Diversity/MIMO antenna

ADC5_IN

Page 62 of 124

2.4 Sample Application

2.4.3 Sample Circuit for Antenna Detection

The following figures explain how an RF antenna detection circuit may be implemented for ALAS5V to be able to detect connected antennas (for basic circuit and diagnostic principles including usage of GPIO and ADCx_IN pads - please refer to Section 2.2.4). Figure 26 gives a general overview, Figure 27 depicts the actual antenna detection layout and shows how ESD protection, i.e., the RF/DC bridge, will have to be handled.

Properties for the components mentioned in Figure 26 and Figure 27 are given in Table 18 - parts list.

Figure 26: Antenna detection circuit sample - Overview



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

BATT+

ADC2_INADC1_IN

Negat ive voltage lim it ation

Ov er voltage li m i tat i on

Level adaption

to ADC inputs

BATT+

GPIOx

Switchi ng on / off

of BATT +

ESD prot ect ion

Coupli ng resis tor

V1 V2

V3 V4

R3 R4

R5 R6

R7 R8

R10

R11

R12

R13 R14

ANT2

C1 C2

C3 C4

ANT1

Low pass f ilter

(DC insertion)

Overvoltage limitation

For component val ues see parts list

2.4 Sample Application

Page 63 of 124



Figure 27: Antenna detection circuit sample - Schematic

ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

2.4 Sample Application

Table 18: Antenna detection reference circuit - parts list

Reference Part Value Tolerance Conditions Size

R1,2 Resistor 22R

Page 64 of 124

R3,4 Resistor 10k > R5,6 Resistor 140k 1% R7,8 Resistor 100k 1% R9,10 Resistor 100k R11,12 Resistor 10k > R13,14 Resistor 4k4

(e.g., 2x2k2 or 4x1k1)

C1,2 Capacitor 22p 50V < C3,4 Capacitor 100n 50V C5,6 Capacitor 100n 10V

V1,2 Schottky diode RB520-40 40V V3,4,6,7 Transistor BC857 V5 Transistor BC847

L1,2 Inductor 39nH Wire wound

1% >

125mW

125mW 300mW

High Q

0402



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

3 GNSS Interface

Page 65 of 124

3 GNSS Interface

ALAS5V integrates a GNSS receiver that offers the full performance of GPS/GLONASS technology. The GNSS receiver is able to continuously track all satellites in view, thus providing accurate satellite position data.

The integrated GNSS receiver supports the NMEA protocol via USB or ASC0 interface. NMEA is a combined electrical and data specification for communication between various (marine) electronic devices including GNSS receivers. It has been defined and controlled by the US based National Marine Electronics Association. For more information on the NMEA Standard please refer to http://www.nmea.org.

Depending on the receiver’s knowledge of last position, current time and ephemeris data, th e receiver’s startup time (i.e., TTFF = Time-To-First-Fix) may vary: If the receiver has no knowledge of its last position or time, a startup takes considerably longer than if the receiver has still knowledge of its last position, time and almanac or has still access to valid ephemeris data and the precise time. For more information see Section 3.1.

By default, the GNSS receiver is switched off. It has to be switched on and configured.

Dead Reckoning Sync Line:

Dead reckoning solutions are used in (automotive) platforms to determine the (vehicles) location even when there is no GPS signal available (e.g. in tunnels, basement garages or even between high buildings in cities).

In addition to dead reckoning related NMEA sentences (for details see [1]: GNSS sentences), ALAS5V provides a dead reckoning synchronization line (DR_SYNC line) to be employed in external dead reckoning applications. DR_SYNC is derived from the GNSS signal clock as 1 pulse per second (1PPS) signal, with a frequency of 1Hz, an accuracy of +/-5 ms, and a high state pulse of 1ms. The DR_SYNC signal is provided as long as synchronized with the GNSS satellite clock, and continues after GNSS signal loss. DR_SYNC can be configured for the GPIO1 pad. For electrical characteristics see Table 22.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Page 66 of 124

3.1 GNSS Interface Characteristics

The following tables list general characteristics of the GNSS interface.

Table 19: GNSS properties

Parameter Conditions Min. Typical Max. Unit

Frequency

Tracking Sensitivity Open sky

Acquisition Sensitivity Open sky

Cold Start sensitivity GPS -145 dBm

Time-to-First-Fix (TTFF)

1. Conditions and measurements not yet finalized.

2. Only measured for GPS.

GPS 1575 1575.42 1585 MHz GLONASS 1597 1602 1607 Beidou

-- -- --

Galileo 1597 1575.42 1585

Active antenna or LNA

-159

dBm

Passive antenna:

GPS GLONASS

Beidou

Galileo

Active antenna or LNA

-156

-154

-150

-149

dBm

Passive antenna:

GPS GLONASS

Beidou

Galileo

-145

-140

GLONASS -140 Beidou

Galileo -140 Cold 25 32 s Warm 10 29 s



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

GNSS supply voltage level

GN SS s u p ply v o lta g e lev e l

GNSS supply voltage level

Page 67 of 124

3.1 GNSS Interface Characteristics

Through the external GNSS antenna DC feeding the module is able to supply an active GNSS antenna. The supply voltage level at the GNSS antenna interface depends on the GNSS configuration.

Table 20: Power supply for active GNSS antenna

Function Setting samples IO Signal form and level

GNSS active antenna supply Supply voltage with:

GNSS receiver off Active antenna off

Supply voltage with: GNSS receiver on Active antenna on SLEEP mode

Supply voltage with: GNSS receiver on Active antenna auto



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4 Operating Characteristics

Page 68 of 124

4 Operating Characteristics

4.1 Operating Modes

The table below briefly summarizes the various operating modes referred to throughout the document.

Table 21: Overview of operating modes

Mode Function

Normal operation

GSM / GPRS / UMTS / HSPA / LTE SLEEP

GSM / GPRS / UMTS / HSPA / LTE IDLE

GSM TALK/ GSM DATA

GPRS DATA GPRS data transfer in progress. Power consumption depends on net-

EGPRS DATA EGPRS data transfer in progress. Power consumption depends on net-

UMTS TALK/ UMTS DATA

HSPA DATA HSPA data transfer in progress. Power consumption depends on net-

LTE DATA LTE data transfer in prog ress. Power consumption depends on network

Power saving set automatically when no call is in progress and the USB connection is detached and no active communication via ASC0. Also, the GNSS active antenna mode has to be turned off or set to "auto"

Power saving disabled or an USB connection active , but no data tra nsfer in progress.

Connection between two subscribers is in progress. Power consumption depends on the GSM network coverage and several connection settings (e.g. DTX off/on, FR/EFR/HR, hopping sequences and antenna connection). The following applies when power is to be measured in TALK_GSM mode: DTX off, FR and no frequency hopping.

work settings (e.g. power control level), uplink / downlink data rates and GPRS configuration (e.g. used multislot settings).

work settings (e.g. power control level), uplink / downlink data rates and EGPRS configuration (e.g. used multislot settings).

UMTS data transfer in progress. Power consumption depends on network settings (e.g. TPC Pattern) and data transfer rate.

work settings (e.g. TPC Pattern) and data transfer rate.

settings, data transfer rates, and carrier aggregation/MIMO configuration.

Power Down

Airplane mode



Normal shutdown after sending the AT^SMSO command. Softwar e is not active. Interfaces are not accessible. Operating voltage (connected to BATT+) remains applied. Only a voltage regulator is active for powering the RTC, as long as operating voltage applied at BATT+ does not drop below approx. 1.4V.

Airplane mode shuts down the radio part of the mo dule, causes th e module to log off from the GSM/GPRS network and disables all AT commands whose execution requires a radio connection. Airplane mode can be controlled by AT command (see [1]).

ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

>100ms

InitialState

Functionacti ve

IGT Systemstartup ,commandInterfaceinitialization

BATT +

IGT

PWR_IN D

VEXT

EMERGOFF

USB

4.2 Power Up/Power Down Scenarios

Page 69 of 124

4.2 Power Up/Power Down Scenarios

In general, be sure not to turn on ALAS5V while it is beyond the safety limits of voltage and temperature stated in Section 6.1. ALAS5V immediately switches off after having started and detected these inappropriate conditions. In extreme cases this can cause permane nt damage to the module.

4.2.1 Turn on ALAS5V

When the ALAS5V module is in Power Down mode, it can be started to Normal mode by driving the IGT (ignition) line to ground. It is required to use an open drain/collector driver to avoid current flowing into this signal line. Pulling this signal low triggers a power-on sequence. To turn on ALAS5V, it is strongly recommended to keep IGT active low at least 100 milliseconds, even though under certain conditions a period of less than 100 milliseconds might be sufficient. After turning on ALAS5V, IGT should be set inactive to prevent the module from turning on again after a shut downby AT command or EMERG_OFF. For details on signal states during startup see also Section 4.2.2.

Figure 28: Power-on with IGT

Note: After power up IGT should remain high. Also note that with a USB connection the USB host may take some seconds to set up the virtual COM port connection.

After startup or mode change the following URCs are sent to every port able to receive AT commands indicating the module’s ready state (this may take up to approx. 32s):

• "^SYSSTART" indicates that the module has entered Normal mode.

• "^SYSSTART AIRPLANE MODE" indicates that the module has entered Airplane mode. These URCs notify the external application that the first ATcommand can be sent to the mod-

ule. If these URCs are not used to detect then the only way of checking the module’s ready state can be checked by polling, e.g., send characters (e.g. "at")until the module is respo nding.

Please note that on USB ports these URCs are only sent if the USB interface is in state 'configured', and with AT^SCFG= "MEopMode/ExpectDTR being enabled (see also Section 4.3) the connected USB host has signaled being ready to receive data.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.2 Power Up/Power Down Scenarios

Page 70 of 124

4.2.2 Signal States after First Startup

Table 22 describes the various states each interface signal passes through after startup and

during operation. Signals are in an initial state while the module is initializing. Once the startup initialization has

completed, i.e. when the software is running, all signals are in defined state. The state of several signals will change again once the respective interface is activated or configured by AT command.

Table 22: Signal states

Signal name Pad no. Reset phase

(ignition) 0 - 100ms

CCIN1 N19 PD PU PU PU CCRST1 L19 L L 1.8V/3V Data L CCIO1 J19 L L 1.8V/3V Data L CCCLK1 M19 PD PD PD --> 1.8V/3V CLK

CCIN2 N18 Tri PD --> PU PU --> Tri Tri CCRST2 K18 Tri PD PD --> L L CCIO2 J18 Tri PD PD --> L L CCCLK2 M18 Tri PD PD --> L L RXD0 F18 Tri PD --> PU PU --> Tri Tri TXD0 H19 Tri PD --> PU PU --> Tri Tri CTS0 G19 Tri PD --> PU PU --> Tri Tri RTS0 G20 Tri PD --> PU PU --> Tri Tri DSR0 F17 PD PD PD PD DTR0 F19 Tri PD PD PD DCD0 G18 PD PD --> PU --> PDPD PD

Hardware init 100ms - 5s

Firmware init 5s - 32s

--> L

System active >32s

RING0 J20 Tri PD --> PU PU PU RXD1 R9 Tri PD --> PU PU --> Tri Tri TXD1 R8 Tri PD --> PU PU --> Tri Tri CTS1 R7 Tri PD --> PU PU --> Tri Tri RTS1 R6 Tri PD --> PU PU --> Tri Tri DIN2 N9 Tri PU --> PD PD PD BCLK2 N10 Tri PD PD PD FSC2 N7 Tri PD PD PD MCLK P11 Tri PD PD PD DOUT2 N8 Tri PD PD PD I2CDAT1 M9 Tri PD --> PU PU PU I2CCLK1 M10 Tri PD --> PU PU PU EMERG_OFF F16 PD/PU PU PU PU PCIE_HOST_

RST PCIE_HOST_

WAKE PCIE_CLK_ REQ R14 Tri PD PD --> L L PCIE_CLK_P P16 Tri/PCIe Tri/PCIe 2 packets activity

R11 Tri PD --> L L L R10 Tri PD PD --> Tri Tri

Tri/PCIe

(11s and 13s)



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Page 71 of 124

4.2 Power Up/Power Down Scenarios

Table 22: Signal states

Signal name Pad no. Reset phase

(ignition) 0 - 100ms

PCIE_CLK_M P17 Tri/PCIe Tri/PCIe 2 packets activity

Hardware init 100ms - 5s

Firmware init 5s - 32s

System active >32s

Tri/PCIe

(11s and 13s)

PCIE_RX_P T12 Tri/PCIe Tri/PCIe 2 packets activity

Tri/PCIe

(11s and 13s)

PCIE_RX_M T13 Tri/PCIe Tri/PCIe 2 packets activity

Tri/PCIe

(11s and 13s)

PCIE_TX_P T15 Tri/PCIe Tri/PCIe 2 packets activity

Tri/PCIe

(11s and 13s)

PCIE_TX_M T16 Tri/PCIe Tri/PCIe 2 packets activity

Tri/PCIe

(11s and 13s) GPIO12 E12 Tri PD PD PD GPIO13 E11 Tri PD PD PD GPIO14 E10 Tri PD PD PD ANT_GNSS_ DC A17 L L L L GNSS_EN D13 PD PD PD PD ADC1_IN D10 Tri Tri Tri Tri ADC2_IN D11 Tri Tri Tri Tri ADC4_IN D8 Tri Tri Tri Tri ADC5_IN D9 Tri Tri Tri Tri JTAG_WD_

M8 Tri PD PD --> H H

DISABLE JTAG_TCK C18 L H H H JTAG_TMS D14 L H H H JTAG_TRST D15 Tri PD PD PD JTAG_TDI D16 L H H H JTAG_SRST D17 L H H H JTAG_TDO D18 L H H H JTAG_PS_

E13 Tri PD --> H H H

HOLD EMMC_D0 N15 Tri PD 50ms PU and 950ms PD50ms PU and

950ms PD

EMMC_D1 M14 Tri PD 50ms PU and 950ms PD50ms PU and

950ms PD

EMMC_D2 N14 Tri PD 50ms PU and 950ms PD50ms PU and

950ms PD

EMMC_D3 P14 Tri PD 50ms PU and 950ms PD50ms PU and

950ms PD EMMC_D4 N12 Tri L L L EMMC_D5 N13 Tri L L L EMMC_D6 M13 Tri L L L EMMC_D7 P12 Tri L L L EMMC_CLK P15 Tri PD --> L 50ms CLK and

950ms PD

50ms CLK and

950ms PD EMMC_CMD P13 Tri PD 50ms PU and 950ms PD50ms PU and

950ms PD EMMC_DETECT L7 Tri PD PD PD EMMC_PWR L15 L L 50ms 2.9V and

950ms L

50ms 2.9V and

950ms L



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Page 72 of 124

4.2 Power Up/Power Down Scenarios

Table 22: Signal states

Signal name Pad no. Reset phase

(ignition) 0 - 100ms

Hardware init 100ms - 5s

Firmware init 5s - 32s

System active

>32s

GPIO1 E8 Tri PD PD --> L L GPIO3 C17 Tri PD PD PD GPIO4 L20 Tri PD PD PD GPIO5 P6 Tri PD PD PD GPIO6 H18 Tri PU --> PD P D PD GPIO7 E9 Tri PD PD PD GPIO8 M20 Tri PD PD PD GPIO11 D12 Tri PD PD PD GPIO12 E12 Tri PD PD PD GPIO13 E11 Tri PD PD PD GPIO14 E10 Tri PD PD PD GPIO15 T9 Tri PD PD --> H (after 3s) H GPIO16 R17 Tri PD PD --> PU (after 28s) PU GPIO17 M7 Tri PD PD --> H (after 24s) H GPIO22 M15 T ri PD PD PD FwSwap T7 Tri PD PD PD USB_SSTX_P H16 Tri/USB Tri/USB Tri/USB Tri/USB USB_SSTX_N H17 Tri/USB Tri/USB Tri/USB Tri/USB USB_SSRX_P K16 Tri/USB Tri/USB Tri/USB Tri/USB USB_SSRX_N K17 Tri/USB Tri/USB Tri/USB Tri/USB USB_DP M16 Tri/USB Tri/USB Tri/USB Tri/USB USB_DN M17 Tri/USB Tri/USB Tri/USB Tri/USB VUSB_IN P18 L L L L IGT D19 PU PU PU PU PWR_IND R5 Tri L L L VEXT E18 L 1.8V 1.8V 1.8V

L = Low level H = High level I = Input O = Output

PD = Pull down resistor between 18k...65k PD(…k) = Pull down resistor with ...k PU = Pull up resistor between 18k...65k PU(…k) = Pull up resistor with ...k, Z = High impedance



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.2 Power Up/Power Down Scenarios

Page 73 of 124

4.2.3 Turn off or Restart ALAS5V

To switch off or restart the module the following procedures may be used:

• Software controlled shutdown procedure: Software controlledby sending an AT command over the serial application interface. See Section 4.2.3.1.

• Software controlled restart procedure: Software controlled by sending an AT commandover the serial application interface. See Section 4.2.3.2.

• Hardware controlled shutdown procedure: Hardware controlled shutdown by IGT line. See

Section 4.2.3.3.

• Hardware controlled shutdown or restart procedure: Hardware controlled shutdown or restart by EMERG_OFF line. See Section 4.2.3.4.

• Automatic shutdown (software controlled): See Section 4.2.4

- Takes effect if ALAS5V board temperature exceeds a critical limit.

4.2.3.1 Switch off ALAS5V Using AT Shutdown Command

The best and safest approach to powering down ALAS5V is to issue the AT^SMSO command. This procedure lets ALAS5V log off from the network and allows the software to enter into a secure state and save data before disconnecting the power supply. The mode is referred to as Power Down mode. After sending AT^SMSO do not enter any other AT commands. While powering down the module may still send some URCs. The AT command’s “OK” response indicates that the data has been stored non-volatile and the module will turn down in a few seconds. The complete power down procedure may take approx. 20s.To verify that the module definitely turned off, it is possible to monitor the PWR_IND signal. A high state of the PWR_IND signal line indicates that the module is being switched off as shown in Figure 29.

Be sure not to disconnect the supply voltage V

before the module’s switch off procedure

BATT+

has been completed. Otherwise you run the risk of losing data. Signal states during switch off are shown in Figure 29.

While ALAS5V is in Power Down mode the application interface is switched off and must not be fed from any other source. Therefore, your application must be designed to avoid any current flow into any digital signal lines of the application interface. No special care is required for the USB interface which is protected from reverse current.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

PWR_IND

Digital outputs

VEXT

Inputs dr iven by application

BATT+ driven by application

Start shutdown

Deregister from net work, system shut down

approx. 20s

4.2 Power Up/Power Down Scenarios

Page 74 of 124

Note 1: VEXT can be used in solutions to prevent back powering (see also Section 2.4.1).

It should have a level lower than 0.3V after module shutdown.

Note 2: After module shutdown by means of AT command, i.e., after the VEXT level went

below 0.3V, please allow for a time period of at least 1 second before restarting the module.

4.2.3.2 Restart ALAS5V Using AT Command

The best and safest approach to restart ALAS5V is by AT command. For more information on the AT^CFUN command please refer to is described in detail in [1].

Figure 29: Signal states during turn-off procedure



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

1 2

>32s

> 100ms >2.1s

1– TriggersswitchONroutine 2– TriggersswitchOFFroutine

IGT

4.2 Power Up/Power Down Scenarios

Page 75 of 124

4.2.3.3 Turn off ALAS5V Using IGT Line

The IGT line can be configured for use in two different switching modes: You can set the IGT line to switch on the module only, or to switch it on and off. The switching mode is determined by the parameter "MEShutdown/OnIgnition" of the AT^SCFG command.

By factory default, the ON/OFF switch mode of IGT is disabled:

AT^SCFG=”MEShutdown/OnIgnition” ^SCFG: "MEShutdown/OnIgnition","off" OK

# Query the current status of IGT. # IGT can be used only to switch on ALAS5V. IGT works as described in Section 4.2.1.

To configure IGT for use as ON/OFF switch:

AT^SCFG=”MEShutdown/OnIgnition”,”on” ^SCFG: "MEShutdown/OnIgnition","on" OK

# Enable the ON/OFF switch mode of IGT. # IGT can be used to switch on and off ALAS5V.

Take great care before changing the switching mode of the IGT line. To ensure that the IGT line works properly as ON/OFF switch it is of vital importance that the following conditions are met:

Switch-on condition: If the ALAS5V is off, the IGT line must be asserted for at least 100 milli-

seconds before being released.

Switch-off condition: If the ALAS5V is on, the IGT line must be asserted for at least 2.1 sec-

onds before being released. The module switches off after the line is released. The switch-off routine is identical with the procedure initiated by AT^SMSO, i.e. the software performs an orderly shutdown as described in Section 4.2.3.1. Before switching off the module wait at least 32 seconds after startup.

Figure 30: Timing of IGT if used as ON/OFF switch



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

EMERG_OFF

PWR_IND

BATT+

IGT

1) The time to Power Down mode (tPD) depends on the operating state, and can be up to 2000ms. PWR_IND should be monitored by the external application. Note that a low impulse at EMERG_OFF for more than 2000ms will reset the module’s RTC.

2) The the power supply voltage (BATT+) may be disconnected only after having reached Power Down mode as indicated by the PWR_IND signal going high. The power sup ply has to be a vailable (again) before the module is restarted.

EMERG_OFF

PWR_IND

BATT+

IGT

RESET

Module on

Module off

Module on

1) The time to module reset (t

RESET

) must be > 100ms

4.2 Power Up/Power Down Scenarios

Page 76 of 124

4.2.3.4 Turn off or Restart ALAS5V in Case of Emergency

Caution: Use the EMERG_OFF line only when, due to serious problems, the software is not responding for more than 5 seconds. Pulling the EMERG_OFF line causes the loss of all information stored in the volatile memory. Therefore, this procedure is intended only for use in case of emergency, e.g. if ALAS5V does not respond, if reset or shutdown via AT command fails.

The EMERG_OFF line is available on the application interface and can be used to turn off or to restart the module. In any case the EMERG_OFF line must be pulled to ground until the Power Down mode is reached, as indicated by PWR_IND=high. To control the EMERG_OFF line it is required to use an open drain / collector driver. EMERG_OFF is pulled high internally.

Now, to permanently turn off the module, the IGT line has to be set to high (inactive) before the EMERG_OFF line is released. The module will then switch off and needs to be restarted at a later time. This switch off behavior is shown in Figure 31.

Figure 31: Shutdown by EMERG_OFF signal

To simply restart the module, the IGT line has to continue to be driven low (active) for at least 100ms after having released the EMERG_OFF line. The module will then switch off an d restart automatically. This restart behavior is shown in Figure 32.



Figure 32: Restart by EMERG_OFF signal

ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Moduleswitchoff...

Waitforatleast25seconds

Switchedoff?

(PWR_IND=High?)

OK,

finished

Yes

ActivateEMERG_OFFline

Waitforatleast1second

OK,

finished

Yes

DisconnectBATT+

Switchedoff?

(PWR_IND=High?)

OK,

finished

SWcontrolled:Enter“AT^SMSO“

HWcontrolled:TurnoffusingIGTline

4.2 Power Up/Power Down Scenarios

Page 77 of 124

4.2.3.5 Overall Shutdown Sequence

In case the above described dedicated software or hardware controlled shutdown procedures fail or hang for some reason, it may become necessary to disconnect BATT+ in order to ultimately shut down the module. Figure 33 shows a flow chart that illustrates how an overall shutdown sequence might be implemented.

Figure 33: Overall shutdown sequence



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.2 Power Up/Power Down Scenarios

Page 78 of 124

4.2.4 Automatic Shutdown

Automatic shutdown takes effect if:

• The ALAS5V board is exceeding the critical limits of overtemperature or undertemperature

• Undervoltage or overvoltage is detected The automatic shutdown procedure is equivalent to the power down initiated with the AT^SMSO

command, i.e. ALAS5V logs off from the network and the software enters a secure state avoiding loss of data.

Alert messages transmitted before the device switches off are implemented as Unsolicited Result Codes (URCs). The presentation of the temperature URCs can be enabled or disabled with the command AT^SCTM. The URC presentation mode varies with the condition, please see

Section 4.2.4.1 to Section 4.2.4.4 for details. For further instructions on AT commands refer to [1].



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.2 Power Up/Power Down Scenarios

Page 79 of 124

4.2.4.1 Thermal Shutdown

The board temperature is constantly monitored by an internal NTC resistor located on the PCB. The values detected by the NTC resistor are measured directly on the board and the refore, are not fully identical with the ambient temperature.

Each time the board temperature goes out of range or back to normal, ALAS5V instantly displays an alert (if enabled).

• URCs indicating the level "1" or "-1" allow the user to take appropriate precautions, such as protecting the module from exposure to extreme conditions. The presentation of the URCs depends on settings selected with the AT^SCTM write command. AT^SCTM=1: Presentation of URCs is always enabled. AT^SCTM=0 (default): Presentation of URCs is enabled during the 2 minutes guard perio d after start-up of ALAS5V. After expiry of the 2 minutes guard period, the presentation will be disabled, i.e. no URCs with alert levels "1" or ''-1" will be generated.

• URCs indicating the level "2" and ”-2” are instantly followed by an orderly shutdown, except for cases described in Section 4.2.4.2. The presentation of these URCs is always enabled, i.e. they will be output even though the factory setting AT^SCTM=0 was never changed.

The (maximum) temperature ratings are stated in Section 4.5. Temperature limits and associated URCs are listed in the below Table 23.

Table 23: Board temperature warning and switch off level

Parameter Temperature URC Notes

High temperature switch off active > +97°C ^SCTM_B: 2 The possible deviation is typiHigh temperature switch off release < High temperature warning active > High temperature warning release < Operating temperature range -30°C...+85°C --Low temperature warning release > Low temperature warning active < Low temperature switch off release > Low temperature switch off active <

+96°C ^SCTM_B: 1 +86°C ^SCTM_B: 1 +85°C ^SCTM_B: 0

-30°C ^SCTM_B: 0 The possible deviation is typi-

-31°C ^SCTM_B: -1

-40°C ^SCTM_B: -1

-42°C ^SCTM_B: -2

cally ± 2°C.

The AT^SCTM command can also be used to check the present status of the board. Depending on the selected mode, the read command returns the current board temperature in degrees Celsius or only a value that indicates whether the board is within the safe or critical temperature range. See [1] for further instructions.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.2 Power Up/Power Down Scenarios

Page 80 of 124

4.2.4.2 Deferred Shutdown at Extreme Temperature Conditions

In the following cases, automatic shutdown will be deferred if a critical temperature limit is exceeded:

• While an emergency call is in progress.

• During a two minute guard period after power-up. This guard period has been introduced in order to allow for the user to make an emergency call. The start of any one of these calls extends the guard period until the end of the call. Any other network activity may be terminated by shutdown upon expiry of the guard time.

While in a "deferred shutdown" situation, ALAS5V continues to measure the temperature and to deliver alert messages, but deactivates the shutdown functionality. Once the 2 minute guard period is expired or the call is terminated, full temperature control will be resumed. If the temperature is still out of range, ALAS5V switches off immediately (without another alert message).

Caution: Automatic shutdown is a safety feature intended to prevent damage to the module. Extended usage of the deferred shutdown facilities provided may result in damage to the module, and possibly other severe consequences.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.2 Power Up/Power Down Scenarios

Page 81 of 124

4.2.4.3 Undervoltage Shutdown

If the measured battery voltage is no more sufficient to set up a call the following URC will be presented:

^SBC: Undervoltage.

The URC indicates that the module is close to the undervoltage threshold. If undervoltage persists the module keeps sending the URC several times before switching off automatically.

This type of URC does not need to be activated by the user. It will be output automatically when fault conditions occur.

4.2.4.4 Overvoltage Shutdown

The overvoltage shutdown threshold is 100mV above the maximum supply voltage V

BATT+

specified in Table 4. When the supply voltage approaches the overvoltage shutdown threshold the module will send

the following URC:

^SBC: Overvoltage warning

This alert is sent once. When the overvoltage shutdown threshold is exceeded the module will send the following URC

^SBC: Overvoltage shutdown

before it shuts down cleanly. This type of URC does not need to be activated by the user. It will be output automatically when

fault conditions occur. Keep in mind that several ALAS5V components are directly linked to BATT+ and, therefore, the

supply voltage remains applied at major parts of ALAS5V, even if the module is switched off. Especially the power amplifier is very sensitive to high voltage and might even be destroyed.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.3 Power Saving

Page 82 of 124

4.3 Power Saving

ALAS5V is able to reduce its functionality to a minimum (during the so-called SLEEP mode) in order to minimize its current consumption. The following sections explain the module’s network dependent power saving behavior. The power saving behavior is further configurable by AT command:

• AT^SCFG= "MEopMode/PwrSave": The power save mode is by default enabled. While inactive, the module stays in power save (SLEEP) state, waking up only upon any of the following events:

- Cyclically to meet basic technical demands, e.g. network requirements (such as regularly

listening to paging messages from the base station as described in Section 4.3.1, Section

4.3.2 and Section 4.3.3.

- Cyclically after expiry of a configured power saving period.

- Data at any interface port, e.g., URCs for incoming calls.

- A level state transition at GPIO3, GPIO5, GPIO7, GPIO8, or GPIO16 (if configured).

• AT^SCFG= "MEopMode/ExpectDTR": Power saving will take effect only if there is no transmission data pending on any of the module’s USB ports. The expect DTR AT command ensures that data becoming pending on any USB port before an external application has signaled its readiness to receive the data is discarded. By default this behavior is enabled for all available USB CDC ACM and CDC ECM ports.

• AT^SCFG="Radio/OutputPowerReduction": Output power reduction is possible for the module in GPRS multislot scenarios to reduce its output power according to 3GPP 45.005 section.

Please refer to [1] for more information on the above AT commands used to configure the module’s power saving behavior.

The implementation of the USB host interface also influences the module’s power saving behavior and therefore its current consumption. For more information see Section 2.1.3.

Another feature influencing the current consumption is the configuration of the GNSS antenna interface. For details see Section 3.1.

Also note that the module does not wake up from SLEEP mode just to measure the supply voltage, and that the command AT^SBV reports an average over the values it was able to measure last (see also Section 4.4.3). Therefore, the shorter the power saving periods are, the faster and more precisely will the reported average adjust to possible voltage changes.

4.3.1 Power Saving while Attached to GSM Networks

The power saving possibilities while attached to a GSM network depend on the paging timing cycle of the base station. The duration of a paging timing cycle can be calculate d using the following formula:

t = 4.615 ms (TDMA frame duration) * 51 (number of frames) * DRX value.

DRX (Discontinuous Reception) is a value from 2 to 9, resulting in paging timing cycles between 0.47 and 2.12 seconds. The DRX value of the base station is assigned by the GSM network operator.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.3 Power Saving

Page 83 of 124

Now, a paging timing cycle consists of the actual fixed length paging plus a variable length pause before the next paging. In the pauses between listening to paging messages, the module resumes power saving, as shown in Figure 34.

Figure 34: Power saving and paging in GSM networks

The varying pauses explain the different potential for power saving. The longer the pause the less power is consumed.

Generally, power saving depends on the module’s application scenario and may differ from the above mentioned normal operation. The power saving interval may be shorter than 0.47 seconds or longer than 2.12 seconds.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.3 Power Saving

Page 84 of 124

4.3.2 Power Saving while Attached to WCDMA Networks

The power saving possibilities while attached to a WCDMA network depend on the paging timing cycle of the base station.

During normal WCDMA operation, i.e., the module is connected to a WCDMA network, the duration of a paging timing cycle varies. It may be calculated using the following formula:

DRX value

t = 2

DRX (Discontinuous Reception) in WCDMA networks is a value between 6 and 9, thus resulting in paging timing cycles between 0.64 and 5.12 seconds. The DRX value of the base station is assigned by the WCDMA network operator.

* 10 ms (WCDMA frame duration).

Figure 35: Power saving and paging in WCDMA networks

The varying pauses explain the different potential for power saving. The longer the pause the less power is consumed.

Generally, power saving depends on the module’s application scenario and may differ from the above mentioned normal operation. The power saving interval may be shorter than 0.64 seconds or longer than 5.12 seconds.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.3 Power Saving

Page 85 of 124

4.3.3 Power Saving while Attached to LTE Networks

The power saving possibilities while attached to an LTE network depend on the paging timing cycle of the base station.

During normal LTE operation, i.e., the module is connected to an LTE network, the duration of a paging timing cycle varies. It may be calculated using the following formula:

t = DRX Cycle Value * 10 ms

DRX cycle value in LTE networks is any of the four values: 32, 64, 128 and 256, thus resulting in paging timing cycles between 0.32 and 2.56 seconds. The DRX cycle value of the base station is assigned by the LTE network operator.

Figure 36: Power saving and paging in LTE networks

The varying pauses explain the different potential for power saving. The longer the pause the less power is consumed.

Generally, power saving depends on the module’s application scenario and may differ from the above mentioned normal operation. The power saving interval may be shorter than 0.32 seconds or longer than 2.56 seconds.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

BATT+

2 2

Decoupling capacitors

e.g. 47µF X5R MLCC

GND

BATT+

BATT+_RF

Module

SMT interface

4.4 Power Supply

Page 86 of 124

4.4 Power Supply

ALAS5V needs to be connected to a power supply at the SMT application interface - 4 lines BATT+, and GND. There are two separate voltage domains for BATT+:

• BATT+_RF with 2 lines for the RF power amplifier supply

• BATT+ with 2 lines for the general power management.

The main power supply from an external application has to be a single voltage source and has to be expanded to two sub paths (star structure). Each voltage domain must be deco upled by application with low ESR capacitors ( as close as possible to LGA pads. Figure 37 shows a sample circuit for decoupling capacitors for BATT+.

> 47µF MLCC @ BATT+; > 4x47µF MLCC @ BATT+_RF)

Figure 37: Decoupling capacitor(s) for BATT+

The power supply of ALAS5V must be able to provide the peak current during the uplink transmission.

All key functions for supplying power to the device are handled by the power managemen t IC. It provides the following features:

• Stabilizes the supply voltages for the baseband using switching regulators a nd low drop linear voltage regulators.

• Switches the module's power voltages for the power-up and -down procedures.

• Delivers, across the VEXT line, a regulated voltage for an external application.

• LDO to provide SIM power supply.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Page 87 of 124

4.4 Power Supply

4.4.1 Power Supply Ratings

Table 24 and Table 25 assemble various voltage supply and current consumption ratings for

the supported modules. Possible ratings are preliminary and will have to be confirmed.

Table 24: Voltage supply ratings

Description Conditions Min Typ Max Unit

BATT+ Supply voltage Directly measured at Module.

Voltage must stay within the min/max values, including voltage drop, ripple, spikes

Maximum allowed voltage drop

Normal condition, power control level for

Pout max during transmit burst

Voltage ripple Normal condition, power control level for

Pout max

@ f <= 250 kHz

@ f > 250 kHz

3.3 3.8 4.2 V

400 mV

12090mV

pp pp



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.4 Power Supply

Table 25: Current consumption ratings

Description Conditions Typical rating Unit

BATT+

OFF State supply current

Average GSM supply current

Power Down RTC off

RTC on

SLEEP

@ DRX=9 (no communication with the module)

SLEEP

@ DRX=5 (no communication with the module)

SLEEP

@ DRX=2 (no communication with the module)

@ DRX=2

IDLE (UART/USB active, but no communication with the module)

Voice call GSM850/900; PCL=5

GPRS Data transfer GSM850/900; PCL=5; 1Tx/4Rx

GPRS Data transfer GSM850/900; PCL=5; 2Tx/3Rx

GPRS Data transfer GSM850/900; PCL=5; 4Tx/1Rx

USB disconnected USB connected USB disconnected USB connected USB disconnected USB suspend

USB disconnected USB suspend

USB disconnected USB active

 330 mA

@ 50

ROPR=8 (max. reduction)

ROPR=4 (no reduction)

ROPR=8 (max. reduction)

ROPR=4 (no reduction)

ROPR=8 (max. reduction)

ROPR=4 (no reduction)

@ total mismatch 1200

Page 88 of 124

30 µA 60 90

120

1.7 mA

13.2

1.9 mA

13.4

2.5 mA 14

60 mA 70

320 mA

430 mA

540

650 mA

980



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.4 Power Supply

Table 25: Current consumption ratings

Description Conditions Typical rating Unit

BATT+

Average GSM supply current

Peak current during GSM transmit burst

Average GSM supply current (GNSS on)

EDGE Data transfer GSM850/900; PCL=5; 1Tx/4Rx

ROPR=8 (max. reduction)

ROPR=4 (no reduction)

EDGE Data transfer GSM850/900; PCL=5; 2Tx/3Rx

ROPR=8 (max. reduction)

ROPR=4 (no reduction)

EDGE Data transfer GSM850/900; PCL=5; 4Tx/1Rx

ROPR=8 (max. reduction)

ROPR=4 (no reduction)

Voice call GSM1800/

 240 mA

@ 50

1900; PCL=0 GPRS Data transfer

GSM1800/1900; PCL=0; 1Tx/4Rx

ROPR=8 (max. reduction)

ROPR=4 (no reduction)

GPRS Data transfer GSM1800/1900; PCL=0; 2Tx/3Rx

ROPR=8 (max. reduction)

ROPR=4 (no reduction)

GPRS Data transfer GSM1800/1900; PCL=0; 4Tx/1Rx

ROPR=8 (max. reduction)

ROPR=4 (no reduction)

EDGE Data transfer GSM1800/1900; PCL=0; 1Tx/4Rx

ROPR=8 (max. reduction)

ROPR=4 (no reduction)

EDGE Data transfer GSM1800/1900; PCL=0; 2Tx/3Rx

ROPR=8 (max. reduction)

ROPR=4 (no reduction)

EDGE Data transfer GSM1800/1900; PCL=0; 4Tx/1Rx

ROPR=8 (max. reduction)

ROPR=4 (no reduction)

Voice call GSM850/900; PCL=5

Voice call GSM1800/ 1900; PCL=0

 2.2 A

@ 50 @ total mismatch 2.9

 1.5 A

@ 50 @ total mismatch 1.7

GSM active (UART/USB active); @ DRX=2 & GNSS NMEA output off

GSM active (UART/USB active); @ DRX=2 & GNSS NMEA output on

Page 89 of 124

220 mA

340 mA

360

600 mA

630

230 mA

340 mA

390

500 mA

690

190 mA

300 mA

330

470 mA

630

80 mA



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.4 Power Supply

Table 25: Current consumption ratings

Description Conditions Typical rating Unit

BATT+

Average UMTS supply current

Voice calls and Data transfers measured @ maximum Pout

Average UMTS supply current (GNSS on)

SLEEP (no communication with the module)

IDLE (UART/USB active, but no communication with the module)

UMTS Data transfer Band I

UMTS Data transfer Band II

UMTS Data transfer Band III

UMTS Data transfer Band IV

UMTS Data transfer Band V/VI/XIX

UMTS Data transfer Band VIII

WCDMA active (UART / USB active); @ DRX=6 & GNSS NMEA output off

WCDMA active (UART / USB active); @ DRX=6 & GNSS NMEA output on

@ DRX=9

@ DRX=8

@ DRX=6

USB disconnected USB suspend

USB disconnected USB active



@ 50 @ total mismatch



@ 50 @ total mismatch



@ 50 @ total mismatch



@ 50 @ total mismatch



@ 50 @ total mismatch



@ 50 @ total mismatch

Page 90 of 124

1.6 mA

13.1

1.8 mA

13.3

2.3 mA

13.8 60 mA

600 mA 810

600 mA 890

640 mA 820

640 mA 790

590 mA 690

530 mA 620

80 mA



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.4 Power Supply

Table 25: Current consumption ratings

Description Conditions Typical rating Unit

BATT+

Average LTE supply current (FDD)

Data transfers measured @ maximum Pout

Average LTE supply current (FDD) (GNSS on)

SLEEP

Occasions" = 256 SLEEP

Occasions" = 128 SLEEP

Occasions" = 64 SLEEP

Occasions" = 32 IDLE

active, but no communication with the module)

LTE Data transfer Band 1

LTE Data transfer Band 2

LTE Data transfer Band 3

LTE Data transfer Band 4

LTE Data transfer Band 5, 18, 19

LTE Data transfer Band 7

LTE Data transfer Band 8

LTE Data transfer Band 12

LTE Data transfer Band 20

LTE Data transfer Band 26

LTE Data transfer Band 28

LTE Data transfer Band 66

LTE active (UART/USB active); IDLE; NMEA output off

LTE active (UART/USB active); IDLE; NMEA output on

@ "Paging

(UART/USB

USB disconnected USB suspend USB disconnected USB suspend USB disconnected USB suspend USB disconnected USB suspend USB disconnected USB active



@ 50 @ total mismatch



@ 50 @ total mismatch

 620 mA

@ 50

@ total mismatch



@ 50 @ total mismatch



@ 50 @ total mismatch



@ 50 @ total mismatch



@ 50 @ total mismatch



@ 50 @ total mismatch



@ 50 @ total mismatch



@ 50 @ total mismatch



@ 50 @ total mismatch



@ 50 @ total mismatch

Page 91 of 124

1.9 mA

13.5

2.3 mA

13.9

2.9 mA

14.5

4.0 mA

15.2 55 mA 65

630 mA 790

630 mA 880

690 660 mA

750 560 mA

590 770 mA

800 550 mA

600 520 mA

590 540 mA

620 510 mA

570 620 mA

690 600 mA

680 110 mA

110 mA



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.4 Power Supply

Table 25: Current consumption ratings

Description Conditions Typical rating Unit

BATT+

Average LTE supply current (TDD)

Data transfers measured @ maximum Pout

Peak LTE current (TDD)

SLEEP

Occasions" = 256 SLEEP

Occasions" = 128 SLEEP

Occasions" = 64 SLEEP

Occasions" = 32 IDLE

active, but no communication with the module)

LTE Data transfer Band 38

LTE Data transfer Band 39

LTE Data transfer Band 40

LTE Data transfer Band 41

LTE Band 39

LTE Band 38 / 40 / 41

@ "Paging

(UART/USB

USB disconnected USB suspend USB disconnected USB suspend USB disconnected USB suspend USB disconnected USB suspend USB disconnected USB active

1 UL / 8 DL 6 UL / 2 DL 1 UL / 8 DL 6 UL / 2 DL 1 UL / 8 DL 6 UL / 2 DL 1 UL / 8 DL 6 UL / 2 DL



@ 50 @ total mismatch @ 50



@ total mismatch

Page 92 of 124

1.9 mA

13.5

2.3 mA

13.9

2.9 mA

14.5

4.0 mA

15.2 55 mA 65

230 mA 490 200 mA 410 210 mA 430 240 mA 530 480 mA

580 640 mA

850



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.4 Power Supply

Table 25: Current consumption ratings

Description Conditions Typical rating Unit

BATT+

Average TDSCDMA supply current (GNSS off)

Data transfers measured @ maximum Pout

SLEEP (no communication with the module)

IDLE (UART/USB active, but no communication with the module)

TD-SCDMA Data transfer Band 34 (Band A) 210 mA TD-SCDMA Data transfer Band 39 (Band F) 210 mA

BATT+

Average TDSCDMA supply current (GNSS on)

VUSB_IN

USB typical and maximum ratings are mentioned in Table 4: VUSB_IN.

1. With an impedance of Z Down ratings that were measured at 3.4V.

2. Measurements start 6 minutes after switching ON the module, Averaging times: SLEEP mode - 3 minutes, transfer modes - 1.5 minutes Communication tester settings:no neighbor cells, no cell reselection etc, RMC (Reference Measurement Channel)

3. The power save mode is disabled via configuration command

4. One fix per second.

5. Communication tester settings:

- Channel Bandwidth: 5MHz

- Number of Resource Blocks: 25 (DL), 1 (UL)

- Modulation: QPSK

TD-SCDMA active (UART / USB active) IDLE @ DRX=6, NMEA output off

TD-SCDMA active (UART / USB active) IDLE @ DRX=6, NMEA output on

LOAD

@ DRX=9

USB disconnected USB suspend

@ DRX=8

USB disconnected USB suspend

@ DRX=6

USB disconnected USB suspend

USB disconnected USB active

=50 at the antenna pads. Measured at 25°C and 4.2V - except for Power

Page 93 of 124

1.6 mA

13.1

1.8 mA

13.3

2.3 mA

13.8 60 mA

80 mA



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.4 Power Supply

Page 94 of 124

4.4.2 Minimizing Power Losses

When designing the power supply for your application please pay specific attention to power losses. Ensure that the input voltage V even in a transmit burst where current consumption can rise to typical peaks of 2A. It should be noted that ALAS5V switches off when exceeding these limits. Any voltage drops that may occur in a transmit burst should not exceed 400mV to ensure the expected RF performance in 2G networks.

never drops below 3.3V on the ALAS5V board, not

BATT+

The module switches off if the minimum battery voltage (V Example:

VImin = 3.3V Dmax = 0.4V

min = VImin + Dmax

BATT

min = 3.3V + 0.4V = 3.7V

BATT

Figure 38: Power supply limits during transmit burst

min) is reached.

BATT

4.4.3 Monitoring Power Supply by AT Command

To monitor the supply voltage you can use the AT^SBV command which returns the averaged value related to BATT+ and GND at the SMT application interface.

As long as not in SLEEP mode, the module measures the voltage periodically every 110 milliseconds. The maximum time the module remains in SLEEP mode can be limited with a the AT command AT^SCFG=”MeOpMode/PwrSave” (see [1]). The displayed voltage (in mV) is an average of the last eight measurement results before the power supply query.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Module PCB

Thermal conducting

gap filler

Heat

source

Module Shielding

Component LGA mounting

Air gap

Reference point PCB temperature

Application

PCB

Heat dissipation

Reference point ambient temperature

LGA mounting

Heat sink

Page 95 of 124

4.5 Operating Temperatures

Table 26: Board temperature

Parameter Min Typ Max Unit

Operating temperature range -30 +25 +85 °C Restricted temperature range Automatic shutdown

Temperature measured on ALAS5V board

1. Restricted operation allows normal mode data transmissions for limited time until automatic thermal shutdown takes effect. Within the restricted temperature range (outside the operating temperature range) the specified electrical characteristics may be in- or decreased.

2. Due to temperature measurement uncertainty, a tolerance on th e stated shutdown thresholds may occur. The possible deviation is in the range of ± 2°C at the overtemperature limit.

See also Section 4.2.4.1 for information about the NTC for on-board temperature measurement, automatic thermal shutdown and alert messages.

-40 +95 °C

<-40 --- >+95 °C

Note that within the specified operating temperature ranges the board temperature may vary to a great extent depending on operating mode, used frequency band, radio output power and current supply voltage. Note also the differences and dependencies that usually exist between board (PCB) temperature and ambient temperature as shown in the following Figure 39. The possible ambient temperature range depends on the mechanical application design including the module and the PCB with its size and layout. A thermal solution will have to take t hese differences into account and should therefore be an integral part of application design.

Figure 39: Board and ambient temperature differences



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

4.6 Electrostatic Discharge

Page 96 of 124

4.6 Electrostatic Discharge

The module is not protected against Electrostatic Discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates a ALAS5V module.

Special ESD protection provided on ALAS5V: BATT+: Inductor/capacitor An example for an enhanced ESD protection for the SIM interface is shown in Section 2.1.8.

The remaining interfaces of ALAS5V with the exception of the antenna interface are not accessible to the user of the final product (since they are installed within the device) and are therefore only protected according to the ANSI/ESDA/JEDEC JS-001-2011 requirements.

ALAS5V has been tested according to the following standards. Electrostatic values can be gathered from the following table.

Table 27: Electrostatic values

Specification / Requirements Contact discharge Air discharge ANSI/ESDA/JEDEC JS-001-2014

All SMT interfaces ± 1kV Human Body Model n.a.

ANSI/ESDA/JEDEC JS-002-2014

All SMT interfaces ± 250V Charged Device Model (CDM) n.a.

ETSI EN 301 489-1/7

Antenna pads n.a. ± 8kV

Note: The values may vary with the individual application design. For example, it matters whether or not the application platform is grounded over external devices like a computer or other equipment.

4.7 Reliability Characteristics

TBD.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description

Top view

Bottom view

5 Mechanical Dimensions and Mounting

107

5 Mechanical Dimensions and Mounting

5.1 Mechanical Dimensions of ALAS5V

Page 97 of 124

Figure 40 shows a 3D view1 of ALAS5V and provides an overview of the board's mechanical

dimensions Length: 40mm Width: 36mm Height: 3mm

. For further details see Figure 41.



Figure 40: ALAS5V – top and bottom view

1. The coloring of the 3D view does not reflect the module’s real color.

2. Note: The holes in the shielding (top view) are significantly smaller than the radiated wavelength from the module. Gemalto guarantees that there will be no emissions outside the limits from these. The RF circuitry of the module is fully shielded.

ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description





[[





[[



ERWWRPYLHZ

WRSYLHZ

QRVROGHUSDGVNHHSDUHDIUHH

















 

       

7 5 3 1

/ .

) ( '























5.1 Mechanical Dimensions of ALAS5V

107

Page 98 of 124

Figure 41: Dimensions of ALAS5V (all dimensions in mm)



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description





[ [









[[



PP[PP PP[PP

3$''LPHQVLRQ

PP[PP

PP

7RSYLHZ

/DQGSDWWHUQ

5.2 Mounting ALAS5V onto the Application Platform

107

Page 99 of 124

5.2 Mounting ALAS5V onto the Application Platform

This section describes how to mount ALAS5V onto the PCBs, including land pattern and stencil design, board-level characterization, soldering conditions, durability and mechanical handling. For more information on issues related to SMT module integration see also [3].

Note: Gemalto strongly recommends to solder all connecting pads for mechanical stability and heat dissipation. Not only must all supply pads and signals be connected appropriately, but all pads denoted as “Do not use“ should also be soldered (but not electrically connected). Note also that in order to avoid short circuits between signal tracks on an exte rnal application's PCB and various markings at the bottom side of the module, it is recommended not to route the signal tracks on the top layer of an external PCB directly under the module, or at least to ensure that signal track routes are sufficiently covered with solder resist.

5.2.1 SMT PCB Assembly

5.2.1.1 Land Pattern and Stencil

The land pattern and stencil design as shown below is based on Gemalto M2M characterizations for lead-free solder paste on a four-layer test PCB and a 110 micron-thick stencil.

The land pattern given in Figure 42 reflects the module‘s pad layout, including signal pads and ground pads (for pad assignment see Section 2.1.1). Besides these pads there are ground areas on the module's bottom side that must not be soldered, e.g., the po sition marker . To p revent short circuits, it has to be ensured that there are no wires on the external application side that may connect to these module ground areas.



Figure 42: Land pattern (top layer)

ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Cinterion® ALAS5V Hardware Interface Description









[ [





[



[



PP[PP

PP

PP[PP

3$''LPHQVLRQ

PP[PP

7RSYLHZ

6WHQFLO

5.2 Mounting ALAS5V onto the Application Platform

107

Page 100 of 124

The stencil design illustrated in Figure 43 is recommended by Gemalto M2M as a result of extensive tests with Gemalto M2M Daisy Chain modules.

Figure 43: Recommended design for 110 micron thick stencil (top layer)

5.2.1.2 Board Level Characterization

Board level characterization issues should also be taken into account if devising an SMT process.

It is recommended to characterize land patterns before an actual PCB production, taking individual processes, materials, equipment, stencil design, and reflow profile into account. For land and stencil pattern design recommendations see also Section 5.2.1.1. Optimizing the solder stencil pattern design and print process is necessary to ensure print uniformity, to decrease solder voids, and to increase board level reliability.

Daisy chain modules for SMT characterization are available on request. For details refer to [3]. Generally, solder paste manufacturer recommendations for screen printing process parame-

ters and reflow profile conditions should be followed. Maximum ratings are described in Section

5.2.3.



ALAS5V_HID_v00.030a 2019-03-20

Confidential / Preliminary

Gemalto M2M ALAS5V W User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Tables

Figures

1 Introduction

1.1 Product Variants

1.2 Key Features at a Glance

1.2.1 Supported Frequency Bands

1.2.2 Supported CA Configurations

1.3 ALAS5V System Overview

1.4 Circuit Concept

2 Interface Characteristics

2.1 Application Interface

2.1.1 Pad Assignment

2.1.2 Signal Properties

2.1.2.1 Absolute Maximum Ratings

2.1.3 USB Interface

2.1.4 Serial Interface ASC0

2.1.5 Serial Interface ASC1

2.1.6 Inter-Integrated Circuit Interface

2.1.7 UICC/SIM/USIM Interface

2.1.8 Enhanced ESD Protection for SIM Interfaces

2.1.9 Digital Audio Interface

2.1.9.1 Pulse Code Modulation Interface (PCM)

2.1.9.2 Inter-IC Sound Interface

2.1.10 Analog-to-Digital Converter (ADC)

2.1.11 RTC Backup

2.1.12 GPIO Interface

2.1.13 Control Signals

2.1.13.1 PWR_IND Signal

2.1.13.2 Remote Wakeup

2.1.13.3 Firmware Swap

2.1.14 JTAG Interface

2.1.15 eMMC Interface

2.1.15.1 eMMC Power Supply

2.2 GSM/UMTS/LTE Antenna Interface

2.2.1 Antenna Interface Specifications

2.2.2 Antenna Installation

2.2.3 RF Line Routing Design

2.2.3.1 Line Arrangement Instructions

2.2.3.2 Routing Examples

2.2.4 RF Antenna Diagnostic

2.3 GNSS Antenna Interface

2.3.1 GNSS Antenna Diagnostic

2.4 Sample Application

2.4.1 Prevent Back Powering

2.4.2 Sample Level Conversion Circuit

2.4.3 Sample Circuit for Antenna Detection

3 GNSS Interface

3.1 GNSS Interface Characteristics

4 Operating Characteristics

4.1 Operating Modes

4.2 Power Up/Power Down Scenarios

4.2.1 Turn on ALAS5V

4.2.2 Signal States after First Startup

4.2.3 Turn off or Restart ALAS5V

4.2.3.1 Switch off ALAS5V Using AT Shutdown Command

4.2.3.2 Restart ALAS5V Using AT Command

4.2.3.3 Turn off ALAS5V Using IGT Line

4.2.3.4 Turn off or Restart ALAS5V in Case of Emergency

4.2.3.5 Overall Shutdown Sequence

4.2.4 Automatic Shutdown

4.2.4.1 Thermal Shutdown

4.2.4.2 Deferred Shutdown at Extreme Temperature Conditions

4.2.4.3 Undervoltage Shutdown

4.2.4.4 Overvoltage Shutdown

4.3 Power Saving

4.3.1 Power Saving while Attached to GSM Networks

4.3.2 Power Saving while Attached to WCDMA Networks

4.3.3 Power Saving while Attached to LTE Networks

4.4 Power Supply

4.4.1 Power Supply Ratings

4.4.2 Minimizing Power Losses

4.4.3 Monitoring Power Supply by AT Command

4.5 Operating Temperatures

4.6 Electrostatic Discharge

4.7 Reliability Characteristics