GE P642, P643, P645 Technical Manual

GE Energy Connections
Grid Solutions

MiCOM P40 Agile

P642, P643, P645

Technical Manual
T

ransformer Protection IED

Hardware Version: M, P
Software Version: 06
Publication Reference: P64x-TM-EN-1.3

Contents

Chapter 1 Introduction 1

1 Chapter Overview 3
2 Foreword 4

2.1 Target Audience 4

2.2 Typographical Conventions 4

2.3 Nomenclature 5

3 Product Scope 6

3.1 Product Versions 6

3.2 Ordering Options 7

4 Features and Functions 8

4.1 Protection Functions 8

4.2 Control Functions 8

4.3 Measurement Functions 9

4.4 Communication Functions 9

5 Compliance 10
6 Functional Overview 11

Chapter 2 Safety Information 13

1 Chapter Overview 15
2 Health and Safety 16
3 Symbols 17
4 Installation, Commissioning and Servicing 18

4.1 Lifting Hazards 18

4.2 Electrical Hazards 18

4.3 UL/CSA/CUL Requirements 19

4.4 Fusing Requirements 19

4.5 Equipment Connections 20

4.6 Protection Class 1 Equipment Requirements 20

4.7 Pre-energisation Checklist 21

4.8 Peripheral Circuitry 21

4.9 Upgrading/Servicing 22

5 Decommissioning and Disposal 23
6 Standards Compliance 24

6.1 EMC Compliance: 2004/108/EC 24

6.2 Product Safety: 2006/95/EC 24

6.3 R&TTE Compliance 24

6.4 UL/CUL Compliance 24

6.5 ATEX Compliance 24

Chapter 3 Hardware Design 27

1 Chapter Overview 29
2 Hardware Architecture 30
3 Mechanical Implementation 31

3.1 Housing Variants 31

3.2 List of Boards 32

4 Front Panel 34

4.1 Front Panel 34

4.1.1 Front Panel Compartments 34

4.1.2 HMI Panel 35

4.1.3 Front Serial Port (SK1) 35

4.1.4 Front Parallel Port (SK2) 36

4.1.5 Fixed Function LEDs 36

Contents P64x

4.1.6 Function Keys 36

4.1.7 Programable LEDs 37

5 Rear Panel 38
6 Boards and Modules 40

6.1 PCBs 40

6.2 Subassemblies 40

6.3 Main Processor Board 41

6.4 Power Supply Board 42

6.4.1 Watchdog 44

6.4.2 Rear Serial Port 45

6.5 Input Module - 1 Transformer Board 46

6.5.1 Input Module Circuit Description 47

6.5.2 Frequency Response 48

6.5.3 Transformer Board 49

6.5.4 Input Board 50

6.6 Standard Output Relay Board 51

6.7 IRIG-B Board 52

6.8 Fibre Optic Board 53

6.9 Rear Communication Board 54

6.10 Ethernet Board 54

6.11 Redundant Ethernet Board 56

6.12 RTD Board 58

6.13 CLIO Board 59

6.14 High Break Output Relay Board 61

Chapter 4 Software Design 63

1 Chapter Overview 65
2 Sofware Design Overview 66
3 System Level Software 67

3.1 Real Time Operating System 67

3.2 System Services Software 67

3.3 Self-Diagnostic Software 67

3.4 Startup Self-Testing 67

3.4.1 System Boot 67

3.4.2 System Level Software Initialisation 68

3.4.3 Platform Software Initialisation and Monitoring 68

3.5 Continuous Self-Testing 68

4 Platform Software 70

4.1 Record Logging 70

4.2 Settings Database 70

4.3 Interfaces 70

5 Protection and Control Functions 71

5.1 Acquisition of Samples 71

5.2 Frequency Tracking 71

5.3 Direct Use of Sample Values 71

5.4 Fourier Signal Processing 71

5.5 Programmable Scheme Logic 72

5.6 Event Recording 73

5.7 Disturbance Recorder 73

5.8 Fault Locator 73

5.9 Function Key Interface 73

Chapter 5 Configuration 75

1 Chapter Overview 77
2 Using the HMI Panel 78

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2.1 Navigating the HMI Panel 79

2.2 Getting Started 79

2.3 Default Display 80

2.4 Default Display Navigation 81

2.5 Password Entry 82

2.6 Processing Alarms and Records 82

2.7 Menu Structure 83

2.8 Changing the Settings 84

2.9 Direct Access (The Hotkey menu) 85

2.9.1 Setting Group Selection Using Hotkeys 85

2.9.2 Control Inputs 85

2.10 Function Keys 86

3 Configuring the Data Protocols 88

3.1 Courier Configuration 88

3.2 DNP3 Configuration 89

3.2.1 DNP3 Configurator 90

3.3 IEC 60870-5-103 Configuration 91

3.4 MODBUS Configuration 92

3.5 IEC 61850 Configuration 93

3.5.1 IEC 61850 Configuration Banks 94

3.5.2 IEC 61850 Network Connectivity 94

4 Date and Time Configuration 95

4.1 Time Zone Compensation 95

4.2 Daylight Saving Time Compensation 95

5 Phase Rotation 96

5.1 CT and VT Reversal 96

Chapter 6 Transformer Differential Protection 97

1 Chapter Overview 99
2 Transformer Differential Protection Principles 100

2.1 Through Fault Stability 100

2.2 Bias Current Compensation 100

2.3 Three-phase Transformer Connection Types 101

2.4 Phase and Amplitude Compensation 104

2.5 Zero Sequence Filtering 105

2.6 Magnetising Inrush Restraint 105

2.7 Overfluxing Restraint 106

3 Implementation 107

3.1 Defining the Power Transformer 107

3.2 Selecting the Current Inputs 107

3.3 Phase Correction 108

3.4 Ratio Correction 108

3.5 CT Parameter Mismatch 109

3.6 Setting up Zero Sequence Filtering 110

3.7 Tripping Characteristics 110

3.7.1 High-Set Function 111

3.7.2 Circuitry Fail Alarm 111

3.8 Tripping Characteristic Stability 112

3.8.1 Maximum Bias 112

3.8.2 Delayed Bias 112

3.8.3 Transient Bias 112

3.8.4 CT Saturation Technique 113

3.8.5 No Gap Detection Technique 113

3.8.6 External Fault Detection Technique 113

3.8.7 Current Transformer Supervision 114

3.8.8 Circuitry Fail Alarm 115

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3.9 Differential Biased Trip Logic 116

4 Harmonic Blocking 117

4.1 2nd Harmonic Blocking 117

4.2 2nd Harmonic Blocking Logic 118

4.3 5th Harmonic Blocking Implementation 118

4.4 5th Harmonic Setting Guideline 119

4.5 Geomagnetic Disturbances 119

4.6 Overall Harmonic Blocking Logic 119

5 Application Notes 121

5.1 Setting Guidelines 121

5.2 Example 1: Two-winding Transformer - No Tap Changer 122

5.3 Example 2: Autotransformer with Loaded Delta Winding 124

5.4 Example 3: Autotransformer with Unloaded Delta Winding 127

5.5 Setting Guidelines for Short-Interconnected Biased Differential Protection 130

5.6 Setting Guidelines for Shunt Reactor Biased Differential Protection 133

5.7 Setting Guidelines for using Spare CT Inputs 135

5.8 Setting Guidelines for Reference Vector Group 136

5.9 Stub Bus Application 137

5.9.1 Stub Bus Implementation 137

5.9.2 Stub Bus Scheme 138

5.10 Transformer Differential Protection CT Requirements 138

5.10.1 CT Requirements - Transformer Application 138

5.10.2 CT Requirements - Small Busbar Application 139

Chapter 7 Transformer Condition Monitoring 141

1 Chapter Overview 143
2 Thermal Overload Protection 144

2.1 Thermal Overload Implementation 144

2.1.1 Thermal Overload Bias Current 145

2.2 The Thermal Model 146

2.2.1 Top Oil Temperature Caculations 146

2.2.2 Hotspot Caculations 146

2.2.3 Thermal State Measurement 147

2.3 Application Notes 147

2.3.1 Alstom Recommendations 147

2.3.2 IEEE Recommendations 147

2.3.3 Data Provided by Transformer Manufacturers 148

3 Loss of Life Statistics 150

3.1 Loss of Life Implementation 150

3.1.1 Loss of Life Calculations 150

3.2 Application Notes 152

3.2.1 LOL Setting Guidelines 152

3.2.2 Example 152

4 Through Fault Monitoring 154

4.1 Through Fault Monitoring Implementation 154

4.2 Through Fault Monitoring Logic 155

4.3 Application Notes 155

4.3.1 TFM Setting Guidelines 155

5 RTD Protection 157

5.1 RTD Protection Implementation 157

5.2 RTD Logic 158

5.3 Application Notes 158

5.3.1 Setting Guidelines for RTD Protection 158

6 CLIO Protection 159

6.1 Current Loop Input Implementation 159

6.2 Current Loop Input Logic 161

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6.3 CLO Implementation 161

6.4 Application Notes 163

6.4.1 CLI Setting Guidelines 163

6.4.2 CLO Setting Guidelines 163

Chapter 8 Restricted Earth Fault Protection 165

1 Chapter Overview 167
2 REF Protection Principles 168

2.1 Resistance-Earthed Star Windings 169

2.2 Solidly-Earthed Star Windings 169

2.3 Through Fault Stability 170

2.4 Restricted Earth Fault Types 170

2.4.1 Low Impedance REF Principle 170

2.4.2 High Impedance REF Principle 171

3 Restricted Earth Fault Protection Implementation 173

3.1 Enabling REF Protection 173

3.2 Selecting the Current Inputs 173

3.3 Low Impedance REF 174

3.3.1 Setting the Bias Characteristic 174

3.3.2 Delayed Bias 175

3.3.3 Transient Bias 175

3.3.4 Restricted Earth Fault Logic 175

3.4 High Impedance REF 175

3.4.1 High Impedance REF Calculation Principles 176

4 Second Harmonic Blocking 177

4.1 REF 2nd harmonic Blocking Logic 177

5 Application Notes 178

5.1 Star Winding Resistance Earthed 178

5.2 Low Impedance REF Protection Application 179

5.2.1 Setting Guidelines for Biased Operation 179

5.2.2 Low Impedance REF Scaling Factor 179

5.2.3 Parameter Calculations 179

5.2.4 Dual CB Application with Different Phase CT Ratios 180

5.2.5 Dual CB Application with Same Phase CT Ratios 181

5.2.6 CT Requirements - Low Impedance REF 181

5.3 High Impedance REF Protection Application 183

5.3.1 High Impedance REF Operating Modes 183

5.3.2 Setting Guidelines for High Impedance Operation 185

5.3.3 Use of Metrosil Non-linear Resistors 187

5.3.4 CT Requirements - High Impedance REF 189

Chapter 9 Current Protection Functions 191

1 Chapter Overview 193
2 Overcurrent Protection Principles 194

2.1 IDMT Characteristics 194

2.1.1 IEC 60255 IDMT Curves 195

2.1.2 European Standards 196

2.1.3 North American Standards 198

2.1.4 Differences Between the North american and European Standards 199

2.2 Principles of Implementation 199

2.2.1 Timer Hold Facility 200

2.3 Magnetising Inrush Restraint 200

3 Phase Overcurrent Protection 202

3.1 Phase Overcurrent Protection for Power Transformers 202

3.2 Phase Overcurrent Protection Implementation 202

3.3 Selecting the Current Inputs 203

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3.4 Non-Directional Overcurrent Logic 204

3.5 Directional Element 205

3.5.1 Implementing Directionalisation 205

3.5.2 Directional Overcurrent Logic 207

3.6 Application Notes 207

3.6.1 Setting Guidelines 207

3.6.2 Parallel Feeders 209

4 Voltage Dependent Overcurrent Element 210

4.1 Current Setting Threshold Selection 210

4.2 VCO Implementation 210

5 Negative Sequence Overcurrent Protection 212

5.1 NPSOC Protection Implementation 212

5.2 Non-Directional NPSOC Logic 212

5.3 Directional Element 213

5.3.1 Directional NPSOC Logic 213

5.4 Application Notes 214

5.4.1 Setting Guidelines (General) 214

5.4.2 Setting Guidelines (Current Threshold) 214

5.4.3 Setting Guidelines (Time Delay) 214

5.4.4 Setting Guidelines (Directional element) 214

6 Earth Fault Protection 216

6.1 Earth Fault Protection Elements 216

6.2 Non-directional Earth Fault Logic 217

6.3 IDG Curve 217

6.4 Directional Element 218

6.4.1 Residual Voltage Polarisation 218

6.4.2 Negative Sequence Polarisation 219

6.5 Application Notes 220

6.5.1 Setting Guidelines (Non-directional) 220

6.5.2 Setting Guidelines (Directional Element) 221

7 Second Harmonic Blocking 222

7.1 Second Harmonic Blocking Implementation 222

7.2 Second Harmonic Blocking Logic 223

7.3 EF Second Harmonic Blocking Logic 223

7.4 Application Notes 223

7.4.1 Setting Guidelines 223

Chapter 10 CB Fail Protection 225

1 Chapter Overview 227
2 Circuit Breaker Fail Protection 228
3 Circuit Breaker Fail Implementation 229

3.1 Circuit Breaker Fail Timers 229

3.2 Zero Crossing Detection 230

4 Circuit Breaker Fail Logic 231
5 Application Notes 233

5.1 Reset Mechanisms for CB Fail Timers 233

5.2 Setting Guidelines (CB fail Timer) 233

5.3 Setting Guidelines (Undercurrent) 234

Chapter 11 Voltage Protection Functions 235

1 Chapter Overview 237
2 Undervoltage Protection 238

2.1 Undervoltage Protection Implementation 238

2.2 Undervoltage Protection Logic 239

2.3 Application Notes 240

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2.3.1 Undervoltage Setting Guidelines 240

3 Overvoltage Protection 241

3.1 Overvoltage Protection Implementation 241

3.2 Overvoltage Protection Logic 242

3.3 Application Notes 242

3.3.1 Overvoltage Setting Guidelines 242

4 Residual Overvoltage Protection 244

4.1 Residual Overvoltage Protection Implementation 244

4.2 Residual Overvoltage Logic 245

4.3 Application Notes 245

4.3.1 Calculation for Solidly Earthed Systems 245

4.3.2 Calculation for Impedance Earthed Systems 246

4.3.3 Setting Guidelines 247

5 Negative Sequence Overvoltage Protection 248

5.1 Negative Sequence Overvoltage Implementation 248

5.2 Negative Sequence Overvoltage Logic 248

5.3 Application Notes 248

5.3.1 Setting Guidelines 248

Chapter 12 Frequency Protection Functions 251

1 Chapter Overview 253
2 Overfluxing Protection 254

2.1 Overfluxing Protection Implementation 254

2.1.1 Time-delayed Overfluxing Protection 255

2.1.2 5th Harmonic Blocking 256

2.1.3 Overfluxing Protection Logic 256

2.2 Application Notes 257

2.2.1 Overfluxing Protection Setting Guidelines 257

3 Frequency Protection 259

3.1 Underfrequency Protection 259

3.1.1 Underfrequency Protection Implementation 259

3.1.2 Underfrequency Protection logic 259

3.1.3 Application Notes 260

3.2 Overfrequency Protection 260

3.2.1 Overfrequency Protection Implementation 260

3.2.2 Overfrequency Protection logic 260

3.2.3 Application Notes 261

Chapter 13 Monitoring and Control 263

1 Chapter Overview 265
2 Event Records 266

2.1 Event Types 266

2.1.1 Opto-input Events 267

2.1.2 Contact Events 267

2.1.3 Alarm Events 267

2.1.4 Fault Record Events 271

2.1.5 Maintenance Events 271

2.1.6 Protection Events 272

2.1.7 Security Events 272

2.1.8 Platform Events 272

3 Disturbance Recorder 273
4 Measurements 274

4.1 Measured Quantities 274

4.1.1 Measured and Calculated Currents 274

4.1.2 Measured and Calculated Voltages 274

4.1.3 Power and Energy Quantities 274

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4.1.4 Demand Values 275

4.1.5 Other Measurements 275

4.2 Measurement Setup 275

4.3 Opto-input Time Stamping 275

5 Current Input Exclusion Function 276

5.1 Current Input Exclusion Logic 276

5.2 Application Notes 276

5.2.1 Current Input Exclusion Example 276

6 Pole Dead Function 278

6.1 Pole Dead Function Implementation 278

6.2 Pole Dead Logic 279

6.3 CB Status Indication 280

Chapter 14 Supervision 283

1 Chapter Overview 285
2 Voltage Transformer Supervision 286

2.1 Loss of One or Two Phase Voltages 286

2.2 Loss of all Three Phase Voltages 286

2.3 Absence of all Three Phase Voltages on Line Energisation 286

2.4 VTS Implementation 287

2.5 VTS Logic 288

3 Current Transformer Supervision 291

3.1 CTS Implementation 291

3.2 CTS Logic 292

3.3 Application Notes 293

3.3.1 Setting Guidelines 293

4 Trip Circuit Supervision 294

4.1 Trip Circuit Supervision Scheme 1 294

4.1.1 Resistor Values 294

4.1.2 PSL for TCS Scheme 1 295

4.2 Trip Circuit Supervision Scheme 2 295

4.2.1 Resistor Values 296

4.2.2 PSL for TCS Scheme 2 296

4.3 Trip Circuit Supervision Scheme 3 296

4.3.1 Resistor Values 297

4.3.2 PSL for TCS Scheme 3 297

Chapter 15 Digital I/O and PSL Configuration 299

1 Chapter Overview 301
2 Configuring Digital Inputs and Outputs 302
3 Scheme Logic 303

3.1 PSL Editor 304

3.2 PSL Schemes 304

3.3 PSL Scheme Version Control 304

4 Configuring the Opto-Inputs 305
5 Assigning the Output Relays 306
6 Fixed Function LEDs 307

6.1 Trip LED Logic 307

7 Configuring Programmable LEDs 308
8 Function Keys 310
9 Control Inputs 311

Chapter 16 Communications 313

1 Chapter Overview 315

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2 Communication Interfaces 316
3 Serial Communication 317

3.1 EIA(RS)232 Bus 317

3.2 EIA(RS)485 Bus 317

3.2.1 EIA(RS)485 Biasing Requirements 318

3.3 K-Bus 318

4 Standard Ethernet Communication 320

4.1 Hot-Standby Ethernet Failover 320

5 Redundant Ethernet Communication 321

5.1 Supported Protocols 321

5.2 Parallel Redundancy Protocol 322

5.3 Rapid Spanning Tree Protocol 323

5.4 Self Healing Protocol 323

5.5 Dual Homing Protocol 325

5.6 Redundant Ethernet Configuration 326

5.6.1 Setting the NIC IP Address 328

5.6.2 Setting the Switch IP Address 328

6 Data Protocols 329

6.1 Courier 329

6.1.1 Physical Connection and Link Layer 329

6.1.2 Courier Database 330

6.1.3 Settings Categories 330

6.1.4 Setting Changes 330

6.1.5 Event Extraction 330

6.1.6 Disturbance Record Extraction 332

6.1.7 Programmable Scheme Logic Settings 332

6.1.8 Time Synchronisation 332

6.1.9 Courier Configuration 333

6.2 IEC 60870-5-103 334

6.2.1 Physical Connection and Link Layer 334

6.2.2 Initialisation 335

6.2.3 Time Synchronisation 335

6.2.4 Spontaneous Events 335

6.2.5 General Interrogation (GI) 335

6.2.6 Cyclic Measurements 335

6.2.7 Commands 335

6.2.8 Test Mode 336

6.2.9 Disturbance Records 336

6.2.10 Command/Monitor Blocking 336

6.2.11 IEC 60870-5-103 Configuration 336

6.3 DNP 3.0 337

6.3.1 Physical Connection and Link Layer 338

6.3.2 Object 1 Binary Inputs 338

6.3.3 Object 10 Binary Outputs 338

6.3.4 Object 20 Binary Counters 339

6.3.5 Object 30 Analogue Input 339

6.3.6 Object 40 Analogue Output 340

6.3.7 Object 50 Time Synchronisation 340

6.3.8 DNP3 Device Profile 340

6.3.9 DNP3 Configuration 348

6.4 MODBUS 349

6.4.1 Physical Connection and Link Layer 350

6.4.2 MODBUS Functions 350

6.4.3 Response Codes 350

6.4.4 Register Mapping 351

6.4.5 Event Extraction 351

6.4.6 Disturbance Record Extraction 352

6.4.7 Setting Changes 360

P64x-TM-EN-1.3 ix

Contents P64x

6.4.8 Password Protection 360

6.4.9 Protection and Disturbance Recorder Settings 360

6.4.10 Time Synchronisation 361

6.4.11 Power and Energy Measurement Data Formats 362

6.4.12 MODBUS Configuration 363

6.5 IEC 61850 364

6.5.1 Benefits of IEC 61850 364

6.5.2 IEC 61850 Interoperability 365

6.5.3 The IEC 61850 Data Model 365

6.5.4 IEC 61850 in MiCOM IEDs 366

6.5.5 IEC 61850 Data Model Implementation 366

6.5.6 IEC 61850 Communication Services Implementation 366

6.5.7 IEC 61850 Peer-to-peer (GOOSE) communications 367

6.5.8 Mapping GOOSE Messages to Virtual Inputs 367

6.5.9 Ethernet Functionality 367

6.5.10 IEC 61850 Configuration 367

7 Read Only Mode 369

7.1 IEC 60870-5-103 Protocol Blocking 369

7.2 Courier Protocol Blocking 369

7.3 IEC 61850 Protocol Blocking 370

7.4 Read-Only Settings 370

7.5 Read-Only DDB Signals 370

8 Time Synchronisation 371

8.1 Demodulated IRIG-B 371

8.1.1 IRIG-B Implementation 371

8.2 SNTP 372

8.3 Time Synchronsiation using the Communication Protocols 372

Chapter 17 Cyber-Security 373

1 Overview 375
2 The Need for Cyber-Security 376
3 Standards 377

3.1 NERC Compliance 377

3.1.1 CIP 002 378

3.1.2 CIP 003 378

3.1.3 CIP 004 378

3.1.4 CIP 005 378

3.1.5 CIP 006 378

3.1.6 CIP 007 379

3.1.7 CIP 008 379

3.1.8 CIP 009 379

3.2 IEEE 1686-2007 379

4 Cyber-Security Implementation 381

4.1 NERC-Compliant Display 381

4.2 Four-level Access 382

4.2.1 Blank Passwords 383

4.2.2 Password Rules 383

4.2.3 Access Level DDBs 384

4.3 Enhanced Password Security 384

4.3.1 Password Strengthening 384

4.3.2 Password Validation 384

4.3.3 Password Blocking 385

4.4 Password Recovery 386

4.4.1 Password Recovery 386

4.4.2 Password Encryption 387

4.5 Disabling Physical Ports 387

4.6 Disabling Logical Ports 387

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4.7 Security Events Management 388

4.8 Logging Out 390

Chapter 18 Installation 391

1 Chapter Overview 393
2 Handling the Goods 394

2.1 Receipt of the Goods 394

2.2 Unpacking the Goods 394

2.3 Storing the Goods 394

2.4 Dismantling the Goods 394

3 Mounting the Device 395

3.1 Flush Panel Mounting 395

3.2 Rack Mounting 396

4 Cables and Connectors 398

4.1 Terminal Blocks 398

4.2 Power Supply Connections 399

4.3 Earth Connnection 399

4.4 Current Transformers 399

4.5 Voltage Transformer Connections 400

4.6 Watchdog Connections 400

4.7 EIA(RS)485 and K-Bus Connections 400

4.8 IRIG-B Connection 400

4.9 Opto-input Connections 400

4.10 Output Relay Connections 400

4.11 Ethernet Metallic Connections 401

4.12 Ethernet Fibre Connections 401

4.13 RS232 connection 401

4.14 Download/Monitor Port 401

4.15 GPS Fibre Connection 401

4.16 Fibre Communication Connections 401

4.17 RTD Connections 402

4.18 CLIO Connections 403

5 Case Dimensions 404

5.1 Case Dimensions 40TE 404

5.2 Case Dimensions 60TE 405

5.3 Case Dimensions 80TE 406

Chapter 19 Commissioning Instructions 407

1 Chapter Overview 409
2 General Guidelines 410
3 Commissioning Test Menu 411

3.1 Opto I/P Status Cell (Opto-input Status) 411

3.2 Relay O/P Status Cell (Relay Output Status) 411

3.3 Test Mode Cell 411

3.4 Test Pattern Cell 412

3.5 Contact Test Cell 412

3.6 Test LEDs Cell 412

3.7 Red and Green LED Status Cells 412

3.8 PSL Verificiation 412

3.8.1 Test Port Status Cell 412

3.8.2 Monitor Bit 1 to 8 Cells 412

3.8.3 Using a Monitor Port Test Box 413

4 Commissioning Equipment 414

4.1 Recommended Commissioning Equipment 414

4.2 Essential Commissioning Equipment 414

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Contents P64x

4.3 Advisory Test Equipment 415

5 Product Checks 416

5.1 Product Checks with the IED De-energised 416

5.1.1 Visual Inspection 417

5.1.2 Current Transformer Shorting Contacts 417

5.1.3 Insulation 417

5.1.4 External Wiring 417

5.1.5 Watchdog Contacts 418

5.1.6 Power Supply 418

5.2 Product Checks with the IED Energised 418

5.2.1 Watchdog Contacts 418

5.2.2 Test LCD 419

5.2.3 Date and Time 419

5.2.4 Test LEDs 420

5.2.5 Test Alarm and Out-of-Service LEDs 420

5.2.6 Test Trip LED 420

5.2.7 Test User-programmable LEDs 420

5.2.8 Test Opto-inputs 420

5.2.9 Test Output Relays 420

5.2.10 RTD Inputs 421

5.2.11 Current Loop Outputs 421

5.2.12 Current Loop Inputs 421

5.2.13 Test Serial Communication Port RP1 422

5.2.14 Test Serial Communication Port RP2 423

5.2.15 Test Ethernet Communication 424

5.3 Secondary Injection Tests 424

5.3.1 Test Current Inputs 424

5.3.2 Test Voltage Inputs 425

6 Setting Checks 426

6.1 Apply Application-specific Settings 426

6.1.1 Transferring Settings from a Settings File 426

6.1.2 Entering settings using the HMI 426

7 Checking the Differential Element 428

7.1 Using the Omicron Advanced Module 428

8 Protection Timing Checks 431

8.1 Bypassing the All Pole Dead Blocking Condition 431

8.2 Overcurrent Check 431

8.3 Connecting the Test Circuit 431

8.4 Performing the Test 431

8.5 Check the Operating Time 431

9 Onload Checks 433

9.1 Confirm Current Connections 433

9.2 Confirm Voltage Connections 433

9.3 On-load Directional Test 434

10 Final Checks 435

Chapter 20 Maintenance and Troubleshooting 437

1 Chapter Overview 439
2 Maintenance 440

2.1 Maintenance Checks 440

2.1.1 Alarms 440

2.1.2 Opto-isolators 440

2.1.3 Output Relays 440

2.1.4 Measurement Accuracy 440

2.2 Replacing the Device 441

2.3 Repairing the Device 442

2.4 Removing the front panel 442

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2.5 Replacing PCBs 443

2.5.1 Replacing the main processor board 443

2.5.2 Replacement of communications boards 444

2.5.3 Replacement of the input module 445

2.5.4 Replacement of the power supply board 445

2.5.5 Replacement of the I/O boards 446

2.6 Recalibration 446

2.7 Changing the battery 446

2.7.1 Post Modification Tests 447

2.7.2 Battery Disposal 447

2.8 Cleaning 447

3 Troubleshooting 448

3.1 Self-Diagnostic Software 448

3.2 Power-up Errors 448

3.3 Error Message or Code on Power-up 448

3.4 Out of Service LED on at power-up 449

3.5 Error Code during Operation 450

3.5.1 Backup Battery 450

3.6 Mal-operation during testing 450

3.6.1 Failure of Output Contacts 450

3.6.2 Failure of Opto-inputs 450

3.6.3 Incorrect Analogue Signals 451

3.7 PSL Editor Troubleshooting 451

3.7.1 Diagram Reconstruction 451

3.7.2 PSL Version Check 451

4 Repair and Modification Procedure 452

Chapter 21 Technical Specifications 453

1 Chapter Overview 455
2 Interfaces 456

2.1 Front Serial Port 456

2.2 Download/Monitor Port 456

2.3 Rear Serial Port 1 456

2.4 Fibre Rear Serial Port 1 456

2.5 Rear Serial Port 2 457

2.6 IRIG-B (Demodulated) 457

2.7 IRIG-B (Modulated) 457

2.8 Rear Ethernet Port Copper 457

2.9 Rear Ethernet Port Fibre 458

2.9.1 100 Base FX Receiver Characteristics 458

2.9.2 100 Base FX Transmitter Characteristics 458

3 Performance of Transformer Differential Protection and Monitoring Functions 459

3.1 Transformer Differential Protection 459

3.2 Matching Factors 459

3.3 Circuitry Fault Alarm 459

3.4 Through Fault Monitoring 460

3.5 Thermal Overload 460

3.6 Low Impedance Restricted Earth Fault 460

3.7 High Impedance Restricted Earth Fault 460

4 Performance of Current Protection Functions 461

4.1 Transient Overreach and Overshoot 461

4.2 Three-phase Overcurrent Protection 461

4.2.1 Three-phase Overcurrent Directional Parameters 461

4.3 Voltage Dependent Overcurrent Protection 461

4.4 Earth Fault Protection 462

4.4.1 Earth Fault Directional Parameters 462

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4.5 Negative Sequence Overcurrent Protection 462

4.5.1 NPSOC Directional Parameters 462

4.6 Circuit Breaker Fail Protection 463

5 Performance of Voltage Protection Functions 464

5.1 Undervoltage Protection (P643/5) 464

5.2 Overvoltage Protection 464

5.3 Residual Overvoltage Protection (P643/5) 464

5.4 Negative Sequence Voltage Protection 464

6 Performance of Frequency Protection Functions 465

6.1 Overfrequency Protection 465

6.2 Underfrequency Protection 465

6.3 Overfluxing Protection 465

7 Performance of Monitoring and Control Functions 466

7.1 Voltage Transformer Supervision 466

7.2 Current Transformer Supervision 466

7.3 Pole Dead Protection 466

7.4 PSL Timers 467

8 Measurements and Recording 468

8.1 General 468

8.2 Disturbance Records 468

8.3 Event, Fault and Maintenance Records 468

8.4 Current Loop Inputs/Outputs 468

9 Standards Compliance 470

9.1 EMC Compliance: 2004/108/EC 470

9.2 Product Safety: 2006/95/EC 470

9.3 R&TTE Compliance 470

9.4 UL/CUL Compliance 470

9.5 ATEX Compliance 470

9.6 IDMT standards 471

10 Mechanical Specifications 472

10.1 Physical Parameters 472

10.2 Enclosure Protection 472

10.3 Mechanical Robustness 472

10.4 Transit Packaging Performance 472

11 Ratings 473

11.1 AC Measuring Inputs 473

11.2 Current Transformer Inputs 473

11.3 Voltage Transformer Inputs 473

12 Power Supply 474

12.1 Auxiliary Supply Voltage 474

12.2 Nominal Burden 474

12.3 Power Supply Interruption 474

12.4 Battery Backup 475

13 Input / Output Connections 476

13.1 Isolated Digital Inputs 476

13.1.1 Nominal Pickup and Reset Thresholds 476

13.2 Standard Output Contacts 476

13.3 High Break Output Contacts 477

13.4 Watchdog Contacts 477

14 Environmental Conditions 478

14.1 Ambient Temperature Range 478

14.2 Temperature Endurance Test 478

14.3 Ambient Humidity Range 478

14.4 Corrosive Environments 478

15 Type Tests 479

15.1 Insulation 479

xiv P64x-TM-EN-1.3

P64x Contents

15.2 Creepage Distances and Clearances 479

15.3 High Voltage (Dielectric) Withstand 479

15.4 Impulse Voltage Withstand Test 479

16 Electromagnetic Compatibility 480

16.1 1 MHz Burst High Frequency Disturbance Test 480

16.2 Damped Oscillatory Test 480

16.3 Immunity to Electrostatic Discharge 480

16.4 Electrical Fast Transient or Burst Requirements 480

16.5 Surge Withstand Capability 480

16.6 Surge Immunity Test 481

16.7 Immunity to Radiated Electromagnetic Energy 481

16.8 Radiated Immunity from Digital Communications 481

16.9 Radiated Immunity from Digital Radio Telephones 481

16.10 Immunity to Conducted Disturbances Induced by Radio Frequency Fields 481

16.11 Magnetic Field Immunity 482

16.12 Conducted Emissions 482

16.13 Radiated Emissions 482

16.14 Power Frequency 482

Appendix A Ordering Options 483

Appendix B Settings and Signals 485

Appendix C Wiring Diagrams 487

P64x-TM-EN-1.3 xv

Contents P64x

xvi P64x-TM-EN-1.3

Table of Figures

Figure 1: P64x version evolution 7

Figure 2: Functional overview 11

Figure 3: Hardware architecture 30

Figure 4: Exploded view of IED 31

Figure 5: Front panel (60TE) 34

Figure 6: HMI panel 35

Figure 7: Rear view of populated case 38

Figure 8: Terminal block types 39

Figure 9: Rear connection to terminal block 40

Figure 10: Main processor board 41

Figure 11: Power supply board 42

Figure 12: Power supply assembly 43

Figure 13: Power supply terminals 44

Figure 14: Watchdog contact terminals 45

Figure 15: Rear serial port terminals 46

Figure 16: Input module - 1 transformer board 46

Figure 17: Input module schematic 47

Figure 18: Frequency response 48

Figure 19: Transformer board 49

Figure 20: Input board 50

Figure 21: Standard output relay board - 8 contacts 51

Figure 22: IRIG-B board 52

Figure 23: Fibre optic board 53

Figure 24: Rear communication board 54

Figure 25: Ethernet board 54

Figure 26: Redundant Ethernet board 56

Figure 27: RTD board 58

Figure 28: RTD board 59

Figure 29: High Break relay output board 61

Figure 30: High Break contact operation 62

Figure 31: Software Architecture 66

Figure 32: Frequency Response (indicative only) 72

Figure 33: Navigating the HMI 79

Figure 34: Default display navigation 81

Figure 35: Compensation using biased differential characteristic 101

Figure 36: Transformer winding connections - part 1 103

Figure 37: Transformer winding connections - part 2 104

Figure 38: Magnetising inrush phenomenon 105

Table of Figures P64x

Figure 39: Typical overflux current waveform 106

Figure 40: CT parameter mismatch logic diagram 109

Figure 41: Transformer biased tripping characteristic 111

Figure 42: Transient bias characteristic 113

Figure 43: Time to saturation - external AN fault 114

Figure 44: Effect of CTS restrain 115

Figure 45: Bias characteristic with circuitry fail alarm 115

Figure 46: Differential biased trip logic 116

Figure 47: 2nd harmonic blocking process 117

Figure 48: 2nd harmonic blocking logic 118

Figure 49: 5th harmonic blocking process 119

Figure 50: Differential protection blocking mechanisms 120

Figure 51: Triple slope characteristic 122

Figure 52: P642 used to protect a two winding transformer 122

Figure 53: P645 used to protect an autotransformer with loaded delta winding 125

Figure 54: P643 used to protect an autotransformer with unloaded delta winding 128

Figure 55: Unloaded delta – current distribution 129

Figure 56: Single bus differential protection zone 131

Figure 57: Busbar biased differential protection 133

Figure 58: Shunt Reactor single line diagram 134

Figure 59: P643 Using spare CT input for overcurrent protection 136

Figure 60: Stub Bus arrangement 137

Figure 61: Stub Bus Scheme Logic 138

Figure 62: Transformer losses 144

Figure 63: Through-fault alarm logic 155

Figure 64: P645 used to protect an autotransformer with loaded delta winding 156

Figure 65: Connection for RTD thermal probes 157

Figure 66: RTD logic 158

Figure 67: Current loop input ranges 160

Figure 68: Current Loop Input logic 161

Figure 69: Current Loop Output ranges 162

Figure 70: REF protection for delta side 168

Figure 71: REF protection for star side 168

Figure 72: REF Protection for resistance-earthed systems 169

Figure 73: REF Protection for solidly earthed system 169

Figure 74: Low Impedance REF Connection 171

Figure 75: Three-slope REF bias characteristic 171

Figure 76: High Impedance REF principle 172

Figure 77: High Impedance REF Connection 172

Figure 78: REF bias characteristic 174

xviii P64x-TM-EN-1.3

P64x Table of Figures

Figure 79: Low impedance restricted Earth Fault logic 175

Figure 80: REF 2nd harmonic blocking logic 177

Figure 81: Star winding, resistance earthed 178

Figure 82: Percentage of winding protected 178

Figure 83: Low Impedance REF Scaling Factor 179

Figure 84: Low-Z REF for dual CB application with different phase CT ratios 180

Figure 85: Low-Z REF for dual CB application with same phase CT ratios 181

Figure 86: Hi-Z REF protection for a grounded star winding 184

Figure 87: Hi-Z REF protection for a delta winding 184

Figure 88: Hi-Z REF Protection for autotransformer configuration 185

Figure 89: High Impedance REF for the LV winding 185

Figure 90: High Impedance REF CT requirement 190

Figure 91: IEC 60255 IDMT curves 196

Figure 92: Principle of protection function implementation 199

Figure 93: Magnetising inrush phenomenon 201

Figure 94: Non-directional overcurrent logic diagram 204

Figure 95: Directional overcurrent logic diagram 207

Figure 96: Typical distribution system using parallel transformers 209

Figure 97: Selecting the current threshold setting 210

Figure 98: Modification of current pickup level for voltage controlled overcurrent protection 211

Figure 99: Negative Sequence Overcurrent logic - non-directional operation 212

Figure 100: Negative Phase equence Overcurrent logic - directional operation 213

Figure 101: Non-directional EF logic (single stage) 217

Figure 102: IDG Characteristic 218

Figure 103: Directional EF logic with neutral voltage polarization (single stage) 219

Figure 104: Directional Earth Fault logic with negative phase sequence polarisation (single

220

stage)

Figure 105: Phase overcurrent 2nd harmonic blocking Logic 223

Figure 106: Earth fault 2nd harmonic blocking Logic 223

Figure 107: Circuit Breaker Fail Logic - part 1 231

Figure 108: Circuit Breaker Fail Logic - part 2 232

Figure 109: CB Fail timing 234

Figure 110: Undervoltage - single and three phase tripping mode (single stage) 239

Figure 111: Overvoltage - single and three phase tripping mode (single stage) 242

Figure 112: Residual Overvoltage logic 245

Figure 113: Residual voltage for a solidly earthed system 246

Figure 114: Residual voltage for an impedance earthed system 247

Figure 115: Negative Sequence Overvoltage logic 248

Figure 116: Variable time overfluxing protection characteristic 255

Figure 117: Overfluxing reset characteristic 256

P64x-TM-EN-1.3 xix

Table of Figures P64x

Figure 118: 5th harmonic blocking time delay in PSL 256

Figure 119: Overfluxing protection logic 257

Figure 120: Multi-stage overfluxing characteristic 258

Figure 121: Scheme logic for multi-stage overfluxing characteristic 258

Figure 122: Underfrequency logic (single stage) 259

Figure 123: Overfrequency logic (single stage) 260

Figure 124: Fault recorder stop conditions 271

Figure 125: CT Exclusion logic 276

Figure 126: CT input exclusion - 1.5 CB application 277

Figure 127: CT input exclusion - auxiliary contact connection 277

Figure 128: Pole Dead logic - P642 279

Figure 129: Pole Dead logic - P643 and P645 280

Figure 130: Forcing CB Closed signals 281

Figure 131: VTS logic (P642 with 2 single-phase VTs) 288

Figure 132: VTS logic (P643 and P645 with 3-phase VTs) 289

Figure 133: CTS restraint region increase 291

Figure 134: CTS logic diagram 292

Figure 135: TCS Scheme 1 294

Figure 136: PSL for TCS Scheme 1 295

Figure 137: TCS Scheme 2 295

Figure 138: PSL for TCS Scheme 2 296

Figure 139: TCS Scheme 3 296

Figure 140: PSL for TCS Scheme 3 297

Figure 141: Scheme Logic Interfaces 303

Figure 142: Trip LED logic 307

Figure 143: RS485 biasing circuit 318

Figure 144: Remote communication using K-Bus 319

Figure 145: IED attached to separate LANs 322

Figure 146: IED attached to redundant Ethernet star or ring circuit 323

Figure 147: IED, bay computer and Ethernet switch with self healing ring facilities 324

Figure 148: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches 324

Figure 149: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches

after failur

e

324

Figure 150: Dual homing mechanism 325

Figure 151: Application of Dual Homing Star at substation level 326

Figure 152: IED and REB switch IP address configuration 327

Figure 153: DIP switches for setting IP address 327

Figure 154: Control input behaviour 339

Figure 155: Manual selection of a disturbance record 355

Figure 156: Automatic selection of disturbance record - method 1 356

xx P64x-TM-EN-1.3

P64x Table of Figures

Figure 157: Automatic selection of disturbance record - method 2 357

Figure 158: Configuration file extraction 358

Figure 159: Data file extraction 359

Figure 160: Data model layers in IEC61850 365

Figure 161: GPS Satellite timing signal 371

Figure 162: Default display navigation 382

Figure 163: Location of battery isolation strip 395

Figure 164: Rack mounting of products 396

Figure 165: Terminal block types 398

Figure 166: 40TE case dimensions 404

Figure 167: 60TE case dimensions 405

Figure 168: 80TE case dimensions 406

Figure 169: RP1 physical connection 422

Figure 170: Remote communication using K-bus 423

Figure 171: Operating Characteristic Diagram 429

Figure 172: Trip Time Test Plane 429

Figure 173: Harmonic Restraint Test Plane 430

Figure 174: Possible terminal block types 442

Figure 175: Front panel assembly 444

P64x-TM-EN-1.3 xxi

Table of Figures P64x

xxii P64x-TM-EN-1.3

CHAPTER 1

INTRODUCTION

Chapter 1 - Introduction P64x

2 P64x-TM-EN-1.3

P64x Chapter 1 - Introduction

1 CHAPTER OVERVIEW

This chapter provides some general information about the technical manual and an introduction to the device(s)
described in this technical manual.

This chapter contains the following sections:

Chapter Overview 3

eword 4

For

Product Scope 6

Features and Functions 8

Compliance 10

Functional Overview 11

P64x-TM-EN-1.3 3

Chapter 1 - Introduction P64x

2 FOREWORD

This technical manual provides a functional and technical description of GE's P642, P643, P645, as well as a

ehensive set of instructions for using the device. The level at which this manual is written assumes that you

compr
are already familiar with protection engineering and have experience in this discipline. The description of principles
and theory is limited to that which is necessary to understand the product. For further details on general
protection engineering theory, we refer you to Alstom's publication NPAG, which is available online or from our
contact centre.

We have attempted to make this manual as accurate, comprehensive and user-friendly as possible. However we
cannot guarantee that it is free from errors. Nor can we state that it cannot be improved. We would therefore be
very pleased to hear from you if you discover any errors, or have any suggestions for improvement. Our policy is to
provide the information necessary to help you safely specify, engineer, install, commission, maintain, and
eventually dispose of this product. We consider that this manual provides the necessary information, but if you
consider that more details are needed, please contact us.

All feedback should be sent to our contact centre via the following URL:

www.gegridsolutions.com/contact

2.1 TARGET AUDIENCE

This manual is aimed towards all professionals charged with installing, commissioning, maintaining,
tr

oubleshooting, or operating any of the products within the specified product range. This includes installation and

commissioning personnel as well as engineers who will be responsible for operating the product.

The level at which this manual is written assumes that installation and commissioning engineers have knowledge
of handling electronic equipment. Also, system and protection engineers have a thorough knowledge of protection
systems and associated equipment.

2.2 TYPOGRAPHICAL CONVENTIONS

The following typographical conventions are used throughout this manual.

● The names for special k

For example: ENTER

● When describing software applications, menu items, buttons, labels etc as they appear on the screen are

written in bold type.
For example: Select Save from the file menu.

● Filenames and paths use the courier font

For example: Example\File.text

● Special terminology is written with leading capitals

For example: Sensitive Earth Fault

● If reference is made to the IED's internal settings and signals database, the menu group heading (column)

text is written in upper case italics
For example: The SYSTEM DATA column

● If reference is made to the IED's internal settings and signals database, the setting cells and DDB signals are

written in bold italics
For example: The Language cell in the SYSTEM DATA column

● If reference is made to the IED's internal settings and signals database, the value of a cell's content is

written in the Courier font
For example: The Language cell in the SYSTEM DATA column contains the value English

eys appear in capital letters.

4 P64x-TM-EN-1.3

P64x Chapter 1 - Introduction

2.3 NOMENCLATURE

Due to the technical nature of this manual, many special terms, abbreviations and acronyms are used throughout
the manual. Some of these terms ar
specific terms used by GE. The first instance of any acronym or term used in a particular chapter is explained. In
addition, a separate glossary is available on the GE website, or from the GE contact centre.

We would like to highlight the following changes of nomenclature however:

● The word 'relay' is no longer used to describe the device itself. Instead, the device is referred to as the 'IED'

(Intelligent Electronic Device), the 'device', or the 'product'. The word 'relay' is used purely to describe the
electromechanical components within the device, i.e. the output relays.

● British English is used throughout this manual.

● The British term 'Earth' is used in favour of the American term 'Ground'.

e well-known industry-specific terms while others may be special product-

P64x-TM-EN-1.3 5

Chapter 1 - Introduction P64x

3 PRODUCT SCOPE

The MiCOM P64x range of devices preserve transformer service life by offering fast protection for transformer
faults. Hosted on an adv
Fault (REF),Thermal, and Overfluxing protection, plus backup protection for uncleared external faults. Further, the
P64x devices provide a range of transformer condition monitoring functions such as Through-fault monitoring,
loss of life statistics, RTD and CLIO protection functionality.

All devices also provide a comprehensive range of additional features to aid with power system diagnosis and fault
analysis.

Model variants cover two and three winding power transformers, with up to five sets of 3-phase CT inputs. Backup
overcurrent protection can be directionalised, if you select the optional 3-phase VT input.

The P64x range consists of three models; the P642, P643, and P645.

● The P642 provides 8 on-board CTs to support two-winding 3-phase power transformers and 1or 2 single-

phase voltage transformers to support directionalisation and a range of voltage-related functions.

● The P643 provides 12 on-board CTs to support three-winding 3-phase power transformers, a single-phase

voltage transformer and an optional three-phase voltage transformer to support directionalisation and a
range of voltage-related functions including undervoltage, overvoltage and residual overvoltage protection.

● The P645 provides 18 on-board CTs to support three-winding 3-phase power transformers and other

applications needing 5 sets of 3-phase current inputs, a single-phase voltage transformer and an optional
three-phase voltage transformer to support directionalisation and a range of voltage-related functions
including undervoltage, overvoltage and residual overvoltage protection.

The difference in model variants are summarised below:

anced IED platform, the P64x products incorporate Current Differential, Restricted Earth

Feature/Variant P642 P643 P645

Case 40TE 60TE/80TE 60TE/80TE

Number of CT Inputs 8 (6 Bias, 2 EF) 12 (9 bias, 3EF) 18 (15 Bias, 3EF)

Number of VT inputs 1 or 2 1 or 4 1 or 4

Number of bias inputs (3-phase CT sets) 2 3 5

Optically coupled digital inputs 8 - 12 16 - 40 16 - 40

Standard relay output contacts 8 - 12 8 - 24 8 - 24

Function keys No 10 10

Undervoltage/Overvoltage/Residual voltage protection No Yes Yes

Underfrequency/Overfrequency protection No Yes Yes

Overfluxing protection 1-phase only 1-phase + 3-phase 1-phase + 3-phase

Programmable LEDs 8 red 18 tri-colour 18 tri-colour

3.1 PRODUCT VERSIONS

Since software version 2, the evolution of the P64x product family has followed two paths as shown below:

6 P64x-TM-EN-1.3

V00035

J, K

02

· Hot-Standby Ethernet Failover

· Cyber Security

· IEC61850 9-2L Edition 1

Hardware version K (P645SV)

Software version 12

· Negative Sequence Overvoltage

· Voltage Controlled Overcurrent

· Low Impedance REF for autotransformer

· High Impedance REF

· User Alarms

· CT Exclusion

Hardware version J (P642), K (P643/5)

Software version 04

· Hot-Standby Ethernet Failover

· Cyber Security

· More Disturbance Record channels

Hardware version P (P642), M (P643/5)

Software version 05

· Extra I/O (40 opto-inputs)

· 2ndharmonic blocking for E/F, REF, POC

· Setting name and DDB signal changes

· Setting range extensions

· Vector Group Reference change

· Changes to default PSL

Hardware version P (P642), M (P643/5)

Software version 06

· IEC61850 9-2LE Edition 2

Hardware version P (P645SV)

Software version 20

P64x Chapter 1 - Introduction

Figure 1: P64x version evolution

3.2 ORDERING OPTIONS

All current models and variants for this product are defined in an interactive spreadsheet called the CORTEC. This is

ailable on the company website.

av

Alternatively, you can obtain it via the Contact Centre at the following URL:

www.gegridsolutions.com/contact

A copy of the CORTEC is also supplied as a static table in the Appendices of this document. However, it should only
be used for guidance as it provides a snapshot of the interactive data taken at the time of publication.

This technical manual is applicable to the product version M06

P64x-TM-EN-1.3 7

Chapter 1 - Introduction P64x

4 FEATURES AND FUNCTIONS

4.1 PROTECTION FUNCTIONS

The P64x range of devices provides the following protection functions:

ANSI IEC 61850 Protection Function P642 P643 P645

87T LzdPDIF Transformer biased differential protection • • •

64 RefPDIF Low Impedance and High Impedance Restricted Earth Fault protection 2 3 3

49 ThmPTTR Thermal Overload (3 stages) • • •

24 PVPH Single-phase and three-phase V/Hz Overfluxing protection (4 stages) 1 1 (2) 1 (2)

LoL Loss of Life • • •

Thru Through-fault monitoring • • •

RTD RtfPTTR RTDs x 10 PT100 temperature probes (•) (•) (•)

CLIO PTUC Current Loop transducer I/O (4 input / 4 output) (•) (•) (•)

50 OcpPTOC Definite time overcurrent protection (4 stages per winding) • • •

50N EfdPTOC Neutral/Ground Definite time overcurrent protection (4 stages per winding) • • •

51 OcpPTOC IDMT overcurrent protection (2 stages per winding) • • •

51N EfdPTOC Neutral/Ground IDMT overcurrent protection (2 stages per winding) • • •

46 NgcPTOC Negative sequence overcurrent (4 stages per winding) • • •

67 OcpPTOC Directional Phase Overcurrent protection (4 stages per winding) • • •

67N EfdPTOC Directional earth fault overcurrent protection (4 stages per winding) • • •

50BF RBRF CB Failure (Breaker Fail) protection (2 stages per winding) 2 3 5

27 VtpPhsPTUV Undervoltage protection (2 stages) (•) (•)

59 VtpPhsPTOV Overvoltage protection (2 stages) (•) (•)

59N VtpResPTOV Residual Overvoltage protection (2 stages) (•) (•)

47 NgvPTOV Negative sequence overvoltage protection (1 stage) (•) (•) (•)

81U FrqPTUF Underfrequency protection (4 stages) (•) (•)

81O FrqPTOF Overfrequency protection (2 stages) (•) (•)

Note:

em is enclosed in brackets, this indicates that the feature is an ordering option.

If it

4.2 CONTROL FUNCTIONS

Feature IEC 61850 ANSI

Watchdog contacts

Read-only mode

NERC compliant cyber-security

Function keys (up to 10) FnkGGIO

Programmable LEDs (up to 18) LedGGIO

Programmable hotkeys (2)

Programmable allocation of digital inputs and outputs

Fully customizable menu texts

Circuit breaker control, status & condition monitoring XCBR 52

8 P64x-TM-EN-1.3

P64x Chapter 1 - Introduction

Feature IEC 61850 ANSI

Trip circuit and coil supervision

Control inputs PloGGIO1

Power-up diagnostics and continuous self-monitoring

Dual rated 1A and 5A CT inputs

Alternative setting groups (4)

Graphical programmable scheme logic (PSL)

4.3 MEASUREMENT FUNCTIONS

Measurement Function IEC 61850 ANSI

Measurement of all instantaneous & integrated values
(Exact range of measur

Disturbance recorder for waveform capture – specified in samples per cycle RDRE DFR

Fault Records

Maintenance Records

Event Records / Event logging Event records

Time Stamping of Opto-inputs Yes Yes

ements depend on the device model)

MET

4.4 COMMUNICATION FUNCTIONS

The device offers the following communication functions:

Feature ANSI

NERC compliant cyber-security

Front RS232 serial communication port for configuration 16S

Rear serial RS485 communication port for SCADA control 16S

2nd Additional rear serial communication ports for SCADA control and
telepr

otection (fibre and copper) (optional)

Ethernet communication (optional) 16E

Redundant Ethernet communication (optional) 16E

Courier protocol 16S

IEC 61850 protocol (optional) 16E

IEC 60870-5-103 protocol (optional) 16S

Modbus protocol (optional) 16S

DNP3.0 protocol over serial link (optional) 16S

DNP3.0 protocol over Ethernet (optional) 16E

IRIG-B time synchronisation (optional) CLK

16S

P64x-TM-EN-1.3 9

Chapter 1 - Introduction P64x

5 COMPLIANCE

The device has undergone a range of extensive testing and certification processes to ensure and prove
compatibility with all tar
Specifications chapter.

get markets. A detailed description of these criteria can be found in the Technical

10 P64x-TM-EN-1.3

47

51V

DT VCO

51V

IDMT VCO

E00031

2nd Remote

Comm. port

Remote

Comm. port

Local

Communication

Ethernet

Fault records

Measurements

Disturbance

Record

Self monitoring

I-HV

V

IN-HV

IN-LV

I-LV

IN-TV

I-TV

I-TV

CLIO

BINARY

I/O

RTDs MEASI

MEASO

Always Available

Optional or Specific

Transformer Differential
Protection P64x

1. The three-phase VT input is optional.

2. The 27, 59, 59N and VTS functions require the three-phase VT input.

3. The frequency required by the 81 function is obtained from any analog signal but the voltage signals have priority over the current signals.

virtual

Thru

CTS

DIFF

P64x Chapter 1 - Introduction

6 FUNCTIONAL OVERVIEW

Figure 2: Functional overview

P64x-TM-EN-1.3 11

Chapter 1 - Introduction P64x

12 P64x-TM-EN-1.3

CHAPTER 2

SAFETY INFORMATION

Chapter 2 - Safety Information P64x

14 P64x-TM-EN-1.3

P64x Chapter 2 - Safety Information

1 CHAPTER OVERVIEW

This chapter provides information about the safe handling of the equipment. The equipment must be properly
installed and handled in or
be familiar with information contained in this chapter before unpacking, installing, commissioning, or servicing the
equipment.

This chapter contains the following sections:

Chapter Overview 15

Health and Safety 16

Symbols 17

Installation, Commissioning and Servicing 18

Decommissioning and Disposal 23

Standards Compliance 24

der to maintain it in a safe condition and to keep personnel safe at all times. You must

P64x-TM-EN-1.3 15

Chapter 2 - Safety Information P64x

2 HEALTH AND SAFETY

Personnel associated with the equipment must be familiar with the contents of this Safety Information.

When electrical equipment is in operation, danger
Improper use of the equipment and failure to observe warning notices will endanger personnel.

Only qualified personnel may work on or operate the equipment. Qualified personnel are individuals who are:

● familiar with the installation, commissioning, and operation of the equipment and the system to which it is

being connected.

● familiar with accepted safety engineering practises and are authorised to energise and de-energise

equipment in the correct manner.

● trained in the care and use of safety apparatus in accordance with safety engineering practises

● trained in emergency procedures (first aid).

The documentation provides instructions for installing, commissioning and operating the equipment. It cannot,
however cover all conceivable circumstances. In the event of questions or problems, do not take any action
without proper authorisation. Please contact your local sales office and request the necessary information.

ous voltages are present in certain parts of the equipment.

16 P64x-TM-EN-1.3

P64x Chapter 2 - Safety Information

3 SYMBOLS

Throughout this manual you will come across the following symbols. You will also see these symbols on parts of
the equipment

.

Caution:

efer to equipment documentation. Failure to do so could result in damage to the

R
equipment

Warning:
Risk of electric shock

Earth terminal. Not
is part of a terminal block or sub-assembly.

Protective conductor (earth) terminal

Instructions on disposal requirements

Note:
The t

erm 'Earth' used in this manual is the direct equivalent of the North American term 'Ground'.

e: This symbol may also be used for a protective conductor (earth) terminal if that terminal

P64x-TM-EN-1.3 17

Chapter 2 - Safety Information P64x

4 INSTALLATION, COMMISSIONING AND SERVICING

4.1 LIFTING HAZARDS

Many injuries are caused by:

● Lifting heavy objects

● Lifting things incorr

● Pushing or pulling heavy objects

● Using the same muscles repetitively

Plan carefully, identify any possible hazards and determine how best to move the product. Look at other ways of
moving the load to avoid manual handling. Use the correct lifting techniques and Personal Protective Equipment
(PPE) to reduce the risk of injury.

4.2 ELECTRICAL HAZARDS

ectly

Caution:
All per

sonnel involved in installing, commissioning, or servicing this equipment must be

familiar with the correct working procedures.

Caution:
Consult the equipment documentation befor
the equipment.

Caution:
Alw

ays use the equipment as specified. Failure to do so will jeopardise the protection

provided by the equipment.

Warning:

emoval of equipment panels or covers may expose hazardous live parts. Do not touch

R
until the electrical power is removed. Take care when there is unlocked access to the
rear of the equipment.

Warning:
Isolat

e the equipment before working on the terminal strips.

Warning:
Use a suitable pr
electric shock due to exposed terminals.

otective barrier for areas with restricted space, where there is a risk of

e installing, commissioning, or servicing

Caution:
Disconnect pow
sensitive electronic circuitry. Take suitable precautions against electrostatic voltage
discharge (ESD) to avoid damage to the equipment.

18 P64x-TM-EN-1.3

er before disassembling. Disassembly of the equipment may expose

P64x Chapter 2 - Safety Information

Caution:
NE

VER look into optical fibres or optical output connections. Always use optical power

meters to determine operation or signal level.

Warning:

esting may leave capacitors charged to dangerous voltage levels. Discharge

T
capacitors by rediucing test voltages to zero before disconnecting test leads.

Caution:

Note:
Contact f

Operat

Caution:
Befor
free cloth dampened with clean water.

ingers of test plugs are normally protected by petroleum jelly, which should not be removed.

e the equipment within the specified electrical and environmental limits.

e cleaning the equipment, ensure that no connections are energised. Use a lint

4.3 UL/CSA/CUL REQUIREMENTS

The information in this section is applicable only to equipment carrying UL/CSA/CUL markings.

Caution:
Equipment int
enclosure, as defined by Underwriters Laboratories (UL).

Caution:
To maintain compliance with UL and CSA/CUL, install the equipment using UL/CSA­recognised parts for: cables, protective fuses, fuse holders and circuit breakers,
insulation crimp terminals, and replacement internal batteries.

ended for rack or panel mounting is for use on a flat surface of a Type 1

4.4 FUSING REQUIREMENTS

Caution:
Wher

e UL/CSA listing of the equipment is required for external fuse protection, a UL or
CSA Listed fuse must be used for the auxiliary supply. The listed protective fuse type is:
Class J time delay fuse, with a maximum current rating of 15 A and a minimum DC
rating of 250 V dc (for example type AJT15).

Caution:

e UL/CSA listing of the equipment is not required, a high rupture capacity (HRC)

Wher
fuse type with a maximum current rating of 16 Amps and a minimum dc rating of 250 V
dc may be used for the auxiliary supply (for example Red Spot type NIT or TIA).
For P50 models, use a 1A maximum T-type fuse.
For P60 models, use a 4A maximum T-type fuse.

P64x-TM-EN-1.3 19

Chapter 2 - Safety Information P64x

Caution:
Digital input cir
maximum rating of 16 A. for safety reasons, current transformer circuits must never be
fused. Other circuits should be appropriately fused to protect the wire used.

Caution:

s must NOT be fused since open circuiting them may produce lethal hazardous

CT
voltages

cuits should be protected by a high rupture capacity NIT or TIA fuse with

4.5 EQUIPMENT CONNECTIONS

Warning:
Terminals exposed during installation, commissioning and maintenance may present a
hazardous voltage unless the equipment is electrically isolated.

Caution:

en M4 clamping screws of heavy duty terminal block connectors to a nominal

Tight
torque of 1.3 Nm.
Tighten captive screws of terminal blocks to 0.5 Nm minimum and 0.6 Nm maximum.

Caution:
Always use insulated crimp terminations for voltage and current connections.

Caution:
Alw

ays use the correct crimp terminal and tool according to the wire size.

Caution:

atchdog (self-monitoring) contacts are provided to indicate the health of the device

W
on some products. We strongly recommend that you hard wire these contacts into the
substation's automation system, for alarm purposes.

4.6 PROTECTION CLASS 1 EQUIPMENT REQUIREMENTS

Caution:

th the equipment with the supplied PCT (Protective Conductor Terminal).

Ear

Caution:
Do not r

Caution:
The P
after adding or removing such earth connections.

20 P64x-TM-EN-1.3

emove the PCT.

CT is sometimes used to terminate cable screens. Always check the PCT’s integrity

P64x Chapter 2 - Safety Information

Caution:
Use a locknut or similar mechanism t

Caution:

ecommended minimum PCT wire size is 2.5 mm² for countries whose mains supply

The r
is 230 V (e.g. Europe) and 3.3 mm² for countries whose mains supply is 110 V (e.g. North
America). This may be superseded by local or country wiring regulations.
For P60 products, the recommended minimum PCT wire size is 6 mm². See product
documentation for details.

Caution:
The PCT connection must have low-inductance and be as short as possible.

Caution:
All connections t
pre-wired, but not used, should be earthed, or connected to a common grouped
potential.

o the equipment must have a defined potential. Connections that are

o ensure the integrity of stud-connected PCTs.

4.7 PRE-ENERGISATION CHECKLIST

Caution:
Check v

Caution:
Check CT cir

Caution:
Check pr

Caution:
Check int

Caution:
Check v
application.

oltage rating/polarity (rating label/equipment documentation).

cuit rating (rating label) and integrity of connections.

otective fuse or miniature circuit breaker (MCB) rating.

egrity of the PCT connection.

oltage and current rating of external wiring, ensuring it is appropriate for the

4.8 PERIPHERAL CIRCUITRY

Warning:
Do not open the secondary circuit of a live CT since the high voltage produced may be
lethal to personnel and could damage insulation. Short the secondary of the line CT
before opening any connections to it.

P64x-TM-EN-1.3 21

Chapter 2 - Safety Information P64x

Note:
For most Alst
is automatically shorted if the module is removed. Therefore external shorting of the CTs may not be required. Check the
equipment documentation and wiring diagrams first to see if this applies.

om equipment with ring-terminal connections, the threaded terminal block for current transformer termination

Caution:

e external components such as resistors or voltage dependent resistors (VDRs) are

Wher
used, these may present a risk of electric shock or burns if touched.

Warning:
T

ake extreme care when using external test blocks and test plugs such as the MMLG,
MMLB and P990, as hazardous voltages may be exposed. Ensure that CT shorting links
are in place before removing test plugs, to avoid potentially lethal voltages.

4.9 UPGRADING/SERVICING

Warning:
Do not inser

t or withdraw modules, PCBs or expansion boards from the equipment
while energised, as this may result in damage to the equipment. Hazardous live
voltages would also be exposed, endangering personnel.

Caution:
Int

ernal modules and assemblies can be heavy and may have sharp edges. Take care

when inserting or removing modules into or out of the IED.

22 P64x-TM-EN-1.3

P64x Chapter 2 - Safety Information

5 DECOMMISSIONING AND DISPOSAL

Caution:

e decommissioning, completely isolate the equipment power supplies (both poles

Befor
of any dc supply). The auxiliary supply input may have capacitors in parallel, which may
still be charged. To avoid electric shock, discharge the capacitors using the external
terminals before decommissioning.

Caution:
Av

oid incineration or disposal to water courses. Dispose of the equipment in a safe,
responsible and environmentally friendly manner, and if applicable, in accordance with
country-specific regulations.

P64x-TM-EN-1.3 23

Chapter 2 - Safety Information P64x

6 STANDARDS COMPLIANCE

Compliance with the European Commission Directive on EMC and LVD is demonstrated by self certification against
international standar

6.1 EMC COMPLIANCE: 2004/108/EC

Compliance with EN60255-26:2009 was used to establish conformity.

6.2 PRODUCT SAFETY: 2006/95/EC

Compliance with EN60255-27:2005 was used to establish conformity.

otective Class

Pr

IEC 60255-27: 2005 Class 1 (unless otherwise specified in equipment documentation). This equipment requires a
protective conductor (earth) to ensure user safety.

ds.

Installation category

IEC 60255-27: 2005 Overvoltage Category 3. Equipment in this category is qualification tested at 5kV peak, 1.2/50
mS, 500 Ohms, 0.5 J, between all supply circuits and earth and also between independent circuits.

Environment

IEC 60255-27: 2005, IEC 60255-26:2009. The equipment is intended for indoor use only. If it is required for use in an
outdoor environment, it must be mounted in a cabinet with the appropriate degree of ingress protection.

6.3 R&TTE COMPLIANCE

Radio and Telecommunications Terminal Equipment (R&TTE) directive 99/5/EC.

Conformity is demonstrated by compliance to both the EMC dir

ective and the Low Voltage directive, to zero volts.

6.4 UL/CUL COMPLIANCE

If marked with this logo, the product is compliant with the requirements of the Canadian and USA Underwriters
Laboratories.

The r

elevant UL file number and ID is shown on the equipment.

6.5 ATEX COMPLIANCE

If marked with the logo, the equipment is compliant with article 192 of European directive 94/9/EC. It is approved
for operation outside an A
motors with rated ATEX protection, equipment category 2, to ensure their safe operation in gas zones 1 and 2
hazardous areas.

Equipment with this marking is not itself suitable for operation within a potentially explosive
atmospher

24 P64x-TM-EN-1.3

TEX hazardous area. It is however approved for connection to Increased Safety, "Ex e",

e.

P64x Chapter 2 - Safety Information

Compliance demonstrated by Notified Body Type Examination Certificate.

ATEX Potentially Explosive Atmospheres directive 94/9/EC for equipment.

P64x-TM-EN-1.3 25

Chapter 2 - Safety Information P64x

26 P64x-TM-EN-1.3

CHAPTER 3

HARDWARE DESIGN

Chapter 3 - Hardware Design P64x

28 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

1 CHAPTER OVERVIEW

This chapter provides information about the product's hardware design.

This chapter contains the following sections:

Chapter Overview 29

dware Architecture 30

Har

Mechanical Implementation 31

Front Panel 34

Rear Panel 38

Boards and Modules 40

P64x-TM-EN-1.3 29

Communications

Analogue Inputs

I/O

I

n

t

e

r

c

o

n

n

e

c

t

i

o

n

Output relay boards

Opto-input boards

CTs

VTs

RS485 modules

Ethernet modules

Keypad

LCD

LEDs

Front port

Watchdog module

PSU module

Watchdog

contacts

+ LED

Auxiliary

Supply

IRIG-B module

P

r

o

c

e

s

s

o

r

m

o

d

u

l

e

F

r

o

n

t

p

a

n

e

l

H

M

I

Output relay contacts

Digital inputs

Power system currents

Power system voltages

RS485 communication

Time synchronisation

Ethernet communication

V00233

Note: Not all modules are applicable to all products

Memory

Flash memory for settings

Battery-backed SRAM

for records

Chapter 3 - Hardware Design P64x

2 HARDWARE ARCHITECTURE

The main components comprising devices based on the Px4x platform are as follows:

● The housing, consisting of a fr

ont panel and connections at the rear

● The Main processor module consisting of the main CPU (Central Processing Unit), memory and an interface

to the front panel HMI (Human Machine Interface)

● A selection of plug-in boards and modules with presentation at the rear for the power supply,

communication functions, digital I/O, analogue inputs, and time synchronisation connectivity

All boards and modules are connected by a parallel data and address bus, which allows the processor module to
send and receive information to and from the other modules as required. There is also a separate serial data bus
for conveying sampled data from the input module to the CPU. These parallel and serial databuses are shown as a
single interconnection module in the following figure, which shows typical modules and the flow of data between
them.

Figure 3: Hardware architecture

30 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

3 MECHANICAL IMPLEMENTATION

All products based on the Px4x platform have common hardware architecture. The hardware is modular and
consists of the following main par

● Case and terminal blocks

● Boards and modules

● Front panel

The case comprises the housing metalwork and terminal blocks at the rear. The boards fasten into the terminal
blocks and are connected together by a ribbon cable. This ribbon cable connects to the processor in the front
panel.

The following diagram shows an exploded view of a typical product. The diagram shown does not necessarily
represent exactly the product model described in this manual.

ts:

Figure 4: Exploded view of IED

3.1 HOUSING VARIANTS

The Px4x range of products are implemented in a range of case sizes. Case dimensions for industrial products
usually follow modular measur

● 1U = 1.75 inches = 44.45 mm

● 1TE = 0.2 inches = 5.08 mm

The products are available in panel-mount or standalone versions. All products are nominally 4U high. This equates
to 177.8 mm or 7 inches.

The cases are pre-finished steel with a conductive covering of aluminium and zinc. This provides good grounding
at all joints, providing a low resistance path to earth that is essential for performance in the presence of external
noise.

The case width depends on the product type and its hardware options. There are three different case widths for
the described range of products: 40TE, 60TE and 80TE. The case dimensions and compatibility criteria are as
follows:

P64x-TM-EN-1.3 31

ement units based on rack sizes. These are: U for height and TE for width, where:

Chapter 3 - Hardware Design P64x

Case width (TE) Case width (mm) Case width (inches)

40TE 203.2 8

60TE 304.8 12

80TE 406.4 16

Note:
Not all case sizes ar

e available for all models.

3.2 LIST OF BOARDS

The product's hardware consists of several modules drawn from a standard range. The exact specification and
number of har
product in question will use a selection of the following boards.

Main Processor board – 40TE or smaller Main Processor board – without support for function keys

Main Processor board – 60TE or larger Main Processor board – with support for function keys

Power supply board 24/54 V DC Power supply input. Accepts DC voltage between 24 V and 54 V

Power supply board - 48/125 V DC Power supply input. Accepts DC voltage between 48 V and 125 V

Power supply board 110/250 V DC Power supply input. Accepts DC voltage between 110 V and 250 V

Instrument Transformer board Contains the voltage and current transformers

Input board Contains the A/D conversion circuitry

Input board with opto-inputs Contains the A/D conversion circuitry + 8 digital opto-inputs

Opto-input board Contains 8 digital opto-inputs

Output relay board Contains 8 digital output relays

Combined Opto-input / Output relay board Contains 4 digital opto-inputs and 4 digital output relays

IRIG-B board - modulated Interface board for modulated IRIG-B timing signal

IRIG-B - demodulated input Interface board for demodulated IRIG-B timing signal

Fibre optic board Interface board for fibre-based RS485 connection

Fibre optic board + IRIG-B Interface board for fibre-based RS485 connection + demodulated IRIG-B

2nd rear communications board Interface board for RS232 / RS485 connections

2nd rear communications board with IRIG-B input Interface board for RS232 / RS485 + IRIG-B connections

100 MHz Ethernet board Standard 100 MHz Ethernet board for LAN connection (fibre + copper)

100 MHz Ethernet board with modulated IRIG-B Standard 100 MHz Ethernet board (fibre / copper) + modulated IRIG-B

100 MHz Ethernet board with demodulated IRIG-B Standard 100 MHz Ethernet board (fibre / copper)+ demodulated IRIG-B

Redundant Ethernet SHP + modulated IRIG-B Redundant SHP Ethernet board (2 fibre ports) + modulated IRIG-B input

Redundant Ethernet SHP + demodulated IRIG-B Redundant SHP Ethernet board (2 fibre ports) + demodulated IRIG-B input

Redundant Ethernet RSTP + modulated IRIG-B Redundant RSTP Ethernet board (2 fibre ports) + modulated IRIG-B input

Redundant Ethernet RSTP + demodulated IRIG-B Redundant RSTP Ethernet board (2 fibre ports) + demodulated IRIG-B input

Redundant Ethernet DHP + modulated IRIG-B Redundant DHP Ethernet board (2 fibre ports) + modulated IRIG-B input

Redundant Ethernet DHP + demodulated IRIG-B Redundant DHP Ethernet board (2 fibre ports) + demodulated IRIG-B input

Redundant Ethernet PRP + modulated IRIG-B Redundant PRP Ethernet board (2 fibre ports) + modulated IRIG-B input

Redundant Ethernet PRP + demodulated IRIG-B Redundant PRP Ethernet board (2 fibre ports) + demodulated IRIG-B input

Redundant Ethernet HSR + modulated IRIG-B Redundant HSR Ethernet board (2 fibre ports) + modulated IRIG-B input

Redundant Ethernet HSR + demodulated IRIG-B Redundant HSR Ethernet board (2 fibre ports) + demodulated IRIG-B input

Output relay output board (8 outputs) Standard output relay board with 8 outputs

dware modules depends on the model number and variant. Depending on the exact model, the

Board Use

32 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

Board Use

RTD board Contains 10 Resistive Temperature Device inputs

CLIO board Contains 4 current loop inputs and 4 current loop outputs

High Break Output Relay Board Output relay board with high breaking capacity relays

P64x-TM-EN-1.3 33

Chapter 3 - Hardware Design P64x

4 FRONT PANEL

4.1 FRONT PANEL

Depending on the exact model and chosen options, the product will be housed in either a 40TE, 60TE or 80TE case.
By w

ay of example, the following diagram shows the front panel of a typical 60TE unit. The front panels of the
products based on 40TE and 80TE cases have a lot of commonality and differ only in the number of hotkeys and
user-programmable LEDs. The hinged covers at the top and bottom of the front panel are shown open. An optional
transparent front cover physically protects the front panel.

Figure 5: Front panel (60TE)

The fr

ont panel consists of:

● Top and bottom compartments with hinged cover

● LCD display

● Keypad

● 9 pin D-type serial port

● 25 pin D-type parallel port

● Fixed function LEDs

● Function keys and LEDs (60TE and 80TE models)

● Programmable LEDs (60TE and 80TE models)

4.1.1 FRONT PANEL COMPARTMENTS

The top compartment contains labels for the:

● Serial number

● Curr

ent and voltage ratings.

34 P64x-TM-EN-1.3

V00262

Clear key
F

or clearing the last

command

Read key
For viewing larger
blocks of text

Cursor keys
For navigating the
menus

Enter key
For executing the
chosen option

Hot keys
For scrolling through the default display
and for control of setting groups

Function keys
For executing user programmable
functions (not all models)

Monochrome LCD display
3 lines of 16 characters displays
selected option

P64x Chapter 3 - Hardware Design

The bottom compartment contains:

● A compar

tment for a 1/2 AA size backup battery (used to back up the real time clock and event, fault , and

disturbance records).

● A 9-pin female D-type front port for an EIA(RS)232 serial connection to a PC.

● A 25-pin female D-type parallel port for monitoring internal signals and downloading software and

language text.

4.1.2 HMI PANEL

The keypad provides full access to the device functionality using a range of menu options. The information is
display

ed on the LCD.The LCD is a high resolution monochrome display with 16 characters by 3 lines and

controllable back light.

Figure 6: HMI panel

Not

e:

As the LCD display has a resolution of 16 characters by 3 lines, some of the information is in a condensed mnemonic form.

4.1.3 FRONT SERIAL PORT (SK1)

The front serial port is a 9-pin female D-type connector, providing RS232 serial data communication. It is situated
under the bottom hinged cov
settings data between the PC and the IED.

The port is intended for temporary connection during testing, installation and commissioning. It is not intended to
be used for permanent SCADA communications. This port supports the Courier communication protocol only.
Courier is a proprietary communication protocol to allow communication with a range of protection equipment,
and between the device and the Windows-based support software package.

This port can be considered as a DCE (Data Communication Equipment) port, so you can connect this port device
to a PC with an EIA(RS)232 serial cable up to 15 m in length.

P64x-TM-EN-1.3 35

er, and is used to communicate with a locally connected PC. It is used to transfer

Chapter 3 - Hardware Design P64x

The inactivity timer for the front port is set to 15 minutes. This controls how long the unit maintains its level of

ord access on the front port. If no messages are received on the front port for 15 minutes, any password

passw
access level that has been enabled is cancelled.

Note:
The front serial port does not support automatic extraction of event and disturbance records, although this data can be
accessed manually.

4.1.3.1 FRONT SERIAL PORT (SK1) CONNECTIONS

The port pin-out follows the standard for Data Communication Equipment (DCE) device with the following pin
connections on a 9-pin connector

Pin number Description

2 Tx Transmit data

3 Rx Receive data

5 0 V Zero volts common

.

You must use the correct serial cable, or the communication will not work. A straight-through serial cable is
r

equired, connecting pin 2 to pin 2, pin 3 to pin 3, and pin 5 to pin 5.

Once the physical connection from the unit to the PC is made, the PC’s communication settings must be set to
match those of the IED. The following table shows the unit’s communication settings for the front port.

Protocol Courier

Baud rate 19,200 bps

Courier address 1

Message format 11 bit - 1 start bit , 8 data bits, 1 parity bit (even parity), 1 stop bit

4.1.4 FRONT PARALLEL PORT (SK2)

The front parallel port uses a 25 pin D-type connector. It is used for commissioning, downloading firmware updates
and menu text editing.

4.1.5 FIXED FUNCTION LEDS

Four fixed-function LEDs on the left-hand side of the front panel indicate the following conditions.

● Trip (R

● Alarm (Yellow) flashes when the IED registers an alarm. This may be triggered by a fault, event or

● Out of service (Yellow) is ON when the IED's functions are unavailable.

● Healthy (Green) is ON when the IED is in correct working order, and should be ON at all times. It goes OFF if

ed) switches ON when the IED issues a trip signal. It is reset when the associated fault record is

cleared from the front display. Also the trip LED can be configured as self-resetting.

maintenance record. The LED flashes until the alarms have been accepted (read), then changes to
constantly ON. When the alarms are cleared, the LED switches OFF.

the unit’s self-tests show there is an error in the hardware or software. The state of the healthy LED is
reflected by the watchdog contacts at the back of the unit.

4.1.6 FUNCTION KEYS

The programmable function keys are available for custom use for some models.

actory default settings associate specific functions to these keys, but by using programmable scheme logic, you

F
can change the default functions of these keys to fit specific needs. Adjacent to these function keys are
programmable LEDs, which are usually set to be associated with their respective function keys.

36 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

4.1.7 PROGRAMABLE LEDS

The device has a number of programmable LEDs, which can be associated with PSL-generated signals. The
pr

ogrammable LEDs for most models are tri-colour and can be set to RED, YELLOW or GREEN. However the
programmable LEDs for some models are single-colour (red) only. The single-colour LEDs can be recognised by
virtue of the fact they are large and slightly oval, whereas the tri-colour LEDs are small and round.

P64x-TM-EN-1.3 37

Chapter 3 - Hardware Design P64x

5 REAR PANEL

The MiCOM Px40 series uses a modular construction. Most of the internal workings are on boards and modules
which fit into slots. Some of the boar
However, some boards such as the communications boards have their own connectors. The rear panel consists of
these terminal blocks plus the rears of the communications boards.

The back panel cut-outs and slot allocations vary. This depends on the product, the type of boards and the
terminal blocks needed to populate the case. The following diagram shows a typical rear view of a case populated
with various boards.

ds plug into terminal blocks, which are bolted onto the rear of the unit.

Figure 7: Rear view of populated case

e:

Not
This diagram is just an example and may not show the exact product described in this manual. It also does not show the full
range of available boards, just a typical arrangement.

Not all slots are the same size. The slot width depends on the type of board or terminal block. For example, HD
(heavy duty) terminal blocks, as r

equired for the analogue inputs, require a wider slot size than MD (medium duty)
terminal blocks. The board positions are not generally interchangeable. Each slot is designed to house a particular
type of board. Again this is model-dependent.

The device may use one or more of the terminal block types shown in the following diagram. The terminal blocks
are fastened to the rear panel with screws.

● Heavy duty (HD) terminal blocks for CT and VT circuits

● Medium duty (MD) terminal blocks for the power supply, opto-inputs, relay outputs and rear

communications port

● MiDOS terminal blocks for CT and VT circuits

● RTD/CLIO terminal block for connection to analogue transducers

38 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

,

Figure 8: Terminal block types

e:

Not
Not all products use all types of terminal blocks. The product described in this manual may use one or more of the above
types.

P64x-TM-EN-1.3 39

Chapter 3 - Hardware Design P64x

6 BOARDS AND MODULES

Each product comprises a selection of PCBs (Printed Circuit Boards) and subassemblies, depending on the chosen
configuration.

6.1 PCBS

A PCB typically consists of the components, a front connector for connecting into the main system parallel bus via
a ribbon cable, and an inter

● Directly presented to the outside world (as is the case for communication boards such as Ethernet Boards)

● Presented to a connector, which in turn connects into a terminal block bolted onto the rear of the case (as is

the case for most of the other board types)

face to the rear. This rear interface may be:

Figure 9: Rear connection to terminal block

6.2 SUBASSEMBLIES

A sub-assembly consists of two or more boards bolted together with spacers and connected with electrical
connectors. It may also have other special requirements such as being encased in a metal housing for shielding
against electromagnetic radiation.

Boards are designated by a part number beginning with ZN, whereas pre-assembled sub-assemblies are
designated with a part number beginning with GN. Sub-assemblies, which are put together at the production
stage, do not have a separate part number.

40 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

The products in the Px40 series typically contain two sub-assemblies:

● The pow

● The input module comprising:

The input module is pre-assembled and is therefore assigned a GN number, whereas the power supply module is
assembled at production stage and does not therefore have an individual part number.

er supply assembly comprising:

○ A power supply board
○ An output relay board

○ One or more transformer boards, which contains the voltage and current transformers (partially or

fully populated)

○ One or more input boards
○ Metal protective covers for EM (electromagnetic) shielding

6.3 MAIN PROCESSOR BOARD

Figure 10: Main processor board

The main pr
including the data communication and user interfaces. This is the only board that does not fit into one of the slots.
It resides in the front panel and connects to the rest of the system using an internal ribbon cable.

The LCD and LEDs are mounted on the processor board along with the front panel communication ports.

The memory on the main processor board is split into two categories: volatile and non-volatile. The volatile
memory is fast access SRAM, used by the processor to run the software and store data during calculations. The
non-volatile memory is sub-divided into two groups:

● Flash memory to store software code, text and configuration data including the present setting values.

● Battery-backed SRAM to store disturbance, event, fault and maintenance record data.

There are two board types available depending on the size of the case:

● For models in 40TE cases

● For models in 60TE cases and larger

ocessor board performs all calculations and controls the operation of all other modules in the IED,

P64x-TM-EN-1.3 41

Chapter 3 - Hardware Design P64x

6.4 POWER SUPPLY BOARD

Figure 11: Power supply board

The pow
board can be fitted to the unit. This is specified at the time of order and depends on the magnitude of the supply
voltage that will be connected to it.

There are three board types, which support the following voltage ranges:

The power supply board connector plugs into a medium duty terminal block. This terminal block is always
positioned on the right hand side of the unit looking from the rear.

The power supply board is usually assembled together with a relay output board to form a complete subassembly,
as shown in the following diagram.

er supply board provides power to the unit. One of three different configurations of the power supply

● 24/54 V DC

● 48/125 V DC or 40-100V AC

● 110/250 V DC or 100-240V AC

42 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

Figure 12: Power supply assembly

The power supply outputs are used to provide isolated power supply rails to the various modules within the unit.
Three voltage levels are used by the unit’s modules:

● 5.1 V for all of the digital circuits

● +/- 16 V for the analogue electronics such as on the input board

● 22 V for driving the output relay coils.

All power supply voltages, including the 0 V earth line, are distributed around the unit by the 64-way ribbon cable.

The power supply board incorporates inrush current limiting. This limits the peak inrush current to approximately
10 A.

Power is applied to pins 1 and 2 of the terminal block, where pin 1 is negative and pin 2 is positive. The pin
numbers are clearly marked on the terminal block as shown in the following diagram.

P64x-TM-EN-1.3 43

Chapter 3 - Hardware Design P64x

Figure 13: Power supply terminals

6.4.1 WATCHDOG

The Watchdog contacts are also hosted on the power supply board. The Watchdog facility provides two output
r

elay contacts, one normally open and one normally closed. These are used to indicate the health of the device
and are driven by the main processor board, which continually monitors the hardware and software when the
device is in service.

44 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

Figure 14: Watchdog contact terminals

6.4.2 REAR SERIAL PORT

The rear serial port (RP1) is housed on the power supply board. This is a three-terminal EIA(RS)485 serial
communications por
SCADA communication. The interface supports half-duplex communication and provides optical isolation for the
serial data being transmitted and received.

The physical connectivity is achieved using three screw terminals; two for the signal connection, and the third for
the earth shield of the cable. These are located on pins 16, 17 and 18 of the power supply terminal block, which is
on the far right looking from the rear. The interface can be selected between RS485 and K-bus. When the K-Bus
option is selected, the two signal connections are not polarity conscious.

The polarity independent K-bus can only be used for the Courier data protocol. The polarity conscious MODBUS,
IEC 60870-5-103 and DNP3.0 protocols need RS485.

The following diagram shows the rear serial port. The pin assignments are as follows:

● Pin 16: Earth shield

● Pin 17: Negative signal

● Pin 18: Positive signal

t and is intended for use with a permanently wired connection to a remote control centre for

P64x-TM-EN-1.3 45

Chapter 3 - Hardware Design P64x

Figure 15: Rear serial port terminals

An additional serial por

t with D-type presentation is available as an optional board, if required.

6.5 INPUT MODULE - 1 TRANSFORMER BOARD

Figure 16: Input module - 1 transformer board

The input module consists of the main input boar
instrument transformer board contains the voltage and current transformers, which isolate and scale the
analogue input signals delivered by the system transformers. The input board contains the A/D conversion and
digital processing circuitry, as well as eight digital isolated inputs (opto-inputs).

The boards are connected together physically and electrically. The module is encased in a metal housing for
shielding against electromagnetic interference.

46 P64x-TM-EN-1.3

d coupled together with an instrument transformer board. The

V00239

Transformer

board

Serial

interface

Serial Link

Optical

Isolator

Noise

filter

Optical

Isolator

Noise

filter

Buffer

8 digital inputs

Parallel Bus

VT
or
CT

A/D Converter

VT
or
CT

P64x Chapter 3 - Hardware Design

6.5.1 INPUT MODULE CIRCUIT DESCRIPTION

Figure 17: Input module schematic

A/D Conv

ersion

The differential analogue inputs from the CT and VT transformers are presented to the main input board as shown.
Each differential input is first converted to a single input quantity referenced to the input board’s earth potential.
The analogue inputs are sampled and converted to digital, then filtered to remove unwanted properties. The
samples are then passed through a serial interface module which outputs data on the serial sample data bus.

The calibration coefficients are stored in non-volatile memory. These are used by the processor board to correct
for any amplitude or phase errors introduced by the transformers and analogue circuitry.

Opto-isolated inputs

The other function of the input board is to read in the state of the digital inputs. As with the analogue inputs, the
digital inputs must be electrically isolated from the power system. This is achieved by means of the 8 on-board
optical isolators for connection of up to 8 digital signals. The digital signals are passed through an optional noise
filter before being buffered and presented to the unit’s processing boards in the form of a parallel data bus.

This selectable filtering allows the use of a pre-set filter of ½ cycle which renders the input immune to induced
power-system noise on the wiring. Although this method is secure it can be slow, particularly for inter-tripping. This
can be improved by switching off the ½ cycle filter, in which case one of the following methods to reduce ac noise
should be considered.

● Use double pole switching on the input

● Use screened twisted cable on the input circuit

The opto-isolated logic inputs can be configured for the nominal battery voltage of the circuit for which they are a
part, allowing different voltages for different circuits such as signalling and tripping.

P64x-TM-EN-1.3 47

Ideal anti-alias filter response

Real anti-alias filter

response

2 3 4

1

0.2

0.4

0.6

0.8

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 241

50 Hz 600 Hz

1200 Hz

V00301

Fourier response without

anti-alias filter

Fourier response with

anti-alias filter

Alias frequency

Chapter 3 - Hardware Design P64x

Note:

o-input circuitry can be provided without the A/D circuitry as a separate board, which can provide supplementary

The opt
opto-inputs.

6.5.2 FREQUENCY RESPONSE

With the exception of the RMS measurements, all other measurements and protection functions are based on the
Fourier

-derived fundamental component. The fundamental component is extracted by using a 24 sample Discrete
Fourier Transform (DFT). This gives good harmonic rejection for frequencies up to the 23rd harmonic. The 23rd is
the first predominant harmonic that is not attenuated by the Fourier filter and this is known as an ‘Alias’. However,
the Alias is attenuated by approximately 85% by an additional, analogue, ‘anti-aliasing’ filter (low pass filter). The
combined affect of the anti-aliasing and Fourier filters is shown below.

Figure 18: Frequency response

For pow

er frequencies that are not equal to the selected rated frequency, the harmonics are attenuated to zero
amplitude. For small deviations of +/-1 Hz, this is not a problem but to allow for larger deviations, frequency
tracking is used.

Frequency tracking automatically adjusts the sampling rate of the analog to digital conversion to match the
applied signal. In the absence of a suitable signal to amplitude track, the sample rate defaults to the selected rated
frequency (Fn). If the a signal is in the tracking range of 45 to 66 Hz, the relay locks onto the signal and the
measured frequency coincides with the power frequency. The outputs for harmonics up to the 23rd are zero. The
device frequency tracks off any voltage or current in the order VA/VB/VC/IA/IB/IC down to 10% Vn for voltage and
5%In for current.

48 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

6.5.3 TRANSFORMER BOARD

Figure 19: Transformer board

The transformer boar
voltages originating from the power systems' current and voltage transformers to levels that can be used by the
devices' electronic circuitry. In addition to this, the on-board CT and VT transformers provide electrical isolation
between the unit and the power system.

The transformer board is connected physically and electrically to the input board to form a complete input module.

For terminal connections, please refer to the wiring diagrams.

d hosts the current and voltage transformers. These are used to step down the currents and

P64x-TM-EN-1.3 49

Chapter 3 - Hardware Design P64x

6.5.4 INPUT BOARD

Figure 20: Input board

The input boar

d is used to convert the analogue signals delivered by the current and voltage transformers into
digital quantities used by the IED. This input board also has on-board opto-input circuitry, providing eight optically­isolated digital inputs and associated noise filtering and buffering. These opto-inputs are presented to the user by
means of a MD terminal block, which sits adjacent to the analogue inputs HD terminal block.

The input board is connected physically and electrically to the transformer board to form a complete input module.

The terminal numbers of the opto-inputs are as follows:

Terminal Number Opto-input

Terminal 1 Opto 1 -ve

Terminal 2 Opto 1 +ve

Terminal 3 Opto 2 -ve

Terminal 4 Opto 2 +ve

Terminal 5 Opto 3 -ve

Terminal 6 Opto 3 +ve

Terminal 7 Opto 4 -ve

Terminal 8 Opto 4 +ve

Terminal 9 Opto 5 -ve

Terminal 10 Opto 5 +ve

Terminal 11 Opto 6 -ve

Terminal 12 Opto 6 +ve

Terminal 13 Opto 7 –ve

Terminal 14 Opto 7 +ve

Terminal 15 Opto 8 –ve

Terminal 16 Opto 8 +ve

50 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

Terminal Number Opto-input

Terminal 17 Common

Terminal 18 Common

6.6 STANDARD OUTPUT RELAY BOARD

Figure 21: Standard output relay board - 8 contacts

This output r

elay board has 8 relays with 6 Normally Open contacts and 2 Changeover contacts.

The output relay board is provided together with the power supply board as a complete assembly, or
independently for the purposes of relay output expansion.

There are two cut-out locations in the board. These can be removed to allow power supply components to
protrude when coupling the output relay board to the power supply board. If the output relay board is to be used
independently, these cut-out locations remain intact.

The terminal numbers are as follows:

Terminal Number Output Relay

Terminal 1 Relay 1 NO

Terminal 2 Relay 1 NO

Terminal 3 Relay 2 NO

Terminal 4 Relay 2 NO

Terminal 5 Relay 3 NO

Terminal 6 Relay 3 NO

Terminal 7 Relay 4 NO

Terminal 8 Relay 4 NO

Terminal 9 Relay 5 NO

Terminal 10 Relay 5 NO

P64x-TM-EN-1.3 51

Chapter 3 - Hardware Design P64x

Terminal Number Output Relay

Terminal 11 Relay 6 NO

Terminal 12 Relay 6 NO

Terminal 13 Relay 7 changeover

Terminal 14 Relay 7 changeover

Terminal 15 Relay 7 common

Terminal 16 Relay 8 changeover

Terminal 17 Relay 8 changeover

Terminal 18 Relay 8 common

6.7 IRIG-B BOARD

Figure 22: IRIG-B board

The IRIG-B boar

d can be fitted to provide an accurate timing reference for the device. The IRIG-B signal is
connected to the board via a BNC connector. The timing information is used to synchronise the IED's internal real­time clock to an accuracy of 1 ms. The internal clock is then used for time tagging events, fault, maintenance and
disturbance records.

IRIG-B interface is available in modulated or demodulated formats.

The IRIG-B facility is provided in combination with other functionality on a number of additional boards, such as:

● Fibre board with IRIG-B

● Second rear communications board with IRIG-B

● Ethernet board with IRIG-B

● Redundant Ethernet board with IRIG-B

There are two types of each of these boards; one type which accepts a modulated IRIG-B input and one type
which accepts a demodulated IRIG-B input.

52 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

6.8 FIBRE OPTIC BOARD

Figure 23: Fibre optic board

This boar
compatible protocols (Courier, IEC 60870-5-103, MODBUS and DNP 3.0). It is a fibre-optic alternative to the metallic
RS485 port presented on the power supply terminal block. The metallic and fibre optic ports are mutually exclusive.

The fibre optic port uses BFOC 2.5 ST connectors.

The board comes in two varieties; one with an IRIG-B input and one without:

d provides an interface for communicating with a master station. This communication link can use all

P64x-TM-EN-1.3 53

Chapter 3 - Hardware Design P64x

6.9 REAR COMMUNICATION BOARD

Figure 24: Rear communication board

The optional communications boar
presented on 9 pin D-type connectors. These interfaces are known as SK4 and SK5. Both connectors are female
connectors, but are configured as DTE ports. This means pin 2 is used to transmit information and pin 3 to receive.

SK4 can be used with RS232, RS485 and K-bus. SK5 can only be used with RS232 and is used for electrical
teleprotection. The optional rear communications board and IRIG-B board are mutually exclusive since they use
the same hardware slot. However, the board comes in two varieties; one with an IRIG-B input and one without.

d containing the secondary communication ports provide two serial interfaces

6.10 ETHERNET BOARD

Figure 25: Ethernet board

54 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

This is a communications board that provides a standard 100-Base Ethernet interface. This board supports one
electrical copper connection and one fibr

e-pair connection.

There are several variants for this board as follows:

● 100 Mbps Ethernet board

● 100 Mbps Ethernet with on-board modulated IRIG-B input

● 100 Mbps Ethernet with on-board unmodulated IRIG-B input

Two of the variants provide an IRIG-B interface. IRIG-B provides a timing reference for the unit – one board for
modulated IRIG-B and one for demodulated. The IRIG B signal is connected to the board with a BNC connector.

The Ethernet and other connection details are described below:

IRIG-B Connector

● Centre connection: Signal

● Outer connection: Earth

LEDs

LED Function On Off Flashing

Green Link Link ok Link broken

Yellow Activity Traffic

Optical Fibre Connectors

Connector Function

Rx Receive

Tx Transmit

RJ45connector

Pin Signal name Signal definition

1 TXP Transmit (positive)

2 TXN Transmit (negative)

3 RXP Receive (positive)

4 - Not used

5 - Not used

6 RXN Receive (negative)

7 - Not used

8 - Not used

P64x-TM-EN-1.3 55

IRIG-B

Pin3

Link Fail

connector

Pin 2

Pin 1

Link channel

A (green LED)

Activity channel
A (yellow LED)

Link channel B

(green LED)

Activity channel B

(yellow LED)

A

B

C

D

V01009

Chapter 3 - Hardware Design P64x

6.11 REDUNDANT ETHERNET BOARD

Figure 26: Redundant Ethernet board

This boar

d provides dual redundant Ethernet (supported by two fibre pairs) together with an IRIG-B interface for

timing.

Different board variants are available, depending on the redundancy protocol and the type of IRIG-B signal
(unmodulated or modulated). The available redundancy protocols are:

● SHP (Self healing Protocol)

● RSTP (Rapid Spanning Tree Protocol)

● DHP (Dual Homing Protocol)

● PRP (Parallel Redundancy Protocol)

There are several variants for this board as follows:

● 100 Mbps redundant Ethernet running RSTP, with on-board modulated IRIG-B

● 100 Mbps redundant Ethernet running RSTP, with on-board unmodulated IRIG-B

● 100 Mbps redundant Ethernet running SHP, with on-board modulated IRIG-B

● 100 Mbps redundant Ethernet running SHP, with on-board unmodulated IRIG-B

● 100 Mbps redundant Ethernet running DHP, with on-board modulated IRIG-B

● 100 Mbps redundant Ethernet running DHP, with on-board unmodulated IRIG-B

● 100 Mbps redundant Ethernet running PRP, with on-board modulated IRIG-B

● 100 Mbps redundant Ethernet running PRP, with on-board demodulated IRIG-B

The Ethernet and other connection details are described below:

IRIG-B Connector

● Centre connection: Signal

● Outer connection: Earth

Link Fail Connector (Ethernet Board Watchdog Relay)

Pin Closed Open

1-2 Link fail Channel 1 (A) Link ok Channel 1 (A)

2-3 Link fail Channel 2 (B) Link ok Channel 2 (B)

56 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

LEDs

LED Function On Off Flashing

Green Link Link ok Link broken

Yellow Activity SHP running PRP, RSTP or DHP traffic

Optical Fibre Connectors (ST)

Connector DHP RSTP SHP PRP

A RXA RX1 RS RXA

B TXA TX1 ES TXA

C RXB RX2 RP RXB

D TXB TX2 EP TXB

RJ45connector

Pin Signal name Signal definition

1 TXP Transmit (positive)

2 TXN Transmit (negative)

3 RXP Receive (positive)

4 - Not used

5 - Not used

6 RXN Receive (negative)

7 - Not used

8 - Not used

P64x-TM-EN-1.3 57

Chapter 3 - Hardware Design P64x

6.12 RTD BOARD

Figure 27: RTD board

The R

TD board provides two banks of 15 terminals to support ten RTD inputs, of the type PT100, Ni100, or Ni120,
depending on the product. There are three terminals for each RTD, therefore 30 terminals altogether. The RTD
board fits into slot B or slot C, depending on the model variant.

The terminal numbers of the RTDs are as follows:

Terminal Number RTD connection

Terminal 1 RTD1 wire 1

Terminal 2 RTD1 wire 2

Terminal 3 RTD1 wire 3

Terminal 4 RTD2 wire 1

Terminal 5 RTD2 wire 2

Terminal 6 RTD2 wire 3

Terminal 7 RTD3 wire 1

Terminal 8 RTD3 wire 2

Terminal 9 RTD3 wire 3

Terminal 10 RTD4 wire 1

Terminal 11 RTD4 wire 2

Terminal 12 RTD4 wire 3

Terminal 13 RTD5 wire 1

Terminal 14 RTD5 wire 2

Terminal 15 RTD5 wire 3

Terminal 16 RTD6 wire 1

58 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

Terminal Number RTD connection

Terminal 17 RTD6 wire 2

Terminal 18 RTD6 wire 3

Terminal 19 RTD7 wire 1

Terminal 20 RTD7 wire 2

Terminal 21 RTD7 wire 3

Terminal 22 RTD8 wire 1

Terminal 23 RTD8 wire 2

Terminal 24 RTD8 wire 3

Terminal 25 RTD9 wire 1

Terminal 26 RTD9 wire 2

Terminal 27 RTD9 wire 3

Terminal 28 RTD10 wire 1

Terminal 29 RTD10 wire 2

Terminal 30 RTD10 wire 3

6.13 CLIO BOARD

Figure 28: RTD board

The CLIO boar

d provides two banks of 15 terminals to support four current loop inputs and four current loop
outputs. There are three terminals for each input and three for each output, therefore 24 of the terminals are used
altogether. The CLIO board fits into slot B or slot C, depending on the model variant.

The terminal numbers of the current loop inputs and outputs are as follows:

P64x-TM-EN-1.3 59

Chapter 3 - Hardware Design P64x

Terminal Number Current Loop Connection

Terminal 1 CLO1 - 20 mA input

Terminal 2 CLO1 - 1 mA input

Terminal 3 CLO1 - common input

Terminal 4 Not used

Terminal 5 CLO2 - 20 mA input

Terminal 6 CLO2 - 1 mA input

Terminal 7 CLO2 - common input

Terminal 8 Not used

Terminal 9 CLO3 - 20 mA input

Terminal 10 CLO3 - 1 mA input

Terminal 11 CLO3 - common input

Terminal 12 Not used

Terminal 13 CLO4 - 20 mA input

Terminal 14 CLO4 - 1 mA input

Terminal 15 CLO4 - common input

Terminal 16 CLI1 - 20 mA input

Terminal 17 CLI1 - 1 mA input

Terminal 18 CLI1 - common input

Terminal 19 Not used

Terminal 20 CLI2 - 20 mA input

Terminal 21 CLI2 - 1 mA input

Terminal 22 CLI2 - common input

Terminal 23 Not used

Terminal 24 CLI3 - 20 mA input

Terminal 25 CLI3 - 1 mA input

Terminal 26 CLI3 - common input

Terminal 27 Not used

Terminal 28 CLI4 - 20 mA input

Terminal 29 CLI4 - 1 mA input

Terminal 30 CLI4 - common input

60 P64x-TM-EN-1.3

P64x Chapter 3 - Hardware Design

6.14 HIGH BREAK OUTPUT RELAY BOARD

Figure 29: High Break relay output board

A High Br
are suitable for high breaking loads.

A High Break contact consists of a high capacity relay with a MOSFET in parallel with it. The MOSFET has a varistor
placed across it to provide protection, which is required when switching off inductive loads. This is because the
stored energy in the inductor causes a high reverse voltage that could damage the MOSFET, if not protected.

When there is a control input command to operate an output contact the miniature relay is operated at the same
time as the MOSFET. The miniature relay contact closes in nominally 3.5 ms and is used to carry the continuous
load current. The MOSFET operates in less than 0.2 ms, but is switched off after 7.5 ms.

When the control input is reset, the MOSFET is again turned on for 7.5 mS. The miniature relay resets in nominally

3.5 ms before the MOSFET. This means the MOSFET is used to break the load. The MOSFET absorbs the energy
when breaking inductive loads and so limits the resulting voltage surge. This contact arrangement is for switching
DC circuits only.

The board number is:

High Break Contact Operation

The following figure shows the timing diagram for High Break contact operation.

eak output relay board is available as an option. It comprises four normally open output contacts, which

● ZN0042 001

P64x-TM-EN-1.3 61

V00246

3.5ms + contact bounce

Load current

Relay contact

Databus
control input

MOSFET reset

MOSFET operate

on

7ms

on

3.5ms

Closed

on

7ms

off

Chapter 3 - Hardware Design P64x

Figure 30: High Break contact operation

High Break Contact Applications

● Efficient scheme engineering

In traditional hard wired scheme designs, High Break capability could only be achieved using external
electromechanical trip relays. Instead, these internal High Break contacts can be used thus reducing space
requirements.

● Accessibility of CB auxiliary contacts

It is common practise to use circuit breaker 52a (CB Closed) auxiliary contacts to break the trip coil current
on breaker opening, thereby easing the duty on the protection contacts. In some cases (such as operation
of disconnectors, or retrofitting), it may be that 52a contacts are either unavailable or unreliable. In such
cases, High Break contacts can be used to break the trip coil current in these applications.

● Breaker fail

In the event of failure of the local circuit breaker (stuck breaker), or defective auxiliary contacts (stuck
contacts), it is incorrect to use 52a contact action. The interrupting duty at the local breaker then falls on the
relay output contacts, which may not be rated to perform this duty. High Break contacts should be used in
this case to avoid the risk of burning out relay contacts.

● Initiation of teleprotection

The High Break contacts also offer fast making, which results in faster tripping. In addition, fast keying of
teleprotection is a benefit. Fast keying bypasses the usual contact operation time, such that permissive,
blocking and intertrip commands can be routed faster.

62 P64x-TM-EN-1.3

Warning:
These relay contacts are POLARITY SENSITIVE. External wiring must comply with the polarity
requirements described in the external connection diagram to ensure correct operation.

CHAPTER 4

SOFTWARE DESIGN

Chapter 4 - Software Design P64x

64 P64x-TM-EN-1.3

P64x Chapter 4 - Software Design

1 CHAPTER OVERVIEW

This chapter describes the software design of the IED.

This chapter contains the following sections:

Chapter Overview 65

ware Design Overview 66

Sof

System Level Software 67

Platform Software 70

Protection and Control Functions 71

P64x-TM-EN-1.3 65

V00300

R

e

c

o

r

d

s

P

r

o

t

e

c

t

i

o

n

a

n

d

c

o

n

t

r

o

l

s

e

t

t

i

n

g

s

Protection and Control Software Layer

Fault locator

task

Disturbance

recorder task

Sampling function

Control of output contacts
and programmable LEDs

Sample data + digital
logic inputs

System Level Softw are Layer

System services (e.g. device drivers) / Real time operating system / Self-diagnostic software

Control of interfaces to keypad , LCD, LEDs,
front & rear ports.
Self-checking maintenance records

Hardware Device L ayer

LEDs / LCD / Keypad / Memory / FPGA

Protection Task

Programmable &

fixed scheme logic

Fourier signal

processing

Protection
algorithms

Supervisor task

Platform Sof tw are Layer

Event, fault,

disturbance,

maintenance record

logging

Remote

communications

interfaces

Front panel

interface

(LCD + Keypad)

Local

communications

interfaces

Settings database

Chapter 4 - Software Design P64x

2 SOFWARE DESIGN OVERVIEW

The device software can be conceptually categorized into several elements as follows:

● The system lev

el software

● The platform software

● The protection and control software

These elements are not distinguishable to the user, and the distinction is made purely for the purposes of
explanation. The following figure shows the software architecture.

Figure 31: Software Architecture

The softw

are, which executes on the main processor, can be divided into a number of functions as illustrated
above. Each function is further broken down into a number of separate tasks. These tasks are then run according
to a scheduler. They are run at either a fixed rate or they are event driven. The tasks communicate with each other
as and when required.

66 P64x-TM-EN-1.3

P64x Chapter 4 - Software Design

3 SYSTEM LEVEL SOFTWARE

3.1 REAL TIME OPERATING SYSTEM

The real-time operating system is used to schedule the processing of the various tasks. This ensures that they are
pr

ocessed in the time available and in the desired order of priority. The operating system also plays a part in

controlling the communication between the software tasks, through the use of operating system messages.

3.2 SYSTEM SERVICES SOFTWARE

The system services software provides the layer between the hardware and the higher-level functionality of the
platform softw
drivers for items such as the LCD display, the keypad and the remote communication ports. It also controls things
like the booting of the processor and the downloading of the processor code into RAM at startup.

3.3 SELF-DIAGNOSTIC SOFTWARE

The device includes several self-monitoring functions to check the operation of its hardware and software while in

vice. If there is a problem with the hardware or software, it should be able to detect and report the problem, and

ser
attempt to resolve the problem by performing a reboot. In this case, the device would be out of service for a short
time, during which the ‘Healthy’ LED on the front of the device is switched OFF and the watchdog contact at the
rear is ON. If the restart fails to resolve the problem, the unit takes itself permanently out of service; the ‘Healthy’
LED stays OFF and watchdog contact stays ON.

are and the protection and control software. For example, the system services software provides

If a problem is detected by the self-monitoring functions, the device attempts to store a maintenance record to
allow the nature of the problem to be communicated to the user.

The self-monitoring is implemented in two stages: firstly a thorough diagnostic check which is performed on boot­up, and secondly a continuous self-checking operation, which checks the operation of the critical functions whilst
it is in service.

3.4 STARTUP SELF-TESTING

The self-testing takes a few seconds to complete, during which time the IED's measurement, recording, control,
and pr

otection functions are unavailable. On a successful start-up and self-test, the ‘health-state’ LED on the front
of the unit is switched on. If a problem is detected during the start-up testing, the device remains out of service
until it is manually restored to working order.

The operations that are performed at start-up are:

1. System boot

2. System software initialisation

3. Platform software initialisation and monitoring

3.4.1 SYSTEM BOOT

The integrity of the Flash memory is verified using a checksum before the program code and stored data is loaded
into R

AM for execution by the processor. When the loading has been completed, the data held in RAM is compared
to that held in the Flash memory to ensure that no errors have occurred in the data transfer and that the two are
the same. The entry point of the software code in RAM is then called. This is the IED's initialisation code.

P64x-TM-EN-1.3 67

Chapter 4 - Software Design P64x

3.4.2 SYSTEM LEVEL SOFTWARE INITIALISATION

The initialization process initializes the processor registers and interrupts, starts the watchdog timers (used by the
har

dware to determine whether the software is still running), starts the real-time operating system and creates

and starts the supervisor task. In the initialization process the device checks the following:

● The status of the backup battery

● The integrity of the battery-backed SRAM that is used to store event, fault and disturbance records

● The operation of the LCD controller

● The watchdog operation

At the conclusion of the initialization software the supervisor task begins the process of starting the platform
software.

3.4.3 PLATFORM SOFTWARE INITIALISATION AND MONITORING

When starting the platform software, the IED checks the following:

● The integrity of the data held in non-v

● The operation of the real-time clock

● The optional IRIG-B function (if applicable)

● The presence and condition of the input board

● The analog data acquisition system (it does this by sampling the reference voltage)

At the successful conclusion of all of these tests the unit is entered into service and the application software is
started up.

olatile memory (using a checksum)

3.5 CONTINUOUS SELF-TESTING

When the IED is in service, it continually checks the operation of the critical parts of its hardware and software. The

ing is carried out by the system services software and the results are reported to the platform software. The

check
functions that are checked are as follows:

● The Flash memory containing all program code and language text is verified by a checksum.

● The code and constant data held in system memory is checked against the corresponding data in Flash

memory to check for data corruption.

● The system memory containing all data other than the code and constant data is verified with a checksum.

● The integrity of the digital signal I/O data from the opto-inputs and the output relay coils is checked by the

data acquisition function every time it is executed.

● The operation of the analog data acquisition system is continuously checked by the acquisition function

every time it is executed. This is done by sampling the reference voltages.

● The operation of the optional Ethernet board is checked by the software on the main processor card. If the

Ethernet board fails to respond an alarm is raised and the card is reset in an attempt to resolve the problem.

● The operation of the optional IRIG-B function is checked by the software that reads the time and date from

the board.

● Where fitted, the operation of the RTD board is checked by reading the temperature indicated by the

reference resistors on the two spare RTD channels

● Where fitted, the operation of the CLIO board is checked

In the event that one of the checks detects an error in any of the subsystems, the platform software is notified and
it attempts to log a maintenance record.

If the problem is with the battery status or the IRIG-B board, the device continues in operation. For problems
detected in any other area, the device initiates a shutdown and re-boot, resulting in a period of up to 10 seconds
when the functionality is unavailable.

68 P64x-TM-EN-1.3

P64x Chapter 4 - Software Design

A restart should clear most problems that may occur. If, however, the diagnostic self-check detects the same

oblem that caused the IED to restart, it is clear that the restart has not cleared the problem, and the device takes

pr
itself permanently out of service. This is indicated by the ‘’health-state’ LED on the front of the device, which
switches OFF, and the watchdog contact which switches ON.

P64x-TM-EN-1.3 69

Chapter 4 - Software Design P64x

4 PLATFORM SOFTWARE

The platform software has three main functions:

o control the logging of records generated by the protection software, including alarms, events, faults, and

● T

maintenance records

● To store and maintain a database of all of the settings in non-volatile memory

● To provide the internal interface between the settings database and the user interfaces, using the front

panel interface and the front and rear communication ports

4.1 RECORD LOGGING

The logging function is used to store all alarms, events, faults and maintenance records. The records are stored in
non-v

olatile memory to provide a log of what has happened. The IED maintains four types of log on a first in first
out basis (FIFO). These are:

● Alarms

● Event records

● Fault records

● Maintenance records

The logs are maintained such that the oldest record is overwritten with the newest record. The logging function
can be initiated from the protection software. The platform software is responsible for logging a maintenance
record in the event of an IED failure. This includes errors that have been detected by the platform software itself or
errors that are detected by either the system services or the protection software function. See the Monitoring and
Control chapter for further details on record logging.

4.2 SETTINGS DATABASE

The settings database contains all the settings and data, which are stored in non-volatile memory. The platform

are manages the settings database and ensures that only one user interface can modify the settings at any

softw
one time. This is a necessary restriction to avoid conflict between different parts of the software during a setting
change.

Changes to protection settings and disturbance recorder settings, are first written to a temporary location SRAM
memory. This is sometimes called 'Scratchpad' memory. These settings are not written into non-volatile memory
immediately. This is because a batch of such changes should not be activated one by one, but as part of a
complete scheme. Once the complete scheme has been stored in SRAM, the batch of settings can be committed to
the non-volatile memory where they will become active.

4.3 INTERFACES

The settings and measurements database must be accessible from all of the interfaces to allow read and modify
operations. The platform softw
display, keypad and all the communications interfaces).

are presents the data in the appropriate format for each of the interfaces (LCD

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5 PROTECTION AND CONTROL FUNCTIONS

The protection and control software processes all of the protection elements and measurement functions. To

e this it has to communicate with the system services software, the platform software as well as organise its

achiev
own operations.

The protection task software has the highest priority of any of the software tasks in the main processor board. This
ensures the fastest possible protection response.

The protection and control software provides a supervisory task, which controls the start-up of the task and deals
with the exchange of messages between the task and the platform software.

5.1 ACQUISITION OF SAMPLES

After initialization, the protection and control task waits until there are enough samples to process. The acquisition
of samples on the main pr
services software.

This sampling function takes samples from the input module and stores them in a two-cycle FIFO buffer. The
sample rate is 24 samples per cycle. This results in a nominal sample rate of 1,200 samples per second for a 50 Hz
system and 1,440 samples per second for a 60 Hz system. However the sample rate is not fixed. It tracks the
power system frequency as described in the next section.

ocessor board is controlled by a ‘sampling function’ which is called by the system

5.2 FREQUENCY TRACKING

The device provides a frequency tracking algorithm so that there are always 24 samples per cycle irrespective of

equency drift within a certain frequency range (see technical specifications). If the frequency falls outside this

fr
range, the sample rate reverts to its default rate of 1200 Hz for 50 Hz or 1440 Hz for 60 Hz.

The frequency tracking of the analog input signals is achieved by a recursive Fourier algorithm which is applied to
one of the input signals. It works by detecting a change in the signal’s measured phase angle. The calculated value
of the frequency is used to modify the sample rate being used by the input module, in order to achieve a constant
sample rate per cycle of the power waveform. The value of the tracked frequency is also stored for use by the
protection and control task.

The frequency tracks off any voltage or current in the order VA, VB, VC, IA, IB, IC, down to 10%Vn for voltage and
5%In for current.

5.3 DIRECT USE OF SAMPLE VALUES

Most of the IED’s protection functionality uses the Fourier components calculated by the device’s signal processing

are. However RMS measurements and some special protection algorithms available in some products use

softw
the sampled values directly.

The disturbance recorder also uses the samples from the input module, in an unprocessed form. This is for
waveform recording and the calculation of true RMS values of current, voltage and power for metering purposes.

In the case of special protection algorithms, using the sampled values directly provides exceptionally fast response
because you do not have to wait for the signal processing task to calculate the fundamental. You can act on the
sampled values immediately.

5.4 FOURIER SIGNAL PROCESSING

When the protection and control task is re-started by the sampling function, it calculates the Fourier components
for the analog signals. Although some pr
harmonic for magnetizing inrush), most protection functions are based on the Fourier-derived fundamental
components of the measured analog signals. The Fourier components of the input current and voltage signals are
stored in memory so that they can be accessed by all of the protection elements’ algorithms.

P64x-TM-EN-1.3 71

otection algorithms use some Fourier-derived harmonics (e.g. second

Ideal anti-alias filter response

Real anti-alias filter

response

2 3 4

1

0.2

0.4

0.6

0.8

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 241

50 Hz 600 Hz

1200 Hz

V00301

Fourier response without

anti-alias filter

Fourier response with

anti-alias filter

Alias frequency

Chapter 4 - Software Design P64x

The Fourier components are calculated using single-cycle Fourier algorithm. This Fourier algorithm always uses
the most r

ecent 24 samples from the 2-cycle buffer.

Most protection algorithms use the fundamental component. In this case, the Fourier algorithm extracts the power
frequency fundamental component from the signal to produce its magnitude and phase angle. This can be
represented in either polar format or rectangular format, depending on the functions and algorithms using it.

The Fourier function acts as a filter, with zero gain at DC and unity gain at the fundamental, but with good
harmonic rejection for all harmonic frequencies up to the nyquist frequency. Frequencies beyond this nyquist
frequency are known as alias frequencies, which are introduced when the sampling frequency becomes less than
twice the frequency component being sampled. However, the Alias frequencies are significantly attenuated by an
anti-aliasing filter (low pass filter), which acts on the analog signals before they are sampled. The ideal cut-off point
of an anti-aliasing low pass filter would be set at:

´

(samples per cycle)

(fundamental frequency)/2

At 24 samples per cycle, this would be nominally 600 Hz for a 50 Hz system, or 720 Hz for a 60 Hz system.

The following figure shows the nominal frequency response of the anti-alias filter and the Fourier filter for a 24­sample single cycle fourier algorithm acting on the fundamental component:

Figure 32: Frequency Response (indicative only)

5.5 PROGRAMMABLE SCHEME LOGIC

The purpose of the programmable scheme logic (PSL) is to allow you to configure your own protection schemes to
suit your particular application. This is done with programmable logic gates and delay timers. To allow greater
flexibility, different PSL is allowed for each of the four setting groups.

The input to the PSL is any combination of the status of the digital input signals from the opto-isolators on the
input board, the outputs of the protection elements such as protection starts and trips, and the outputs of the fixed
protection scheme logic (FSL). The fixed scheme logic provides the standard protection schemes. The PSL consists
of software logic gates and timers. The logic gates can be programmed to perform a range of different logic
functions and can accept any number of inputs. The timers are used either to create a programmable delay,
and/or to condition the logic outputs, such as to create a pulse of fixed duration on the output regardless of the
length of the pulse on the input. The outputs of the PSL are the LEDs on the front panel of the relay and the output
contacts at the rear.

The execution of the PSL logic is event driven. The logic is processed whenever any of its inputs change, for
example as a result of a change in one of the digital input signals or a trip output from a protection element. Also,
only the part of the PSL logic that is affected by the particular input change that has occurred is processed. This
reduces the amount of processing time that is used by the PSL. The protection & control software updates the logic
delay timers and checks for a change in the PSL input signals every time it runs.

The PSL can be configured to create very complex schemes. Because of this PSL desing is achieved by means of a
PC support package called the PSL Editor. This is available as part of the settings application software MiCOm S1
Agile, or as a standalone software module.

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5.6 EVENT RECORDING

A change in any digital input signal or protection element output signal is used to indicate that an event has taken
place. When this happens, the pr
an event is available to be processed and writes the event data to a fast buffer controlled by the supervisor task.
When the supervisor task receives an event record, it instructs the platform software to create the appropriate log
in non-volatile memory (battery backed-up SRAM). The operation of the record logging to battery backed-up SRAM
is slower than the supervisor buffer. This means that the protection software is not delayed waiting for the records
to be logged by the platform software. However, in the rare case when a large number of records to be logged are
created in a short period of time, it is possible that some will be lost, if the supervisor buffer is full before the
platform software is able to create a new log in battery backed-up SRAM. If this occurs then an event is logged to
indicate this loss of information.

Maintenance records are created in a similar manner, with the supervisor task instructing the platform software to
log a record when it receives a maintenance record message. However, it is possible that a maintenance record
may be triggered by a fatal error in the relay in which case it may not be possible to successfully store a
maintenance record, depending on the nature of the problem.

For more information, see the Monitoring and Control chapter.

otection and control task sends a message to the supervisor task to indicate that

5.7 DISTURBANCE RECORDER

The disturbance recorder operates as a separate task from the protection and control task. It can record the
w

aveforms of the calibrated analog channels, plus the values of the digital signals. The recording time is user
selectable up to a maximum of 10.5 seconds. The disturbance recorder is supplied with data by the protection and
control task once per cycle, and collates the received data into the required length disturbance record. The
disturbance records can be extracted using application software or the SCADA system, which can also store the
data in COMTRADE format, allowing the use of other packages to view the recorded data.

For more information, see the Monitoring and Control chapter.

5.8 FAULT LOCATOR

The fault locator uses 12 cycles of the analog input signals to calculate the fault location. The result is returned to

otection and control task, which includes it in the fault record. The pre-fault and post-fault voltages are also

the pr
presented in the fault record. When the fault record is complete, including the fault location, the protection and
control task sends a message to the supervisor task to log the fault record.

The Fault Locator is not available on all models.

5.9 FUNCTION KEY INTERFACE

The function keys interface directly into the PSL as digital input signals. A change of state is only recognized when

ey press is executed on average for longer than 200 ms. The time to register a change of state depends on

a k
whether the function key press is executed at the start or the end of a protection task cycle, with the additional
hardware and software scan time included. A function key press can provide a latched (toggled mode) or output
on key press only (normal mode) depending on how it is programmed. It can be configured to individual protection
scheme requirements. The latched state signal for each function key is written to non-volatile memory and read
from non-volatile memory during relay power up thus allowing the function key state to be reinstated after power­up, should power be inadvertently lost.

P64x-TM-EN-1.3 73

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74 P64x-TM-EN-1.3

CHAPTER 5

CONFIGURATION

Chapter 5 - Configuration P64x

76 P64x-TM-EN-1.3