GE Energy Connections
Grid Solutions
MiCOM P40 Agile
P642, P643, P645
Technical Manual
T
ransformer Protection IED
Hardware Version: M, P
Software Version: 06
Publication Reference: P64x-TM-EN-1.3
Contents
Chapter 1 Introduction 1
1 Chapter Overview 3
2 Foreword 4
2.1 Target Audience 4
2.2 Typographical Conventions 4
2.3 Nomenclature 5
3 Product Scope 6
3.1 Product Versions 6
3.2 Ordering Options 7
4 Features and Functions 8
4.1 Protection Functions 8
4.2 Control Functions 8
4.3 Measurement Functions 9
4.4 Communication Functions 9
5 Compliance 10
6 Functional Overview 11
Chapter 2 Safety Information 13
1 Chapter Overview 15
2 Health and Safety 16
3 Symbols 17
4 Installation, Commissioning and Servicing 18
4.1 Lifting Hazards 18
4.2 Electrical Hazards 18
4.3 UL/CSA/CUL Requirements 19
4.4 Fusing Requirements 19
4.5 Equipment Connections 20
4.6 Protection Class 1 Equipment Requirements 20
4.7 Pre-energisation Checklist 21
4.8 Peripheral Circuitry 21
4.9 Upgrading/Servicing 22
5 Decommissioning and Disposal 23
6 Standards Compliance 24
6.1 EMC Compliance: 2004/108/EC 24
6.2 Product Safety: 2006/95/EC 24
6.3 R&TTE Compliance 24
6.4 UL/CUL Compliance 24
6.5 ATEX Compliance 24
Chapter 3 Hardware Design 27
1 Chapter Overview 29
2 Hardware Architecture 30
3 Mechanical Implementation 31
3.1 Housing Variants 31
3.2 List of Boards 32
4 Front Panel 34
4.1 Front Panel 34
4.1.1 Front Panel Compartments 34
4.1.2 HMI Panel 35
4.1.3 Front Serial Port (SK1) 35
4.1.4 Front Parallel Port (SK2) 36
4.1.5 Fixed Function LEDs 36
Contents P64x
4.1.6 Function Keys 36
4.1.7 Programable LEDs 37
5 Rear Panel 38
6 Boards and Modules 40
6.1 PCBs 40
6.2 Subassemblies 40
6.3 Main Processor Board 41
6.4 Power Supply Board 42
6.4.1 Watchdog 44
6.4.2 Rear Serial Port 45
6.5 Input Module - 1 Transformer Board 46
6.5.1 Input Module Circuit Description 47
6.5.2 Frequency Response 48
6.5.3 Transformer Board 49
6.5.4 Input Board 50
6.6 Standard Output Relay Board 51
6.7 IRIG-B Board 52
6.8 Fibre Optic Board 53
6.9 Rear Communication Board 54
6.10 Ethernet Board 54
6.11 Redundant Ethernet Board 56
6.12 RTD Board 58
6.13 CLIO Board 59
6.14 High Break Output Relay Board 61
Chapter 4 Software Design 63
1 Chapter Overview 65
2 Sofware Design Overview 66
3 System Level Software 67
3.1 Real Time Operating System 67
3.2 System Services Software 67
3.3 Self-Diagnostic Software 67
3.4 Startup Self-Testing 67
3.4.1 System Boot 67
3.4.2 System Level Software Initialisation 68
3.4.3 Platform Software Initialisation and Monitoring 68
3.5 Continuous Self-Testing 68
4 Platform Software 70
4.1 Record Logging 70
4.2 Settings Database 70
4.3 Interfaces 70
5 Protection and Control Functions 71
5.1 Acquisition of Samples 71
5.2 Frequency Tracking 71
5.3 Direct Use of Sample Values 71
5.4 Fourier Signal Processing 71
5.5 Programmable Scheme Logic 72
5.6 Event Recording 73
5.7 Disturbance Recorder 73
5.8 Fault Locator 73
5.9 Function Key Interface 73
Chapter 5 Configuration 75
1 Chapter Overview 77
2 Using the HMI Panel 78
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2.1 Navigating the HMI Panel 79
2.2 Getting Started 79
2.3 Default Display 80
2.4 Default Display Navigation 81
2.5 Password Entry 82
2.6 Processing Alarms and Records 82
2.7 Menu Structure 83
2.8 Changing the Settings 84
2.9 Direct Access (The Hotkey menu) 85
2.9.1 Setting Group Selection Using Hotkeys 85
2.9.2 Control Inputs 85
2.10 Function Keys 86
3 Configuring the Data Protocols 88
3.1 Courier Configuration 88
3.2 DNP3 Configuration 89
3.2.1 DNP3 Configurator 90
3.3 IEC 60870-5-103 Configuration 91
3.4 MODBUS Configuration 92
3.5 IEC 61850 Configuration 93
3.5.1 IEC 61850 Configuration Banks 94
3.5.2 IEC 61850 Network Connectivity 94
4 Date and Time Configuration 95
4.1 Time Zone Compensation 95
4.2 Daylight Saving Time Compensation 95
5 Phase Rotation 96
5.1 CT and VT Reversal 96
Chapter 6 Transformer Differential Protection 97
1 Chapter Overview 99
2 Transformer Differential Protection Principles 100
2.1 Through Fault Stability 100
2.2 Bias Current Compensation 100
2.3 Three-phase Transformer Connection Types 101
2.4 Phase and Amplitude Compensation 104
2.5 Zero Sequence Filtering 105
2.6 Magnetising Inrush Restraint 105
2.7 Overfluxing Restraint 106
3 Implementation 107
3.1 Defining the Power Transformer 107
3.2 Selecting the Current Inputs 107
3.3 Phase Correction 108
3.4 Ratio Correction 108
3.5 CT Parameter Mismatch 109
3.6 Setting up Zero Sequence Filtering 110
3.7 Tripping Characteristics 110
3.7.1 High-Set Function 111
3.7.2 Circuitry Fail Alarm 111
3.8 Tripping Characteristic Stability 112
3.8.1 Maximum Bias 112
3.8.2 Delayed Bias 112
3.8.3 Transient Bias 112
3.8.4 CT Saturation Technique 113
3.8.5 No Gap Detection Technique 113
3.8.6 External Fault Detection Technique 113
3.8.7 Current Transformer Supervision 114
3.8.8 Circuitry Fail Alarm 115
P64x-TM-EN-1.3 iii
Contents P64x
3.9 Differential Biased Trip Logic 116
4 Harmonic Blocking 117
4.1 2nd Harmonic Blocking 117
4.2 2nd Harmonic Blocking Logic 118
4.3 5th Harmonic Blocking Implementation 118
4.4 5th Harmonic Setting Guideline 119
4.5 Geomagnetic Disturbances 119
4.6 Overall Harmonic Blocking Logic 119
5 Application Notes 121
5.1 Setting Guidelines 121
5.2 Example 1: Two-winding Transformer - No Tap Changer 122
5.3 Example 2: Autotransformer with Loaded Delta Winding 124
5.4 Example 3: Autotransformer with Unloaded Delta Winding 127
5.5 Setting Guidelines for Short-Interconnected Biased Differential Protection 130
5.6 Setting Guidelines for Shunt Reactor Biased Differential Protection 133
5.7 Setting Guidelines for using Spare CT Inputs 135
5.8 Setting Guidelines for Reference Vector Group 136
5.9 Stub Bus Application 137
5.9.1 Stub Bus Implementation 137
5.9.2 Stub Bus Scheme 138
5.10 Transformer Differential Protection CT Requirements 138
5.10.1 CT Requirements - Transformer Application 138
5.10.2 CT Requirements - Small Busbar Application 139
Chapter 7 Transformer Condition Monitoring 141
1 Chapter Overview 143
2 Thermal Overload Protection 144
2.1 Thermal Overload Implementation 144
2.1.1 Thermal Overload Bias Current 145
2.2 The Thermal Model 146
2.2.1 Top Oil Temperature Caculations 146
2.2.2 Hotspot Caculations 146
2.2.3 Thermal State Measurement 147
2.3 Application Notes 147
2.3.1 Alstom Recommendations 147
2.3.2 IEEE Recommendations 147
2.3.3 Data Provided by Transformer Manufacturers 148
3 Loss of Life Statistics 150
3.1 Loss of Life Implementation 150
3.1.1 Loss of Life Calculations 150
3.2 Application Notes 152
3.2.1 LOL Setting Guidelines 152
3.2.2 Example 152
4 Through Fault Monitoring 154
4.1 Through Fault Monitoring Implementation 154
4.2 Through Fault Monitoring Logic 155
4.3 Application Notes 155
4.3.1 TFM Setting Guidelines 155
5 RTD Protection 157
5.1 RTD Protection Implementation 157
5.2 RTD Logic 158
5.3 Application Notes 158
5.3.1 Setting Guidelines for RTD Protection 158
6 CLIO Protection 159
6.1 Current Loop Input Implementation 159
6.2 Current Loop Input Logic 161
iv P64x-TM-EN-1.3
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6.3 CLO Implementation 161
6.4 Application Notes 163
6.4.1 CLI Setting Guidelines 163
6.4.2 CLO Setting Guidelines 163
Chapter 8 Restricted Earth Fault Protection 165
1 Chapter Overview 167
2 REF Protection Principles 168
2.1 Resistance-Earthed Star Windings 169
2.2 Solidly-Earthed Star Windings 169
2.3 Through Fault Stability 170
2.4 Restricted Earth Fault Types 170
2.4.1 Low Impedance REF Principle 170
2.4.2 High Impedance REF Principle 171
3 Restricted Earth Fault Protection Implementation 173
3.1 Enabling REF Protection 173
3.2 Selecting the Current Inputs 173
3.3 Low Impedance REF 174
3.3.1 Setting the Bias Characteristic 174
3.3.2 Delayed Bias 175
3.3.3 Transient Bias 175
3.3.4 Restricted Earth Fault Logic 175
3.4 High Impedance REF 175
3.4.1 High Impedance REF Calculation Principles 176
4 Second Harmonic Blocking 177
4.1 REF 2nd harmonic Blocking Logic 177
5 Application Notes 178
5.1 Star Winding Resistance Earthed 178
5.2 Low Impedance REF Protection Application 179
5.2.1 Setting Guidelines for Biased Operation 179
5.2.2 Low Impedance REF Scaling Factor 179
5.2.3 Parameter Calculations 179
5.2.4 Dual CB Application with Different Phase CT Ratios 180
5.2.5 Dual CB Application with Same Phase CT Ratios 181
5.2.6 CT Requirements - Low Impedance REF 181
5.3 High Impedance REF Protection Application 183
5.3.1 High Impedance REF Operating Modes 183
5.3.2 Setting Guidelines for High Impedance Operation 185
5.3.3 Use of Metrosil Non-linear Resistors 187
5.3.4 CT Requirements - High Impedance REF 189
Chapter 9 Current Protection Functions 191
1 Chapter Overview 193
2 Overcurrent Protection Principles 194
2.1 IDMT Characteristics 194
2.1.1 IEC 60255 IDMT Curves 195
2.1.2 European Standards 196
2.1.3 North American Standards 198
2.1.4 Differences Between the North american and European Standards 199
2.2 Principles of Implementation 199
2.2.1 Timer Hold Facility 200
2.3 Magnetising Inrush Restraint 200
3 Phase Overcurrent Protection 202
3.1 Phase Overcurrent Protection for Power Transformers 202
3.2 Phase Overcurrent Protection Implementation 202
3.3 Selecting the Current Inputs 203
P64x-TM-EN-1.3 v
Contents P64x
3.4 Non-Directional Overcurrent Logic 204
3.5 Directional Element 205
3.5.1 Implementing Directionalisation 205
3.5.2 Directional Overcurrent Logic 207
3.6 Application Notes 207
3.6.1 Setting Guidelines 207
3.6.2 Parallel Feeders 209
4 Voltage Dependent Overcurrent Element 210
4.1 Current Setting Threshold Selection 210
4.2 VCO Implementation 210
5 Negative Sequence Overcurrent Protection 212
5.1 NPSOC Protection Implementation 212
5.2 Non-Directional NPSOC Logic 212
5.3 Directional Element 213
5.3.1 Directional NPSOC Logic 213
5.4 Application Notes 214
5.4.1 Setting Guidelines (General) 214
5.4.2 Setting Guidelines (Current Threshold) 214
5.4.3 Setting Guidelines (Time Delay) 214
5.4.4 Setting Guidelines (Directional element) 214
6 Earth Fault Protection 216
6.1 Earth Fault Protection Elements 216
6.2 Non-directional Earth Fault Logic 217
6.3 IDG Curve 217
6.4 Directional Element 218
6.4.1 Residual Voltage Polarisation 218
6.4.2 Negative Sequence Polarisation 219
6.5 Application Notes 220
6.5.1 Setting Guidelines (Non-directional) 220
6.5.2 Setting Guidelines (Directional Element) 221
7 Second Harmonic Blocking 222
7.1 Second Harmonic Blocking Implementation 222
7.2 Second Harmonic Blocking Logic 223
7.3 EF Second Harmonic Blocking Logic 223
7.4 Application Notes 223
7.4.1 Setting Guidelines 223
Chapter 10 CB Fail Protection 225
1 Chapter Overview 227
2 Circuit Breaker Fail Protection 228
3 Circuit Breaker Fail Implementation 229
3.1 Circuit Breaker Fail Timers 229
3.2 Zero Crossing Detection 230
4 Circuit Breaker Fail Logic 231
5 Application Notes 233
5.1 Reset Mechanisms for CB Fail Timers 233
5.2 Setting Guidelines (CB fail Timer) 233
5.3 Setting Guidelines (Undercurrent) 234
Chapter 11 Voltage Protection Functions 235
1 Chapter Overview 237
2 Undervoltage Protection 238
2.1 Undervoltage Protection Implementation 238
2.2 Undervoltage Protection Logic 239
2.3 Application Notes 240
vi P64x-TM-EN-1.3
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2.3.1 Undervoltage Setting Guidelines 240
3 Overvoltage Protection 241
3.1 Overvoltage Protection Implementation 241
3.2 Overvoltage Protection Logic 242
3.3 Application Notes 242
3.3.1 Overvoltage Setting Guidelines 242
4 Residual Overvoltage Protection 244
4.1 Residual Overvoltage Protection Implementation 244
4.2 Residual Overvoltage Logic 245
4.3 Application Notes 245
4.3.1 Calculation for Solidly Earthed Systems 245
4.3.2 Calculation for Impedance Earthed Systems 246
4.3.3 Setting Guidelines 247
5 Negative Sequence Overvoltage Protection 248
5.1 Negative Sequence Overvoltage Implementation 248
5.2 Negative Sequence Overvoltage Logic 248
5.3 Application Notes 248
5.3.1 Setting Guidelines 248
Chapter 12 Frequency Protection Functions 251
1 Chapter Overview 253
2 Overfluxing Protection 254
2.1 Overfluxing Protection Implementation 254
2.1.1 Time-delayed Overfluxing Protection 255
2.1.2 5th Harmonic Blocking 256
2.1.3 Overfluxing Protection Logic 256
2.2 Application Notes 257
2.2.1 Overfluxing Protection Setting Guidelines 257
3 Frequency Protection 259
3.1 Underfrequency Protection 259
3.1.1 Underfrequency Protection Implementation 259
3.1.2 Underfrequency Protection logic 259
3.1.3 Application Notes 260
3.2 Overfrequency Protection 260
3.2.1 Overfrequency Protection Implementation 260
3.2.2 Overfrequency Protection logic 260
3.2.3 Application Notes 261
Chapter 13 Monitoring and Control 263
1 Chapter Overview 265
2 Event Records 266
2.1 Event Types 266
2.1.1 Opto-input Events 267
2.1.2 Contact Events 267
2.1.3 Alarm Events 267
2.1.4 Fault Record Events 271
2.1.5 Maintenance Events 271
2.1.6 Protection Events 272
2.1.7 Security Events 272
2.1.8 Platform Events 272
3 Disturbance Recorder 273
4 Measurements 274
4.1 Measured Quantities 274
4.1.1 Measured and Calculated Currents 274
4.1.2 Measured and Calculated Voltages 274
4.1.3 Power and Energy Quantities 274
P64x-TM-EN-1.3 vii
Contents P64x
4.1.4 Demand Values 275
4.1.5 Other Measurements 275
4.2 Measurement Setup 275
4.3 Opto-input Time Stamping 275
5 Current Input Exclusion Function 276
5.1 Current Input Exclusion Logic 276
5.2 Application Notes 276
5.2.1 Current Input Exclusion Example 276
6 Pole Dead Function 278
6.1 Pole Dead Function Implementation 278
6.2 Pole Dead Logic 279
6.3 CB Status Indication 280
Chapter 14 Supervision 283
1 Chapter Overview 285
2 Voltage Transformer Supervision 286
2.1 Loss of One or Two Phase Voltages 286
2.2 Loss of all Three Phase Voltages 286
2.3 Absence of all Three Phase Voltages on Line Energisation 286
2.4 VTS Implementation 287
2.5 VTS Logic 288
3 Current Transformer Supervision 291
3.1 CTS Implementation 291
3.2 CTS Logic 292
3.3 Application Notes 293
3.3.1 Setting Guidelines 293
4 Trip Circuit Supervision 294
4.1 Trip Circuit Supervision Scheme 1 294
4.1.1 Resistor Values 294
4.1.2 PSL for TCS Scheme 1 295
4.2 Trip Circuit Supervision Scheme 2 295
4.2.1 Resistor Values 296
4.2.2 PSL for TCS Scheme 2 296
4.3 Trip Circuit Supervision Scheme 3 296
4.3.1 Resistor Values 297
4.3.2 PSL for TCS Scheme 3 297
Chapter 15 Digital I/O and PSL Configuration 299
1 Chapter Overview 301
2 Configuring Digital Inputs and Outputs 302
3 Scheme Logic 303
3.1 PSL Editor 304
3.2 PSL Schemes 304
3.3 PSL Scheme Version Control 304
4 Configuring the Opto-Inputs 305
5 Assigning the Output Relays 306
6 Fixed Function LEDs 307
6.1 Trip LED Logic 307
7 Configuring Programmable LEDs 308
8 Function Keys 310
9 Control Inputs 311
Chapter 16 Communications 313
1 Chapter Overview 315
viii P64x-TM-EN-1.3
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2 Communication Interfaces 316
3 Serial Communication 317
3.1 EIA(RS)232 Bus 317
3.2 EIA(RS)485 Bus 317
3.2.1 EIA(RS)485 Biasing Requirements 318
3.3 K-Bus 318
4 Standard Ethernet Communication 320
4.1 Hot-Standby Ethernet Failover 320
5 Redundant Ethernet Communication 321
5.1 Supported Protocols 321
5.2 Parallel Redundancy Protocol 322
5.3 Rapid Spanning Tree Protocol 323
5.4 Self Healing Protocol 323
5.5 Dual Homing Protocol 325
5.6 Redundant Ethernet Configuration 326
5.6.1 Setting the NIC IP Address 328
5.6.2 Setting the Switch IP Address 328
6 Data Protocols 329
6.1 Courier 329
6.1.1 Physical Connection and Link Layer 329
6.1.2 Courier Database 330
6.1.3 Settings Categories 330
6.1.4 Setting Changes 330
6.1.5 Event Extraction 330
6.1.6 Disturbance Record Extraction 332
6.1.7 Programmable Scheme Logic Settings 332
6.1.8 Time Synchronisation 332
6.1.9 Courier Configuration 333
6.2 IEC 60870-5-103 334
6.2.1 Physical Connection and Link Layer 334
6.2.2 Initialisation 335
6.2.3 Time Synchronisation 335
6.2.4 Spontaneous Events 335
6.2.5 General Interrogation (GI) 335
6.2.6 Cyclic Measurements 335
6.2.7 Commands 335
6.2.8 Test Mode 336
6.2.9 Disturbance Records 336
6.2.10 Command/Monitor Blocking 336
6.2.11 IEC 60870-5-103 Configuration 336
6.3 DNP 3.0 337
6.3.1 Physical Connection and Link Layer 338
6.3.2 Object 1 Binary Inputs 338
6.3.3 Object 10 Binary Outputs 338
6.3.4 Object 20 Binary Counters 339
6.3.5 Object 30 Analogue Input 339
6.3.6 Object 40 Analogue Output 340
6.3.7 Object 50 Time Synchronisation 340
6.3.8 DNP3 Device Profile 340
6.3.9 DNP3 Configuration 348
6.4 MODBUS 349
6.4.1 Physical Connection and Link Layer 350
6.4.2 MODBUS Functions 350
6.4.3 Response Codes 350
6.4.4 Register Mapping 351
6.4.5 Event Extraction 351
6.4.6 Disturbance Record Extraction 352
6.4.7 Setting Changes 360
P64x-TM-EN-1.3 ix
Contents P64x
6.4.8 Password Protection 360
6.4.9 Protection and Disturbance Recorder Settings 360
6.4.10 Time Synchronisation 361
6.4.11 Power and Energy Measurement Data Formats 362
6.4.12 MODBUS Configuration 363
6.5 IEC 61850 364
6.5.1 Benefits of IEC 61850 364
6.5.2 IEC 61850 Interoperability 365
6.5.3 The IEC 61850 Data Model 365
6.5.4 IEC 61850 in MiCOM IEDs 366
6.5.5 IEC 61850 Data Model Implementation 366
6.5.6 IEC 61850 Communication Services Implementation 366
6.5.7 IEC 61850 Peer-to-peer (GOOSE) communications 367
6.5.8 Mapping GOOSE Messages to Virtual Inputs 367
6.5.9 Ethernet Functionality 367
6.5.10 IEC 61850 Configuration 367
7 Read Only Mode 369
7.1 IEC 60870-5-103 Protocol Blocking 369
7.2 Courier Protocol Blocking 369
7.3 IEC 61850 Protocol Blocking 370
7.4 Read-Only Settings 370
7.5 Read-Only DDB Signals 370
8 Time Synchronisation 371
8.1 Demodulated IRIG-B 371
8.1.1 IRIG-B Implementation 371
8.2 SNTP 372
8.3 Time Synchronsiation using the Communication Protocols 372
Chapter 17 Cyber-Security 373
1 Overview 375
2 The Need for Cyber-Security 376
3 Standards 377
3.1 NERC Compliance 377
3.1.1 CIP 002 378
3.1.2 CIP 003 378
3.1.3 CIP 004 378
3.1.4 CIP 005 378
3.1.5 CIP 006 378
3.1.6 CIP 007 379
3.1.7 CIP 008 379
3.1.8 CIP 009 379
3.2 IEEE 1686-2007 379
4 Cyber-Security Implementation 381
4.1 NERC-Compliant Display 381
4.2 Four-level Access 382
4.2.1 Blank Passwords 383
4.2.2 Password Rules 383
4.2.3 Access Level DDBs 384
4.3 Enhanced Password Security 384
4.3.1 Password Strengthening 384
4.3.2 Password Validation 384
4.3.3 Password Blocking 385
4.4 Password Recovery 386
4.4.1 Password Recovery 386
4.4.2 Password Encryption 387
4.5 Disabling Physical Ports 387
4.6 Disabling Logical Ports 387
x P64x-TM-EN-1.3
P64x Contents
4.7 Security Events Management 388
4.8 Logging Out 390
Chapter 18 Installation 391
1 Chapter Overview 393
2 Handling the Goods 394
2.1 Receipt of the Goods 394
2.2 Unpacking the Goods 394
2.3 Storing the Goods 394
2.4 Dismantling the Goods 394
3 Mounting the Device 395
3.1 Flush Panel Mounting 395
3.2 Rack Mounting 396
4 Cables and Connectors 398
4.1 Terminal Blocks 398
4.2 Power Supply Connections 399
4.3 Earth Connnection 399
4.4 Current Transformers 399
4.5 Voltage Transformer Connections 400
4.6 Watchdog Connections 400
4.7 EIA(RS)485 and K-Bus Connections 400
4.8 IRIG-B Connection 400
4.9 Opto-input Connections 400
4.10 Output Relay Connections 400
4.11 Ethernet Metallic Connections 401
4.12 Ethernet Fibre Connections 401
4.13 RS232 connection 401
4.14 Download/Monitor Port 401
4.15 GPS Fibre Connection 401
4.16 Fibre Communication Connections 401
4.17 RTD Connections 402
4.18 CLIO Connections 403
5 Case Dimensions 404
5.1 Case Dimensions 40TE 404
5.2 Case Dimensions 60TE 405
5.3 Case Dimensions 80TE 406
Chapter 19 Commissioning Instructions 407
1 Chapter Overview 409
2 General Guidelines 410
3 Commissioning Test Menu 411
3.1 Opto I/P Status Cell (Opto-input Status) 411
3.2 Relay O/P Status Cell (Relay Output Status) 411
3.3 Test Mode Cell 411
3.4 Test Pattern Cell 412
3.5 Contact Test Cell 412
3.6 Test LEDs Cell 412
3.7 Red and Green LED Status Cells 412
3.8 PSL Verificiation 412
3.8.1 Test Port Status Cell 412
3.8.2 Monitor Bit 1 to 8 Cells 412
3.8.3 Using a Monitor Port Test Box 413
4 Commissioning Equipment 414
4.1 Recommended Commissioning Equipment 414
4.2 Essential Commissioning Equipment 414
P64x-TM-EN-1.3 xi
Contents P64x
4.3 Advisory Test Equipment 415
5 Product Checks 416
5.1 Product Checks with the IED De-energised 416
5.1.1 Visual Inspection 417
5.1.2 Current Transformer Shorting Contacts 417
5.1.3 Insulation 417
5.1.4 External Wiring 417
5.1.5 Watchdog Contacts 418
5.1.6 Power Supply 418
5.2 Product Checks with the IED Energised 418
5.2.1 Watchdog Contacts 418
5.2.2 Test LCD 419
5.2.3 Date and Time 419
5.2.4 Test LEDs 420
5.2.5 Test Alarm and Out-of-Service LEDs 420
5.2.6 Test Trip LED 420
5.2.7 Test User-programmable LEDs 420
5.2.8 Test Opto-inputs 420
5.2.9 Test Output Relays 420
5.2.10 RTD Inputs 421
5.2.11 Current Loop Outputs 421
5.2.12 Current Loop Inputs 421
5.2.13 Test Serial Communication Port RP1 422
5.2.14 Test Serial Communication Port RP2 423
5.2.15 Test Ethernet Communication 424
5.3 Secondary Injection Tests 424
5.3.1 Test Current Inputs 424
5.3.2 Test Voltage Inputs 425
6 Setting Checks 426
6.1 Apply Application-specific Settings 426
6.1.1 Transferring Settings from a Settings File 426
6.1.2 Entering settings using the HMI 426
7 Checking the Differential Element 428
7.1 Using the Omicron Advanced Module 428
8 Protection Timing Checks 431
8.1 Bypassing the All Pole Dead Blocking Condition 431
8.2 Overcurrent Check 431
8.3 Connecting the Test Circuit 431
8.4 Performing the Test 431
8.5 Check the Operating Time 431
9 Onload Checks 433
9.1 Confirm Current Connections 433
9.2 Confirm Voltage Connections 433
9.3 On-load Directional Test 434
10 Final Checks 435
Chapter 20 Maintenance and Troubleshooting 437
1 Chapter Overview 439
2 Maintenance 440
2.1 Maintenance Checks 440
2.1.1 Alarms 440
2.1.2 Opto-isolators 440
2.1.3 Output Relays 440
2.1.4 Measurement Accuracy 440
2.2 Replacing the Device 441
2.3 Repairing the Device 442
2.4 Removing the front panel 442
xii P64x-TM-EN-1.3
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2.5 Replacing PCBs 443
2.5.1 Replacing the main processor board 443
2.5.2 Replacement of communications boards 444
2.5.3 Replacement of the input module 445
2.5.4 Replacement of the power supply board 445
2.5.5 Replacement of the I/O boards 446
2.6 Recalibration 446
2.7 Changing the battery 446
2.7.1 Post Modification Tests 447
2.7.2 Battery Disposal 447
2.8 Cleaning 447
3 Troubleshooting 448
3.1 Self-Diagnostic Software 448
3.2 Power-up Errors 448
3.3 Error Message or Code on Power-up 448
3.4 Out of Service LED on at power-up 449
3.5 Error Code during Operation 450
3.5.1 Backup Battery 450
3.6 Mal-operation during testing 450
3.6.1 Failure of Output Contacts 450
3.6.2 Failure of Opto-inputs 450
3.6.3 Incorrect Analogue Signals 451
3.7 PSL Editor Troubleshooting 451
3.7.1 Diagram Reconstruction 451
3.7.2 PSL Version Check 451
4 Repair and Modification Procedure 452
Chapter 21 Technical Specifications 453
1 Chapter Overview 455
2 Interfaces 456
2.1 Front Serial Port 456
2.2 Download/Monitor Port 456
2.3 Rear Serial Port 1 456
2.4 Fibre Rear Serial Port 1 456
2.5 Rear Serial Port 2 457
2.6 IRIG-B (Demodulated) 457
2.7 IRIG-B (Modulated) 457
2.8 Rear Ethernet Port Copper 457
2.9 Rear Ethernet Port Fibre 458
2.9.1 100 Base FX Receiver Characteristics 458
2.9.2 100 Base FX Transmitter Characteristics 458
3 Performance of Transformer Differential Protection and Monitoring Functions 459
3.1 Transformer Differential Protection 459
3.2 Matching Factors 459
3.3 Circuitry Fault Alarm 459
3.4 Through Fault Monitoring 460
3.5 Thermal Overload 460
3.6 Low Impedance Restricted Earth Fault 460
3.7 High Impedance Restricted Earth Fault 460
4 Performance of Current Protection Functions 461
4.1 Transient Overreach and Overshoot 461
4.2 Three-phase Overcurrent Protection 461
4.2.1 Three-phase Overcurrent Directional Parameters 461
4.3 Voltage Dependent Overcurrent Protection 461
4.4 Earth Fault Protection 462
4.4.1 Earth Fault Directional Parameters 462
P64x-TM-EN-1.3 xiii
Contents P64x
4.5 Negative Sequence Overcurrent Protection 462
4.5.1 NPSOC Directional Parameters 462
4.6 Circuit Breaker Fail Protection 463
5 Performance of Voltage Protection Functions 464
5.1 Undervoltage Protection (P643/5) 464
5.2 Overvoltage Protection 464
5.3 Residual Overvoltage Protection (P643/5) 464
5.4 Negative Sequence Voltage Protection 464
6 Performance of Frequency Protection Functions 465
6.1 Overfrequency Protection 465
6.2 Underfrequency Protection 465
6.3 Overfluxing Protection 465
7 Performance of Monitoring and Control Functions 466
7.1 Voltage Transformer Supervision 466
7.2 Current Transformer Supervision 466
7.3 Pole Dead Protection 466
7.4 PSL Timers 467
8 Measurements and Recording 468
8.1 General 468
8.2 Disturbance Records 468
8.3 Event, Fault and Maintenance Records 468
8.4 Current Loop Inputs/Outputs 468
9 Standards Compliance 470
9.1 EMC Compliance: 2004/108/EC 470
9.2 Product Safety: 2006/95/EC 470
9.3 R&TTE Compliance 470
9.4 UL/CUL Compliance 470
9.5 ATEX Compliance 470
9.6 IDMT standards 471
10 Mechanical Specifications 472
10.1 Physical Parameters 472
10.2 Enclosure Protection 472
10.3 Mechanical Robustness 472
10.4 Transit Packaging Performance 472
11 Ratings 473
11.1 AC Measuring Inputs 473
11.2 Current Transformer Inputs 473
11.3 Voltage Transformer Inputs 473
12 Power Supply 474
12.1 Auxiliary Supply Voltage 474
12.2 Nominal Burden 474
12.3 Power Supply Interruption 474
12.4 Battery Backup 475
13 Input / Output Connections 476
13.1 Isolated Digital Inputs 476
13.1.1 Nominal Pickup and Reset Thresholds 476
13.2 Standard Output Contacts 476
13.3 High Break Output Contacts 477
13.4 Watchdog Contacts 477
14 Environmental Conditions 478
14.1 Ambient Temperature Range 478
14.2 Temperature Endurance Test 478
14.3 Ambient Humidity Range 478
14.4 Corrosive Environments 478
15 Type Tests 479
15.1 Insulation 479
xiv P64x-TM-EN-1.3
P64x Contents
15.2 Creepage Distances and Clearances 479
15.3 High Voltage (Dielectric) Withstand 479
15.4 Impulse Voltage Withstand Test 479
16 Electromagnetic Compatibility 480
16.1 1 MHz Burst High Frequency Disturbance Test 480
16.2 Damped Oscillatory Test 480
16.3 Immunity to Electrostatic Discharge 480
16.4 Electrical Fast Transient or Burst Requirements 480
16.5 Surge Withstand Capability 480
16.6 Surge Immunity Test 481
16.7 Immunity to Radiated Electromagnetic Energy 481
16.8 Radiated Immunity from Digital Communications 481
16.9 Radiated Immunity from Digital Radio Telephones 481
16.10 Immunity to Conducted Disturbances Induced by Radio Frequency Fields 481
16.11 Magnetic Field Immunity 482
16.12 Conducted Emissions 482
16.13 Radiated Emissions 482
16.14 Power Frequency 482
Appendix A Ordering Options 483
Appendix B Settings and Signals 485
Appendix C Wiring Diagrams 487
P64x-TM-EN-1.3 xv
Contents P64x
xvi P64x-TM-EN-1.3
Table of Figures
Figure 1: P64x version evolution 7
Figure 2: Functional overview 11
Figure 3: Hardware architecture 30
Figure 4: Exploded view of IED 31
Figure 5: Front panel (60TE) 34
Figure 6: HMI panel 35
Figure 7: Rear view of populated case 38
Figure 8: Terminal block types 39
Figure 9: Rear connection to terminal block 40
Figure 10: Main processor board 41
Figure 11: Power supply board 42
Figure 12: Power supply assembly 43
Figure 13: Power supply terminals 44
Figure 14: Watchdog contact terminals 45
Figure 15: Rear serial port terminals 46
Figure 16: Input module - 1 transformer board 46
Figure 17: Input module schematic 47
Figure 18: Frequency response 48
Figure 19: Transformer board 49
Figure 20: Input board 50
Figure 21: Standard output relay board - 8 contacts 51
Figure 22: IRIG-B board 52
Figure 23: Fibre optic board 53
Figure 24: Rear communication board 54
Figure 25: Ethernet board 54
Figure 26: Redundant Ethernet board 56
Figure 27: RTD board 58
Figure 28: RTD board 59
Figure 29: High Break relay output board 61
Figure 30: High Break contact operation 62
Figure 31: Software Architecture 66
Figure 32: Frequency Response (indicative only) 72
Figure 33: Navigating the HMI 79
Figure 34: Default display navigation 81
Figure 35: Compensation using biased differential characteristic 101
Figure 36: Transformer winding connections - part 1 103
Figure 37: Transformer winding connections - part 2 104
Figure 38: Magnetising inrush phenomenon 105
Table of Figures P64x
Figure 39: Typical overflux current waveform 106
Figure 40: CT parameter mismatch logic diagram 109
Figure 41: Transformer biased tripping characteristic 111
Figure 42: Transient bias characteristic 113
Figure 43: Time to saturation - external AN fault 114
Figure 44: Effect of CTS restrain 115
Figure 45: Bias characteristic with circuitry fail alarm 115
Figure 46: Differential biased trip logic 116
Figure 47: 2nd harmonic blocking process 117
Figure 48: 2nd harmonic blocking logic 118
Figure 49: 5th harmonic blocking process 119
Figure 50: Differential protection blocking mechanisms 120
Figure 51: Triple slope characteristic 122
Figure 52: P642 used to protect a two winding transformer 122
Figure 53: P645 used to protect an autotransformer with loaded delta winding 125
Figure 54: P643 used to protect an autotransformer with unloaded delta winding 128
Figure 55: Unloaded delta – current distribution 129
Figure 56: Single bus differential protection zone 131
Figure 57: Busbar biased differential protection 133
Figure 58: Shunt Reactor single line diagram 134
Figure 59: P643 Using spare CT input for overcurrent protection 136
Figure 60: Stub Bus arrangement 137
Figure 61: Stub Bus Scheme Logic 138
Figure 62: Transformer losses 144
Figure 63: Through-fault alarm logic 155
Figure 64: P645 used to protect an autotransformer with loaded delta winding 156
Figure 65: Connection for RTD thermal probes 157
Figure 66: RTD logic 158
Figure 67: Current loop input ranges 160
Figure 68: Current Loop Input logic 161
Figure 69: Current Loop Output ranges 162
Figure 70: REF protection for delta side 168
Figure 71: REF protection for star side 168
Figure 72: REF Protection for resistance-earthed systems 169
Figure 73: REF Protection for solidly earthed system 169
Figure 74: Low Impedance REF Connection 171
Figure 75: Three-slope REF bias characteristic 171
Figure 76: High Impedance REF principle 172
Figure 77: High Impedance REF Connection 172
Figure 78: REF bias characteristic 174
xviii P64x-TM-EN-1.3
P64x Table of Figures
Figure 79: Low impedance restricted Earth Fault logic 175
Figure 80: REF 2nd harmonic blocking logic 177
Figure 81: Star winding, resistance earthed 178
Figure 82: Percentage of winding protected 178
Figure 83: Low Impedance REF Scaling Factor 179
Figure 84: Low-Z REF for dual CB application with different phase CT ratios 180
Figure 85: Low-Z REF for dual CB application with same phase CT ratios 181
Figure 86: Hi-Z REF protection for a grounded star winding 184
Figure 87: Hi-Z REF protection for a delta winding 184
Figure 88: Hi-Z REF Protection for autotransformer configuration 185
Figure 89: High Impedance REF for the LV winding 185
Figure 90: High Impedance REF CT requirement 190
Figure 91: IEC 60255 IDMT curves 196
Figure 92: Principle of protection function implementation 199
Figure 93: Magnetising inrush phenomenon 201
Figure 94: Non-directional overcurrent logic diagram 204
Figure 95: Directional overcurrent logic diagram 207
Figure 96: Typical distribution system using parallel transformers 209
Figure 97: Selecting the current threshold setting 210
Figure 98: Modification of current pickup level for voltage controlled overcurrent protection 211
Figure 99: Negative Sequence Overcurrent logic - non-directional operation 212
Figure 100: Negative Phase equence Overcurrent logic - directional operation 213
Figure 101: Non-directional EF logic (single stage) 217
Figure 102: IDG Characteristic 218
Figure 103: Directional EF logic with neutral voltage polarization (single stage) 219
Figure 104: Directional Earth Fault logic with negative phase sequence polarisation (single
220
stage)
Figure 105: Phase overcurrent 2nd harmonic blocking Logic 223
Figure 106: Earth fault 2nd harmonic blocking Logic 223
Figure 107: Circuit Breaker Fail Logic - part 1 231
Figure 108: Circuit Breaker Fail Logic - part 2 232
Figure 109: CB Fail timing 234
Figure 110: Undervoltage - single and three phase tripping mode (single stage) 239
Figure 111: Overvoltage - single and three phase tripping mode (single stage) 242
Figure 112: Residual Overvoltage logic 245
Figure 113: Residual voltage for a solidly earthed system 246
Figure 114: Residual voltage for an impedance earthed system 247
Figure 115: Negative Sequence Overvoltage logic 248
Figure 116: Variable time overfluxing protection characteristic 255
Figure 117: Overfluxing reset characteristic 256
P64x-TM-EN-1.3 xix
Table of Figures P64x
Figure 118: 5th harmonic blocking time delay in PSL 256
Figure 119: Overfluxing protection logic 257
Figure 120: Multi-stage overfluxing characteristic 258
Figure 121: Scheme logic for multi-stage overfluxing characteristic 258
Figure 122: Underfrequency logic (single stage) 259
Figure 123: Overfrequency logic (single stage) 260
Figure 124: Fault recorder stop conditions 271
Figure 125: CT Exclusion logic 276
Figure 126: CT input exclusion - 1.5 CB application 277
Figure 127: CT input exclusion - auxiliary contact connection 277
Figure 128: Pole Dead logic - P642 279
Figure 129: Pole Dead logic - P643 and P645 280
Figure 130: Forcing CB Closed signals 281
Figure 131: VTS logic (P642 with 2 single-phase VTs) 288
Figure 132: VTS logic (P643 and P645 with 3-phase VTs) 289
Figure 133: CTS restraint region increase 291
Figure 134: CTS logic diagram 292
Figure 135: TCS Scheme 1 294
Figure 136: PSL for TCS Scheme 1 295
Figure 137: TCS Scheme 2 295
Figure 138: PSL for TCS Scheme 2 296
Figure 139: TCS Scheme 3 296
Figure 140: PSL for TCS Scheme 3 297
Figure 141: Scheme Logic Interfaces 303
Figure 142: Trip LED logic 307
Figure 143: RS485 biasing circuit 318
Figure 144: Remote communication using K-Bus 319
Figure 145: IED attached to separate LANs 322
Figure 146: IED attached to redundant Ethernet star or ring circuit 323
Figure 147: IED, bay computer and Ethernet switch with self healing ring facilities 324
Figure 148: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches 324
Figure 149: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches
after failur
e
324
Figure 150: Dual homing mechanism 325
Figure 151: Application of Dual Homing Star at substation level 326
Figure 152: IED and REB switch IP address configuration 327
Figure 153: DIP switches for setting IP address 327
Figure 154: Control input behaviour 339
Figure 155: Manual selection of a disturbance record 355
Figure 156: Automatic selection of disturbance record - method 1 356
xx P64x-TM-EN-1.3
P64x Table of Figures
Figure 157: Automatic selection of disturbance record - method 2 357
Figure 158: Configuration file extraction 358
Figure 159: Data file extraction 359
Figure 160: Data model layers in IEC61850 365
Figure 161: GPS Satellite timing signal 371
Figure 162: Default display navigation 382
Figure 163: Location of battery isolation strip 395
Figure 164: Rack mounting of products 396
Figure 165: Terminal block types 398
Figure 166: 40TE case dimensions 404
Figure 167: 60TE case dimensions 405
Figure 168: 80TE case dimensions 406
Figure 169: RP1 physical connection 422
Figure 170: Remote communication using K-bus 423
Figure 171: Operating Characteristic Diagram 429
Figure 172: Trip Time Test Plane 429
Figure 173: Harmonic Restraint Test Plane 430
Figure 174: Possible terminal block types 442
Figure 175: Front panel assembly 444
P64x-TM-EN-1.3 xxi
Table of Figures P64x
xxii P64x-TM-EN-1.3
CHAPTER 1
INTRODUCTION
Chapter 1 - Introduction P64x
2 P64x-TM-EN-1.3
P64x Chapter 1 - Introduction
1 CHAPTER OVERVIEW
This chapter provides some general information about the technical manual and an introduction to the device(s)
described in this technical manual.
This chapter contains the following sections:
Chapter Overview 3
eword 4
For
Product Scope 6
Features and Functions 8
Compliance 10
Functional Overview 11
P64x-TM-EN-1.3 3
Chapter 1 - Introduction P64x
2 FOREWORD
This technical manual provides a functional and technical description of GE's P642, P643, P645, as well as a
ehensive set of instructions for using the device. The level at which this manual is written assumes that you
compr
are already familiar with protection engineering and have experience in this discipline. The description of principles
and theory is limited to that which is necessary to understand the product. For further details on general
protection engineering theory, we refer you to Alstom's publication NPAG, which is available online or from our
contact centre.
We have attempted to make this manual as accurate, comprehensive and user-friendly as possible. However we
cannot guarantee that it is free from errors. Nor can we state that it cannot be improved. We would therefore be
very pleased to hear from you if you discover any errors, or have any suggestions for improvement. Our policy is to
provide the information necessary to help you safely specify, engineer, install, commission, maintain, and
eventually dispose of this product. We consider that this manual provides the necessary information, but if you
consider that more details are needed, please contact us.
All feedback should be sent to our contact centre via the following URL:
www.gegridsolutions.com/contact
2.1 TARGET AUDIENCE
This manual is aimed towards all professionals charged with installing, commissioning, maintaining,
tr
oubleshooting, or operating any of the products within the specified product range. This includes installation and
commissioning personnel as well as engineers who will be responsible for operating the product.
The level at which this manual is written assumes that installation and commissioning engineers have knowledge
of handling electronic equipment. Also, system and protection engineers have a thorough knowledge of protection
systems and associated equipment.
2.2 TYPOGRAPHICAL CONVENTIONS
The following typographical conventions are used throughout this manual.
● The names for special k
For example: ENTER
● When describing software applications, menu items, buttons, labels etc as they appear on the screen are
written in bold type.
For example: Select Save from the file menu.
● Filenames and paths use the courier font
For example: Example\File.text
● Special terminology is written with leading capitals
For example: Sensitive Earth Fault
● If reference is made to the IED's internal settings and signals database, the menu group heading (column)
text is written in upper case italics
For example: The SYSTEM DATA column
● If reference is made to the IED's internal settings and signals database, the setting cells and DDB signals are
written in bold italics
For example: The Language cell in the SYSTEM DATA column
● If reference is made to the IED's internal settings and signals database, the value of a cell's content is
written in the Courier font
For example: The Language cell in the SYSTEM DATA column contains the value English
eys appear in capital letters.
4 P64x-TM-EN-1.3
P64x Chapter 1 - Introduction
2.3 NOMENCLATURE
Due to the technical nature of this manual, many special terms, abbreviations and acronyms are used throughout
the manual. Some of these terms ar
specific terms used by GE. The first instance of any acronym or term used in a particular chapter is explained. In
addition, a separate glossary is available on the GE website, or from the GE contact centre.
We would like to highlight the following changes of nomenclature however:
● The word 'relay' is no longer used to describe the device itself. Instead, the device is referred to as the 'IED'
(Intelligent Electronic Device), the 'device', or the 'product'. The word 'relay' is used purely to describe the
electromechanical components within the device, i.e. the output relays.
● British English is used throughout this manual.
● The British term 'Earth' is used in favour of the American term 'Ground'.
e well-known industry-specific terms while others may be special product-
P64x-TM-EN-1.3 5
Chapter 1 - Introduction P64x
3 PRODUCT SCOPE
The MiCOM P64x range of devices preserve transformer service life by offering fast protection for transformer
faults. Hosted on an adv
Fault (REF),Thermal, and Overfluxing protection, plus backup protection for uncleared external faults. Further, the
P64x devices provide a range of transformer condition monitoring functions such as Through-fault monitoring,
loss of life statistics, RTD and CLIO protection functionality.
All devices also provide a comprehensive range of additional features to aid with power system diagnosis and fault
analysis.
Model variants cover two and three winding power transformers, with up to five sets of 3-phase CT inputs. Backup
overcurrent protection can be directionalised, if you select the optional 3-phase VT input.
The P64x range consists of three models; the P642, P643, and P645.
● The P642 provides 8 on-board CTs to support two-winding 3-phase power transformers and 1or 2 single-
phase voltage transformers to support directionalisation and a range of voltage-related functions.
● The P643 provides 12 on-board CTs to support three-winding 3-phase power transformers, a single-phase
voltage transformer and an optional three-phase voltage transformer to support directionalisation and a
range of voltage-related functions including undervoltage, overvoltage and residual overvoltage protection.
● The P645 provides 18 on-board CTs to support three-winding 3-phase power transformers and other
applications needing 5 sets of 3-phase current inputs, a single-phase voltage transformer and an optional
three-phase voltage transformer to support directionalisation and a range of voltage-related functions
including undervoltage, overvoltage and residual overvoltage protection.
The difference in model variants are summarised below:
anced IED platform, the P64x products incorporate Current Differential, Restricted Earth
Feature/Variant P642 P643 P645
Case 40TE 60TE/80TE 60TE/80TE
Number of CT Inputs 8 (6 Bias, 2 EF) 12 (9 bias, 3EF) 18 (15 Bias, 3EF)
Number of VT inputs 1 or 2 1 or 4 1 or 4
Number of bias inputs (3-phase CT sets) 2 3 5
Optically coupled digital inputs 8 - 12 16 - 40 16 - 40
Standard relay output contacts 8 - 12 8 - 24 8 - 24
Function keys No 10 10
Undervoltage/Overvoltage/Residual voltage protection No Yes Yes
Underfrequency/Overfrequency protection No Yes Yes
Overfluxing protection 1-phase only 1-phase + 3-phase 1-phase + 3-phase
Programmable LEDs 8 red 18 tri-colour 18 tri-colour
3.1 PRODUCT VERSIONS
Since software version 2, the evolution of the P64x product family has followed two paths as shown below:
6 P64x-TM-EN-1.3